Freescale MKL05Z8VLC4 Kl05 sub-family data sheet Datasheet

Freescale Semiconductor
Data Sheet: Technical Data
Document Number: KL05P48M48SF1
Rev. 3, 11/29/2012
KL05P48M48SF1
KL05 Sub-Family Data Sheet
Supports: MKL05Z8VFK4,
MKL05Z16VFK4, MKL05Z32VFK4,
MKL05Z8VLC4, MKL05Z16VLC4,
MKL05Z32VLC4, MKL05Z8VFM4,
MKL05Z16VFM4, MKL05Z32VFM4,
MKL05Z16VLF4, MKL05Z32VLF4
Features
• Operating Characteristics
– Voltage range: 1.71 to 3.6 V
– Flash write voltage range: 1.71 to 3.6 V
– Temperature range (ambient): -40 to 105°C
• Performance
– Up to 48 MHz ARM® Cortex-M0+ core
• Memories and memory interfaces
– Up to 32 KB program flash memory
– Up to 4 KB RAM
• Clocks
– 32 kHz to 40 kHz or 3 MHz to 32 MHz crystal
oscillator
– Multi-purpose clock source
• System peripherals
– Nine low-power modes to provide power
optimization based on application requirements
– 4-channel DMA controller, supporting up to 63
request sources
– COP Software watchdog
– Low-leakage wakeup unit
– SWD interface and Micro Trace buffer
– Bit Manipulation Engine (BME)
• Security and integrity modules
– 80-bit unique identification (ID) number per chip
• Human-machine interface
– Low-power hardware touch sensor interface (TSI)
– General-purpose input/output
• Analog modules
– 12-bit SAR ADC
– 12-bit DAC
– Analog comparator (CMP) containing a 6-bit DAC
and programmable reference input
• Timers
– Two 2-channel Timer/PWM (TPM)
– Periodic interrupt timers
– 16-bit low-power timer (LPTMR)
– Real-time clock
• Communication interfaces
– One 8-bit SPI module
– I2C module
– One low power UART module
Freescale reserves the right to change the detail specifications as may be
required to permit improvements in the design of its products.
© 2012 Freescale Semiconductor, Inc.
Table of Contents
1 Ordering parts...........................................................................3
5.3 Switching specifications.....................................................21
1.1 Determining valid orderable parts......................................3
5.3.1
Device clock specifications...................................21
2 Part identification......................................................................3
5.3.2
General Switching Specifications..........................21
2.1 Description.........................................................................3
5.4 Thermal specifications.......................................................22
2.2 Format...............................................................................3
5.4.1
Thermal operating requirements...........................22
2.3 Fields.................................................................................3
5.4.2
Thermal attributes.................................................22
2.4 Example............................................................................4
6 Peripheral operating requirements and behaviors....................23
3 Terminology and guidelines......................................................4
6.1 Core modules....................................................................23
3.1 Definition: Operating requirement......................................4
6.1.1
SWD Electricals ...................................................23
3.2 Definition: Operating behavior...........................................4
6.2 System modules................................................................24
3.3 Definition: Attribute............................................................5
6.3 Clock modules...................................................................24
3.4 Definition: Rating...............................................................5
6.3.1
MCG specifications...............................................24
3.5 Result of exceeding a rating..............................................6
6.3.2
Oscillator electrical specifications.........................25
3.6 Relationship between ratings and operating
requirements......................................................................6
6.4 Memories and memory interfaces.....................................28
6.4.1
Flash electrical specifications................................28
3.7 Guidelines for ratings and operating requirements............7
6.5 Security and integrity modules..........................................29
3.8 Definition: Typical value.....................................................7
6.6 Analog...............................................................................29
3.9 Typical Value Conditions...................................................8
6.6.1
ADC electrical specifications.................................29
4 Ratings......................................................................................8
6.6.2
CMP and 6-bit DAC electrical specifications.........33
4.1 Thermal handling ratings...................................................8
6.6.3
12-bit DAC electrical characteristics.....................34
4.2 Moisture handling ratings..................................................9
6.7 Timers................................................................................37
4.3 ESD handling ratings.........................................................9
6.8 Communication interfaces.................................................37
4.4 Voltage and current operating ratings...............................9
6.8.1
SPI switching specifications..................................37
5 General.....................................................................................9
6.8.2
I2C.........................................................................41
5.1 AC electrical characteristics..............................................9
6.8.3
UART....................................................................41
5.2 Nonswitching electrical specifications...............................10
6.9 Human-machine interfaces (HMI)......................................42
5.2.1
Voltage and current operating requirements.........10
6.9.1
TSI electrical specifications...................................42
5.2.2
LVD and POR operating requirements.................11
7 Dimensions...............................................................................42
5.2.3
Voltage and current operating behaviors..............12
7.1 Obtaining package dimensions.........................................42
5.2.4
Power mode transition operating behaviors..........12
8 Pinout........................................................................................42
5.2.5
Power consumption operating behaviors..............13
8.1 KL05 signal multiplexing and pin assignments..................42
5.2.6
Designing with radiated emissions in mind...........20
8.2 KL05 Pinouts.....................................................................44
5.2.7
Capacitance attributes..........................................20
9 Revision History........................................................................48
KL05 Sub-Family Data Sheet Data Sheet, Rev. 3, 11/29/2012.
2
Freescale Semiconductor, Inc.
Ordering parts
1 Ordering parts
1.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable part
numbers for this device, go to www.freescale.com and perform a part number search for
the following device numbers: PKL05 and MKL05
2 Part identification
2.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
2.2 Format
Part numbers for this device have the following format:
Q KL## A FFF R T PP CC N
2.3 Fields
This table lists the possible values for each field in the part number (not all combinations
are valid):
Field
Description
Values
Q
Qualification status
• M = Fully qualified, general market flow
• P = Prequalification
KL##
Kinetis family
• KL05
A
Key attribute
• Z = Cortex-M0+
FFF
Program flash memory size
• 8 = 8 KB
• 16 = 16 KB
• 32 = 32 KB
R
Silicon revision
• (Blank) = Main
• A = Revision after main
Table continues on the next page...
KL05 Sub-Family Data Sheet Data Sheet, Rev. 3, 11/29/2012.
Freescale Semiconductor, Inc.
3
Terminology and guidelines
Field
Description
Values
T
Temperature range (°C)
• V = –40 to 105
PP
Package identifier
•
•
•
•
CC
Maximum CPU frequency (MHz)
• 4 = 48 MHz
N
Packaging type
• R = Tape and reel
• (Blank) = Trays
FK = 24 QFN (4 mm x 4 mm)
LC = 32 LQFP (7 mm x 7 mm)
FM = 32 QFN (5 mm x 5 mm)
LF = 48 LQFP (7 mm x 7 mm)
2.4 Example
This is an example part number:
MKL05Z8VLC4
3 Terminology and guidelines
3.1 Definition: Operating requirement
An operating requirement is a specified value or range of values for a technical
characteristic that you must guarantee during operation to avoid incorrect operation and
possibly decreasing the useful life of the chip.
3.1.1 Example
This is an example of an operating requirement, which you must meet for the
accompanying operating behaviors to be guaranteed:
Symbol
VDD
Description
1.0 V core supply
voltage
Min.
0.9
Max.
Unit
1.1
V
KL05 Sub-Family Data Sheet Data Sheet, Rev. 3, 11/29/2012.
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Freescale Semiconductor, Inc.
Terminology and guidelines
3.2 Definition: Operating behavior
An operating behavior is a specified value or range of values for a technical
characteristic that are guaranteed during operation if you meet the operating requirements
and any other specified conditions.
3.2.1 Example
This is an example of an operating behavior, which is guaranteed if you meet the
accompanying operating requirements:
Symbol
IWP
Description
Min.
Digital I/O weak pullup/ 10
pulldown current
Max.
130
Unit
µA
3.3 Definition: Attribute
An attribute is a specified value or range of values for a technical characteristic that are
guaranteed, regardless of whether you meet the operating requirements.
3.3.1 Example
This is an example of an attribute:
Symbol
CIN_D
Description
Input capacitance:
digital pins
Min.
—
Max.
7
Unit
pF
3.4 Definition: Rating
A rating is a minimum or maximum value of a technical characteristic that, if exceeded,
may cause permanent chip failure:
• Operating ratings apply during operation of the chip.
• Handling ratings apply when the chip is not powered.
KL05 Sub-Family Data Sheet Data Sheet, Rev. 3, 11/29/2012.
Freescale Semiconductor, Inc.
5
Terminology and guidelines
3.4.1 Example
This is an example of an operating rating:
Symbol
VDD
Description
Min.
1.0 V core supply
voltage
Max.
–0.3
Unit
1.2
V
3.5 Result of exceeding a rating
40
Failures in time (ppm)
30
The likelihood of permanent chip failure increases rapidly as
soon as a characteristic begins to exceed one of its operating ratings.
20
10
0
Operating rating
Measured characteristic
3.6 Relationship between ratings and operating requirements
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Fatal range
Degraded operating range
Normal operating range
Degraded operating range
Fatal range
Expected permanent failure
- No permanent failure
- Possible decreased life
- Possible incorrect operation
- No permanent failure
- Correct operation
- No permanent failure
- Possible decreased life
- Possible incorrect operation
Expected permanent failure
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Expected permanent failure
–∞
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Handling (power off)
KL05 Sub-Family Data Sheet Data Sheet, Rev. 3, 11/29/2012.
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Freescale Semiconductor, Inc.
Terminology and guidelines
3.7 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
• Never exceed any of the chip’s ratings.
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal
operation (for example, during power sequencing), limit the duration as much as
possible.
3.8 Definition: Typical value
A typical value is a specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Given the typical manufacturing process, is representative of that characteristic
during operation when you meet the typical-value conditions or other specified
conditions
Typical values are provided as design guidelines and are neither tested nor guaranteed.
3.8.1 Example 1
This is an example of an operating behavior that includes a typical value:
Symbol
IWP
Description
Digital I/O weak
pullup/pulldown
current
Min.
10
Typ.
70
Max.
130
Unit
µA
3.8.2 Example 2
This is an example of a chart that shows typical values for various voltage and
temperature conditions:
KL05 Sub-Family Data Sheet Data Sheet, Rev. 3, 11/29/2012.
Freescale Semiconductor, Inc.
7
Ratings
5000
4500
4000
TJ
IDD_STOP (μA)
3500
150 °C
3000
105 °C
2500
25 °C
2000
–40 °C
1500
1000
500
0
0.90
0.95
1.00
1.05
1.10
VDD (V)
3.9 Typical Value Conditions
Typical values assume you meet the following conditions (or other conditions as
specified):
Symbol
Description
Value
Unit
TA
Ambient temperature
25
°C
VDD
3.3 V supply voltage
3.3
V
4 Ratings
4.1 Thermal handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
TSTG
Storage temperature
–55
150
°C
1
TSDR
Solder temperature, lead-free
—
260
°C
2
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
KL05 Sub-Family Data Sheet Data Sheet, Rev. 3, 11/29/2012.
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Freescale Semiconductor, Inc.
General
4.2 Moisture handling ratings
Symbol
MSL
Description
Moisture sensitivity level
Min.
Max.
Unit
Notes
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
4.3 ESD handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
VHBM
Electrostatic discharge voltage, human body model
-2000
+2000
V
1
VCDM
Electrostatic discharge voltage, charged-device model
-500
+500
V
2
Latch-up current at ambient temperature of 105°C
-100
+100
mA
ILAT
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body
Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
4.4 Voltage and current operating ratings
Symbol
Description
Min.
Max.
Unit
VDD
Digital supply voltage
–0.3
3.8
V
IDD
Digital supply current
—
120
mA
–0.3
VDD + 0.3
V
–0.3
VDD + 0.3
V
–25
25
mA
VDD – 0.3
VDD + 0.3
V
VDIO
VAIO
ID
VDDA
Digital pin input voltage (except RESET)
Analog
pins1and
RESET pin input voltage
Instantaneous maximum current single pin limit (applies to all
port pins)
Analog supply voltage
1. Analog pins are defined as pins that do not have an associated general purpose I/O port function.
5 General
KL05 Sub-Family Data Sheet Data Sheet, Rev. 3, 11/29/2012.
Freescale Semiconductor, Inc.
9
General
5.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
Figure 1. Input signal measurement reference
All digital I/O switching characteristics, unless otherwise specified, assume:
1. output pins
• have CL=30pF loads,
• are slew rate disabled, and
• are normal drive strength
5.2 Nonswitching electrical specifications
5.2.1 Voltage and current operating requirements
Table 1. Voltage and current operating requirements
Symbol
Description
Min.
Max.
Unit
VDD
Supply voltage
1.71
3.6
V
VDDA
Analog supply voltage
1.71
3.6
V
VDD – VDDA VDD-to-VDDA differential voltage
–0.1
0.1
V
VSS – VSSA VSS-to-VSSA differential voltage
–0.1
0.1
V
• 2.7 V ≤ VDD ≤ 3.6 V
0.7 × VDD
—
V
• 1.7 V ≤ VDD ≤ 2.7 V
0.75 × VDD
—
V
• 2.7 V ≤ VDD ≤ 3.6 V
—
0.35 × VDD
V
• 1.7 V ≤ VDD ≤ 2.7 V
—
0.3 × VDD
V
0.06 × VDD
—
V
VIH
VIL
VHYS
Notes
Input high voltage
Input low voltage
Input hysteresis
Table continues on the next page...
KL05 Sub-Family Data Sheet Data Sheet, Rev. 3, 11/29/2012.
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Freescale Semiconductor, Inc.
General
Table 1. Voltage and current operating requirements (continued)
Symbol
IICIO
Description
Min.
Notes
1
mA
• VIN > VDD+0.3V (Positive current injection)
Contiguous pin DC injection current —regional limit,
includes sum of negative injection currents or sum of
positive injection currents of 16 contiguous pins
• Negative current injection
• Positive current injection
VRAM
Unit
I/O pin DC injection current — single pin
• VIN < VSS-0.3V (Negative current injection)
IICcont
Max.
VDD voltage required to retain RAM
-3
—
—
+3
-25
—
—
+25
1.2
—
mA
V
1. All analog pins are internally clamped to VSS and VDD through ESD protection diodes. If VIN is greater than VAIO_MIN
(=VSS-0.3V) and VIN is less than VAIO_MAX(=VDD+0.3V) is observed, then there is no need to provide current limiting
resistors at the pads. If these limits cannot be observed then a current limiting resistor is required. The negative DC
injection current limiting resistor is calculated as R=(VAIO_MIN-VIN)/|IIC|. The positive injection current limiting resistor is
calcualted as R=(VIN-VAIO_MAX)/|IIC|. Select the larger of these two calculated resistances.
5.2.2 LVD and POR operating requirements
Table 2. VDD supply LVD and POR operating requirements
Symbol
Description
Min.
Typ.
Max.
Unit
VPOR
Falling VDD POR detect voltage
0.8
1.1
1.5
V
VLVDH
Falling low-voltage detect threshold — high
range (LVDV=01)
2.48
2.56
2.64
V
Low-voltage warning thresholds — high range
1
VLVW1H
• Level 1 falling (LVWV=00)
2.62
2.70
2.78
V
VLVW2H
• Level 2 falling (LVWV=01)
2.72
2.80
2.88
V
VLVW3H
• Level 3 falling (LVWV=10)
2.82
2.90
2.98
V
VLVW4H
• Level 4 falling (LVWV=11)
2.92
3.00
3.08
V
—
±60
—
mV
1.54
1.60
1.66
V
VHYSH
Low-voltage inhibit reset/recover hysteresis —
high range
VLVDL
Falling low-voltage detect threshold — low range
(LVDV=00)
Low-voltage warning thresholds — low range
1
VLVW1L
• Level 1 falling (LVWV=00)
1.74
1.80
1.86
V
VLVW2L
• Level 2 falling (LVWV=01)
1.84
1.90
1.96
V
VLVW3L
• Level 3 falling (LVWV=10)
1.94
2.00
2.06
V
VLVW4L
• Level 4 falling (LVWV=11)
2.04
2.10
2.16
V
—
±40
—
mV
VHYSL
Low-voltage inhibit reset/recover hysteresis —
low range
Notes
Table continues on the next page...
KL05 Sub-Family Data Sheet Data Sheet, Rev. 3, 11/29/2012.
Freescale Semiconductor, Inc.
11
General
Table 2. VDD supply LVD and POR operating requirements (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
VBG
Bandgap voltage reference
0.97
1.00
1.03
V
tLPO
Internal low power oscillator period — factory
trimmed
900
1000
1100
μs
Notes
1. Rising thresholds are falling threshold + hysteresis voltage
5.2.3 Voltage and current operating behaviors
Table 3. Voltage and current operating behaviors
Symbol
VOH
VOH
Description
Min.
VDD – 0.5
—
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -1.5 mA
VDD – 0.5
—
V
Output high voltage — High drive pad
1
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -18 mA
VDD – 0.5
—
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -6 mA
VDD – 0.5
—
V
—
100
mA
VOL
Output low voltage — Normal drive pad
Notes
1
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -5 mA
Output high current total for all ports
IOLT
Unit
Output high voltage — Normal drive pad
IOHT
VOL
Max.
1
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 5 mA
—
0.5
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 1.5 mA
—
0.5
V
Output low voltage — High drive pad
1
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 18 mA
—
0.5
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 6 mA
—
0.5
V
Output low current total for all ports
—
100
mA
IIN
Input leakage current (per pin) for full temperature
range
—
1
μA
2
IIN
Input leakage current (per pin) at 25 °C
—
0.025
μA
2
IIN
Input leakage current (total all pins) for full temperature
range
—
41
μA
2
IOZ
Hi-Z (off-state) leakage current (per pin)
—
1
μA
RPU
Internal pullup resistors
20
50
kΩ
3
1. PTA12, PTA13, PTB0 and PTB1 I/O have both high drive and normal drive capability selected by the associated
PTx_PCRn[DSE] control bit. All other GPIOs are normal drive only.
2. Measured at VDD = 3.6 V
3. Measured at VDD supply voltage = VDD min and Vinput = VSS
KL05 Sub-Family Data Sheet Data Sheet, Rev. 3, 11/29/2012.
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Freescale Semiconductor, Inc.
General
5.2.4 Power mode transition operating behaviors
All specifications except tPOR and VLLSx→RUN recovery times in the following table
assume this clock configuration:
• CPU and system clocks = 48 MHz
• Bus and flash clock = 24 MHz
• FEI clock mode
Table 4. Power mode transition operating behaviors
Symbol
tPOR
Description
After a POR event, amount of time from the point
VDD reaches 1.8 V to execution of the first
instruction across the operating temperature
range of the chip.
Min.
Typ.
Max.
Unit
—
—
300
μs
—
95
115
μs
—
93
115
μs
—
42
53
μs
—
4
4.6
μs
—
4
4.4
μs
—
4
4.4
μs
Notes
• VLLS0 → RUN
• VLLS1 → RUN
• VLLS3 → RUN
• LLS → RUN
• VLPS → RUN
• STOP → RUN
5.2.5 Power consumption operating behaviors
Table 5. Power consumption operating behaviors
Symbol
IDDA
Description
Analog supply current
Min.
Typ.
Max.
Unit
Notes
—
—
See note
mA
1
IDD_RUNCO Run mode current in compute operation - 48
MHz core / 24 MHz flash / bus clock disabled,
code of while(1) loop executing from flash
—
• at 3.0 V
IDD_RUN
2
4.1
5.2
mA
Run mode current - 48 MHz core / 24 MHz bus
and flash, all peripheral clocks disabled, code of
while(1) loop executing from flash
2
—
• at 3.0 V
4.9
5.6
mA
Table continues on the next page...
KL05 Sub-Family Data Sheet Data Sheet, Rev. 3, 11/29/2012.
Freescale Semiconductor, Inc.
13
General
Table 5. Power consumption operating behaviors (continued)
Symbol
Description
Min.
IDD_RUN
Run mode current - 48 MHz core / 24 MHz bus
and flash, all peripheral clocks enabled, code of
while(1) loop executing from flash
Typ.
Max.
Unit
Notes
2, 3
• at 3.0 V
• at 25 °C
• at 125 °C
IDD_WAIT
IDD_WAIT
Wait mode current - core disabled / 48 MHz
system / 24 MHz bus / flash disabled (flash doze
enabled), all peripheral clocks disabled
• at 3.0 V
Wait mode current - core disabled / 24 MHz
system / 24 MHz bus / flash disabled (flash doze
enabled), all peripheral clocks disabled
• at 3.0 V
IDD_PSTOP2 Stop mode current with partial stop 2 clocking
option - core and system disabled / 10.5 MHz
bus
• at 3.0 V
IDD_VLPRCO Very-low-power run mode current in compute
operation - 4 MHz core / 0.8 MHz flash / bus
clock disabled, code of while(1) loop executing
from flash
• at 3.0 V
IDD_VLPR
IDD_VLPR
IDD_VLPW
Very-low-power run mode current - 4 MHz core /
0.8 MHz bus and flash, all peripheral clocks
disabled, code of while(1) loop executing from
flash
• at 3.0 V
Very-low-power run mode current - 4 MHz core /
0.8 MHz bus and flash, all peripheral clocks
enabled, code of while(1) loop executing from
flash
• at 3.0 V
Very-low-power wait mode current - core
disabled / 4 MHz system / 0.8 MHz bus / flash
disabled (flash doze enabled), all peripheral
clocks disabled
• at 3.0 V
—
5.6
6.8
mA
—
6
7.2
mA
2
—
3.0
4.2
mA
2
—
2.4
3.36
mA
2
—
2.25
3.38
mA
4
—
182
522
μA
4
—
213.33
577.8
μA
3, 4
—
242.8
631.8
μA
—
106.1
399.42
μA
4
Table continues on the next page...
KL05 Sub-Family Data Sheet Data Sheet, Rev. 3, 11/29/2012.
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Freescale Semiconductor, Inc.
General
Table 5. Power consumption operating behaviors (continued)
Symbol
Description
IDD_STOP
Stop mode current
• at 3.0 V
• at 25 °C
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
IDD_VLPS
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
Max.
—
273
441
—
281.2
620
—
301.6
647.64
—
331
710.64
—
406.6
1001.84
—
3.08
16.01
—
5.46
34.73
—
12.08
46.73
—
22.89
77.37
—
53.24
190.28
—
1.7
3.69
—
3
22
—
5.8
28.19
—
10.4
40.29
—
24
65.5
Unit
Notes
μA
μA
Low-leakage stop mode current
• at 3.0 V
• at 25 °C
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
IDD_VLLS3
Typ.
Very-low-power stop mode current
• at 3.0 V
• at 25 °C
IDD_LLS
Min.
Very-low-leakage stop mode 3 current
• at 3.0 V
μA
μA
• at 25 °C
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
IDD_VLLS1
—
1.3
3
—
2.3
11.04
—
4.4
13.68
—
8
20.14
—
18.6
37.82
—
0.78
1.6
—
1.5
13.61
—
3.3
15.59
—
6.3
16.68
—
15.2
26.40
Very-low-leakage stop mode 1 current
• at 3.0 V
• at 25°C
• at 50°C
• at 70°C
• at 85°C
• at 105°C
μA
Table continues on the next page...
KL05 Sub-Family Data Sheet Data Sheet, Rev. 3, 11/29/2012.
Freescale Semiconductor, Inc.
15
General
Table 5. Power consumption operating behaviors (continued)
Symbol
IDD_VLLS0
Description
Min.
Typ.
Max.
Unit
—
449.6
959.2
nA
—
1200
12155.08
—
2900
15323.29
—
5900
16384.55
—
14800
26773.45
Notes
Very-low-leakage stop mode 0 current
(SMC_STOPCTRL[PORPO] = 0)
• at 3.0 V
• at 25 °C
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
IDD_VLLS0
Very-low-leakage stop mode 0 current
(SMC_STOPCTRL[PORPO] = 1)
• at 3.0 V
5
• at 25 °C
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
—
221.7
894.24
—
1000
3784.55
—
2600
12018.39
—
5600
18722.23
—
14400
24665.06
nA
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See
each module's specification for its supply current.
2. MCG configured for FEI mode.
3. Incremental current consumption from peripheral activity is not included.
4. MCG configured for BLPI mode.
5. No brownout
Table 6. Low power mode peripheral adders — typical value
Symbol
Description
Temperature (°C)
Unit
-40
25
50
70
85
105
IIREFSTEN4MHz
4 MHz internal reference clock (IRC)
adder. Measured by entering STOP or
VLPS mode with 4 MHz IRC enabled.
56
56
56
56
56
56
µA
IIREFSTEN32KHz
32 kHz internal reference clock (IRC)
adder. Measured by entering STOP
mode with the 32 kHz IRC enabled.
52
52
52
52
52
52
µA
IEREFSTEN4MHz
External 4 MHz crystal clock adder.
Measured by entering STOP or VLPS
mode with the crystal enabled.
206
228
237
245
251
258
uA
Table continues on the next page...
KL05 Sub-Family Data Sheet Data Sheet, Rev. 3, 11/29/2012.
16
Freescale Semiconductor, Inc.
General
Table 6. Low power mode peripheral adders — typical value (continued)
Symbol
IEREFSTEN32KHz
Description
Temperature (°C)
Unit
-40
25
50
70
85
105
440
490
540
560
570
580
440
490
540
560
570
580
490
490
540
560
570
680
510
560
560
560
610
680
510
560
560
560
610
680
External 32 kHz crystal clock adder by
means of the OSC0_CR[EREFSTEN
and EREFSTEN] bits. Measured by
entering all modes with the crystal
enabled.
VLLS1
VLLS3
LLS
VLPS
STOP
nA
ICMP
CMP peripheral adder measured by
placing the device in VLLS1 mode with
CMP enabled using the 6-bit DAC and a
single external input for compare.
Includes 6-bit DAC power consumption.
22
22
22
22
22
22
µA
IRTC
RTC peripheral adder measured by
placing the device in VLLS1 mode with
external 32 kHz crystal enabled by
means of the RTC_CR[OSCE] bit and
the RTC ALARM set for 1 minute.
Includes ERCLK32K (32 kHz external
crystal) power consumption.
432
357
388
475
532
810
nA
IUART
UART peripheral adder measured by
placing the device in STOP or VLPS
mode with selected clock source waiting
for RX data at 115200 baud rate.
Includes selected clock source power
consumption.
66
66
66
66
66
66
µA
214
237
246
254
260
268
MCGIRCLK (4 MHz internal reference
clock)
OSCERCLK (4 MHz external crystal)
ITPM
TPM peripheral adder measured by
placing the device in STOP or VLPS
mode with selected clock source
configured for output compare
generating 100 Hz clock signal. No load
is placed on the I/O generating the clock
signal. Includes selected clock source
and I/O switching currents.
MCGIRCLK (4 MHz internal reference
clock)
OSCERCLK (4 MHz external crystal)
IBG
Bandgap adder when BGEN bit is set
and device is placed in VLPx, LLS, or
VLLSx mode.
µA
86
86
86
86
86
86
235
256
265
274
280
287
45
45
45
45
45
45
µA
Table continues on the next page...
KL05 Sub-Family Data Sheet Data Sheet, Rev. 3, 11/29/2012.
Freescale Semiconductor, Inc.
17
General
Table 6. Low power mode peripheral adders — typical value (continued)
Symbol
IADC
5.2.5.1
Description
ADC peripheral adder combining the
measured values at VDD and VDDA by
placing the device in STOP or VLPS
mode. ADC is configured for low power
mode using the internal clock and
continuous conversions.
Temperature (°C)
Unit
-40
25
50
70
85
105
366
366
366
366
366
366
µA
Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
•
•
•
•
MCG in FBE for run mode, and BLPE for VLPR mode
No GPIOs toggled
Code execution from flash with cache enabled
For the ALLOFF curve, all peripheral clocks are disabled except FTFA
KL05 Sub-Family Data Sheet Data Sheet, Rev. 3, 11/29/2012.
18
Freescale Semiconductor, Inc.
General
Run Mode Current VS Core Frequency
Temperature = 25, VDD = 3, CACHE = Enable, Code Residence = Flash, Clocking Mode = FBE
7.00E-03
6.00E-03
Current Consumption on VDD (A)
5.00E-03
4.00E-03
All Peripheral CLK Gates
All Off
All On
3.00E-03
2.00E-03
1.00E-03
000.00E+00
'1-1
'1-1
'1-1
'1-1
'1-1
'1-1
'1-1
'1-2
1
2
3
4
6
12
24
48
CLK Ratio
Flash-Core
Core Freq (MHz)
Figure 2. Run mode supply current vs. core frequency
KL05 Sub-Family Data Sheet Data Sheet, Rev. 3, 11/29/2012.
Freescale Semiconductor, Inc.
19
General
VLPR Mode Current VS Core Frequency
Temperature = 25, VDD = 3, CACHE = Enable, Code Residence = Flash, Clocking Mode = BLPE
350.00E-06
300.00E-06
Current Consumption on VDD (A)
250.00E-06
200.00E-06
All Peripheral CLK Gates
All Off
All On
150.00E-06
100.00E-06
50.00E-06
000.00E+00
'1-1
'1-2
1
'1-2
'1-4
2
4
CLK Ratio
Flash-Core
Core Freq (MHz)
Figure 3. VLPR mode current vs. core frequency
5.2.6 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
1. Go to www.freescale.com.
2. Perform a keyword search for “EMC design.”
5.2.7 Capacitance attributes
Table 7. Capacitance attributes
Symbol
Description
Min.
Max.
Unit
CIN_A
Input capacitance: analog pins
—
7
pF
CIN_D
Input capacitance: digital pins
—
7
pF
KL05 Sub-Family Data Sheet Data Sheet, Rev. 3, 11/29/2012.
20
Freescale Semiconductor, Inc.
General
5.3 Switching specifications
5.3.1 Device clock specifications
Symbol
Description
Min.
Max.
Unit
Notes
Normal run mode
fSYS
System and core clock
—
48
MHz
fBUS
Bus clock
—
24
MHz
fFLASH
Flash clock
—
24
MHz
fLPTMR
LPTMR clock
—
24
MHz
VLPR
mode1
fSYS
System and core clock
—
4
MHz
fBUS
Bus clock
—
1
MHz
fFLASH
Flash clock
—
1
MHz
fLPTMR
LPTMR clock
—
24
MHz
fERCLK
External reference clock
—
16
MHz
LPTMR clock
—
24
MHz
—
16
MHz
Oscillator crystal or resonator frequency — high
frequency mode (high range) (MCG_C2[RANGE]=1x)
—
16
MHz
TPM asynchronous clock
—
8
MHz
UART0 asynchronous clock
—
8
MHz
fLPTMR_pin
fLPTMR_ERCL LPTMR external reference clock
K
fosc_hi_2
fTPM
fUART0
1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for any
other module.
5.3.2 General Switching Specifications
These general purpose specifications apply to all signals configured for GPIO, UART,
and I2C signals.
Symbol
Description
Min.
Max.
Unit
Notes
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
1.5
—
Bus clock
cycles
1
External RESET and NMI pin interrupt pulse width —
Asynchronous path
100
—
ns
2
GPIO pin interrupt pulse width — Asynchronous path
16
—
ns
2
Port rise and fall time
3
—
36
ns
KL05 Sub-Family Data Sheet Data Sheet, Rev. 3, 11/29/2012.
Freescale Semiconductor, Inc.
21
General
1. The greater synchronous and asynchronous timing must be met.
2. This is the shrtest pulse that is guaranteed to be recognized.
3. 75 pF load
5.4 Thermal specifications
5.4.1 Thermal operating requirements
Table 8. Thermal operating requirements
Symbol
Description
Min.
Max.
Unit
TJ
Die junction temperature
–40
125
°C
TA
Ambient temperature
–40
105
°C
5.4.2 Thermal attributes
Table 9. Thermal attributes
Board type
Symbol
Single-layer (1S)
RθJA
Four-layer (2s2p)
Description
48
LQFP
32
LQFP
32 QFN
24 QFN
Unit
Notes
Thermal resistance, junction
to ambient (natural
convection)
82
88
97
110
°C/W
1
RθJA
Thermal resistance, junction
to ambient (natural
convection)
58
59
34
42
°C/W
Single-layer (1S)
RθJMA
Thermal resistance, junction
to ambient (200 ft./min. air
speed)
70
74
81
92
°C/W
Four-layer (2s2p)
RθJMA
Thermal resistance, junction
to ambient (200 ft./min. air
speed)
52
52
28
36
°C/W
—
RθJB
Thermal resistance, junction
to board
36
35
13
18
°C/W
2
—
RθJC
Thermal resistance, junction
to case
27
26
2.3
3.7
°C/W
3
—
ΨJT
Thermal characterization
parameter, junction to
package top outside center
(natural convection)
8
8
8
10
°C/W
4
1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions
—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method
Environmental Conditions—Forced Convection (Moving Air).
2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental Conditions
—Junction-to-Board.
KL05 Sub-Family Data Sheet Data Sheet, Rev. 3, 11/29/2012.
22
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate
temperature used for the case temperature. The value includes the thermal resistance of the interface material between
the top of the package and the cold plate.
4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions
—Natural Convection (Still Air).
6 Peripheral operating requirements and behaviors
6.1 Core modules
6.1.1 SWD Electricals
Table 10. SWD full voltage range electricals
Symbol
J1
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
0
25
MHz
1/J1
—
ns
20
—
ns
SWD_CLK frequency of operation
• Serial wire debug
J2
SWD_CLK cycle period
J3
SWD_CLK clock pulse width
• Serial wire debug
J4
SWD_CLK rise and fall times
—
3
ns
J9
SWD_DIO input data setup time to SWD_CLK rise
10
—
ns
J10
SWD_DIO input data hold time after SWD_CLK rise
0
—
ns
J11
SWD_CLK high to SWD_DIO data valid
—
32
ns
J12
SWD_CLK high to SWD_DIO high-Z
5
—
ns
J2
J3
J3
SWD_CLK (input)
J4
J4
Figure 4. Serial wire clock input timing
KL05 Sub-Family Data Sheet Data Sheet, Rev. 3, 11/29/2012.
Freescale Semiconductor, Inc.
23
Peripheral operating requirements and behaviors
SWD_CLK
J9
SWD_DIO
J10
Input data valid
J11
SWD_DIO
Output data valid
J12
SWD_DIO
J11
SWD_DIO
Output data valid
Figure 5. Serial wire data timing
6.2 System modules
There are no specifications necessary for the device's system modules.
6.3 Clock modules
6.3.1 MCG specifications
Table 11. MCG specifications
Symbol
Description
fints_ft
Internal reference frequency (slow clock) —
factory trimmed at nominal VDD and 25 °C
fints_t
Internal reference frequency (slow clock) — user
trimmed
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM and SCFTRIM
Δfdco_t
Total deviation of trimmed average DCO output
frequency over voltage and temperature
Min.
Typ.
Max.
Unit
Notes
—
32.768
—
kHz
31.25
—
39.0625
kHz
—
± 0.3
± 0.6
%fdco
1
—
+0.5/-0.7
±3
%fdco
1, 2
Table continues on the next page...
KL05 Sub-Family Data Sheet Data Sheet, Rev. 3, 11/29/2012.
24
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 11. MCG specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
Δfdco_t
Total deviation of trimmed average DCO output
frequency over fixed voltage and temperature
range of 0 - 70 °C
—
± 0.4
± 1.5
%fdco
1, 2
Internal reference frequency (fast clock) —
factory trimmed at nominal VDD and 25 °C
—
4
—
MHz
Δfintf_ft
Frequency deviation of internal reference clock
(fast clock) over temperature and voltage —
factory trimmed at nominal VDD and 25 °C
—
+1/-2
±3
%fintf_ft
fintf_t
Internal reference frequency (fast clock) — user
trimmed at nominal VDD and 25 °C
3
—
5
MHz
fintf_ft
2
floc_low
Loss of external clock minimum frequency —
RANGE = 00
(3/5) x
fints_t
—
—
kHz
floc_high
Loss of external clock minimum frequency —
RANGE = 01, 10, or 11
(16/5) x
fints_t
—
—
kHz
31.25
—
39.0625
kHz
20
20.97
25
MHz
40
41.94
48
MHz
—
23.99
—
MHz
—
47.97
—
MHz
—
180
—
ps
7
—
—
1
ms
8
FLL
ffll_ref
fdco
FLL reference frequency range
DCO output
frequency range
Low range (DRS = 00)
3, 4
640 × ffll_ref
Mid range (DRS = 01)
1280 × ffll_ref
fdco_t_DMX32 DCO output
frequency
Low range (DRS = 00)
5, 6
732 × ffll_ref
Mid range (DRS = 01)
1464 × ffll_ref
Jcyc_fll
FLL period jitter
• fVCO = 48 MHz
tfll_acquire
FLL target frequency acquisition time
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
2. The deviation is relative to the factory trimmed frequency at nominal VDD and 25 °C, fints_ft.
3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 0.
4. The resulting system clock frequencies must not exceed their maximum specified values. The DCO frequency deviation
(Δfdco_t) over voltage and temperature must be considered.
5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 1.
6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
7. This specification is based on standard deviation (RMS) of period or frequency.
8. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
6.3.2 Oscillator electrical specifications
This section provides the electrical characteristics of the module.
KL05 Sub-Family Data Sheet Data Sheet, Rev. 3, 11/29/2012.
Freescale Semiconductor, Inc.
25
Peripheral operating requirements and behaviors
6.3.2.1
Oscillator DC electrical specifications
Table 12. Oscillator DC electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VDD
Supply voltage
1.71
—
3.6
V
IDDOSC
IDDOSC
Supply current — low-power mode (HGO=0)
Notes
1
• 32 kHz
—
500
—
nA
• 4 MHz
—
200
—
μA
• 8 MHz (RANGE=01)
—
300
—
μA
• 16 MHz
—
950
—
μA
• 24 MHz
—
1.2
—
mA
• 32 MHz
—
1.5
—
mA
Supply current — high gain mode (HGO=1)
1
• 32 kHz
—
25
—
μA
• 4 MHz
—
400
—
μA
• 8 MHz (RANGE=01)
—
500
—
μA
• 16 MHz
—
2.5
—
mA
• 24 MHz
—
3
—
mA
• 32 MHz
—
4
—
mA
Cx
EXTAL load capacitance
—
—
—
2, 3
Cy
XTAL load capacitance
—
—
—
2, 3
RF
Feedback resistor — low-frequency, low-power
mode (HGO=0)
—
—
—
MΩ
Feedback resistor — low-frequency, high-gain
mode (HGO=1)
—
10
—
MΩ
Feedback resistor — high-frequency, low-power
mode (HGO=0)
—
—
—
MΩ
Feedback resistor — high-frequency, high-gain
mode (HGO=1)
—
1
—
MΩ
Series resistor — low-frequency, low-power
mode (HGO=0)
—
—
—
kΩ
Series resistor — low-frequency, high-gain mode
(HGO=1)
—
200
—
kΩ
Series resistor — high-frequency, low-power
mode (HGO=0)
—
—
—
kΩ
—
0
—
kΩ
RS
2, 4
Series resistor — high-frequency, high-gain
mode (HGO=1)
Table continues on the next page...
KL05 Sub-Family Data Sheet Data Sheet, Rev. 3, 11/29/2012.
26
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 12. Oscillator DC electrical specifications (continued)
Symbol
Vpp5
Description
Min.
Typ.
Max.
Unit
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, low-power mode
(HGO=0)
—
0.6
—
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, high-gain mode
(HGO=1)
—
VDD
—
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, low-power mode
(HGO=0)
—
0.6
—
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, high-gain mode
(HGO=1)
—
VDD
—
V
Notes
1. VDD=3.3 V, Temperature =25 °C
2. See crystal or resonator manufacturer's recommendation
3. Cx,Cy can be provided by using the integrated capacitors when the low frequency oscillator (RANGE = 00) is used. For all
other cases external capacitors must be used.
4. When low power mode is selected, RF is integrated and must not be attached externally.
5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any
other devices.
6.3.2.2
Symbol
Oscillator frequency specifications
Table 13. Oscillator frequency specifications
Description
Min.
Typ.
Max.
Unit
fosc_lo
Oscillator crystal or resonator frequency — low
frequency mode (MCG_C2[RANGE]=00)
32
—
40
kHz
fosc_hi_1
Oscillator crystal or resonator frequency — high
frequency mode (low range)
(MCG_C2[RANGE]=01)
3
—
8
MHz
fosc_hi_2
Oscillator crystal or resonator frequency — high
frequency mode (high range)
(MCG_C2[RANGE]=1x)
8
—
32
MHz
fec_extal
Input clock frequency (external clock mode)
—
—
48
MHz
tdc_extal
Input clock duty cycle (external clock mode)
40
50
60
%
Crystal startup time — 32 kHz low-frequency,
low-power mode (HGO=0)
—
—
ms
Crystal startup time — 32 kHz low-frequency,
high-gain mode (HGO=1)
—
—
ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), low-power mode
(HGO=0)
—
0.6
—
ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), high-gain mode
(HGO=1)
—
1
—
ms
tcst
Notes
1, 2
3, 4
1. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL.
2. When transitioning from FBE to FEI mode, restrict the frequency of the input clock so that, when it is divided by FRDIV, it
remains within the limits of the DCO input clock frequency.
KL05 Sub-Family Data Sheet Data Sheet, Rev. 3, 11/29/2012.
Freescale Semiconductor, Inc.
27
Peripheral operating requirements and behaviors
3. Proper PC board layout procedures must be followed to achieve specifications.
4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S register
being set.
NOTE
The 32 kHz oscillator works in low power mode by default and
cannot be moved into high power/gain mode.
6.4 Memories and memory interfaces
6.4.1 Flash electrical specifications
This section describes the electrical characteristics of the flash memory module.
6.4.1.1
Flash timing specifications — program and erase
The following specifications represent the amount of time the internal charge pumps are
active and do not include command overhead.
Table 14. NVM program/erase timing specifications
Symbol
Description
Min.
Typ.
Max.
Unit
thvpgm4
thversscr
Notes
Longword Program high-voltage time
—
7.5
18
μs
Sector Erase high-voltage time
—
13
113
ms
1
1. Maximum time based on expectations at cycling end-of-life.
6.4.1.2
Flash timing specifications — commands
Table 15. Flash command timing specifications
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
trd1sec1k
Read 1s Section execution time (flash sector)
—
—
60
μs
1
tpgmchk
Program Check execution time
—
—
45
μs
1
trdrsrc
Read Resource execution time
—
—
30
μs
1
tpgm4
Program Longword execution time
—
65
145
μs
tersscr
Erase Flash Sector execution time
—
14
114
ms
trd1all
Read 1s All Blocks execution time
—
—
0.5
ms
trdonce
Read Once execution time
—
—
25
μs
Program Once execution time
—
65
—
μs
tersall
Erase All Blocks execution time
—
55
465
ms
2
tvfykey
Verify Backdoor Access Key execution time
—
—
30
μs
1
tpgmonce
2
1
1. Assumes 25 MHz flash clock frequency.
KL05 Sub-Family Data Sheet Data Sheet, Rev. 3, 11/29/2012.
28
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
6.4.1.3
Flash high voltage current behaviors
Table 16. Flash high voltage current behaviors
Symbol
Description
IDD_PGM
IDD_ERS
6.4.1.4
Symbol
Min.
Typ.
Max.
Unit
Average current adder during high voltage
flash programming operation
—
2.5
6.0
mA
Average current adder during high voltage
flash erase operation
—
1.5
4.0
mA
Reliability specifications
Table 17. NVM reliability specifications
Description
Min.
Typ.1
Max.
Unit
Notes
Program Flash
tnvmretp10k Data retention after up to 10 K cycles
5
50
—
years
tnvmretp1k
Data retention after up to 1 K cycles
20
100
—
years
nnvmcycp
Cycling endurance
10 K
50 K
—
cycles
2
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant
25°C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering
Bulletin EB619.
2. Cycling endurance represents number of program/erase cycles at -40°C ≤ Tj ≤ 125°C.
6.5 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
6.6 Analog
6.6.1 ADC electrical specifications
All ADC channels meet the 12-bit single-ended accuracy specifications.
KL05 Sub-Family Data Sheet Data Sheet, Rev. 3, 11/29/2012.
Freescale Semiconductor, Inc.
29
Peripheral operating requirements and behaviors
6.6.1.1
12-bit ADC operating conditions
Table 18. 12-bit ADC operating conditions
Symbol
Description
Conditions
Min.
Typ.1
Max.
Unit
VDDA
Supply voltage
Absolute
1.71
—
3.6
V
ΔVDDA
Supply voltage
Delta to VDD (VDD - VDDA)
-100
0
+100
mV
2
ΔVSSA
Ground voltage
Delta to VSS (VSS - VSSA)
-100
0
+100
mV
2
VREFH
ADC reference
voltage high
1.13
VDDA
VDDA
V
3
VREFL
ADC reference
voltage low
VSSA
VSSA
VSSA
V
3
VADIN
Input voltage
VREFL
—
VREFH
V
CADIN
Input capacitance
—
4
5
pF
RADIN
Input resistance
—
2
5
kΩ
RAS
• 8-/10-/12-bit modes
Analog source
resistance
12-bit modes
fADCK < 4 MHz
—
—
5
kΩ
fADCK
ADC conversion
clock frequency
≤ 12-bit mode
1.0
—
18.0
MHz
Crate
ADC conversion
rate
≤ 12 bit modes
No ADC hardware averaging
Notes
4
5
6
20.000
—
818.330
Ksps
Continuous conversions
enabled, subsequent
conversion time
1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
2. DC potential difference.
3. For packages without dedicated VREFH and VREFL pins, VREFH is internally tied to VDDA, and VREFL is internally tied to
VSSA.
4. This resistance is external to MCU. The analog source resistance must be kept as low as possible to achieve the best
results. The results in this data sheet were derived from a system which has < 8 Ω analog source resistance. The RAS/CAS
time constant should be kept to < 1ns.
5. To use the maximum ADC conversion clock frequency, the ADHSC bit must be set and the ADLPC bit must be clear.
6. For guidelines and examples of conversion rate calculation, download the ADC calculator tool
KL05 Sub-Family Data Sheet Data Sheet, Rev. 3, 11/29/2012.
30
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
Z ADIN
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
leakage
due to
input
protection
Z AS
R AS
ADC SAR
ENGINE
R ADIN
V ADIN
C AS
V AS
R ADIN
INPUT PIN
R ADIN
INPUT PIN
R ADIN
INPUT PIN
C ADIN
Figure 6. ADC input impedance equivalency diagram
6.6.1.2
12-bit ADC electrical characteristics
Table 19. 12-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA)
Conditions1
Symbol
Description
IDDA_ADC
Supply current
fADACK
ADC
asynchronous
clock source
Sample Time
TUE
DNL
INL
EFS
Min.
Typ.2
Max.
Unit
Notes
0.215
—
1.7
mA
3
• ADLPC = 1, ADHSC = 0
1.2
2.4
3.9
MHz
• ADLPC = 1, ADHSC = 1
2.4
4.0
6.1
MHz
tADACK = 1/
fADACK
• ADLPC = 0, ADHSC = 0
3.0
5.2
7.3
MHz
• ADLPC = 0, ADHSC = 1
4.4
6.2
9.5
MHz
LSB4
5
LSB4
5
LSB4
5
LSB4
VADIN =
VDDA
See Reference Manual chapter for sample times
Total unadjusted
error
• 12-bit modes
—
±4
±6.8
• <12-bit modes
—
±1.4
±2.1
Differential nonlinearity
• 12-bit modes
—
±0.7
-1.1 to +1.9
Integral nonlinearity
-0.3 to 0.5
• <12-bit modes
—
±0.2
• 12-bit modes
—
±1.0
-2.7 to +1.9
-0.7 to +0.5
Full-scale error
• <12-bit modes
—
±0.5
• 12-bit modes
—
-4
-5.4
• <12-bit modes
—
-1.4
-1.8
5
Table continues on the next page...
KL05 Sub-Family Data Sheet Data Sheet, Rev. 3, 11/29/2012.
Freescale Semiconductor, Inc.
31
Peripheral operating requirements and behaviors
Table 19. 12-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol
Description
EQ
Quantization
error
EIL
Input leakage
error
Conditions1
• 12-bit modes
Min.
Typ.2
Max.
Unit
—
—
±0.5
LSB4
IIn × RAS
mV
Notes
IIn =
leakage
current
(refer to
the MCU's
voltage
and current
operating
ratings)
VTEMP25
Temp sensor
slope
Across the full temperature
range of the device
—
1.715
—
mV/°C
Temp sensor
voltage
25 °C
—
719
—
mV
1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA
2. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and the ADLPC bit (low power).
For lowest power operation the ADLPC bit must be set, the HSC bit must be clear with 1 MHz ADC conversion clock
speed.
4. 1 LSB = (VREFH - VREFL)/2N
5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11)
Figure 7. Typical ENOB vs. ADC_CLK for 12-bit single-ended mode
KL05 Sub-Family Data Sheet Data Sheet, Rev. 3, 11/29/2012.
32
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
6.6.2 CMP and 6-bit DAC electrical specifications
Table 20. Comparator and 6-bit DAC electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VDD
Supply voltage
1.71
—
3.6
V
IDDHS
Supply current, high-speed mode (EN = 1, PMODE =
1)
—
—
200
μA
IDDLS
Supply current, low-speed mode (EN = 1, PMODE = 0)
—
—
20
μA
VAIN
Analog input voltage
VSS
—
VDD
V
VAIO
Analog input offset voltage
—
—
20
mV
• CR0[HYSTCTR] = 00
—
5
—
mV
• CR0[HYSTCTR] = 01
—
10
—
mV
• CR0[HYSTCTR] = 10
—
20
—
mV
• CR0[HYSTCTR] = 11
—
30
—
mV
VDD – 0.5
—
—
V
VH
Analog comparator
VCMPOh
Output high
VCMPOl
hysteresis1
Output low
—
—
0.5
V
tDHS
Propagation delay, high-speed mode (EN = 1, PMODE
= 1)
20
50
200
ns
tDLS
Propagation delay, low-speed mode (EN = 1, PMODE
= 0)
80
250
600
ns
Analog comparator initialization delay2
—
—
40
μs
IDAC6b
—
7
—
μA
INL
6-bit DAC current adder (enabled)
6-bit DAC integral non-linearity
–0.5
—
0.5
LSB3
DNL
6-bit DAC differential non-linearity
–0.3
—
0.3
LSB
1. Typical hysteresis is measured with input voltage range limited to 0.7 to VDD – 0.7 V.
2. Comparator initialization delay is defined as the time between software writes to change control inputs (writes to DACEN,
VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level.
3. 1 LSB = Vreference/64
KL05 Sub-Family Data Sheet Data Sheet, Rev. 3, 11/29/2012.
Freescale Semiconductor, Inc.
33
Peripheral operating requirements and behaviors
CMP Hysteresis vs Vinn
90.00E-03
80.00E-03
70.00E-03
CMP Hysteresis (V)
60.00E-03
HYSTCTR
Setting
50.00E-03
0
1
40.00E-03
2
3
30.00E-03
20.00E-03
10.00E-03
000.00E+00
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vinn (V)
Figure 8. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)
CMP Hysteresis vs Vinn
180.00E-03
160.00E-03
140.00E-03
CMP Hysteresis (V)
120.00E-03
HYSTCTR
Setting
100.00E-03
0
1
80.00E-03
2
3
60.00E-03
40.00E-03
20.00E-03
000.00E+00
0.1
-20.00E-03
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vinn (V)
Figure 9. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)
6.6.3 12-bit DAC electrical characteristics
6.6.3.1
Symbol
12-bit DAC operating requirements
Table 21. 12-bit DAC operating requirements
Desciption
Min.
VDDA
Supply voltage
VDACR
Reference voltage
1.13
Max.
Unit
3.6
V
3.6
V
TA
Temperature
Operating temperature
range of the device
CL
Output load capacitance
—
100
pF
IL
Output load current
—
1
mA
Notes
1
°C
2
1. The DAC reference can be selected to be VDDA or the voltage output of the VREF module (VREF_OUT)
2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC
KL05 Sub-Family Data Sheet Data Sheet, Rev. 3, 11/29/2012.
34
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
6.6.3.2
Symbol
12-bit DAC operating behaviors
Table 22. 12-bit DAC operating behaviors
Description
IDDA_DACL Supply current — low-power mode
Min.
Typ.
Max.
Unit
—
—
250
μA
—
—
900
μA
Notes
P
IDDA_DACH Supply current — high-speed mode
P
tDACLP
Full-scale settling time (0x080 to 0xF7F) —
low-power mode
—
100
200
μs
1
tDACHP
Full-scale settling time (0x080 to 0xF7F) —
high-power mode
—
15
30
μs
1
—
0.7
1
μs
1
—
—
100
mV
tCCDACLP Code-to-code settling time (0xBF8 to 0xC08)
— low-power mode and high-speed mode
Vdacoutl
DAC output voltage range low — high-speed
mode, no load, DAC set to 0x000
Vdacouth
DAC output voltage range high — highspeed mode, no load, DAC set to 0xFFF
VDACR
−100
—
VDACR
mV
INL
Integral non-linearity error — high speed
mode
—
—
±8
LSB
2
DNL
Differential non-linearity error — VDACR > 2
V
—
—
±1
LSB
3
DNL
Differential non-linearity error — VDACR =
VREF_OUT
—
—
±1
LSB
4
—
±0.4
±0.8
%FSR
5
Gain error
—
±0.1
±0.6
%FSR
5
Power supply rejection ratio, VDDA ≥ 2.4 V
60
—
90
dB
TCO
Temperature coefficient offset voltage
—
3.7
—
μV/C
TGE
Temperature coefficient gain error
—
0.000421
—
%FSR/C
Rop
Output resistance load = 3 kΩ
—
—
250
SR
Slew rate -80h→ F7Fh→ 80h
VOFFSET Offset error
EG
PSRR
BW
1.
2.
3.
4.
5.
6.
6
Ω
V/μs
• High power (SPHP)
1.2
1.7
—
• Low power (SPLP)
0.05
0.12
—
3dB bandwidth
kHz
• High power (SPHP)
550
—
—
• Low power (SPLP)
40
—
—
Settling within ±1 LSB
The INL is measured for 0 + 100 mV to VDACR −100 mV
The DNL is measured for 0 + 100 mV to VDACR −100 mV
The DNL is measured for 0 + 100 mV to VDACR −100 mV with VDDA > 2.4 V
Calculated by a best fit curve from VSS + 100 mV to VDACR − 100 mV
VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC set to
0x800, temperature range is across the full range of the device
KL05 Sub-Family Data Sheet Data Sheet, Rev. 3, 11/29/2012.
Freescale Semiconductor, Inc.
35
Peripheral operating requirements and behaviors
Figure 10. Typical INL error vs. digital code
KL05 Sub-Family Data Sheet Data Sheet, Rev. 3, 11/29/2012.
36
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Figure 11. Offset at half scale vs. temperature
6.7 Timers
See General switching specifications.
6.8 Communication interfaces
6.8.1 SPI switching specifications
The Serial Peripheral Interface (SPI) provides a synchronous serial bus with master and
slave operations. Many of the transfer attributes are programmable. The following tables
provide timing characteristics for classic SPI timing modes. See the SPI chapter of the
chip's Reference Manual for information about the modified transfer formats used for
communicating with slower peripheral devices.
KL05 Sub-Family Data Sheet Data Sheet, Rev. 3, 11/29/2012.
Freescale Semiconductor, Inc.
37
Peripheral operating requirements and behaviors
All timing is shown with respect to 20% VDD and 80% VDD thresholds, unless noted, as
well as input signal transitions of 3 ns and a 30 pF maximum load on all SPI pins.
Table 23. SPI master mode timing on slew rate disabled pads
Num.
Symbol
Description
Max.
Unit
Note
fperiph/2048
fperiph/2
Hz
1
2 x tperiph
2048 x
tperiph
ns
2
1
fop
2
tSPSCK
3
tLead
Enable lead time
1/2
—
tSPSCK
—
4
tLag
Enable lag time
1/2
—
tSPSCK
—
5
tWSPSCK
tperiph - 30
1024 x
tperiph
ns
—
6
tSU
Data setup time (inputs)
16
—
ns
—
7
tHI
Data hold time (inputs)
0
—
ns
—
8
tv
Data valid (after SPSCK edge)
—
10
ns
—
9
tHO
Data hold time (outputs)
0
—
ns
—
10
tRI
Rise time input
—
tperiph - 25
ns
—
tFI
Fall time input
tRO
Rise time output
—
25
ns
—
tFO
Fall time output
11
Frequency of operation
Min.
SPSCK period
Clock (SPSCK) high or low time
1. For SPI0 fperiph is the bus clock (fBUS).
2. tperiph = 1/fperiph
Table 24. SPI master mode timing on slew rate enabled pads
Num.
Symbol
1
fop
2
tSPSCK
3
tLead
4
tLag
5
tWSPSCK
6
tSU
7
tHI
8
tv
9
10
11
Description
Min.
Max.
Unit
Note
fperiph/2048
fperiph/2
Hz
1
2 x tperiph
2048 x
tperiph
ns
2
Enable lead time
1/2
—
tSPSCK
—
Enable lag time
1/2
—
tSPSCK
—
tperiph - 30
1024 x
tperiph
ns
—
Data setup time (inputs)
96
—
ns
—
Data hold time (inputs)
0
—
ns
—
Data valid (after SPSCK edge)
—
52
ns
—
tHO
Data hold time (outputs)
0
—
ns
—
tRI
Rise time input
—
tperiph - 25
ns
—
tFI
Fall time input
tRO
Rise time output
—
36
ns
—
tFO
Fall time output
Frequency of operation
SPSCK period
Clock (SPSCK) high or low time
1. For SPI0 fperiph is the bus clock (fBUS).
2. tperiph = 1/fperiph
KL05 Sub-Family Data Sheet Data Sheet, Rev. 3, 11/29/2012.
38
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
SS1
(OUTPUT)
3
2
SPSCK
(CPOL = 0)
(OUTPUT)
10
11
10
11
4
5
5
SPSCK
(CPOL = 1)
(OUTPUT)
6
7
MISO
(INPUT)
MSB IN2
BIT 6 . . . 1
LSB IN
8
MOSI
(OUTPUT)
MSB OUT2
9
BIT 6 . . . 1
LSB OUT
1. If configured as an output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 12. SPI master mode timing (CPHA = 0)
SS1
(OUTPUT)
2
3
SPSCK
(CPOL = 0)
(OUTPUT)
5
SPSCK
(CPOL = 1)
(OUTPUT)
5
6
MISO
(INPUT)
10
11
10
11
4
7
MSB IN2
BIT 6 . . . 1
8
MOSI
2
(OUTPUT)PORT DATA MASTER MSB OUT
LSB IN
9
BIT 6 . . . 1
MASTER LSB OUT
PORT DATA
1.If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 13. SPI master mode timing (CPHA = 1)
Table 25. SPI slave mode timing on slew rate disabled pads
Num.
Symbol
1
fop
2
tSPSCK
3
tLead
4
tLag
5
tWSPSCK
Description
Frequency of operation
Min.
Max.
Unit
Note
0
fperiph/4
Hz
1
4 x tperiph
—
ns
2
Enable lead time
1
—
tperiph
—
Enable lag time
1
—
tperiph
—
tperiph - 30
—
ns
—
SPSCK period
Clock (SPSCK) high or low time
Table continues on the next page...
KL05 Sub-Family Data Sheet Data Sheet, Rev. 3, 11/29/2012.
Freescale Semiconductor, Inc.
39
Peripheral operating requirements and behaviors
Table 25. SPI slave mode timing on slew rate disabled pads (continued)
1.
2.
3.
4.
Num.
Symbol
6
tSU
7
Description
Min.
Max.
Unit
Note
Data setup time (inputs)
2
—
ns
—
tHI
Data hold time (inputs)
7
—
ns
—
8
ta
Slave access time
—
tperiph
ns
3
9
tdis
Slave MISO disable time
—
tperiph
ns
4
10
tv
Data valid (after SPSCK edge)
—
22
ns
—
11
tHO
Data hold time (outputs)
0
—
ns
—
12
tRI
Rise time input
—
tperiph - 25
ns
—
tFI
Fall time input
13
tRO
Rise time output
—
25
ns
—
tFO
Fall time output
For SPI0 fperiph is the bus clock (fBUS).
tperiph = 1/fperiph
Time to data active from high-impedance state
Hold time to high-impedance state
Table 26. SPI slave mode timing on slew rate enabled pads
Num.
Symbol
1
fop
2
tSPSCK
3
tLead
Enable lead time
4
tLag
Enable lag time
5
tWSPSCK
6
tSU
7
Frequency of operation
SPSCK period
Min.
Max.
Unit
Note
0
fperiph/4
Hz
1
4 x tperiph
—
ns
2
1
—
tperiph
—
1
—
tperiph
—
tperiph - 30
—
ns
—
Data setup time (inputs)
2
—
ns
—
tHI
Data hold time (inputs)
7
—
ns
—
8
ta
Slave access time
—
tperiph
ns
3
9
tdis
Slave MISO disable time
—
tperiph
ns
4
10
tv
Data valid (after SPSCK edge)
—
122
ns
—
11
tHO
Data hold time (outputs)
0
—
ns
—
12
tRI
Rise time input
—
tperiph - 25
ns
—
tFI
Fall time input
tRO
Rise time output
—
36
ns
—
tFO
Fall time output
13
1.
2.
3.
4.
Description
Clock (SPSCK) high or low time
For SPI0 fperiph is the bus clock (fBUS).
tperiph = 1/fperiph
Time to data active from high-impedance state
Hold time to high-impedance state
KL05 Sub-Family Data Sheet Data Sheet, Rev. 3, 11/29/2012.
40
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
SS
(INPUT)
2
SPSCK
(CPOL = 0)
(INPUT)
5
3
SPSCK
(CPOL = 1)
(INPUT)
5
13 4
12
13
9
8
MISO
(OUTPUT)
12
10
see
note
SLAVE MSB
6
11
11
BIT 6 . . . 1
SLAVE LSB OUT
SEE
NOTE
7
MOSI
(INPUT)
BIT 6 . . . 1
MSB IN
LSB IN
NOTE: Not defined
Figure 14. SPI slave mode timing (CPHA = 0)
SS
(INPUT)
4
2
3
SPSCK
(CPOL = 0)
(INPUT)
5
SPSCK
(CPOL = 1)
(INPUT)
5
see
note
SLAVE
8
MSB OUT
6
MOSI
(INPUT)
13
12
13
9
11
10
MISO
(OUTPUT)
12
BIT 6 . . . 1
SLAVE LSB OUT
7
MSB IN
BIT 6 . . . 1
LSB IN
NOTE: Not defined
Figure 15. SPI slave mode timing (CPHA = 1)
6.8.2 I2C
See General switching specifications.
6.8.3 UART
See General switching specifications.
KL05 Sub-Family Data Sheet Data Sheet, Rev. 3, 11/29/2012.
Freescale Semiconductor, Inc.
41
Dimensions
6.9 Human-machine interfaces (HMI)
6.9.1 TSI electrical specifications
Table 27. TSI electrical specifications
Symbol
Description
Min.
Type
Max
Unit
TSI_RUNF
Fixed power consumption in run mode
—
100
—
µA
TSI_RUNV
Variable power consumption in run mode
(depends on oscillator's current selection)
1.0
—
128
µA
TSI_EN
Power consumption in enable mode
—
100
—
µA
TSI_DIS
Power consumption in disable mode
—
1.2
—
µA
TSI_TEN
TSI analog enable time
—
66
—
µs
TSI_CREF
TSI reference capacitor
—
1.0
—
pF
TSI_DVOLT
Voltage variation of VP & VM around nominal
values
0.19
—
1.03
V
7 Dimensions
7.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to www.freescale.com and perform a keyword search for
the drawing’s document number:
If you want the drawing for this package
Then use this document number
24-pin QFN
98ASA00474D
32-pin QFN
98ASA00473D
32-pin LQFP
98ASH70029A
48-pin LQFP
98ASH00962A
8 Pinout
KL05 Sub-Family Data Sheet Data Sheet, Rev. 3, 11/29/2012.
42
Freescale Semiconductor, Inc.
Pinout
8.1 KL05 signal multiplexing and pin assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
48
LQFP
32
QFN
32
LQFP
24
QFN
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
1
1
1
1
PTB6/
IRQ_2/
LPTMR0_ALT3
DISABLED
DISABLED
PTB6/
IRQ_2/
LPTMR0_ALT3
TPM0_CH3
2
2
2
2
PTB7/
IRQ_3
DISABLED
DISABLED
PTB7/
IRQ_3
TPM0_CH2
3
—
—
—
PTA14
DISABLED
DISABLED
PTA14
TPM_CLKIN0
4
—
—
—
PTA15
DISABLED
DISABLED
PTA15
CLKOUT
5
3
3
3
VDD
VDD
VDD
6
4
4
3
VREFH
VREFH
VREFH
7
5
5
4
VREFL
VREFL
VREFL
8
6
6
4
VSS
VSS
VSS
9
7
7
5
PTA3
EXTAL0
EXTAL0
PTA3
I2C0_SCL
I2C0_SDA
10
8
8
6
PTA4/
LLWU_P0
XTAL0
XTAL0
PTA4/
LLWU_P0
I2C0_SDA
I2C0_SCL
11
—
—
—
VSS
VSS
VSS
12
—
—
—
PTB18
DISABLED
DISABLED
PTB18
13
—
—
—
PTB19
DISABLED
DISABLED
PTB19
14
9
9
7
PTA5/
LLWU_P1/
RTC_CLK_IN
DISABLED
DISABLED
PTA5/
LLWU_P1/
RTC_CLK_IN
TPM0_CH5
SPI0_SS_b
15
10
10
8
PTA6/
LLWU_P2
DISABLED
DISABLED
PTA6/
LLWU_P2
TPM0_CH4
SPI0_MISO
16
11
11
—
PTB8
ADC0_SE11
ADC0_SE11
PTB8
TPM0_CH3
17
12
12
—
PTB9
ADC0_SE10
ADC0_SE10
PTB9
TPM0_CH2
18
—
—
—
PTA16/
IRQ_4
DISABLED
DISABLED
PTA16/
IRQ_4
19
—
—
—
PTA17/
IRQ_5
DISABLED
DISABLED
PTA17/
IRQ_5
20
—
—
—
PTA18/
IRQ_6
DISABLED
DISABLED
PTA18/
IRQ_6
21
13
13
9
PTB10
ADC0_SE9/
TSI0_IN7
ADC0_SE9/
TSI0_IN7
PTB10
TPM0_CH1
22
14
14
10
PTB11
ADC0_SE8/
TSI0_IN6
ADC0_SE8/
TSI0_IN6
PTB11
TPM0_CH0
23
15
15
11
PTA7/
IRQ_7/
LLWU_P3
ADC0_SE7/
TSI0_IN5
ADC0_SE7/
TSI0_IN5
PTA7/
IRQ_7/
LLWU_P3
SPI0_MISO
SPI0_MOSI
24
16
16
12
PTB0/
IRQ_8/
LLWU_P4
ADC0_SE6/
TSI0_IN4
ADC0_SE6/
TSI0_IN4
PTB0/
IRQ_8/
LLWU_P4
EXTRG_IN
SPI0_SCK
TPM_CLKIN1
KL05 Sub-Family Data Sheet Data Sheet, Rev. 3, 11/29/2012.
Freescale Semiconductor, Inc.
43
Pinout
48
LQFP
32
QFN
32
LQFP
24
QFN
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
25
17
17
13
PTB1/
IRQ_9
ADC0_SE5/
TSI0_IN3/
DAC0_OUT/
CMP0_IN3
ADC0_SE5/
TSI0_IN3/
DAC0_OUT/
CMP0_IN3
PTB1/
IRQ_9
UART0_TX
UART0_RX
26
18
18
14
PTB2/
IRQ_10/
LLWU_P5
ADC0_SE4/
TSI0_IN2
ADC0_SE4/
TSI0_IN2
PTB2/
IRQ_10/
LLWU_P5
UART0_RX
UART0_TX
27
19
19
15
PTA8
ADC0_SE3/
TSI0_IN1
ADC0_SE3/
TSI0_IN1
PTA8
28
20
20
16
PTA9
ADC0_SE2/
TSI0_IN0
ADC0_SE2/
TSI0_IN0
PTA9
29
—
—
—
PTB20
DISABLED
DISABLED
PTB20
30
—
—
—
VSS
VSS
VSS
31
—
—
—
VDD
VDD
VDD
32
—
—
—
PTB14/
IRQ_11
DISABLED
DISABLED
PTB14/
IRQ_11
33
21
21
—
PTA10/
IRQ_12
DISABLED
TSI0_IN11
PTA10/
IRQ_12
34
22
22
—
PTA11/
IRQ_13
DISABLED
TSI0_IN10
PTA11/
IRQ_13
35
23
23
17
PTB3/
IRQ_14
DISABLED
DISABLED
PTB3/
IRQ_14
I2C0_SCL
UART0_TX
36
24
24
18
PTB4/
IRQ_15/
LLWU_P6
DISABLED
DISABLED
PTB4/
IRQ_15/
LLWU_P6
I2C0_SDA
UART0_RX
37
25
25
19
PTB5/
IRQ_16
NMI_b
ADC0_SE1/
CMP0_IN1
PTB5/
IRQ_16
TPM1_CH1
NMI_b
38
26
26
20
PTA12/
IRQ_17/
LPTMR0_ALT2
ADC0_SE0/
CMP0_IN0
ADC0_SE0/
CMP0_IN0
PTA12/
IRQ_17/
LPTMR0_ALT2
TPM1_CH0
TPM_CLKIN0
39
27
27
—
PTA13
TSI0_IN9
TSI0_IN9
PTA13
40
28
28
—
PTB12
TSI0_IN8
TSI0_IN8
PTB12
41
—
—
—
PTA19
DISABLED
DISABLED
PTA19
42
—
—
—
PTB15
DISABLED
DISABLED
PTB15
SPI0_MOSI
SPI0_MISO
43
—
—
—
PTB16
DISABLED
DISABLED
PTB16
SPI0_MISO
SPI0_MOSI
44
—
—
—
PTB17
DISABLED
DISABLED
PTB17
TPM_CLKIN1
SPI0_SCK
45
29
29
21
PTB13
ADC0_SE13
ADC0_SE13
PTB13
TPM1_CH1
RTC_CLKOUT
46
30
30
22
PTA0/
IRQ_0/
LLWU_P7
SWD_CLK
ADC0_SE12/
CMP0_IN2
PTA0/
IRQ_0/
LLWU_P7
TPM1_CH0
SWD_CLK
47
31
31
23
PTA1/
IRQ_1/
LPTMR0_ALT1
RESET_b
DISABLED
PTA1/
IRQ_1/
LPTMR0_ALT1
TPM_CLKIN0
RESET_b
48
32
32
24
PTA2
SWD_DIO
DISABLED
PTA2
CMP0_OUT
SWD_DIO
EXTRG_IN
SPI0_SS_b
KL05 Sub-Family Data Sheet Data Sheet, Rev. 3, 11/29/2012.
44
Freescale Semiconductor, Inc.
Pinout
8.2 KL05 Pinouts
PTA2
PTA1/IRQ_1/LPTMR0_ALT1
PTA0/IRQ_0/LLWU_P7
PTB13
PTB17
PTB16
PTB15
PTA19
PTB12
PTA13
PTA12/IRQ_17/LPTMR0_ALT2
PTB5/IRQ_16
48
47
46
45
44
43
42
41
40
39
38
37
The following figures show the pinout diagrams for the devices supported by this
document. Many signals may be multiplexed onto a single pin. To determine what signals
can be used on which pin, see the previous section.
VREFL
7
30
VSS
VSS
8
29
PTB20
PTA3
9
28
PTA9
PTA4/LLWU_P0
10
27
PTA8
VSS
11
26
PTB2/IRQ_10/LLWU_P5
PTB18
12
25
PTB1/IRQ_9
24
VDD
PTB0/IRQ_8/LLWU_P4
31
23
6
PTA7/IRQ_7/LLWU_P3
VREFH
22
PTB14/IRQ_11
PTB11
32
21
5
PTB10
VDD
20
PTA10/IRQ_12
PTA18/IRQ_6
33
19
4
PTA17/IRQ_5
PTA15
18
PTA11/IRQ_13
PTA16/IRQ_4
34
17
3
PTB9
PTA14
16
PTB3/IRQ_14
PTB8
35
15
2
PTA6/LLWU_P2
PTB7/IRQ_3
14
PTB4/IRQ_15/LLWU_P6
PTA5/LLWU_P1/RTC_CLK_IN
36
13
1
PTB19
PTB6/IRQ_2/LPTMR0_ALT3
Figure 16. KL05 48-pin LQFP pinout diagram
KL05 Sub-Family Data Sheet Data Sheet, Rev. 3, 11/29/2012.
Freescale Semiconductor, Inc.
45
PTA2
PTA1/IRQ_1/LPTMR0_ALT1
PTA0/IRQ_0/LLWU_P7
PTB13
PTB12
PTA13
PTA12/IRQ_17/LPTMR0_ALT2
PTB5/IRQ_16
32
31
30
29
28
27
26
25
Pinout
21
PTA10/IRQ_12
VREFL
5
20
PTA9
VSS
6
19
PTA8
PTA3
7
18
PTB2/IRQ_10/LLWU_P5
PTA4/LLWU_P0
8
17
PTB1/IRQ_9
PTA6/LLWU_P2
PTA5/LLWU_P1/RTC_CLK_IN
16
4
PTB0/IRQ_8/LLWU_P4
VREFH
15
PTA11/IRQ_13
PTA7/IRQ_7/LLWU_P3
22
14
3
PTB11
VDD
13
PTB3/IRQ_14
PTB10
23
12
2
PTB9
PTB7/IRQ_3
11
PTB4/IRQ_15/LLWU_P6
PTB8
24
10
1
9
PTB6/IRQ_2/LPTMR0_ALT3
Figure 17. KL05 32-pin LQFP pinout diagram
KL05 Sub-Family Data Sheet Data Sheet, Rev. 3, 11/29/2012.
46
Freescale Semiconductor, Inc.
PTA2
PTA1/IRQ_1/LPTMR0_ALT1
PTA0/IRQ_0/LLWU_P7
PTB13
PTB12
PTA13
PTA12/IRQ_17/LPTMR0_ALT2
PTB5/IRQ_16
32
31
30
29
28
27
26
25
Pinout
21
PTA10/IRQ_12
VREFL
5
20
PTA9
VSS
6
19
PTA8
PTA3
7
18
PTB2/IRQ_10/LLWU_P5
PTA4/LLWU_P0
8
17
PTB1/IRQ_9
PTA6/LLWU_P2
PTA5/LLWU_P1/RTC_CLK_IN
16
4
PTB0/IRQ_8/LLWU_P4
VREFH
15
PTA11/IRQ_13
PTA7/IRQ_7/LLWU_P3
22
14
3
PTB11
VDD
13
PTB3/IRQ_14
PTB10
23
12
2
PTB9
PTB7/IRQ_3
11
PTB4/IRQ_15/LLWU_P6
PTB8
24
10
1
9
PTB6/IRQ_2/LPTMR0_ALT3
Figure 18. KL05 32-pin QFN pinout diagram
KL05 Sub-Family Data Sheet Data Sheet, Rev. 3, 11/29/2012.
Freescale Semiconductor, Inc.
47
PTA2
PTA1/IRQ_1/LPTMR0_ALT1
PTA0/IRQ_0/LLWU_P7
PTB13
PTA12/IRQ_17/LPTMR0_ALT2
PTB5/IRQ_16
24
23
22
21
20
19
Revision History
3
16
PTA9
VREFL VSS
4
15
PTA8
PTA3
5
14
PTB2/IRQ_10/LLWU_P5
PTA4/LLWU_P0
6
13
PTB1/IRQ_9
PTB10
PTA6/LLWU_P2
PTA5/LLWU_P1/RTC_CLK_IN
12
VDD VREFH
PTB0/IRQ_8/LLWU_P4
PTB3/IRQ_14
11
17
PTA7/IRQ_7/LLWU_P3
2
10
PTB7/IRQ_3
PTB11
PTB4/IRQ_15/LLWU_P6
9
18
8
1
7
PTB6/IRQ_2/LPTMR0_ALT3
Figure 19. KL05 24-pin QFN pinout diagram
9 Revision History
The following table provides a revision history for this document.
Table 28. Revision History
Rev. No.
Date
Substantial Changes
1
7/2012
Initial NDA release.
2
9/2012
Initial public release.
3
11/2012
Completed all the TBDs.
KL05 Sub-Family Data Sheet Data Sheet, Rev. 3, 11/29/2012.
48
Freescale Semiconductor, Inc.
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Rev. 3, 11/29/2012
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