IDT IDT723656L12PF Cmos triple bus syncfifotm with bus-matching Datasheet

CMOS TRIPLE BUS SyncFIFOTM WITH BUS-MATCHING
2,048 x 36 x 2
4,096 x 36 x 2
8,192 x 36 x 2
FEATURES
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Memory storage capacity:
IDT723656 – 2,048 x 36 x 2
IDT723666 – 4,096 x 36 x 2
IDT723676 – 8,192 x 36 x 2
Clock frequencies up to 83 MHz (8ns access time)
Two independent FIFOs buffer data between one bidirectional
36-bit port and two unidirectional 18-bit ports (Port C receives
and Port B transmits)
18-bit (word) and 9-bit (byte) bus sizing of 18 bits (word) on
Ports B and C
Select IDT Standard timing (using EFA , EFB , FFA , and FFC flag
functions) or First Word Fall Through Timing (using ORA, ORB,
IRA, and IRC flag functions)
Programmable Almost-Empty and Almost-Full flags; each has
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IDT723656
IDT723666
IDT723676
five default offsets (8, 16, 64, 256 and 1024)
Serial or parallel programming of partial flags
Big- or Little-Endian format for word and byte bus sizes
Loopback mode on Port A
Retransmit Capability
Master Reset clears data and configures FIFO, Partial Reset
clears data but retains configuration settings
Mailbox bypass registers for each FIFO
Free-running CLKA, CLKB and CLKC may be asynchronous or
coincident (simultaneous reading and writing of data on a single
clock edge is permitted)
Auto power down minimizes power dissipation
Available in a space-saving 128-pin Thin Quad Flatpack (TQFP)
Pin compatible to the lower density parts, IDT723626/3636/3646
Industrial temperature range (–40°° C to +85°°C) is available
FUNCTIONAL BLOCK DIAGRAM
MBF1
MRS1
PRS1
RAM ARRAY
36
2,048 x 36
4,096 x 36
8,192 x 36
36
18
B0-B17
Output
Register
Port-A
Control
Logic
Output BusMatching
Mail 1
Register
Input
Register
CLKA
CSA
W/RA
ENA
MBA
LOOP
Port-B
Control
Logic
FIFO1,
Mail1
Reset
Logic
Read
Pointer
Write
Pointer
CLKB
RENB
CSB
MBB
SIZEB
36
FFA/IRA
AFA
Status Flag
Logic
FIFO1
FS2
FS0/SD
FS1/SEN
A0-A35
Programmable Flag
Offset Registers
FIFO2
36
Write
Pointer
RAM ARRAY
2,048 x 36
4,096 x 36
8,192 x 36
36
FIFO2,
Mail2
Reset
Logic
Input
Register
FIFO1 and
FIFO2
Retransmit
Logic
BE
FWFT
FFC/IRC
AFC
Input BusMatching
Read
Pointer
Output
Register
RT2
Timing
Mode
Status Flag
Logic
36
RTM
Common
Port
Control
Logic
(B and C)
13
EFA/ORA
AEA
RT1
EFB/ORB
AEB
Mail 2
Register
MBF2
18
Port-C
Control
Logic
MRS2
PRS2
C0-C17
CLKC
WENC
MBC
SIZEC
5611 drw01
IDT and the IDT logo are registered trademark of Integrated Device Technology, Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc.
NOVEMBER 2003
COMMERCIAL TEMPERATURE RANGE
1
 2003 Integrated Device Technology, Inc.
All rights reserved.
Product specifications subject to change without notice.
DSC-5611/4
IDT723656/723666/723676 CMOS TRIPLE BUS SyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
18-bit buses (Port B transmits data, Port C receives data.) FIFO data can be
read out of Port B and written into Port C using either 18-bit or 9-bit formats with
a choice of Big- or Little-Endian configurations.
These devices are a synchronous (clocked) FIFO, meaning each port
employs a synchronous interface. All data transfers through a port are gated
to the LOW-to-HIGH transition of a port clock by enable signals. The clocks for
DESCRIPTION
The IDT723656/723666/723676 is a monolithic, high-speed, low-power,
CMOS Triple Bus synchronous (clocked) FIFO memory which supports clock
frequencies up to 83 MHz and has read access times as fast as 8ns. Two
independent 2,048/4,096/8,192 x 36 dual-port SRAM FIFOs on board each
chip buffer data between a bidirectional 36-bit bus (Port A) and two unidirectional
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
W/RA
ENA
CLKA
GND
A35
A34
A33
A32
Vcc
A31
A30
GND
A29
A28
A27
A26
A25
A24
A23
BE/FWFT
GND
A22
Vcc
A21
A20
A19
A18
GND
A17
A16
A15
A14
A13
Vcc
A12
GND
A11
A10
A9
A8
A7
A6
GND
A5
A4
A3
FS2
VCC
A2
A1
A0
GND
B0
B1
B2
B3
B4
B5
GND
B6
VCC
B7
B8
B9
INDEX
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
CSA
FFA/IRA
EFA/ORA
PRS1/RT1
VCC
AFA
AEA
MBF2
MBA
MRS1
FS0/SD
CLKC
GND
FS1/SEN
MRS2
MBB
MBF1
VCC
AEB
AFC
EFB/ORB
FFC/IRC
GND
CSB
WENC
RENB
PIN CONFIGURATION
TQFP (PK128-1, order code: PF)
TOP VIEW
2
CLKB
PRS2/RT2
LOOP
C17
C16
C15
C14
RTM
MBC
C13
C12
C11
C10
C9
C8
VCC
C7
C6
SIZEB
GND
C5
C4
C3
C2
C1
C0
GND
B17
B16
SIZEC
VCC
B15
B14
B13
B12
GND
B11
B10
5611 drw02
IDT723656/723666/723676 CMOS TRIPLE BUS SyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
a selected number of words remain in the FIFO memory. AFA and AFC indicate
when the FIFO contains more than a selected number of words.
FFA/IRA, FFC/IRC, AFA and AFC are two-stage synchronized to the Port
Clock that writes data into its array. EFA/ORA, EFB/ORB, AEA, and AEB are
two-stage synchronized to the Port Clock that reads data from its array.
Programmable offsets for AEA, AEB, AFA, AFC are loaded in parallel using
Port A or in serial via the SD input. Five default offset settings are also provided.
The AEA and AEB threshold can be set at 8, 16, 64, 256, and 1,024 locations
from the empty boundary and the AFA and AFC threshold can be set at 8, 16,
64, 256 or 1,024 locations from the full boundary. All these choices are made
using the FS0, FS1 and FS2 inputs during Master Reset.
Interspersed Parity can also be selected during a Master Reset of the FIFO.
If Interspersed Parity is selected then during parallel programming of the flag
offset values, the device will ignore data line A8. If Non-Interspersed Parity is
selected then data line A8 will become a valid bit.
A Loopback function is provided on Port A. When the Loop feature is selected
via the LOOP pin, the data output from FIFO2 will be directed to the data input
of FIFO1. If Loop is selected and Port A is set-up for write operation via W/RA
pin, then data output from FIFO2 will be written to FIFO1, but will not be placed
on the output Port A (A0-A35). If Port A is set-up for read operation via W/RA
then data output from FIFO2 will be written into FIFO1 and placed onto Port A
(A0-A35). The Loop will continue to happen provided that FIFO1 is not full and
FIFO2 is not empty. If during a Loop sequence FIFO1 becomes full then any
data that continues to be read out from FIFO2 will only be placed on the Port
A (A0-A35) lines, provided that Port A is set-up for read operation. If during
a Loop sequence the FIFO2 becomes empty, then the last word from FIFO2
will continue to be clocked into FIFO1 until FIFO1 becomes full or until the Loop
function is stopped. The Loop feature can be useful when performing system
debugging and remote loopbacks.
Two or more FIFOs may be used in parallel to create wider data paths. Such
a width expansion requires no additional, external components. Furthermore,
two IDT723656/723666/723676 FIFOs can be combined with unidirectional
FIFOs capable of First Word Fall Through timing (i.e. the SuperSync FIFO
family) to form a depth expansion.
If, at any time, the FIFO is not actively performing a function, the chip will
automatically power down. During the power down state, supply current
consumption (ICC) is at a minimum. Initiating any operation (by activating control
inputs) will immediately take the device out of the power down state.
The IDT723656/723666/723676 are characterized for operation from 0°C
to 70°C. Industrial temperature range (-40°C to +85°C) is available by special
order. They are fabricated using IDT’s high speed, submicron CMOS
technology.
each port are independent of one another and can be asynchronous or
coincident. The enables for each port are arranged to provide a simple
bidirectional interface between microprocessors and/or buses with synchronous control.
Communication between each port may bypass the FIFOs via two mailbox
registers. The mailbox registers' width matches the selected bus width of ports
B and C. Each mailbox register has a flag (MBF1 and MBF2) to signal when
new mail has been stored.
Two kinds of reset are available on these FIFOs: Master Reset and Partial
Reset. Master Reset initializes the read and write pointers to the first location
of the memory array and selects serial flag programming, parallel flag programming, or one of five possible default flag offset settings, 8, 16, 64, 256 or 1,024.
Each FIFO has its own, independent Master Reset pin, MRS1 and MRS2.
Partial Reset also sets the read and write pointers to the first location of the
memory. Unlike Master Reset, any settings existing prior to Partial Reset (i.e.,
programming method and partial flag default offsets) are retained. Partial Reset
is useful since it permits flushing of the FIFO memory without changing any
configuration settings. Each FIFO has its own, independent Partial Reset pin,
PRS1 and PRS2. Note that the Retransmit Mode, RTM pin must be LOW at the
point a partial reset is performed.
Both FIFO's have Retransmit capability, when a Retransmit is performed on
a respective FIFO only the read pointer is reset to the first memory location. A
Retransmit is performed by using the Retransmit Mode, RTM pin in conjunction
with the Retransmit pins RT1 or RT2, for each respective FIFO. Note that the
two Retransmit pins RT1 and RT2 are muxed with the Partial Reset pins.
These devices have two modes of operation: In the IDT Standard mode, the
first word written to an empty FIFO is deposited into the memory array. A read
operation is required to access that word (along with all other words residing
in memory). In the First Word Fall Through mode (FWFT), the first word written
to an empty FIFO appears automatically on the outputs, no read operation
required (Nevertheless, accessing subsequent words does necessitate a
formal read request). The state of the BE/FWFT pin during Master Reset
determines the mode in use.
Each FIFO has a combined Empty/Output Ready Flag (EFA/ORA and EFB/
ORB) and a combined Full/Input Ready Flag (FFA/IRA and FFC/IRC). The
EF and FF functions are selected in the IDT Standard mode. EF indicates
whether or not the FIFO memory is empty. FF shows whether the memory is
full or not. The IR and OR functions are selected in the First Word Fall Through
mode. IR indicates whether or not the FIFO has available memory locations.
OR shows whether the FIFO has data available for reading or not. It marks the
presence of valid data on the outputs.
Each FIFO has a programmable Almost-Empty flag (AEA and AEB) and a
programmable Almost-Full flag (AFA and AFC). AEA and AEB indicate when
3
IDT723656/723666/723676 CMOS TRIPLE BUS SyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTIONS
Symbol
Name
I/O
Description
A0-A35
Port A Data
I/O
36-bit bidirectional data port for side A.
AEA
Port A AlmostEmpty Flag
O
Programmable Almost-Empty flag synchronized to CLKA. It is LOW when the number of words in FIFO2
is less than or equal to the value in the Almost-Empty A Offset register, X2.
AEB
Port B AlmostEmpty Flag
O
Programmable Almost-Empty flag synchronized to CLKB. It is LOW when the number of words in FIFO1
is less than or equal to the value in the Almost-Empty B Offset register, X1.
AFA
Port A AlmostFull Flag
O
Programmable Almost-Full flag synchronized to CLKA. It is LOW when the number of empty locations
in FIFO1 is less than or equal to the value in the Almost-Full A Offset register, Y1.
AFC
Port C AlmostFull Flag
O
Programmable Almost-Full flag synchronized to CLKC. It is LOW when the number of empty locations
in FIFO2 is less than or equal to the value in the Almost-Full C Offset register, Y2.
B0-B17
Port B Data
O
18-bit output data port for side B.
BE/FWFT
Big-Endian/
First Word Fall
Through Select
I
This is a dual purpose pin. During Master Reset, a HIGH on BE will select Big-Endian operation.
In this case, depending on the bus size, the most significant byte or word on Port A is read from
Port B first (A-to-B data flow) or is written to Port C first (C-to-A data flow). A LOW on BE will select
Little-Endian operation. In this case, the least significant byte or word on Port A is read from Port B first
(A-to-B data flow) or is written to Port C first (C-to-A data flow).
After Master Reset, this pin selects the timing mode. A HIGH on FWFT selects IDT Standard mode, a
LOW selects First Word Fall Through mode. Once the timing mode has been selected, the level on
FWFT must be static throughout device operation.
C0-C17
Port C Data
I
18-bit input data port for side C.
CLKA
Port A Clock
I
CLKA is a continuous clock that synchronizes all data transfers through Port A and can be
asynchronous or coincident to CLKB. FFA/IRA, EFA/ORA, AFA, and AEA are all synchronized to
the LOW-to-HIGH transition of CLKA.
CLKB
Port B Clock
I
CLKB is a continuous clock that synchronizes all data transfers through Port B and can be asynchronous
or coincident to CLKA. EFB/ORB and AEB are synchronized to the LOW-to-HIGH transition of CLKB.
CLKC
Port C Clock
I
CLKC is a continuous clock that synchronizes all data transfers through Port C and can be asynchronous
or coincident to CLKA. FFC/IRC and AFC are synchronized to the LOW-to-HIGH transition of CLKC.
CSA
Port A Chip
Select
I
CSA must be LOW to enable to LOW-to-HIGH transition of CLKA to read or write on Port A. The A0-A35
outputs are in the high-impedance state when CSA is HIGH.
CSB
Port B Chip
Select
I
CSB must be LOW to enable a LOW-to-HIGH transition of CLKB to read data on Port B. The B0-B17
outputs are in the high-impedance state when CSB is HIGH.
EFA/ORA
Port A Empty/
Output Ready
Flag
O
This is a dual function pin. In the IDT Standard mode, the EFA function is selected. EFA indicates
whether or not the FIFO2 memory is empty. In the FWFT mode, the ORA function is selected. ORA
indicates the presence of valid data on the A0-A35 outputs, available for reading. EFA/ORA is
synchronized to the LOW-to-HIGH transition of CLKA.
EFB/ORB
Port B Empty/
Output Ready Flag
O
This is a dual function pin. In the IDT Standard mode, the EFB function is selected. EFB indicates
whether or not the FIFO1 memory is empty. In the FWFT mode, the ORB function is selected. ORB
indicates the presence of valid data on the B0-B17 outputs, available for reading. EFB/ORB is synchronized
to the LOW-to-HIGH transition of CLKB.
ENA
Port A Enable
I
ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on Port A.
FFA/IRA
Port A Full/
Input Ready Flag
O
This is a dual function pin. In the IDT Standard mode, the FFA function is selected. FFA indicates
whether or not the FIFO1 memory is full. In the FWFT mode, the IRA function is selected. IRA
indicates whether or not there is space available for writing to the FIFO1 memory. FFA/IRA is
synchronized to the LOW-to-HIGH transition of CLKA.
FFC/IRC
Port C Full/
Input Ready Flag
O
This is a dual function pin. In the IDT Standard mode, the FFC function is selected. FFC indicates
whether or not the FIFO2 memory is full. In the FWFT mode, the IRC function is selected. IRC
indicates whether or not there is space available for writing to the FIFO2 memory. FFC/IRC is
synchronized to the LOW-to-HIGH transition of CLKC.
4
IDT723656/723666/723676 CMOS TRIPLE BUS SyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTIONS (CONTINUED)
Symbol
Name
I/O
Description
FS0/SD
Flag Offset Select 0/
Serial Data
I
FS1/SEN
Flag Offset Select 1/
Serial Enable
I
FS2(1)
Flag Offset Select 2
I
LOOP
Loopback Select
I
MBA
Port A Mailbox
Select
I
A HIGH level on MBA chooses a mailbox register for a Port A read or write operation. When the A0-A35
outputs are active, a HIGH level on MBA selects data from the mail2 register for output and a LOW level selects
FIFO2 output-register data for output.
MBB
Port B Mailbox
Select
I
A HIGH level on MBB chooses a mailbox register for a Port B read operation. When the B0-B17 outputs are
active, a HIGH level on MBB selects data from the mail1 register for output and a LOW level selects FIFO1 output
register data for output.
MBC
Port C Mailbox
Select
I
A HIGH level on MBC chooses the mail2 register for a Port C write operation. This pin must be HIGH during
Master Reset.
MBF1
Mail1 Register
Flag
O MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register. Writes to the mail1
register are inhibited while MBF1 is LOW. MBF1 is set HIGH by a LOW-to-HIGH transition of CLKB when a
Port B read is selected and MBB is HIGH. MBF1 is set HIGH following either a Master or Partial Reset of FIFO1.
MBF2
Mail2 Register
Flag
O MBF2 is set LOW by a LOW-to-HIGH transition of CLKC that writes data to the mail2 register. Writes to the mail2
register are inhibited while MBF2 is LOW. MBF2 is set HIGH by a LOW-to-HIGH transition of CLKA when a
Port A read is selected and MBA is HIGH. MBF2 is set HIGH following either a Master or Partial Reset of FIFO2.
MRS1
Master Reset
I
MRS2
Master Reset
I A LOW on this pin initializes the FIFO2 read and write pointers to the first location of memory and sets the Port A
output register to all zeroes. A LOW-to-HIGH transition on MRS2, toggled simultaneously with MRS1, selects
the programming method (serial or parallel) and one of the five flag default offsets for FIFO2. Four LOW-to-HIGH
transitions of CLKA and four LOW-to-HIGH transitions of CLKC must occur while MRS2 is LOW.
PRS1/
RT1
Partial Reset/
Retransmit FIFO1
I
PRS2/
Partial Reset/
I This pin is muxed for both Partial Reset and Retransmit operations, it is used in conjunction with the RTM pin. If RTM
RT2
Retransmit FIFO2
is in a LOW condition, a LOW on this pin performs a Partial Reset on FIFO2 and initializes the FIFO2 read and write
selected bus size, endian arrangement, programming method (serial or parallel), and programmable flag settings are
all retained. If RTM is HIGH, a LOW on this pin performs a Retransmit and initializes the FIFO2 read pointer only to
the first memory location.
RENB
RTM
Port B Read Enable I
Retransmit Mode
I
RENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read data on Port B.
This pin is used in conjunction with the RT1 and RT2 pins. When RTM is HIGH a Retransmit is performed on FIFO1
or FIFO2 respectively.
FS1/SEN and FS0/SD are dual-purpose inputs used for flag Offset register programming. During Master Reset,
FS1/SEN and FS0/SD, together with FS2, select the flag offset programming method. Three Offset register
programming methods are available: automatically load one of five preset values (8, 16, 64, 256 or 1,024),
parallel load from Port A, and serial load.
When serial load is selected for flag Offset register programming, FS1/SEN is used as an enable synchronous to
the LOW-to-HIGH transition of CLKA. When FS1/SEN is LOW, a rising edge on CLKA load the bit present on
FS0/SD into the X and Y registers. The number of bit writes required to program the Offset registers is 44 for the
IDT723656, 48 for the IDT723666, and 52 for the IDT723676. The first bit write stores the Y-register (Y1) MSB
and the last bit write stores the X-register (X2) LSB.
This pin selects the loopback feature for Port A. During Loopback data from FIFO2 will be directed to the input of
FIFO1. to initiate a Loop the LOOP pin must be held LOW and the ENA pin must be HIGH.
A LOW on this pin initializes the FIFO1 read and write pointers to the first location of memory and sets the Port B
output register to all zeroes. A LOW-to-HIGH transition on MRS1 selects the programming method (serial or
parallel) and one of five programmable flag default offsets for FIFO1 and FIFO2. It also configures ports B and
C for bus size and endian arrangement. Four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH
transitions of CLKB must occur while MRS1 is LOW.
This pin is muxed for both Partial Reset and Retransmit operations, it is used in conjunction with the RTM pin. If RTM
is in a LOW condition, a LOW on this pin performs a Partial Reset on FIFO1 and initializes the FIFO1 read and write
pointers to the first location of memory and sets the Port B output register to all zeroes. During Partial Reset, the currently
selected bus size, endian arrangement, programming method (serial or parallel), and programmable flag settings are
all retained. If RTM is HIGH, a LOW on this pin performs a Retransmit and initializes the FIFO1 read pointer only to
the first memory location.
5
IDT723656/723666/723676 CMOS TRIPLE BUS SyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTIONS (CONTINUED)
Symbol
Name
I/O
(1)
SIZEB
Port B
Bus Size Select
I
SIZEC(1)
Port C
Bus Size Select
I
WENC
W/RA
Port C Write Enable
Port A Write/
Read Select
I
I
Description
SIZEB determines the bus width of Port B. A HIGH on this pin selects byte (9-bit) bus size. A LOW on this pin
selects word (18-bit) bus size. SIZEB works with SIZEC and BE to select the bus size and endian arrangement
for ports B and C. The level of SIZEB must be static throughout device operation.
SIZEC determines the bus width of Port C. A HIGH on this pin selects byte (9-bit) bus size. A LOW on this pin
selects word (18-bit) bus size. SIZEC works with SIZEB and BE to select the bus size and endian arrangement
for ports B and C. The level of SIZEC must be static throughout device operation.
WENC must be HIGH to enable a LOW-to-HIGH transition of CLKC to write data on Port C.
A HIGH selects a write operation and a LOW selects a read operation on Port A for a LOW-to-HIGH transition of
CLKA. The A0-A35 outputs are in the HIGH impedance state when W/RA is HIGH.
NOTE:
1. FS2, SIZEB and SIZEC inputs are not TTL compatible. These inputs should be tied to GND or VCC.
6
IDT723656/723666/723676 CMOS TRIPLE BUS SyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR
TEMPERATURE RANGE (Unless otherwise noted)(1)
Symbol
V CC
Commercial
Unit
–0.5 to +7.0
V
Input Voltage Range
–0.5 to VCC+0.5
V
Output Voltage Range
–0.5 to VCC+0.5
V
Supply Voltage Range
(2)
VI
VO
Rating
(2)
IIK
Input Clamp Current (VI < 0 or VI > VCC)
±20
mA
IOK
Output Clamp Current (VO = < 0 or VO > VCC)
±50
mA
I OUT
Continuous Output Current (VO = 0 to VCC)
±50
mA
I CC
Continuous Current Through VCC or GND
±400
mA
T STG
Storage Temperature Range
–65 to 150
°C
NOTES:
1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these
or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect
device reliability.
2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min.
Max.
Unit
4.5
5.5
V
VCC
Supply Voltage
VIH
HIGH Level Input Voltage
2
—
V
VIL
LOW-Level Input Voltage
—
0.8
V
IOH
HIGH-Level Output Current
—
–4
mA
IOL
LOW-Level Output Current
—
8
mA
TA
Operating Free-air Temperature
0
70
°C
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING FREEAIR TEMPERATURE RANGE (Unless otherwise noted)
Symbol
Parameter
Test Conditions
IDT723656
IDT723666
IDT723676
Commercial
tCLK = 12, 15ns
Min.
Typ.(1)
Max.
Unit
VOH
Output Logic "1" Voltage
VCC = 4.5V,
IOH = –4 mA
2.4
—
—
V
VOL
Output Logic "0" Voltage
VCC = 4.5V,
IOL = 8 mA
—
—
0.5
V
ILI
Input Leakage Current (Any Input)
VCC = 5.5V,
VI = VCC or 0
—
—
±10
µA
ILO
Output Leakage Current
VCC = 5.5V,
VO = VCC or 0
—
—
±10
µA
ICC2(2)
Standby Current (with CLKA, CLKB and CLKC running)
VCC = 5.5V,
VI = VCC –0.2V or 0V
—
—
8
mA
ICC3(2)
Standby Current (no clocks running)
VCC = 5.5V,
VI = VCC –0.2V or 0V
—
—
1
mA
CIN
(3)
COUT(3)
Input Capacitance
VI = 0,
f = 1 MHz
—
4
—
pF
Output Capacitance
VO = 0,
f = 1 MHZ
—
8
—
pF
NOTES:
1. All typical values are at VCC = 5V, TA = 25°C.
2. For additional ICC information, see Figure 1, Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS).
3. Characterized values, not currently tested.
4. Industrial temperature range is available by special order.
7
IDT723656/723666/723676 CMOS TRIPLE BUS SyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION
The ICC(f) current for the graph in Figure 1 was taken while simultaneously reading and writing a FIFO on the IDT723656/723666/723676 with CLKA,
CLKB and CLKC set to fS. All data inputs and data outputs change state during each clock cycle to consume the highest supply current. Data outputs were
disconnected to normalize the graph to a zero capacitance load. Once the capacitance load per data-output channel and the number of these device's inputs
driven by TTL HIGH levels are known, the power dissipation can be calculated with the equation below.
CALCULATING POWER DISSIPATION
With ICC(f) taken from Figure 1, the maximum power dissipation (PT) of these FIFOs may be calculated by:
PT = VCC x [ICC(f) + (N x ∆ICC x dc)] + Σ(CL x VCC2 X fo)
N
where:
N
∆I CC
dc
CL
fo
ICC(f)
Supply Current
mA
300
=
=
=
=
=
number of inputs driven by TTL levels
increase in power supply current for each input at a TTL HIGH level
duty cycle of inputs at a TTL HIGH level of 3.4V
output capacitance load
switching frequency of an output
fdata = 1/2 fS
TA = 25oC
CL = 0 pF
250
VCC = 5.5V
VCC = 5.0V
200
VCC = 4.5V
150
100
50
0
0
10
20
30
40
50
60
70
fS  Clock Frequency  MHz
Figure 1. Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS)
8
80
90
5611 drw02a
IDT723656/723666/723676 CMOS TRIPLE BUS SyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C)
Symbol
Commercial
IDT723656L12 IDT723656L15
IDT723666L12 IDT723666L15
IDT723676L12 IDT723676L15
Min.
Max.
Min.
Max.
Parameter
Unit
fS
Clock Frequency, CLKA, CLKB, or CLKC
—
83
—
66.7
MHz
tCLK
Clock Cycle Time, CLKA, CLKB, or CLKC
12
—
15
—
ns
tCLKH
Pulse Duration, CLKA, CLKB, or CLKC HIGH
5
—
6
—
ns
tCLKL
Pulse Duration, CLKA, CLKB, OR CLKC LOW
5
—
6
—
ns
tDS
Setup Time, A0-A35 before CLKA↑ and C0-C17 before CLKC↑
3
—
4
—
ns
tENS1
Setup Time, CSA and W/RA before CLKA↑; CSB before CLKB↑
4
—
4.5
—
ns
tENS2
Setup Time, ENA, and MBA before CLKA↑; RENB and MBB before CLKB↑;
WENC and MBC before CLKC↑
3
—
4.5
—
ns
tRSTS
Setup Time, MRS1, MRS2, PRS1, PRS2, RT1 or RT2 LOW before CLKA↑ or CLKB↑(1)
5
—
5
—
ns
tFSS
Setup Time, FS0, FS1, FS2 before MRS1 and MRS2 HIGH
7.5
—
7.5
—
ns
tBES
Setup Time, BE/FWFT before MRS1 and MRS2 HIGH
7.5
—
7.5
—
ns
tSDS
Setup Time, FS0/SD before CLKA↑
3
—
4
—
ns
tSENS
Setup Time, FS1/SEN before CLKA↑
3
—
4
—
ns
tFWS
Setup Time, BE/FWFT before CLKA↑
0
—
0
—
ns
tRTMS
Setup Time, RTM before RT1; RTM before RT2
5
—
5
—
ns
tDH
Hold Time, A0-A35 after CLKA↑ and C0-C17 after CLKC↑
0.5
—
1
—
ns
tENH
Hold Time, CSA, W/RA, ENA, and MBA after CLKA↑; CSB, RENB, and MBB after
CLKB↑; WENC and MBC after CLKC↑
0.5
—
1
—
ns
tRSTH
Hold Time, MRS1, MRS2, PRS1, PRS2, RT1 or RT2 LOW after CLKA↑ or CLKB↑(1)
4
—
4
—
ns
tFSH
Hold Time, FS0, FS1, FS2 after MRS1 and MRS2 HIGH
2
—
2
—
ns
tBEH
Hold Time, BE/FWFT after MRS1 and MRS2 HIGH
2
—
2
—
ns
tSDH
Hold Time, FS0/SD after CLKA↑
0.5
—
1
—
ns
tSENH
Hold Time, FS1/SEN HIGH after CLKA↑
0.5
—
1
—
ns
tSPH
Hold Time, FS1/SEN HIGH after MRS1 and MRS2 HIGH
2
—
2
—
ns
tRTMH
Hold Time, RTM after RT1; RTM after RT2
5
—
5
—
ns
tSKEW1(2)
Skew Time, between CLKA↑ and CLKB↑ for EFB/ORB and FFA/IRA; between CLKA↑
and CLKC↑ for EFA/ORA and FFC/IRC
5
—
7.5
—
ns
tSKEW2(2,3)
Skew Time, between CLKA↑ and CLKB↑ for AEB and AFA; between CLKA↑ and
CLKC↑ for AEA and AFC
12
—
12
—
ns
NOTES:
1. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
2. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship among CLKA cycle, CLKB cycle, and CLKC cycle.
3. Design simulated, not tested.
4. Industrial temperature range is available by special order.
9
IDT723656/723666/723676 CMOS TRIPLE BUS SyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, CL = 30PF
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C)
Symbol
Commercial
IDT723656L12
IDT723656L15
IDT723666L12
IDT723666L15
IDT723676L12
IDT723676L15
Min.
Max.
Min.
Max.
Parameter
Unit
tA
Access Time, CLKA↑ to A0-A35 and CLKB↑ to B0-B17
2
8
2
10
ns
tWFF
Propagation Delay Time, CLKA↑ to FFA/IRA and CLKC↑ to FFC/IRC
2
8
2
8
ns
tREF
Propagation Delay Time, CLKA↑ to EFA/ORA and CLKB↑ to EFB/ORB
1
8
1
8
ns
tPAE
Propagation Delay Time, CLKA↑ to AEA and CLKB↑ to AEB
1
8
1
8
ns
tPAF
Propagation Delay Time, CLKA↑ to AFA and CLKC↑ to AFC
1
8
1
8
ns
tPMF
Propagation Delay Time, CLKA↑ to MBF1 LOW or MBF2 HIGH, CLKB↑ to MBF1
HIGH, and CLKC↑ to MBF2 LOW
0
8
0
8
ns
tPMR
Propagation Delay Time, CLKA↑ to B0-B17(1) and CLKC↑ to A0-A35(2)
2
8
2
10
ns
tMDV
Propagation Delay Time, MBA to A0-A35 valid and MBB to B0-B17 valid
2
8
2
10
ns
tRSF
Propagation Delay Time, MRS1 or PRS1 LOW to AEB LOW, AFA HIGH, and MBF1
HIGH and MRS2 or PRS2 LOW to AEA LOW, AFC HIGH, and MBF2 HIGH
1
10
1
15
ns
tEN
Enable Time, CSA or W/RA LOW to A0-A35 Active and CSB LOW to B0-B17 Active
2
6
2
10
ns
tDIS
Disable Time, CSA or W/RA HIGH to A0-A35 at high impedance and CSB HIGH
to B0-B17 at HIGH impedance
1
6
1
8
ns
NOTES:
1. Writing data to the mail1 register when the B0-B17 outputs are active and MBB is HIGH.
2. Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH.
3. Industrial temperature range is available by special order.
10
IDT723656/723666/723676 CMOS TRIPLE BUS SyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
RETRANSMIT ( RT1, RT2 )
The FIFO1 memory of these devices undergoes a Retransmit by taking its
associated Retransmit (RT1) input LOW for at least four Port A Clock (CLKA)
and four Port B Clock (CLKB) LOW-to-HIGH transitions. The Retransmit
initializes the read pointer of FIFO1 to the first memory location.
The FIFO2 memory undergoes a Retransmit by taking its associated
Retransmit (RT2) input LOW for at least four Port A Clock (CLKA) and four Port
C Clock (CLKC) LOW-to-HIGH transitions. The Retransmit initializes the read
pointer of FIFO1 to the first memory location.
The RTM pin must be HIGH during the time of Retransmit. Note that the RT1
input is muxed with the PRS1 input, the state of the RTM pin determining whether
this pin performs a Retransmit or Partial Reset. Also, the RT2 input is muxed
with the PRS2 input, the state of the RTM pin determining whether this pin
performs a Retransmit or Partial Reset. See Figures 30, 31, 32 and 33 for
Retransmit timing diagrams.
SIGNAL DESCRIPTION
MASTER RESET ( MRS1, MRS2 )
After power up, a Master Reset operation must be performed by providing
a LOW pulse to MRS1 and MRS2 simultaneously. Afterwards, the FIFO1
memory of the IDT723656/723666/723676 undergoes a complete reset by
taking its associated Master Reset (MRS1) input LOW for at least four Port A Clock
(CLKA) and four Port B Clock (CLKB) LOW-to-HIGH transitions. The FIFO2
memory undergoes a complete reset by taking its associated Master Reset
(MRS2) input LOW for at least four Port A Clock (CLKA) and four Port C Clock
(CLKC) LOW-to-HIGH transitions. The Master Reset inputs can switch
asynchronously to the clocks. A Master Reset initializes the associated read and
write pointers to the first location of the memory and forces the Full/Input Ready
flag (FFA/IRA, FFC/IRC) LOW, the Empty/Output Ready flag (EFA/ORA, EFB/
ORB) LOW, the Almost-Empty flag (AEA, AEB) LOW and the Almost-Full flag
(AFA, AFC) HIGH. A Master Reset also forces the associated Mailbox Flag
(MBF1, MBF2) of the parallel mailbox register HIGH. After a Master Reset, the
FIFO's Full/Input Ready flag is set HIGH after two Write Clock cycles. Then the
FIFO is ready to be written to.
A LOW-to-HIGH transition on the FIFO1 Master Reset (MRS1) input latches
the value of the Big-Endian (BE) input for determining the order by which bytes
are transferred through Ports B and C. It also latches the values of the Flag Select
(FS0, FS1 and FS2) inputs for choosing the Almost-Full and Almost-Empty
offsets and programming method.
A LOW-to-HIGH transition on the FIFO2 Master Reset (MRS2) clears the flag
offset registers of FIFO2 (X2, Y2). A LOW-to-HIGH transition on the FIFO2
Master Reset (MRS2) together with the FIFO1 Master Reset input (MRS1)
latches the value of the Big-Endian (BE) input for Ports B and C and also latches
the values of the Flag Select (FS0, FS1 and FS2) inputs for choosing the AlmostFull and Almost-Empty offsets and programming method (for details see Table
1, Flag Programming, and Almost-Empty and Almost-Full flag offset programming section). The relevant Master Reset timing diagrams can be found in
Figure 4 and 5.
Note that MBC must be HIGH during Master Reset (until FFA/IRA and
FFC/IRC go HIGH). MBA and MBB are "don't care" inputs1 during Master
Reset.
BIG-ENDIAN/FIRST WORD FALL THROUGH ( BE/FWFT )
— ENDIAN SELECTION
This is a dual purpose pin. At the time of Master Reset, the BE select function
is active, permitting a choice of Big- or Little-Endian byte arrangement for data
written to Port C or read from Port B. This selection determines the order by
which bytes (or words) of data are transferred through those ports. For the
following illustrations, note that both ports B and C are configured to have a byte
(or a word) bus size.
A HIGH on the BE/FWFT input when the Master Reset (MRS1, MRS2) inputs
go from LOW to HIGH will select a Big-Endian arrangement. When data is
moving in the direction from Port A to Port B, the most significant byte (word) of
the long word written to Port A will be read from Port B first; the least significant
byte (word) of the long word written to Port A will be read from Port B last. When
data is moving in the direction from Port C to Port A, the byte (word) written to
Port C first will be read from Port A as the most significant byte (word) of the long
word; the byte (word) written to Port C last will be read from Port A as the least
significant byte (word) of the long word.
A LOW on the BE/FWFT input when the Master Reset (MRS1, MRS2) inputs
go from LOW to HIGH will select a Little-Endian arrangement. When data is
moving in the direction from Port A to Port B, the least significant byte (word) of
the long word written to Port A will be read from Port B first; the most significant
byte (word) of the long word written to Port A will be read from Port B last. When
data is moving in the direction from Port C to Port A, the byte (word) written to
Port C first will be read from Port A as the least significant byte (word) of the long
word; the byte (word) written to Port C last will be read from Port A as the most
significant byte (word) of the long word. Refer to Figure 2 and 3 for illustrations
of the BE function. See Figure 4 (FIFO1 Master Reset) and 5 (FIFO2 Master
Reset) for Endian Select timing diagrams.
PARTIAL RESET (PRS1, PRS2)
The FIFO1 memory of these devices undergoes a limited reset by taking its
associated Partial Reset (PRS1) input LOW for at least four Port A Clock (CLKA)
and four Port B Clock (CLKB) LOW-to-HIGH transitions. The FIFO2 memory
undergoes a limited reset by taking its associated Partial Reset (PRS2) input
LOW for at least four Port A Clock (CLKA) and four Port C Clock (CLKC) LOWto-HIGH transitions. The RTM pin must be LOW during the time of partial reset.
The Partial Reset inputs can switch asynchronously to the clocks. A Partial Reset
initializes the internal read and write pointers and forces the Full/Input Ready
flag (FFA/IRA, FFC/IRC) LOW, the Empty/Output Ready flag (EFA/ORA, EFB/
ORB) LOW, the Almost-Empty flag (AEA, AEB) LOW, and the Almost-Full flag
(AFA, AFC) HIGH. A Partial Reset also forces the Mailbox Flag (MBF1, MBF2)
of the parallel mailbox register HIGH. After a Partial Reset, the FIFO’s Full/Input
Ready flag is set HIGH after two Write Clock cycles.
Whatever flag offsets, programming method (parallel or serial), and timing
mode (FWFT or IDT Standard mode) are currently selected at the time a Partial
Reset is initiated, those settings will remain unchanged upon completion of the
reset operation. A Partial Reset may be useful in the case where reprogramming
a FIFO following a Master Reset would be inconvenient. See Figure 6 and 7
for Partial Reset timing diagrams.
— TIMING MODE SELECTION
After Master Reset, the FWFT select function is available, permitting a choice
between two possible timing modes: IDT Standard mode or First Word Fall
Through (FWFT) mode. Once the Master Reset (MRS1, MRS2) input is HIGH,
a HIGH on the BE/FWFT input during the next LOW-to-HIGH transition of CLKA
(for FIFO1) and CLKC (for FIFO2) will select IDT Standard mode. This mode
uses the Empty Flag function (EFA, EFB) to indicate whether or not there are
any words present in the FIFO memory. It uses the Full Flag function (FFA,
FFC) to indicate whether or not the FIFO memory has any free space for writing.
In IDT Standard mode, every word read from the FIFO, including the first, must
be requested using a formal read operation.
NOTE:
1. Either a HIGH or LOW can be applied to a "don't care" input with no change to the logical operation of the FIFO. Nevertheless, inputs that are temporarily "don't care" (along with unused
inputs) must not be left open, rather they must be either HIGH or LOW.
11
IDT723656/723666/723676 CMOS TRIPLE BUS SyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
Once the Master Reset (MRS1, MRS2) input is HIGH, a LOW on the BE/
FWFT input during the next LOW-to-HIGH transition of CLKA (for FIFO1) and
CLKC (for FIFO2) will select FWFT mode. This mode uses the Output Ready
function (ORA, ORB) to indicate whether or not there is valid data at the data
outputs (A0-A35 or B0-B17). It also uses the Input Ready function (IRA, IRC)
to indicate whether or not the FIFO memory has any free space for writing. In
the FWFT mode, the first word written to an empty FIFO goes directly to the data
outputs, no read request necessary. Subsequent words must be accessed by
performing a formal read operation.
Following Master Reset, the level applied to the BE/FWFT input to choose
the desired timing mode must remain static throughout FIFO operation. Refer
to Figure 4 (FIFO1 Master Reset) and Figure 5 (FIFO2 Master Reset) for First
Word Fall Through select timing diagrams.
COMMERCIAL TEMPERATURE RANGE
simultaneously with FIFO1 Master Reset (MRS1). For relevant Preset value
loading timing diagrams, see Figure 4 and 5.
— PARALLEL LOAD FROM PORT A
To program the X1, X2, Y1, and Y2 registers from Port A, perform a Master
Reset on both FlFOs simultaneously with FS2 HIGH or LOW, FS0 and FS1
LOW during the LOW-to-HIGH transition of MRS1 and MRS2. The state of FS2
at this point of reset will determine whether the parallel programming method has
Interspersed Parity or Non-Interspersed Parity. Refer to Table 1 for Flag
Programming Flag Offset setup . It is important to note that once parallel
programming has been selected during a Master Reset by holding both FS0
& FS1 LOW, these inputs must remain LOW during all subsequent FIFO
operation. They can only be toggled HIGH when future Master Resets are
performed and other programming methods are desired.
After this reset is complete, the first four writes to FIFO1 do not store data in
RAM but load the Offset registers in the order Y1, X1, Y2, X2. For NonInterspersed Parity mode the Port A data inputs used by the Offset registers are
(A10-A0), (A11-A0), or (A12-A0) for the IDT723656, IDT723666, or
IDT723676, respectively. For Interspersed Parity mode the Port A data inputs
used by the Offset registers are (A11-A9, A7-A0), (A12-A9, A7-A0), or (A13A9, A7-A0) for the IDT723656, IDT723666, or IDT723676, respectively. The
highest numbered input is used as the most significant bit of the binary number
in each case. Valid programming values for the registers range from 1 to 2,044
for the IDT723656; 1 to 4,092 for the IDT723666; and 1 to 8,188 for the
IDT723676. After all the Offset registers are programmed from Port A, the Port
C Full/Input Ready flag (FFC/IRC) is set HIGH, and both FIFOs begin normal
operation. Refer to Figure 8 for a timing diagram illustration for parallel
programming of the flag offset values.
PROGRAMMING THE ALMOST-EMPTY AND ALMOST-FULL FLAGS
Four registers in these FIFOs are used to hold the offset values for the AlmostEmpty and Almost-Full flags. The Port B Almost-Empty flag (AEB) Offset register
is labeled X1 and the Port A Almost-Empty flag (AEA) Offset register is labeled
X2. The Port A Almost-Full flag (AFA) Offset register is labeled Y1 and the Port
C Almost-Full flag (AFC) Offset register is labeled Y2. The index of each register
name corresponds to its FIFO number. The Offset registers can be loaded with
preset values during the reset of a FIFO, programmed in parallel using the
FIFO’s Port A data inputs, or programmed in serial using the Serial Data (SD)
input (see Table 1).
FS0/SD, FS1/SEN and FS2 function the same way in both IDT Standard
and FWFT modes.
— PRESET VALUES
To load a FIFO’s Almost-Empty flag and Almost-Full flag Offset registers with
one of the five preset values listed in Table 1, the flag select inputs must be HIGH
or LOW during a master reset. For example, to load the preset value of 64 into
X1 and Y1, FS0, FS1 and FS2 must be HIGH when FlFO1 reset (MRS1) returns
HIGH. Flag Offset registers associated with FIFO2 are loaded with one of the
preset values in the same way with FIFO2 Master Reset (MRS2) toggled
INTERSPERSED PARITY
Interspersed Parity is selected during a Master Reset of the FIFO. Refer to
Table 1 for the set-up configuration of Interspersed Parity. The Interspersed
Parity function allows the user to select the location of the parity bits in the word
loaded into the parallel port (A0-An) during programming of the flag offset values.
TABLE 1 — FLAG PROGRAMMING
FS2
FS1/SEN
FS0/SD
MRS1
MRS2
H
H
H
↑
X
H
H
H
X
H
H
L
↑
H
H
L
H
L
H
X1 AND Y1 REGlSTERS(1)
X2 AND Y2 REGlSTERS(2)
64
X
↑
X
64
X
16
X
X
↑
X
16
↑
X
8
X
H
L
H
X
↑
X
8
L
L
L
H
H
L
H
H
H
↑
X
↑
X
↑
X
256
X
1,024
X
256
X
L
L
H
L
L
H
L
L
H
L
L
L
X
↑
↑
↑
↑
↑
↑
↑
X
Serial programming via SD
Parallel programming via Port A(3, 5)
IP Mode(4, 5)
1,024
Serial programming via SD
Parallel programming via Port A(3, 5)
IP Mode(4, 5)
NOTES:
1. X1 register holds the offset for AEB; Y1 register holds the offset for AFA.
2. X2 register holds the offset for AEA; Y2 register holds the offset for AFC.
3. When this method of parallel programming is selected, Port A will assume Non-Interspersed Parity.
4. When IP Mode is selected, only parallel programming of the offset values via Port A, can be performed and Port A will assume Interspersed Parity.
5. IF parallel programming is selected during a Master Reset, then FS0 & FS1 must remain LOW during FIFO operation.
12
IDT723656/723666/723676 CMOS TRIPLE BUS SyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
TABLE 2 — PORT A ENABLE FUNCTION TABLE
CSA
LOOP
Data A(A0-A35) I/O
X
H
High-Impedance
None
X
H
Input
None
↑
H
Input
FIFO1 write
H
↑
H
Input
Mail1 write
L
X
H
Output
None
H
L
↑
H
Output
FIFO2 read
L
H
X
H
Output
None
L
H
H
↑
H
Output
Mail2 read (set MBF2 HIGH)
H
H
L
↑
L
Output
Loop the data output of FIFO2 to input
of FIFO1 only
H
L
↑
L
Output
Loop the data output of FIFO2 to input
of FIFO1 and put data on Port A
W/RA
ENA
MBA
H
X
X
X
L
H
L
X
L
H
H
L
L
H
H
L
L
L
L
L
L
L
L
L
L
L
CLKA
PORT FUNCTION
TABLE 3 — PORT B ENABLE FUNCTION TABLE
CSB
RENB
MBB
CLKB
Data B (B0-B17) Outputs
H
X
X
X
High-Impedance
None
L
L
L
X
Output
None
PORT FUNCTION
L
H
L
↑
Output
FIFO1 read
L
L
H
X
Output
None
L
H
H
↑
Output
Mail1 read (set MBF1 HIGH)
TABLE 4 — PORT C ENABLE FUNCTION TABLE
WENC
MBC
CLKC
Data C (C0-C17) Inputs
PORT FUNCTION
H
L
↑
Input
FIFO2 write
H
H
↑
Input
Mail2 write
L
L
X
Input
None
L
H
X
Input
None
IRC) flag also remains LOW throughout the serial programming process, until
all register bits are written. FFC/IRC is set HIGH by the LOW-to-HIGH transition
of CLKC after the last bit is loaded to allow normal FIFO2 operation.
See Figure 9 timing diagram, Serial Programming of the Almost-Full Flag
and Almost-Empty Flag Offset Values after Reset (IDT Standard and FWFT
Modes).
If Interspersed Parity is selected then during parallel programming of the flag
offset values, the device will ignore data line A8. If Non-Interspersed Parity is
selected then data line A8 will become a valid bit. If Interspersed Parity is selected
serial programming of the offset values is not permitted, only parallel programming can be done.
— SERIAL LOAD
To program the X1, X2, Y1, and Y2 registers serially, initiate a Master Reset
with FS2 LOW, FS0/SD LOW and FS1/SEN HIGH during the LOW-to-HIGH
transition of MRS1 and MRS2. After this reset is complete, the X and Y register
values are loaded bit-wise through the FS0/SD input on each LOW-to-HIGH
transition of CLKA that the FS1/SEN input is LOW. There are 44-, 48-, or 52bit writes needed to complete the programming for the IDT723656, IDT723666,
or IDT723676, respectively. The four registers are written in the order Y1, X1,
Y2 and finally, X2. The first-bit write stores the most significant bit of the Y1 register
and the last-bit write stores the least significant bit of the X2 register. Each register
value can be programmed from 1 to 2,044 (IDT723656), 1 to 4,092 (IDT723666),
or 1 to 8,188 (IDT723676).
When the option to program the Offset registers serially is chosen, the Port
A Full/Input Ready (FFA/IRA) flag remains LOW until all register bits are written.
FFA/IRA is set HIGH by the LOW-to-HIGH transition of CLKA after the last bit
is loaded to allow normal FIFO1 operation. The Port B Full/Input Ready (FFC/
FIFO WRITE/READ OPERATION
The state of the Port A data (A0-A35) outputs is controlled by Port A Chip
Select (CSA) and Port A Write/Read Select (W/RA). The A0-A35 outputs are
in the high-impedance state when either CSA or W/RA is HIGH. The A0-A35
outputs are active when both CSA and W/RA are LOW.
Data is loaded into FIFO1 from the A0-A35 inputs on a LOW-to-HIGH
transition of CLKA when CSA is LOW, W/RA is HIGH, ENA is HIGH, MBA is
LOW, and FFA/IRA is HIGH. Data is read from FIFO2 to the A0-A35 outputs
by a LOW-to-HIGH transition of CLKA when CSA is LOW, W/RA is LOW, ENA
is HIGH, MBA is LOW, and EFA/ORA is HIGH (see Table 2). FIFO reads
and writes on Port A are independent of any concurrent Port B or Port C
operation.
The state of the Port B data (B0-B17) outputs is controlled by the Port B
Chip Select (CSB). The B0-B17 outputs are in the high-impedance state
when CSB is HIGH. The B0-B17 outputs are active when CSB is LOW.
13
IDT723656/723666/723676 CMOS TRIPLE BUS SyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
data residing in the FIFO’s memory array is clocked to the output register only
when a read is selected using CSA, W/RA, ENA and MBA at Port A or using
CSB, RENB and MBB at Port B. Relevant write and read timing diagrams for
Port A can be found in Figure 10 and 15. Relevant read and write timing
diagrams for Port B and Port C, together with Bus-Matching and Endian select
operation, can be found in Figure 11 to 14.
Data is read from FIFO1 to the B0-B17 outputs by a LOW-to-HIGH
transition of CLKB when CSB is LOW, RENB is HIGH, MBB is LOW and EFB/
ORB is HIGH (see Table 3). FIFO reads on Port B are independent of any
concurrent Port A and Port C operations.
Data is loaded into FIFO2 from the C0-C17 inputs on a LOW-to-HIGH
transition of CLKC when WENB is HIGH, MBC is LOW, and FFC/IRC is HIGH
(see Table 4). FIFO writes on Port C are independent of any concurrent Port
A and Port B operation.
The setup and hold time constraints for CSA and W/RA with regard to CLKA
as well as CSB with regard to CLKB are only for enabling write and read
operations and are not related to high-impedance control of the data outputs.
If ENA is LOW during a clock cycle, either CSA or W/RA may change states
during the setup and hold time window of the cycle. This is also true for CSB
when RENB is LOW.
When operating the FIFO in FWFT mode and the Output Ready flag is LOW,
the next word written is automatically sent to the FIFO’s output register by the
LOW-to-HIGH transition of the port clock that sets the Output Ready flag HIGH.
When the Output Ready flag is HIGH, subsequent data is clocked to the output
registers only when a read is selected using CSA, W/RA, ENA and MBA at Port
A or using CSB, RENB and MBB at Port B.
When operating the FIFO in IDT Standard mode, the first word will cause the
Empty Flag to change state on the second LOW-to-HIGH transition of the Read
Clock. The data word will not be automatically sent to the output register. Instead,
LOOPBACK (LOOP)
A Loopback function is provided on Port A and is selected by setting the LOOP
pin LOW. When the Loop feature is selected, the data output from FIFO2 will be
directed to the data input of FIFO1. If Loop is selected and Port A is set-up for
write operation via the W/RA pin being HIGH, then data output from FIFO2 will
be written to FIFO1, on every LOW-to-HIGH transition of CLKA, provided CSA
is LOW and ENA is HIGH. However, FIFO2 data output will not be placed on
the output Port A (A0-A35). If Port A is set-up for read operation via the W/RA
pin being LOW, then data output from FIFO2 will be written into FIFO1 on every
LOW-to-HIGH transition of CLKA, provided CSA is LOW and ENA is HIGH. Also
FIFO2 data will be output to Port A (A0-A35). When the LOOP pin is HIGH then
Port A operates in the normal manner. Refer to Table 2 for the input set-up of
the Loop feature.
The Loop operation will continue to happen provided that FIFO1 is not full
and FIFO2 is not empty. If during a Loop sequence FIFO1 becomes full then
any data that continues to be read out from FIFO2 will only be placed on the
TABLE 5 — FIFO1 FLAG OPERATION (IDT Standard and FWFT modes)
Synchronized
to CLKB
Number of Words in FIFO Memory(1,2)
IDT723656(3)
IDT723666(3)
IDT723676(3)
Synchronized
to CLKA
EFB/ORB
AEB
AFA
FFA/IRA
0
0
0
L
L
H
H
1 to X1
1 to X1
1 to X1
H
L
H
H
(X1+1) to [2,048-(Y1+1)]
(X1+1) to [4,096-(Y1+1)]
(X1+1) to [8,192-(Y1+1)]
H
H
H
H
(2,048-Y1) to 2,047
(4,096-Y1) to 4,095
(8,192-Y1) to 8,191
H
H
L
H
2,048
4,096
8,192
H
H
L
L
NOTES:
1. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
2. Data in the output register does not count as a "word in FIFO memory". Since in FWFT mode, the first word written to an empty FIFO goes unrequested to the output register (no read operation
necessary), it is not included in the FIFO memory count.
3. X1 is the almost-empty offset for FIFO1 used by AEB. Y1 is the almost-full offset for FIFO1 used by AFA. Both X1 and Y1 are selected during a FIFO1 reset or port A programming.
4. The ORB and IRA functions are active during FWFT mode; the EFB and FFA functions are active in IDT Standard mode.
TABLE 6 — FIFO2 FLAG OPERATION (IDT Standard and FWFT modes)
Synchronized
to CLKA
Number of Words in FIFO Memory(1,2)
Synchronized
to CLKC
IDT723656(3)
IDT723666(3)
IDT723676(3)
EFA/ORA
AEA
AFC
FFC/IRC
0
0
0
L
L
H
H
1 to X2
1 to X2
1 to X2
H
L
H
H
(X2+1) to [2,048-(Y2+1)]
(X2+1) to [4,096-(Y2+1)]
(X2+1) to [8,192-(Y2+1)]
H
H
H
H
(2,048-Y2) to 2,047
(4,096-Y2) to 4,095
(8,192-Y2) to 8,191
H
H
L
H
2,048
4,096
8,192
H
H
L
L
NOTES:
1. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
2. Data in the output register does not count as a "word in FIFO memory". Since in FWFT mode, the first word written to an empty FIFO goes unrequested to the output register (no read operation
necessary), it is not included in the FIFO memory count.
3. X2 is the almost-empty offset for FIFO2 used by AEA. Y2 is the almost-full offset for FIFO2 used by AFC. Both X2 and Y2 are selected during a FIFO2 reset or port A programming.
4. The ORA and IRC functions are active during FWFT mode; the EFA and FFC functions are active in IDT Standard mode.
14
IDT723656/723666/723676 CMOS TRIPLE BUS SyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
function is selected. For both timing modes, when the Full/Input Ready flag is
HIGH, a memory location is free in the FIFO to receive new data. No memory
locations are free when the Full/Input Ready flag is LOW and attempted writes
to the FIFO are ignored.
The Full/Input Ready flag of a FlFO is synchronized to the port clock that writes
data to its array. For both FWFT and IDT Standard modes, each time a word
is written to a FIFO, its write pointer is incremented. The state machine that
controls a Full/Input Ready flag monitors a write pointer and read pointer
comparator that indicates when the FlFO memory status is full, full-1, or full-2.
From the time a word is read from a FIFO, its previous memory location is ready
to be written to in a minimum of two cycles of the Full/Input Ready flag
synchronizing clock. Therefore, an Full/Input Ready flag is LOW if less than
two cycles of the Full/Input Ready flag synchronizing clock have elapsed since
the next memory write location has been read. The second LOW-to-HIGH
transition on the Full/Input Ready flag synchronizing clock after the read sets
the Full/Input Ready flag HIGH.
A LOW-to-HIGH transition on a Full/Input Ready flag synchronizing clock
begins the first synchronization cycle of a read if the clock transition occurs at
time tSKEW1 or greater after the read. Otherwise, the subsequent clock cycle
can be the first synchronization cycle (see Figure 20, 21, 22, and 23).
Port A (A0-A35) lines, (provided that Port A is set-up for read operation). If
during a Loop sequence the FIFO2 becomes empty, then the last word from
FIFO2 will continue to be clocked into FIFO1 until FIFO1 becomes full or until
the Loop function is stopped. The Loop feature can be useful when performing
system debugging and remote loopbacks. See Figures 34 and 35 for Loopback
timing diagrams.
SYNCHRONIZED FIFO FLAGS
Each FIFO is synchronized to its port clock through at least two flip-flop stages.
This is done to improve flag signal reliability by reducing the probability of
metastable events when CLKA operates asynchronously with respect to either
CLKB or CLKC. EFA/ORA, AEA, FFA/IRA, and AFA are synchronized to
CLKA. EFB/ORB and AEB are synchronized to CLKB. FFC/IRC and AFC
are synchronized to CLKC. Tables 5 and 6 show the relationship of each port
flag to FIFO1 and FIFO2.
EMPTY/OUTPUT READY FLAGS (EFA/ORA, EFB/ORB)
These are dual purpose flags. In the FWFT mode, the Output Ready (ORA,
ORB) function is selected. When the Output Ready flag is HIGH, new data is
present in the FIFO output register. When the Output Ready flag is LOW, the
previous data word is present in the FIFO output register and attempted FIFO
reads are ignored.
In the IDT Standard mode, the Empty Flag (EFA, EFB) function is selected.
When the Empty Flag is HIGH, data is available in the FIFO’s RAM memory for
reading to the output register. When the Empty Flag is LOW, the previous data
word is present in the FIFO output register and attempted FIFO reads are
ignored.
The Empty/Output Ready flag of a FIFO is synchronized to the port clock that
reads data from its array. For both the FWFT and IDT Standard modes, the
FIFO read pointer is incremented each time a new word is clocked to its output
register. The state machine that controls an Output Ready flag monitors a write
pointer and read pointer comparator that indicates when the FIFO memory
status is empty, empty+1, or empty+2.
In FWFT mode, from the time a word is written to a FIFO, it can be shifted to
the FIFO output register in a minimum of three cycles of the Output Ready flag
synchronizing clock. Therefore, an Output Ready flag is LOW if a word in
memory is the next data to be sent to the FlFO output register and three cycles
of the port clock that reads data from the FIFO have not elapsed since the time
the word was written. The Output Ready flag of the FIFO remains LOW until
the third LOW-to-HIGH transition of the synchronizing clock occurs, simultaneously forcing the Output Ready flag HIGH and shifting the word to the FIFO
output register.
In IDT Standard mode, from the time a word is written to a FIFO, the Empty
Flag will indicate the presence of data available for reading in a minimum of two
cycles of the Empty Flag synchronizing clock. Therefore, an Empty Flag is LOW
if a word in memory is the next data to be sent to the FlFO output register and
two cycles of the port Clock that reads data from the FIFO have not elapsed since
the time the word was written. The Empty Flag of the FIFO remains LOW until
the second LOW-to-HIGH transition of the synchronizing clock occurs, forcing
the Empty Flag HIGH; only then can data be read.
A LOW-to-HIGH transition on an Empty/Output Ready flag synchronizing
clock begins the first synchronization cycle of a write if the clock transition occurs
at time tSKEW1 or greater after the write. Otherwise, the subsequent clock cycle
can be the first synchronization cycle (see Figure 16, 17, 18 and 19).
ALMOST-EMPTY FLAGS (AEA, AEB)
The Almost-Empty flag of a FIFO is synchronized to the port clock that reads
data from its array. The state machine that controls an Almost-Empty flag
monitors a write pointer and read pointer comparator that indicates when the
FIFO memory status is almost-empty, almost-empty+1, or almost-empty+2. The
almost-empty state is defined by the contents of register X1 for AEB and register
X2 for AEA. These registers are loaded with preset values during a FIFO reset,
programmed from Port A, or programmed serially (see the Almost-Empty flag
and Almost-Full flag offset programming section). An Almost-Empty flag is LOW
when its FIFO contains X or less words and is HIGH when its FIFO contains
(X+1) or more words. A data word present in the FIFO output register has been
read from memory.
Two LOW-to-HIGH transitions of the Almost-Empty flag synchronizing clock
are required after a FIFO write for its Almost-Empty flag to reflect the new level
of fill. Therefore, the Almost-Full flag of a FIFO containing (X+1) or more words
remains LOW if two cycles of its synchronizing clock have not elapsed since the
write that filled the memory to the (X+1) level. An Almost-Empty flag is set HIGH
by the second LOW-to-HIGH transition of its synchronizing clock after the FIFO
write that fills memory to the (X+1) level. A LOW-to-HIGH transition of an AlmostEmpty flag synchronizing clock begins the first synchronization cycle if it occurs
at time tSKEW2 or greater after the write that fills the FIFO to (X+1) words.
Otherwise, the subsequent synchronizing clock cycle may be the first synchronization cycle. (See Figure 24 and 25).
ALMOST-FULL FLAGS (AFA, AFC)
The Almost-Full flag of a FIFO is synchronized to the port clock that writes
data to its array. The state machine that controls an Almost-Full flag monitors
a write pointer and read pointer comparator that indicates when the FIFO
memory status is almost-full, almost-full-1, or almost-full-2. The almost-full state
is defined by the contents of register Y1 for AFA and register Y2 for AFC. These
registers are loaded with preset values during a FlFO reset, programmed from
Port A, or programmed serially (see Almost-Empty flag and Almost-Full flag
offset programming section). An Almost-Full flag is LOW when the number of
words in its FIFO is greater than or equal to (2,048-Y), (4,096-Y), or (8,192Y) for the IDT723656, IDT723666, or IDT723676 respectively. An Almost-Full
flag is HIGH when the number of words in its FIFO is less than or equal to [2,048(Y+1)], [4,096-(Y+1)], or [8,192-(Y+1)] for the IDT723656, IDT723666, or
FULL/INPUT READY FLAGS (FFA/IRA, FFC/IRC)
These are dual purpose flags. In FWFT mode, the Input Ready (IRA and
IRC) function is selected. In IDT Standard mode, the Full Flag (FFA and FFC)
15
IDT723656/723666/723676 CMOS TRIPLE BUS SyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
Note that MBC must be HIGH during Master Reset (until FFA/IRA and FFC/
IRC go HIGH. MBA and MBB are don't care inputs during Master Reset. For
mail register and mail register flag timing diagrams, see Figure 28 and 29.
IDT723676 respectively. Note that a data word present in the FIFO output
register has been read from memory.
Two LOW-to-HIGH transitions of the Almost-Full flag synchronizing clock are
required after a FIFO read for its Almost-Full flag to reflect the new level of fill.
Therefore, the Almost-Full flag of a FIFO containing [2,048/4,096/8,192-(Y+1)]
or less words remains LOW if two cycles of its synchronizing clock have not
elapsed since the read that reduced the number of words in memory to [2,048/
4,096/8,192-(Y+1)]. An Almost-Full flag is set HIGH by the second LOW-toHIGH transition of its synchronizing clock after the FIFO read that reduces the
number of words in memory to [2,048/4,096/8,192-(Y+1)]. A LOW-to-HIGH
transition of an Almost-Full flag synchronizing clock begins the first synchronization cycle if it occurs at time tSKEW2 or greater after the read that reduces the
number of words in memory to [2,048/4,096/8,192-(Y+1)]. Otherwise, the
subsequent synchronizing clock cycle may be the first synchronization cycle
(see Figure 26 and 27).
BUS SIZING
Port B may be configured in either an 18-bit word or a 9-bit byte format for
data read from FIFO1. Port C may be configured in either an 18-bit word or
a 9-bit byte format for data written to FIFO2. The bus size can be selected
independently for Ports B and C. The level applied to the Port B Size Select
(SIZEB) input determines the Port B bus size and the level applied to the Port
C Size Select (SIZEC) input determines the Port C bus size. These levels
should be static throughout FIFO operation. Both bus size selections are
implemented at the completion of Master Reset, by the time the Full/Input Ready
flag is set HIGH, as shown in Figure 2 and 3.
Two different methods for sequencing data transfer are available for Ports
B and C regardless of whether the bus size selection is byte- or word-size. They
are referred to as Big-Endian (most significant byte first) and Little-Endian (least
significant byte first). The level applied to the Big-Endian Select (BE) input
during the LOW-to-HIGH transition of MRS1 and MRS2 selects the endian
method that will be active during FIFO operation. This selection applies to both
ports B and C. The endian method is implemented at the completion of Master
Reset, by the time the Full/Input Ready flag is set HIGH, as shown in Figure
2 and 3 (see Endian Selection section).
Only 36-bit long word data is written to or read from the two FIFO memories
on these devices. Bus-Matching operations are done after data is read from
the FIFO1 RAM (Port B) and before data is written to the FIFO2 RAM (Port
C). The Endian select operations are not available when transferring data via
mailbox registers. Furthermore, both the word- and byte-size bus selections
limit the width of the data bus that can be used for mail register operations. In
this case, only those byte lanes belonging to the selected word- or byte-size
bus can carry mailbox data. The remaining data outputs will be indeterminate.
The remaining data inputs will be don’t care inputs. For example, when a wordsize bus is selected on Port B, then mailbox data can be transmitted only from
A0-A17 to B0-B17. When a byte-size bus is selected on Port B, then mailbox
data can be transmitted only from A0-A8 to B0-B8. Similarly, when a wordsize bus is selected on Port C, then mailbox data can be transmitted only from
C0-C17 to A18-A35. When a byte-size bus is selected on Port C, then mailbox
data can be transmitted only from C0-C8 to A18-A26.
MAILBOX REGISTERS
Each FIFO has an 18-bit bypass register allowing the passage of command
and control information from Port A to Port B or from Port C to Port A without putting
it in queue. The Mailbox Select (MBA, MBB and MBC) inputs choose between
a mail register and a FIFO for a port data transfer operation. The usable width
of both the Mail1 and Mail2 registers matches the selected bus size for port
B and C.
When sending data from Port A to Port B via the Mail1 Register, the following
is the case: A LOW-to-HIGH transition on CLKA writes data to the Mail1 Register
when a Port A write is selected by CSA, W/RA, and ENA with MBA HIGH. If
the selected Port B bus size is 18 bits, then the usable width of the Mail1 Register
employs data lines A0-A17. (In this case, A18-A35 are don’t care inputs.) If
the selected Port B bus size is 9 bits, then the usable width of the Mail1 Register
employs data lines A0-A8. (In this case, A9-A35 are don’t care inputs.)
When sending data from Port C to Port A via the Mail2 Register, the following
is the case: A LOW-to-HIGH transition on CLKC writes data to the Mail2 Register
when a Port C write is selected by WENC with MBC HIGH. If the selected Port
C bus size is 18 bits, then the usable width of the Mail2 Register employs data
lines C0-C17. If the selected Port C bus size is 9 bits, then the usable width of
the Mail2 Register employs data lines C0-C8. (In this case, C9-C17 are don’t
care inputs.)
Writing data to a mail register sets its corresponding flag (MBF1 or MBF2)
LOW. Attempted writes to a mail register are ignored while the mail flag is LOW.
When data outputs of a port are active, the data on the bus comes from the
FIFO output register when the port Mailbox select input is LOW and from the
mail register when the port mailbox select input is HIGH.
The Mail1 Register Flag (MBF1) is set HIGH by a LOW-to-HIGH transition
on CLKB when a Port B read is selected by CSB, and RENB with MBB HIGH.
For an 18-bit bus size, 18 bits of mailbox data are placed on B0-B17. For the
9-bit bus size, 9 bits of mailbox data are placed on B0-B8. (In this case, B9B17 are indeterminate.)
The Mail2 Register Flag (MBF2) is set HIGH by a LOW-to-HIGH transition
on CLKA when a Port A read is selected by CSA, W/RA, and ENA with MBA
HIGH. The data in a mail register remains intact after it is read and changes
only when new data is written to the register. For an 18-bit bus size, 18 bits
of mailbox data appear on A18-A35. (In this case, A0-A17 are indeterminate.)
For a 9-bit bus size, 9 bits of mailbox data appear on A18-A26. (In this case,
A0-A17 and A27-A35 are indeterminate.)
The data in a mail register remains intact after it is read and changes only
when new data is written to the register. The Endian Select feature has no effect
on mailbox data.
BUS-MATCHING FIFO1 READS
Data is read from the FIFO1 RAM in 36-bit long word increments. Since Port
B can have a byte or word size, only the first one or two bytes appear on the
selected portion of the FIFO1 output register, with the rest of the long word stored
in auxiliary registers. In this case, subsequent FIFO1 reads output the rest of
the long word to the FIFO1 output register in the order shown by Figure 2.
When reading data from FIFO1 in byte format, the unused B9-B17 outputs
are indeterminate.
BUS-MATCHING FIFO2 WRITES
Data is written to the FIFO2 RAM in 36-bit long word increments. Data written
to FIFO2 with a byte or word bus size stores the initial bytes or words in auxiliary
registers. The CLKC rising edge that writes the fourth byte or the second word
of long word to FIFO2 also stores the entire long word in the FIFO2 memory.
The bytes are arranged in the manner shown in Figure 3.
When writing data to FIFO2 in byte format, the unused C9-C17 inputs are
don't care inputs.
16
IDT723656/723666/723676 CMOS TRIPLE BUS SyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
BYTE ORDER ON PORT A:
A35 A27
A26 A18
B
A
BYTE ORDER ON PORT B:
BE
SIZEB
H
L
COMMERCIAL TEMPERATURE RANGE
A17 A9
A8  A0
C
D
B17 B9
B8  B0
A
B
B17 B9
B8  B0
C
D
Write to FIFO1
1st: Read from FIFO1
2nd: Read from FIFO1
(b) WORD SIZE  BIG ENDIAN
BE
SIZEB
L
L
B17 B9
B8  B0
C
D
B17 B9
B8  B0
A
B
1st: Read from FIFO1
2nd: Read from FIFO1
(c) WORD SIZE  LITTLE ENDIAN
B17 B9
BE
SIZEB
H
H
B8  B0
A
B17 B9
1st: Read from FIFO1
B8  B0
B
B17 B9
2nd: Read from FIFO1
B8  B0
C
B17 B9
3rd: Read from FIFO1
B8  B0
D
4th: Read from FIFO1
(d) BYTE SIZE  BIG ENDIAN
B17 B9
BE
L
B8  B0
SIZEB
H
D
B17 B9
1st: Read from FIFO1
B8  B0
C
B17 B9
2nd: Read from FIFO1
B8  B0
B
B17 B9
3rd: Read from FIFO1
B8  B0
A
(e) BYTE SIZE  LITTLE ENDIAN
Figure 2. Port B Bus Sizing
17
4th: Read from FIFO1
5611 drw 03
IDT723656/723666/723676 CMOS TRIPLE BUS SyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
BYTE ORDER ON PORT A:
A35 A27
A26 A18
B
A
BYTE ORDER ON PORT C:
BE
SIZEC
H
L
COMMERCIAL TEMPERATURE RANGE
A17 A9
A8  A0
C
D
C17 C9
C8  C0
A
B
C17 C9
C8  C0
C
D
Read from FIFO2
1st: Write to FIFO2
2nd: Write to FIFO2
(b) WORD SIZE  BIG ENDIAN
BE
SIZEC
L
L
C17 C9
C8  C0
C
D
C17 C9
C8  C0
A
B
1st: Write to FIFO2
2nd: Write to FIFO2
(c) WORD SIZE  LITTLE ENDIAN
C17 C9
BE
SIZEC
H
H
C8  C0
A
C17 C9
1st: Write to FIFO2
C8  C0
B
C17 C9
2nd: Write to FIFO2
C8  C0
C
C17 C9
3rd: Write to FIFO2
C8  C0
D
4th: Write to FIFO2
(d) BYTE SIZE  BIG ENDIAN
C17 C9
BE
L
C8  C0
SIZEC
H
D
C17 C9
1st: Write to FIFO2
C8  C0
C
C17 C9
2nd: Write to FIFO2
C8  C0
B
C17 C9
3rd: Write to FIFO2
C8  C0
A
(e) BYTE SIZE  LITTLE ENDIAN
Figure 3. Port C Bus Sizing
18
4th: Write to FIFO2
5611 drw 04
IDT723656/723666/723676 CMOS TRIPLE BUS SyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
CLKA
1
COMMERCIAL TEMPERATURE RANGE
2
CLKB
tRSTH
tRSTS
MRS1
tBEH
tBES
BE/FWFT
tFWS
BE
FWFT
tFSS
tFSH
0,1
FS2,FS1
,FS0
tWFF
tWFF
FFA/IRA
(2)
tREF
EFB/ORB
tRSF
AEB
tRSF
AFA
tRSF
MBF1
RTM
LOW
LOOP
HIGH
5611 drw 05
NOTES:
1. PRS1 and MBC must be HIGH during Master Reset until the rising edge of FFA/IRA goes HIGH.
2. If BE/FWFT is HIGH, then EFB/ORB will go LOW one CLKB cycle earlier than in this case where BE/FWFT is LOW.
Figure 4. FIFO1 Master Reset and Loading X1 and Y1 with a Preset Value of Eight (IDT Standard and FWFT Modes)
CLKC
1
2
CLKA
tRSTH
tRSTS
MRS2(3)
tBEH
tBES
BE/FWFT
BE
tFSS
FS2,FS1
,FS0
tFWS
FWFT
tFSH
0,1
tWFF
tWFF
FFC/IRC
(2)
tREF
EFA/ORA
tRSF
AEA
tRSF
AFC
tRSF
MBF2
RTM
LOW
LOOP
HIGH
5611 drw 06
NOTES:
1. PRS2 and MBC must be HIGH during Master Reset until the rising edge of FFC/IRC goes HIGH.
2. If BE/FWFT is HIGH, then EFA/ORA will go LOW one CLKA cycle earlier than in this case where BE/FWFT is LOW.
3. MRS2 must toggle simultaneously with MRS1.
Figure 5. FIFO2 Master Reset and Loading X2 and Y2 with a Preset Value of Eight (IDT Standard and FWFT Modes)
19
IDT723656/723666/723676 CMOS TRIPLE BUS SyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
CLKA
1
COMMERCIAL TEMPERATURE RANGE
2
CLKB
tRSTH
tRSTS
PRS1
tWFF
tWFF
FFA/IRA
(2)
tREF
EFB/ORB
tRSF
AEB
tRSF
AFA
tRSF
MBF1
RTM
LOW
5611 drw 07
NOTES:
1. MRS1 must be HIGH during Partial Reset.
2. If BE/FWFT is HIGH, then EFB/ORB will go LOW one CLKB cycle earlier than in this case where BE/FWFT is LOW.
Figure 6. FIFO1 Partial Reset (IDT Standard and FWFT Modes)
CLKC
CLKA
tRSTS
tRSTH
PRS2
tWFF
tWFF
FFC/IRC
tREF (2)
EFA/ORA
tRSF
AEA
tRSF
AFC
tRSF
MBF1
5611 drw 08
NOTES:
1. MRS2 must be HIGH during Partial Reset.
2. If BE/FWFT is HIGH, then EFA/ORA will go LOW one CLKA cycle earlier than in this case where BE/FWFT is LOW.
Figure 7. FIFO2 Partial Reset (IDT Standard and FWFT Modes)
20
IDT723656/723666/723676 CMOS TRIPLE BUS SyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
CLKA
COMMERCIAL TEMPERATURE RANGE
4
MRS1,
MRS2
tFSS
tFSH
tFSS
tFSH
FS2
FS1,FS0
0,0
tWFF
FFA/IRA
tENS2
tSKEW1 (1)
tENH
ENA
tDS
tDH
A0-A35
AFA Offset
(Y1)
AEB Offset
(X1)
AFC Offset
(Y2)
AEA Offset
(X2)
First Word to FIFO1
CLKC
1
2
tWFF
FFC/IRC
5611 drw 09
NOTES:
1. tSKEW1 is the minimum time between the rising CLKA edge and a rising CLKC edge for FFC/IRC to transition HIGH in the next cycle. If the time between the rising edge of CLKA and rising
edge of CLKC is less than tSKEW1, then FFC/IRC may transition HIGH one CLKC cycle later than shown.
2. CSA = LOW, W/RA = HIGH, MBA = LOW. It is not necessary to program Offset register on consecutive clock cycles.
Figure 8. Parallel Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset (IDT Standard and FWFT Modes)
CLKA
4
MRS1,
MRS2
tFSS
tFSH
FS2
tWFF
tSKEW(1)
FFA/IRA
tFSS
tSPH
tSENS
tSENH
tSENS
tSENH
FS1/SEN
tSDS
tSDH
tSDS
tSDH
FS0/SD(3)
AFA Offset
(Y1) MSB
CLKC
AEA Offset
(X2) LSB
4
tWFF
FFC/IRC
5611 drw 10
NOTES:
1. tSKEW1 is the minimum time between the rising CLKA edge and a rising CLKC edge for FFC/IRC to transition HIGH in the next cycle. If the time between the rising edge of CLKA and rising
edge of CLKC is less than tSKEW1, then FFC/IRC may transition HIGH one CLKC cycle later than shown.
2. It is not necessary to program Offset register bits on consecutive clock cycles. FIFO write attempts are ignored until FFA/IRA, FFC/IRC is set HIGH.
3. Programmable offsets are written serially to the SD input in the order AFA offset (Y1), AEB offset (X1), AFC offset (Y2), and AEA offset (X2).
Figure 9. Serial Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset (IDT Standard and FWFT Modes)
21
IDT723656/723666/723676 CMOS TRIPLE BUS SyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
tCLK
tCLKH
tCLKL
CLKA
FFA/IRA HIGH
tENS1
CSA
tENS1
tENH
tENH
W/RA
tENS2
tENH
MBA
tENS2
tENH
tENS2
tENH
tENH
tENS2
ENA
tDS
W1(1)
A0-A35
tDH
W2(1)
No Operation
5611 drw11
NOTE:
1. Written to FIFO1.
Figure 10. Port A Write Cycle Timing for FIFO1 (IDT Standard and FWFT Modes)
CLKC
FFC/IRC HIGH
tENS2
tENH
tENS2
tENH
tENS2
tENH
tENS2
tENH
MBC
WENC
tDS
tDH
C0-C17
5611 drw12
DATA SIZE TABLE FOR WORD WRITES TO FIFO2
SIZE MODE(1)
WRITE
DATA WRITTEN
NO.
SIZEC
BE
L
H
L
L
DATA READ FROM FIFO2
TO FIFO2
C17-C9
C8-C0
A35-A27
A26-A18
A17-A9
A8-A0
1
2
A
C
B
D
A
B
C
D
1
2
C
A
D
B
A
B
C
D
NOTE:
1. BE is selected at Master Reset; SIZEB and SIZEC must be static throughout device operation.
Figure 11. Port C Word Write Cycle Timing for FIFO2 (IDT Standard and FWFT Modes)
22
IDT723656/723666/723676 CMOS TRIPLE BUS SyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
CLKC
FFC/IRC HIGH
tENS2
tENH
tENS2
tENH
tENH
MBC
tENS2
tENH
WENC
tDS
tDH
C0-C8
5611 drw 13
DATA SIZE TABLE FOR BYTE WRITES TO FIFO2
SIZE MODE(1)
SIZEC
WRITE
NO.
BE
H
H
H
L
DATA WRITTEN
TO FIFO2
C8-C0
1
2
3
4
1
2
3
4
DATA READ FROM FIFO2
A
B
C
D
D
C
B
A
A35-A27
A26-A18
A17-A9
A8-A0
A
B
C
D
A
B
C
D
NOTE:
1. BE is selected at Master Reset; SIZEB and SIZEC must be static throughout device operation.
Figure 12. Port C Byte Write Cycle Timing for FIFO2 (IDT Standard and FWFT Modes)
CLKB
EFB/ORB
HIGH
CSB
MBB
tENS2
tENH
RENB
tEN
B0-B17
tMDV
(Standard Mode)
OR
tEN
B0-B17
tMDV
(FWFT Mode)
No Operation
tA
tA
Previous Data
Read 1
tA
Read 1
Read 2
tDIS
Read 2
tDIS
tA
Read 3
5611 drw 14
DATA SIZE TABLE FOR WORD READS FROM FIFO1
SIZE MODE(1)
DATA WRITTEN TO FIFO1
READ
NO.
SIZEB
H
BE
H
A35-A27
A
A26-A18
B
A17-A9
C
A8-A0
D
H
L
A
B
C
D
1
2
1
2
DATA READ FROM FIFO1
B17-B9
A
C
C
A
NOTE:
1. BE is selected at Master Reset; SIZEB and SIZEC must be static throughout device operation.
Figure 13. Port B Word Read Cycle Timing for FIFO1 (IDT Standard and FWFT Modes)
23
B8-B0
B
D
D
B
IDT723656/723666/723676 CMOS TRIPLE BUS SyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
CLKB
EFB/ORB HIGH
CSB
MBB
tENS2
tENH
RENB
tEN
B0-B8
tMDV
tA
Previous Data
(Standard Mode)
OR
tEN
B0-B8
tMDV
tA
Read 1
tA
tA
Read 3
tA
tA
tA
Read 1
(FWFT Mode)
tA
Read 2
Read 2
Read 3
No Operation
tDIS
Read 4
tDIS
Read 5
Read 4
5611 drw 15
NOTE:
1. Unused bytes B9-B17 are indeterminate for byte-size reads.
DATA SIZE TABLE FOR BYTE READS FROM FIFO1
SIZE MODE(1)
SIZEB
DATA WRITTEN TO FIFO1
BE
H
A35-A27
H
H
A26-A18
A
L
A17-A9
B
A
READ
NO.
A8-A0
C
B
DATA READ FROM FIFO1
D
C
D
B8-B0
1
2
3
4
A
B
C
D
1
D
2
C
3
B
4
A
NOTE:
1. BE is selected at Master Reset; SIZEB must be static throughout device operation.
Figure 14. Port B Byte Read Cycle Timing for FIFO1 (IDT Standard and FWFT Modes)
tCLKH
tCLK
tCLKL
CLKA
EFA/ORA
HIGH
CSA
W/RA
MBA
tENH
tENS2
tENS2
tENH
tENS2
tENH
ENA
tMDV
A0-A35
tEN
A0-A35
tEN
(FWFT Mode)
tA
tMDV
No Operation
W1(1)
Previous Data
(Standard Mode)
OR
tA
W2(1)
tDIS
tA
tA
W2(1)
W1(1)
tDIS
W3(1)
5611 drw16
NOTE:
1. Read From FIFO2.
Figure 15. Port A Read Cycle Timing for FIFO2 (IDT Standard and FWFT Modes)
24
IDT723656/723666/723676 CMOS TRIPLE BUS SyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
tCLK
tCLKH tCLKL
CLKA
CSA LOW
WRA
HIGH tENS2
tENH
tENS2
tENH
tDS
tDH
MBA
ENA
IRA HIGH
W1
A0-A35
(1)
tSKEW1
CLKB
tCLK
tCLKH
tCLKL
1
2
3
tREF
ORB
FIFO1 Empty
CSB
LOW
MBB
LOW
tREF
tENS2
tENH
RENB
tA
B0-B17
tA
Read 1
Read 2
5611 drw17
NOTES:
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for ORB to transition HIGH and to clock the next word to the FIFO1 output register in three CLKB cycles.
If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of ORB HIGH and load of the first word to the output register may occur one CLKB
cycle later than shown.
2. If Port B size is word or byte, ORB is set LOW by the last word or byte read from FIFO1, respectively (the word-size case is shown).
Figure 16. ORB Flag Timing and First Data Word Fall Through when FIFO1 is Empty (FWFT Mode)
25
IDT723656/723666/723676 CMOS TRIPLE BUS SyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
tCLK
tCLKH tCLKL
CLKA
CSA
LOW
WRA
HIGH tENS2
tENH
tENS2
tENH
tDS
tDH
MBA
ENA
FFA
HIGH
A0-A35
W1
(1)
tSKEW1
CLKB
tCLK
tCLKH tCLKL
1
2
tREF
EFB
FIFO1 Empty
CSB
LOW
MBB
LOW
tREF
tENS2
tENH
RENB
tA
B0-B17
tA
Read 1
Read 2
5611 drw18
NOTES:
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising
CLKB edge is less than tSKEW1, then the transition of EFB HIGH may occur one CLKB cycle later than shown.
2. If Port B size is word or byte, EFB is set LOW by the last word or byte read from FIFO1, respectively (the word-size case is shown).
Figure 17. EFB Flag Timing and First Data Read Fall Through when FIFO1 is Empty (IDT Standard Mode)
26
IDT723656/723666/723676 CMOS TRIPLE BUS SyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
tCLK
tCLKH tCLKL
CLKC
tENS2
tENH
tENS2
tENH
MBC
WENC
IRC
C0-C17
HIGH
tDS
tDH tDS
Write 1
tDH
Write 2
(1)
tSKEW1
CLKA
ORA
FIFO2 Empty
CSA
LOW
W/RA
LOW
MBA
LOW
tCLK
tCLKH tCLKL
1
2
3
tREF
tENS2
tREF
tENH
ENA
tA
A0-A35
Old Data in FIFO2 Output Register
W1
5611 drw19
NOTES:
1. tSKEW1 is the minimum time between a rising CLKC edge and a rising CLKA edge for ORA to transition HIGH and to clock the next word to the FIFO2 output register in three CLKA cycles.
If the time between the CLKC edge and the rising CLKA edge is less than tSKEW1, then the transition of ORA HIGH and load of the first word to the output register may occur one CLKA
cycle later than shown.
2. If Port C size is word or byte, tSKEW1 is referenced to the rising CLKC edge that writes the last word or byte write of the long word, respectively.
Figure 18. ORA Flag Timing and First Data Word Fall through when FIFO2 is Empty (FWFT Mode)
27
IDT723656/723666/723676 CMOS TRIPLE BUS SyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
tCLK
tCLKH tCLKL
CLKC
tENS2
tENH
tENS2
tENH
MBC
WENC
FFC
C0-C17
HIGH
tDS
tDH tDS
Write 1
tDH
Write 2
(1)
tSKEW1
CLKA
tCLK
tCLKH tCLKL
1
2
tREF
EFA
FIFO2 Empty
CSA
LOW
W/RA
LOW
MBA
LOW
tENS2
tREF
tENH
ENA
tA
A0-A35
W1
5611 drw20
NOTES:
1. tSKEW1 is the minimum time between a rising CLKC edge and a rising CLKA edge for EFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKC edge and rising
CLKA edge is less than tSKEW1, then the transition of EFA HIGH may occur one CLKA cycle later than shown.
2. If Port C size is word or byte, tSKEW1 is referenced to the rising CLKC edge that writes the last word or byte of the long word, respectively.
Figure 19. EFA Flag Timing and First Data Read when FIFO2 is Empty (IDT Standard Mode)
28
IDT723656/723666/723676 CMOS TRIPLE BUS SyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
tCLK
tCLKH
tCLKL
CLKB
CSB
LOW
MBB LOW
tENS2
tENH
RENB
ORB
HIGH
tA
B0-B17
tA
Read 1
Previous Word in
FIFO1 Output Register
CLKA
Read 2
tSKEW1
(1)
tCLKH
1
tCLK
tCLKL
2
tWFF
tWFF
IRA
FIFO1 Full
CSA
LOW
W/RA
HIGH
tENH
tENS2
MBA
tENS2
tENH
ENA
tDS
A0-A35
tDH
Write
To FIFO1
5611 drw21
NOTES:
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for IRA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising
CLKA edge is less than tSKEW1, then IRA may transition HIGH one CLKA cycle later than shown.
2. If Port B size is word or byte, tSKEW1 is referenced to the rising CLKB edge that reads the last word or byte write of the long word, respectively (the word-size case is shown).
Figure 20. IRA Flag Timing and First Available Write when FIFO1 is Full (FWFT Mode)
29
IDT723656/723666/723676 CMOS TRIPLE BUS SyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
tCLK
tCLKH
tCLKL
CLKB
CSB LOW
MBB LOW
tENS2
tENH
RENB
EFB HIGH
tA
B0-B17
tA
Read 1
Previous Word in
FIFO1 Output Register
CLKA
Read 2
tSKEW1
(1)
tCLKH
1
tCLK
tCLKL
2
tWFF
tWFF
FFA FIFO1 Full
CSA
LOW
W/RA
HIGH
tENS2
tENH
tENS2
tENH
MBA
ENA
tDS
A0-A35
tDH
Write
To FIFO1
5611 drw22
NOTES:
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for FFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising
CLKA edge is less than tSKEW1, then FFA may transition HIGH one CLKA cycle later than shown.
2. If Port B size is word or byte, tSKEW1 is referenced from the rising CLKB edge that reads the last word or byte of the long word, respectively (the word-size case is shown).
Figure 21. FFA Flag Timing and First Available Write when FIFO1 is Full (IDT Standard Mode)
30
IDT723656/723666/723676 CMOS TRIPLE BUS SyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
tCLK
tCLKH
tCLKL
CLKA
CSA
LOW
W/RA
LOW
MBA
LOW
tENS2
tENH
ENA
ORA
A0-A35
HIGH
tA
Next Word From FIFO2
Previous Word in FIFO2 Output Register
tSKEW1
CLKC
(1)
tCLKH
1
tCLK
tCLKL
2
tWFF
tWFF
IRC
FIFO2 Full
tENS2
tENH
MBC
tENS2
tENH
WENC
tDS
C0-C17
tDH
tDS
tDH
Write
To FIFO2
5611 drw23
NOTES:
1. tSKEW1 is the minimum time between a rising CLKC edge and a rising CLKC edge for IRC to transition HIGH in the next CLKC cycle. If the time between the rising CLKA edge and rising
CLKC edge is less than tSKEW1, then IRC may transition HIGH one CLKC cycle later than shown.
2. If Port C size is word or byte, IRC is set LOW by the last word or byte write of the long word, respectively (the word-size case is shown).
Figure 22. IRC Flag Timing and First Available Write when FIFO2 is Full (FWFT Mode)
31
IDT723656/723666/723676 CMOS TRIPLE BUS SyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
tCLK
tCLKH
tCLKL
CLKA
CSA
LOW
W/RA
LOW
MBA
LOW
tENS2
tENH
ENA
EFA
A0-A35
HIGH
tA
Previous Word in FIFO2 Output Register
Next Word From FIFO2
tSKEW1(1)
tCLKH
1
CLKC
tCLK
tCLKL
2
tWFF
FFC
tWFF
FIFO2 Full
tENS2
tENH
tENS2
tENH
MBC
ENC
tDH
tDS
C0-C17
tDS
tDH
Write
To FIFO2
5611 drw24
NOTES:
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKC edge for FFC to transition HIGH in the next CLKC cycle. If the time between the rising CLKA edge and rising
CLKC edge is less than tSKEW1, then FFC may transition HIGH one CLKC cycle later than shown.
2. If Port C size is word or byte, FFC is set LOW by the last word or byte write of the long word, respectively (the word-size case is shown).
Figure 23. FFC Flag Timing and First Available Write when FIFO2 is Full (IDT Standard Mode)
CLKA
tENS2
tENH
ENA
tSKEW2
CLKB
(1)
1
2
tPAE
tPAE
AEB
X1 Word in FIFO1
(X1+1) Words in FIFO1
tENS2
tENH
RENB
5611 drw 25
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising
CLKB edge is less than tSKEW2, then AEB may transition HIGH one CLKB cycle later than shown.
2. FIFO1 Write (CSA = LOW, W/RA = LOW, MBA = LOW), FIFO1 read (CSB = LOW, MBB = LOW). Data in the FIFO1 output register has been read from the FIFO.
3. If Port B size is word or byte, AEB is set LOW by the last word or byte read from FIFO1, respectively.
Figure 24. Timing for AEB when FIFO1 is Almost-Empty (IDT Standard and FWFT Modes)
32
IDT723656/723666/723676 CMOS TRIPLE BUS SyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
CLKC
tENS2
tENH
WENC
tSKEW2
(1)
CLKA
1
2
tPAE
tPAE
AEA
X2 Words in FIFO2
(X2+1) Words in FIFO2
tENS2
tENH
ENA
5611 drw 26
NOTES:
1. tSKEW2 is the minimum time between a rising CLKC edge and a rising CLKA edge for AEA to transition HIGH in the next CLKA cycle. If the time between the rising CLKC edge and rising
CLKA edge is less than tSKEW2, then AEA may transition HIGH one CLKA cycle later than shown.
2. FIFO2 Write (MBC = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO.
3. If Port C size is word or byte, tSKEW2 is referenced to the rising CLKC edge that writes the last word or byte of the long word, respectively.
Figure 25. Timing for AEA when FIFO2 is Almost-Empty (IDT Standard and FWFT Modes)
tSKEW2
(1)
1
CLKA
tENS2
2
tENH
ENA
tPAF
AFA
tPAF
(D-Y1) Words in FIFO1
[D-(Y1+1)] Words in FIFO1
CLKB
tENH
tENS2
RENB
5611 drw 27
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKA edge and rising
CLKB edge is less than tSKEW2, then AFA may transition HIGH one CLKA cycle later than shown.
2. FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, MBB = LOW). Data in the FIFO1 output register has been read from the FIFO.
3. D = Maximum FIFO Depth = 2,048 for the IDT723656, 4,096 for the IDT723666, 8,192 for the IDT723676.
4. If Port B size is word or byte, tSKEW2 is referenced from the rising CLKB edge that reads the last word or byte of the long word, respectively.
Figure 26. Timing for AFA when FIFO1 is Almost-Full (IDT Standard and FWFT Modes)
tSKEW2
(1)
1
CLKC
tENS2
2
tENH
WENC
tPAF
tPAF
AFC
(D-Y2) Words in FIFO2
[D-(Y2+1)] Words in FIFO2
CLKA
tENS2
tENH
ENA
5611 drw 28
NOTES:
1. tSKEW2 is the minimum time between a rising CLKC edge and a rising CLKA edge for AFC to transition HIGH in the next CLKC cycle. If the time between the rising CLKC edge and rising
CLKA edge is less than tSKEW2, then AFC may transition HIGH one CLKC cycle later than shown.
2. FIFO2 write (MBC = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO.
3. D = Maximum FIFO Depth = 2,048 for the IDT723656, 4,096 for the IDT723666, 8,192 for the IDT723676.
4. Port C size is word or byte, AFC is set LOW by the last word or byte write of the long word, respectively.
Figure 27. Timing for AFC when FIFO2 is Almost-Full (IDT Standard and FWFT Modes)
33
IDT723656/723666/723676 CMOS TRIPLE BUS SyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
CLKA
tENS1
tENH
tENS1
tENH
tENS2
tENH
tENS2
tENH
CSA
W/RA
MBA
ENA
tDS
W1
A0-A35
tDH
CLKB
tPMF
tPMF
MBF1
CSB
MBB
tENS2
tENH
RENB
tEN
B0-B17
tMDV
FIFO1 Output Register
tPMR
tDIS
W1 (Remains valid in Mail1 Register after read)
5611 drw29
NOTE:
1. If Port B is configured for word size, data can be written to the Mail1 register using A0-A17 (A18-A35 are don't care inputs). In this first case B0-B17 will have valid data. If Port
B is configured for byte size, data can be written to the Mail1 Register using A0-A8 (A9-A35 are don't care inputs). In this second case, B0-B8 will have valid data (B9-B17 will
be indeterminate).
Figure 28. Timing for Mail1 Register and MBF1 Flag (IDT Standard and FWFT Modes)
CLKC
tENS2
tENH
tENS2
tENH
MBC
ENC
tDS
W1
C0-C17
tDH
CLKA
tPMF
tPMF
MBF2
CSA
W/RA
MBA
tENS2
tENH
ENA
tPMR
tMDV
FIFO2 Output Register
tEN
A0-A35
tDIS
W1 (Remains valid in Mail2 Register after read)
5611 drw30
NOTE:
1. If Port C is configured for word size, data can be written to the Mail2 register using C0-C17. In this first case, A18-A35 will have valid data (A0-A17 will be indeterminate). If Port C is configured
for byte size, data can be written to the Mail2 register using C0-C8 (C9-C17 are don't care inputs). In this second case, A18-A26 will have valid data (A0-A17 and A27-A35 will be
indeterminate).
Figure 29. Timing for Mail2 Register and MBF2 Flag (IDT Standard and FWFT Modes)
34
IDT723656/723666/723676 CMOS TRIPLE BUS SyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
CLKA
1
CLKB
2
4
3
2
1
COMMERCIAL TEMPERATURE RANGE
3
4
tENS2
tENH
RENB
tRSTH
tRSTS
RT1
tRTMS
tRTMH
RTM
(2)
(2)
tREF
tREF
EFB
tA
B0-Bn
Wx
W1
5611 drw31
NOTES:
1. CSB = LOW
2. Retransmit setup is complete after EFB returns HIGH, only then can a read operation begin.
3. W1 = first word written to the FIFO1 after Master Reset on FIFO1.
4. No more than D-2 may be written to the FIFO1 between Reset of FIFO1 (Master or Partial) and Retransmit setup. Therefore, FFA will be LOW throughout the Retransmit
setup procedure. D = 2,048, 4,096 and 8,192 for the IDT723656, IDT723666 and IDT723676 respectively.
Figure 30. Retransmit Timing for FIFO1 (IDT Standard Mode)
CLKC
1
CLKA
2
1
4
3
2
3
4
tENS2
tENH
ENA
tRSTH
tRSTS
RT2
tRTMS
tRTMH
RTM
(2)
(2)
tREF
tREF
EFA
tA
A0-An
Wx
W1
5611 drw32
NOTES:
1. CSA = LOW
2. Retransmit setup is complete after EFA returns HIGH, only then can a read operation begin.
3. W1 = first word written to the FIFO1 after Master Reset on FIFO2.
4. No more than D-2 may be written to the FIFO1 between Reset of FIFO2 (Master or Partial) and Retransmit setup. Therefore, FFC will be LOW throughout the Retransmit
setup procedure. D = 2,048, 4,096 and 8,192 for the IDT723656, IDT723666 and IDT723676 respectively.
Figure 31. Retransmit Timing for FIFO2 (IDT Standard Mode)
35
IDT723656/723666/723676 CMOS TRIPLE BUS SyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
CLKA
1
CLKB
RENB
RT1
2
4
3
2
1
COMMERCIAL TEMPERATURE RANGE
3
4
LOW
tRSTS
tRSTH
tRTMS
tRTMH
RTM
tREF(2)
tREF(2)
ORB
tA
B0-Bn
Wx
W1
5611 drw33
NOTES:
1. CSB = LOW
2. Retransmit setup is complete after ORB returns HIGH, only then can a read operation begin.
3. W1 = first word written to the FIFO1 after Master Reset on FIFO1.
4. No more than D-2 may be written to the FIFO1 between Reset of FIFO1 (Master or Partial) and Retransmit setup. Therefore, IRA will be LOW throughout the Retransmit
setup procedure. D = 2,049, 4,097 and 8,193 for the IDT723656, IDT723666 and IDT723676 respectively.
Figure 32. Retransmit Timing for FIFO1 (FWFT Mode)
CLKC
1
CLKA
ENA
2
1
4
3
2
3
4
LOW
tRSTH
tRSTS
RT2
tRTMS
tRTMH
RTM
tREF(2)
tREF(2)
ORA
tA
A0-An
Wx
W1
5611 drw34
NOTES:
1. CSA = LOW
2. Retransmit setup is complete after ORA returns HIGH, only then can a read operation begin.
3. W1 = first word written to the FIFO2 after Master Reset on FIFO2.
4. No more than D-2 may be written to the FIFO2 between Reset of FIFO2 (Master or Partial) and Retransmit setup. Therefore, IRC will be LOW throughout the Retransmit
setup procedure. D = 2,049, 4,097 and 8,193 for the IDT723656, IDT723666 and IDT723676 respectively.
Figure 33. Retransmit Timing for FIFO2 (FWFT Mode)
36
IDT723656/723666/723676 CMOS TRIPLE BUS SyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
tCLK
tCLKH
tCLKL
CLKA
LOOP
CSA
W/RA
MBA
tENS2
tENH
tENS2
tENH
tENS2
tENH
ENA
tMDV
tA
tEN
Wn-1(1)
A0-A35
Write to FIFO 1
tA
No Operation
Wn(1)
Write to FIFO 1
tDIS
Wn+1
5611 drw35
NOTES:
1. Data is read from FIFO2 and written into FIFO1 & placed on Port A simultaneously. The first data word written into FIFO1 is the Previous Data Word (Wn-1)
2. All FIFO status flags operate as normal, based on the contents of respective FIFO's.
3. Loopback is available in both Standard IDT and FWFT modes. The diagram above is for both.
Figure 34. Loopback Operation (FIFO2 data transfer to FIFO1 and Port A)
tCLKH
tCLK
tCLKL
CLKA
LOOP
CSA
W/RA
MBA
tENS2
tENH
tENS2
tENH
tENS2
tENH
ENA
tMDV
(4) WRITE
tEN
to FIFO 1
A0-A35
tA
Wn-1(1)
Write to FIFO 1
tA
Wn(1)
Write to FIFO 1
No Operation
tDIS
Wn+1
HIGH-Z
5611 drw36
NOTES:
1. Data is read from FIFO2 and written into FIFO1 only. The data from FIFO2 is NOT placed on Port A. Port A is held in the high impedance state.
2. All FIFO status flags operate as normal, based on the contents of respective FIFO's.
3. Loopback is available in both Standard IDT and FWFT modes. The diagram above is for both.
4. Write operations to FIFO1 cannot be accessed via Port A.
Figure 35. Loopback Operation (FIFO2 data transfer to FIFO1)
37
IDT723656/723666/723676 CMOS TRIPLE BUS SyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
PARAMETER MEASUREMENT INFORMATION
5.0V
1.1KΩ
From Output
Under Test
30 pF
(1)
680Ω
PROPAGATION DELAY
LOAD CIRCUIT
3V
Timing
Input
1.5V
GND
tS
th
GND
tW
3V
1.5V
1.5V
1.5V
1.5V
3V
Data,
Enable
Input
Low-Level
Input
GND
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5V
1.5V
GND
VOLTAGE WAVEFORMS
PULSE DURATIONS
3V
Output
Enable
1.5V
tPLZ
1.5V
tPZL
GND
3V
Input
1.5V
Low-Level
Output
VOL
tPZH
VOH
High-Level
Output
3V
High-Level
Input
1.5V
tPD
tPD
GND
VOH
In-Phase
Output
1.5V
tPHZ
3V
1.5V
1.5V
1.5V
OV
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
4665 drw 37
NOTE:
1. Includes probe and jig capacitance.
Figure 36. Load Circuit and Voltage Waveforms
38
ORDERING INFORMATION
IDT
XXXXXX
Device Type
X
Power
XX
Speed
XX
Package
X
Process/
Temperature
Range
BLANK
Commercial (0°C to +70°C)
PF
Thin Quad Flat Pack (TQFP, PK128-1)
12
15
Commercial Only
L
Low Power
723656
723666
723676
2,048 x 36 x 2  Triple Bus SyncFIFO with Bus-Matching
4,096 x 36 x 2  Triple Bus SyncFIFO with Bus-Matching
8,192 x 36 x 2  Triple Bus SyncFIFO with Bus-Matching
Clock Cycle Time (tCLK)
Speed in Nanoseconds
5611 drw 38
NOTE:
1. Industrial temperature range is available by special order.
DATASHEET DOCUMENT HISTORY
12/21/2000
03/21/2001
08/01/2001
11/03/2003
pgs.
pgs.
pgs.
pg.
13 and 22.
7 and 8.
7, 9, 10 and 39.
1.
CORPORATE HEADQUARTERS
2975 Stender Way
Santa Clara, CA 95054
for SALES:
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com
39
for TECH SUPPORT:
408-330-1753
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