H CAT28C16A EE GEN FR ALO 16K-Bit CMOS PARALLEL EEPROM LE A D F R E ETM FEATURES ■ Fast read access times: 90 ns, 120 ns, 200 ns ■ End of write detection: DATA polling ■ Low power CMOS cissipation: ■ Hardware write protection –Active: 25 mA Max. –Standby: 100 µA Max. ■ CMOS and TTL compatible I/O ■ 10,000 or 100,000 Program/erase cycles ■ Simple write operation: ■ 10 or 100 year data retention –On-chip address and data latches –Self-timed write cycle with auto-clear ■ Commercial, industrial and automotive temperature ranges ■ Fast write cycle time: 10ms max DESCRIPTION The CAT28C16A is a fast, low power, 5V-only CMOS Parallel EEPROM organized as 2K x 8-bits. It requires a simple interface for in-system programming. On-chip address and data latches, self-timed write cycle with auto-clear and VCC power up/down write protection eliminate additional timing and protection hardware. DATA Polling signals the start and end of the self-timed write cycle. Additionally, the CAT28C16A features hardware write protection. The CAT28C16A is manufactured using Catalyst’s advanced CMOS floating gate technology. It is designed to endure 10,000 program/erase cycles and has a data retention of 10 years. The device is available in JEDEC approved 24-pin DIP and SOIC or 32-pin PLCC packages. BLOCK DIAGRAM A4–A10 ADDR. BUFFER & LATCHES ROW DECODER VCC INADVERTENT WRITE PROTECTION HIGH VOLTAGE GENERATOR CE OE WE CONTROL LOGIC 2,048 x 8 EEPROM ARRAY I/O BUFFERS TIMER DATA POLLING I/O0–I/O7 A0–A3 © 2004 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice ADDR. BUFFER & LATCHES COLUMN DECODER 1 Doc. No. 1076, Rev. D CAT28C16A PIN CONFIGURATION A7 A6 1 2 24 23 VCC A5 A4 A3 3 4 5 6 22 21 20 A9 WE OE 19 18 A10 7 8 9 10 11 12 A0 I/O0 I/O1 I/O2 VSS 17 16 15 14 13 A7 A6 A5 A4 A3 1 24 VCC 2 3 23 A8 22 4 5 21 20 A9 WE OE A2 A1 6 7 19 18 A0 I/O0 8 9 17 16 I/O1 I/O2 10 11 12 15 A8 CE I/O7 I/O6 I/O5 I/O4 I/O3 VSS 14 13 A10 CE I/O7 PLCC Package (N, G) 4 3 2 1 32 31 30 A6 A5 5 6 29 28 A4 A3 7 8 9 10 11 12 27 26 25 24 23 22 I/O6 I/O5 A2 A1 A0 I/O4 I/O3 NC I/O0 13 21 14 15 16 17 18 19 20 PIN FUNCTIONS Pin Name TOP VIEW A8 A9 NC NC OE A10 CE I/O7 I/O6 I/O1 I/O2 VSS NC I/O3 I/O4 I/O5 A2 A1 SOIC Package (J, K, W, X) A7 NC NC NC VCC WE NC DIP Package (P, L) Function A0–A10 Address Inputs I/O0–I/O7 Data Inputs/Outputs CE Chip Enable OE Output Enable WE Write Enable VCC 5V Supply VSS Ground NC No Connect MODE SELECTION Mode CE WE OE Read L H Byte Write (WE Controlled) L Byte Write (CE Controlled) I/O Power L DOUT ACTIVE H DIN ACTIVE L H DIN ACTIVE Standby, and Write Inhibit H X X High-Z STANDBY Read and Write Inhibit X H H High-Z ACTIVE CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V Symbol Test Max. Units Conditions CI/O(1) Input/Output Capacitance 10 pF VI/O = 0V CIN(1) Input Capacitance 6 pF VIN = 0V Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. Doc. No. 1076, Rev. D 2 CAT28C16A ABSOLUTE MAXIMUM RATINGS* *COMMENT Temperature Under Bias ................. –55°C to +125°C Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. Storage Temperature ....................... –65°C to +150°C Voltage on Any Pin with Respect to Ground(2) ........... –2.0V to +VCC + 2.0V VCC with Respect to Ground ............... –2.0V to +7.0V Package Power Dissipation Capability (Ta = 25°C) ................................... 1.0W Lead Soldering Temperature (10 secs) ............ 300°C Output Short Circuit Current(3) ........................ 100 mA RELIABILITY CHARACTERISTICS Symbol NEND (1, 7) TDR(1, 7) VZAP (1) ILTH(1)(4) Parameter Min Max Units Endurance 100,000 Cycles/Byte Data Retention 100 Years ESD Susceptibility 2000 Volts Latch-Up 100 mA D.C. OPERATING CHARACTERISTICS VCC = 5V ±10%, unless otherwise specified. Limits Symbol Parameter Min Typ Max Units Test Conditions ICC VCC Current (Operating, TTL) 35 mA CE = OE = VIL, f = 1/tRC min, All I/O’s Open ICCC(5) VCC Current (Operating, CMOS) 25 mA CE = OE = VILC, f = 1/tRC min, All I/O’s Open ISB VCC Current (Standby, TTL) 1 mA CE = VIH, All I/O’s Open ISBC(6) VCC Current (Standby, CMOS) 100 µA CE = VIHC, All I/O’s Open ILI Input Leakage Current –10 10 µA VIN = GND to VCC ILO Output Leakage Current –10 10 µA VOUT = GND to VCC, CE = VIH VIH(6) High Level Input Voltage 2 VCC +0.3 V VIL(5) Low Level Input Voltage –0.3 0.8 V VOH High Level Output Voltage 2.4 VOL Low Level Output Voltage VWI Write Inhibit Voltage 0.4 3.0 V IOH = –400µA V IOL = 2.1mA V Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns. (3) Output shorted for no more than one second. No more than one output shorted at a time. (4) Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC +1V. (5) VILC = –0.3V to +0.3V. (6) VIHC = VCC –0.3V to VCC +0.3V. (7) For the CAT28C16A-20, the minimum endurance is 10,000 cycles and the minimum data retention is 10 years. Doc. No. 1076, Rev. D 3 CAT28C16A A.C. CHARACTERISTICS, Read Cycle VCC = 5V ±10%, unless otherwise specified. Symbol Parameter 28C16A-90 28C16A-12 Min Min Max 90 Max 28C16A-20 Min 120 Max 200 Units tRC Read Cycle Time ns tCE CE Access Time 90 120 200 ns tAA Address Access Time 90 120 200 ns tOE OE Access Time 50 60 80 ns tLZ(1) CE Low to Active Output 0 0 0 ns tOLZ(1) OE Low to Active Output 0 0 0 ns tHZ(1)(2) CE High to High-Z Output 50 50 55 ns tOHZ(1)(2) OE High to High-Z Output 50 50 55 ns tOH(1) Output Hold from Address Change 0 0 0 Figure 1. A.C. Testing Input/Output Waveform(3) 2.4 V 2.0 V INPUT PULSE LEVELS REFERENCE POINTS 0.8 V 0.45 V Figure 2. A.C. Testing Load Circuit (example) 1.3V 1N914 3.3K DEVICE UNDER TEST OUT CL = 100 pF CL INCLUDES JIG CAPACITANCE Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) Output floating (High-Z) is defined as the state when the external data line is no longer driven by the output buffer. (3) Input rise and fall times (10% and 90%) < 10 ns. Doc. No. 1076, Rev. D 4 ns CAT28C16A A.C. CHARACTERISTICS, Write Cycle VCC = 5V ±10%, unless otherwise specified. 28C16A-90 Symbol Parameter Min Max 28C16A-12 Min Max Min Units 10 ms Write Cycle Time tAS Address Setup Time 0 0 10 ns tAH Address Hold Time 100 100 100 ns tCS CE Setup Time 0 0 0 ns tCH CE Hold Time 0 0 0 ns tCW(2) CE Pulse Time 110 110 150 ns tOES OE Setup Time 0 0 15 ns tOEH OE Hold Time 0 0 15 ns tWP(2) WE Pulse Width 110 110 150 ns tDS Data Setup Time 60 60 50 ns tDH Data Hold Time 0 0 10 ns tDL Data Latch Time 5 10 5 10 50 ns .05 100 .05 100 5 Write Inhibit Period After Power-up 5 Max tWC tINIT(1) 5 28C16A-20 20 ms Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) A write pulse of less than 20ns duration will not initiate a write cycle. Doc. No. 1076, Rev. D 5 CAT28C16A DEVICE OPERATION low. The data bus is set to a high impedance state when either CE or OE goes high. This 2-line control architecture can be used to eliminate bus contention in a system environment. Read Data stored in the CAT28C16A is transferred to the data bus when WE is held high, and both OE and CE are held Figure 3. Read Cycle tRC ADDRESS tCE CE tOE OE VIH tLZ WE tOHZ tOLZ DATA OUT tHZ tOH HIGH-Z DATA VALID DATA VALID tAA Figure 4. Byte Write Cycle [WE Controlled] tWC ADDRESS tAS tAH tCH tCS CE OE tOES tWP tOEH WE tDL DATA OUT DATA IN HIGH-Z DATA VALID tDS Doc. No. 1076, Rev. D tDH 6 CAT28C16A Byte Write DATA Polling A write cycle is executed when both CE and WE are low, and OE is high. Write cycles can be initiated using either WE or CE, with the address input being latched on the falling edge of WE or CE, whichever occurs last. Data, conversely, is latched on the rising edge of WE or CE, whichever occurs first. Once initiated, a byte write cycle automatically erases the addressed byte and the new data is written within 10 ms. DATA polling is provided to indicate the completion of a byte write cycle. Once a byte write cycle is initiated, attempting to read the last byte written will output the complement of that data on I/O7 (I/O0–I/O6 are indeterminate) until the programming cycle is complete. Upon completion of the self-timed byte write cycle, all I/O’s will output true data during a read cycle. Figure 5. Byte Write Cycle [CE Controlled] tWC ADDRESS tAS tAH tDL tCW CE tOEH OE tCS tOES tCH WE HIGH-Z DATA OUT DATA IN DATA VALID tDS tDH Figure 6. DATA Polling ADDRESS CE WE tOEH tOES tOE OE tWC I/O7 DIN = X DOUT = X DOUT = X Doc. No. 1076, Rev. D 7 CAT28C16A HARDWARE DATA PROTECTION teristics), provides a 5 to 20 ms delay before a write sequence, after VCC has reached 3.0V min. The following is a list of hardware data protection features that are incorporated into the CAT28C16A. (3) Write inhibit is activated by holding any one of OE low, CE high or WE high. (1) VCC sense provides for write protection when VCC falls below 3.0V min. (4) Noise pulses of less than 20 ns on the WE or CE inputs will not result in a write cycle. (2) A power on delay mechanism, tINIT (see AC charac- Doc. No. 1076, Rev. D 8 CAT28C16A ORDERING INFORMATION Prefix Device # CAT 28C16A Optional Company ID Product Number Suffix N T -20 I Temperature Range Tape & Reel * Package P: PDIP N: PLCC J: SOIC (JEDEC) K: SOIC (EIAJ) L: PDIP (Lead free, Halogen free) G: PLCC (Lead free, Halogen free) W: SOIC (JEDEC) (Lead free, Halogen free) X: SOIC (EIAJ) (Lead free, Halogen free) Speed 90: 90ns 12: 120ns 20: 200ns * -40˚C to +125˚C is available upon request Notes: (1) The device used in the above example is a CAT28C16ANI-20T (PLCC, Industrial temperature, 200 ns Access Time, Tape & Reel). Doc. No. 1076, Rev. D 9 REVISION HISTORY Date 3/30/2004 Revision Comments A Added Green packages in all areas 04/19/04 B Delete data sheet designation Update Block Diagram Update Ordering Information Update Revision History Update Rev Number 09/21/04 C Update Features Update AC Characteristics tables Update Ordering Information 09/22/04 D Minor changes Copyrights, Trademarks and Patents Trademarks and registered trademarks of Catalyst Semiconductor include each of the following: DPP ™ AE2 ™ Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000. CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES. Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur. Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete. Catalyst Semiconductor, Inc. Corporate Headquarters 1250 Borregas Avenue Sunnyvale, CA 94089 Phone: 408.542.1000 Fax: 408.542.1200 www.catsemi.com Publication #: Revison: Issue date: 1076 D 09/22/04