LMV641 www.ti.com SNOSAW3C – SEPTEMBER 2007 – REVISED FEBRUARY 2013 LMV641 10 MHz, 12V, Low Power Amplifier Check for Samples: LMV641 FEATURES DESCRIPTION • • • • • • • • • • • The LMV641 is a low power, wide bandwidth operational amplifier with an extended power supply voltage range of 2.7V to 12V. 1 Guaranteed 2.7V, and ±5V Performance Low Power Supply Current 138 µA High Unity Gain Bandwidth 10 MHz Max Input Offset Voltage 500 µV CMRR 120 dB PSRR 105 dB Input Referred Voltage Noise 14 nV/√Hz 1/f Corner Frequency 4 Hz Output Swing with 2 kΩ Load 40 mV from Rail Total Harmonic Distortion 0.002% @ 1kHz, 2kΩ Temperature Range −40°C to 125°C APPLICATIONS • • • It features 10 MHz of gain bandwidth product with unity gain stability on a typical supply current of 138 μA. Other key specifications are a PSRR of 105 dB, CMRR of 120 dB, VOS of 500 μV, input referred voltage noise of 14 nV/ , and a THD of 0.002%. This amplifier has a rail-to-rail output stage, and a common mode input voltage which includes the negative supply. The LMV641 operates over a temperature range of −40°C to +125°C and is offered in the board space saving 5-Pin SC70, SOT-23, and 8-Pin SOIC packages. Portable equipment Battery powered systems Sensors and instrumentation 20 180 UNITS TESTED = 12,000 18 150 - 10 8 RL = 10 k: 120 PHASE TA = 25°C 12 150 - V = -6V 120 VCM = 0V 14 GAIN (dB) PERCENTAGE (%) V = +6V V = -5V 16 180 + + V = +5V CL = 20 pF 90 60 GAIN 90 60 30 30 0 0 PHASE (°) 2 6 4 -30 -30 2 0 -400 -300 -200 -100 0 100 200 300 400 OFFSET VOLTAGE (PV) Figure 1. Offset Voltage Distribution -60 100 1k 10k 100k 1M 10M -60 100M FREQUENCY (Hz) Figure 2. Open Loop Gain and Phase vs. Frequency These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007–2013, Texas Instruments Incorporated LMV641 SNOSAW3C – SEPTEMBER 2007 – REVISED FEBRUARY 2013 Absolute Maximum Ratings ESD Tolerance www.ti.com (1) (2) (3) Human Body Model 2000V Machine Model 200V Differential Input VID ±0.3V Supply Voltage (VS = V+ - V−) 13.2V V+ +0.3V, V− −0.3V Input/Output Pin Voltage −65°C to +150°C Storage Temperature Range Junction Temperature (4) +150°C Soldering Information Infrared or Convection (20 sec) 235°C Wave Soldering Lead Temp (10 sec) 260°C (1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test conditions, see the Electrical Characteristics Tables. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office / Distributors for availability and specifications. Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC)Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC). The maximum power dissipation is a function of TJ(MAX, θJA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) - TA)/ θJA. All numbers apply for packages soldered directly onto a PC board. (2) (3) (4) Operating Ratings Temperature Range (1) (2) −40°C to 125°C Supply Voltage (VS = V+ - V−) 2.7V to 12V Package Thermal Resistance (θJA) (2) 5-Pin SC70 456°C/W 8-Pin SOIC 166°C/W 5-Pin SOT-23 325°C/W (1) (2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test conditions, see the Electrical Characteristics Tables. The maximum power dissipation is a function of TJ(MAX, θJA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) - TA)/ θJA. All numbers apply for packages soldered directly onto a PC board. 2.7V DC Electrical Characteristics Unless otherwise specified, all limits are guaranteed for TA = 25°C, V+ = 2.7V, V− = 0V, VO = VCM = V+/2, and RL > 1 MΩ. Boldface limits apply at the temperature extremes. Symbol Parameter VOS Input Offset Voltage TC VOS Input Offset Average Drift IB Input Bias Current IOS Input Offset Current CMRR (1) (2) (3) 2 Common Mode Rejection Ratio Conditions Min (1) Typ Max (1) Units 30 500 750 µV (2) μV/°C 0.1 (3) 0V ≤ VCM ≤ 1.7V 89 84 75 95 110 nA 0.9 5 nA 114 dB Limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlations using Statistical Quality Control (SQC) method. Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not guaranteed on shipped production material. Positive current corresponds to current flowing into the device. Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LMV641 LMV641 www.ti.com SNOSAW3C – SEPTEMBER 2007 – REVISED FEBRUARY 2013 2.7V DC Electrical Characteristics (continued) Unless otherwise specified, all limits are guaranteed for TA = 25°C, V+ = 2.7V, V− = 0V, VO = VCM = V+/2, and RL > 1 MΩ. Boldface limits apply at the temperature extremes. Symbol PSRR CMVR Min Typ 2.7V ≤ V+ ≤ 10V, VCM = 0.5 94.5 92.5 105 2.7V ≤ V+ ≤ 12V, VCM = 0.5 94 92 100 Parameter Conditions (1) Power Supply Rejection Ratio Input Common-Mode Voltage Range CMRR ≥ 80 dB CMRR ≥ 68 dB 0 V+/2 + AVOL Large Signal Voltage Gain (2) Max (1) dB 1.8 0.3V ≤ VO ≤ 2.4V, RL = 2 kΩ to 0.4V ≤ VO ≤ 2.3V, RL = 2 kΩ to V /2 82 78 88 0.3V ≤ VO ≤ 2.4V, RL = 10 kΩ to V+/2 0.4V ≤ VO ≤ 2.3V, RL = 10 kΩ to V+/2 86 82 98 42 58 68 RL = 10 kΩ to V+/2, VIN = 100 mV 22 35 40 RL = 2 kΩ to V+/2, VIN = 100 mV 38 48 58 RL = 10 kΩ to V+/2, VIN = 100 mV 18 30 35 VIN_DIFF = 100 mV to VO = V+/2 (4) Sourcing 22 Sinking 25 VO Output Swing Low V dB RL = 2 kΩ to V+/2, VIN = 100 mV Output Swing High Units mV from rail IOUT Sourcing and Sinking Output Current IS Supply Current SR Slew Rate GBW Gain Bandwidth Product en Input-Referred Voltage Noise f = 1 kHz 14 nV/ in Input-Referred Current Noise f = 1 kHz 0.15 pA/ THD Total Harmonic Distortion f = 1 kHz, AV = 2, RL = 2 kΩ 0.014 (4) 138 AV = +1, VO = 1 VPP Rising (10% to 90%) 2.3 Falling (90% to 10%) 1.6 mA 170 220 μA V/μs 10 MHz % The part is not short circuit protected and is not recommended for operation with low resistive loads. Typical sourcing and sinking output current curves are provided in the Typical Performance Characteristics and should be consulted before designing for heavy loads. 10V DC Electrical Characteristics Unless otherwise specified, all limits are guaranteed for TA = 25°C, V+ = 10V, V− = 0V,VO = VCM = V+/2, and RL > 1 MΩ. Boldface limits apply at the temperature extremes. Symbol Parameter VOS Input Offset Voltage TC VOS Input Offset Average Drift IB Input Bias Current IOS Input Offset Current CMRR (1) (2) (3) Common Mode Rejection Ratio Conditions Min (1) Typ Max Units 5 500 750 µV (2) (1) μV/°C 0.1 (3) 0V ≤ VCM ≤ 9V 94 90 70 90 105 nA 0.7 5 nA 120 dB Limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlations using Statistical Quality Control (SQC) method. Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not guaranteed on shipped production material. Positive current corresponds to current flowing into the device. Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LMV641 3 LMV641 SNOSAW3C – SEPTEMBER 2007 – REVISED FEBRUARY 2013 www.ti.com 10V DC Electrical Characteristics (continued) Unless otherwise specified, all limits are guaranteed for TA = 25°C, V+ = 10V, V− = 0V,VO = VCM = V+/2, and RL > 1 MΩ. Boldface limits apply at the temperature extremes. Symbol PSRR CMVR Parameter Conditions Min Typ 2.7V ≤ V+ ≤ 10V, VCM = 0.5V 94.5 92.5 105 2.7V ≤ V+ ≤ 12V, VCM = 0.5V 94 92 100 (1) Power Supply Rejection Ratio Input Common-Mode Voltage Range CMRR ≥ 80 dB CMRR ≥ 76 dB Large Signal Voltage Gain (1) 9.1 0.3V ≤ VO ≤ 9.7V, RL = 2 kΩ to 0.4V ≤ VO ≤ 9.6V, RL = 2 kΩ to V /2 90 85 99 0.3V ≤ VO ≤ 9.7V, RL = 10 kΩ to V+/2 0.4V ≤ VO ≤ 9.6V, RL = 10 kΩ to V+/2 97 92 104 68 95 125 RL = 10 kΩ to V+/2, VIN = 100 mV 37 55 65 RL = 2 kΩ to V+/2, VIN = 100 mV 65 90 110 RL = 10 kΩ to V+/2, VIN = 100 mV 32 42 52 VIN_DIFF = 100 mV to VO = V+/2 (4) Sourcing 26 Sinking 112 VO Output Swing Low V dB RL = 2 kΩ to V+/2, VIN = 100 mV Output Swing High Units dB 0 V+/2 + AVOL Max (2) mV from rail IOUT Sourcing and Sinking Output Current IS Supply Current SR Slew Rate GBW Gain Bandwidth Product en Input-Referred Voltage Noise f = 1 kHz 14 nV/ in Input-Referred Current Noise f = 1 kHz 0.15 pA/ THD Total Harmonic Distortion f = 1 kHz, AV = 2, RL = 2 kΩ 0.002 (4) mA 158 AV = +1, VO = 2V to 8 VPP Rising (10% to 90%) 2.6 Falling (90% to 10%) 1.6 190 240 μA V/μs 10 MHz % The part is not short circuit protected and is not recommended for operation with low resistive loads. Typical sourcing and sinking output current curves are provided in the Typical Performance Characteristics and should be consulted before designing for heavy loads. CONNECTION DIAGRAMS 1 N/C - 2 + 3 - 4 VIN VIN V Figure 3. 5-Pin SOT-23/SC70 Top View 4 8 - 7 + 6 5 N/C + V VOUT N/C Figure 4. 8-Pin SOIC Top View Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LMV641 LMV641 www.ti.com SNOSAW3C – SEPTEMBER 2007 – REVISED FEBRUARY 2013 Typical Performance Characteristics Unless otherwise specified, TA = 25°C, V+ = 10V, V− = 0V, VCM = VS/2. Supply Current vs. Supply Voltage Offset Voltage vs. Supply Voltage 220 40 125°C 20 180 OFFSET VOLTAGE (PV) SUPPLY CURRENT (PA) 200 160 25°C 140 120 -40°C 100 80 0 25°C -20 -40 125°C -60 -80 60 40 -40°C 2 3 4 5 6 7 8 9 -100 10 11 12 2 3 4 SUPPLY VOLTAGE (V) 6 8 9 10 11 12 Figure 6. Offset Voltage vs. VCM Offset Voltage vs. VCM 50 -40°C OFFSET VOLTAGE (PV) -30 -40 25°C -50 -60 -70 125°C -80 + V = +2.7V - V = 0V 30 -40°C 20 10 0 25°C -10 -20 -30 -40 - V = 0V -100 -50 0 + V = +5V 40 -20 -90 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 125°C 0 0.5 1 1.5 Offset Voltage vs. VCM Offset Voltage vs. VCM 50 + V = +10V V = 0V OFFSET VOLTAGE (PV) -40°C 20 10 25°C 0 -10 -20 -30 125°C -40 3 4 5 4 6 7 + - V = 0V -40°C 30 20 10 0 25°C -10 -20 -30 -40 -50 2 3.5 V = +12V 40 - 1 3 Figure 8. 40 0 2.5 Figure 7. 50 30 2 VCM (V) VCM (V) OFFSET VOLTAGE (PV) 7 Figure 5. 0 -10 OFFSET VOLTAGE (PV) 5 SUPPLY VOLTAGE (V) 8 125°C -50 9 0 1 2 3 4 5 6 7 VCM (V) VCM (V) Figure 9. Figure 10. 8 9 10 11 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LMV641 5 LMV641 SNOSAW3C – SEPTEMBER 2007 – REVISED FEBRUARY 2013 www.ti.com Typical Performance Characteristics (continued) Unless otherwise specified, TA = 25°C, V+ = 10V, V− = 0V, VCM = VS/2. Offset Voltage Distribution 20 UNITS TESTED = 12,000 UNITS TESTED = 12,000 V = +1.35V 18 PERCENTAGE (%) TA = 25°C 12 10 8 6 VCM = 0V 14 10 8 6 4 4 2 0 TA = 25°C 12 2 0 -400 -300 -200 -100 - V = -5V 16 VCM = 0V 14 + V = +5V 18 - V = -1.35V 16 PERCENTAGE (%) Offset Voltage Distribution 20 + 0 -400 -300 -200 -100 100 200 300 400 0 100 200 300 400 OFFSET VOLTAGE (PV) OFFSET VOLTAGE (PV) Figure 11. Figure 12. CMRR vs. Frequency PSRR vs. Frequency 130 160 +PSRR + V = 5V 140 V = +5V 110 - V = -5V RL = 1 k: 120 80 100 PSRR (dB) CMRR (dB) + - V = 5V 80 60 -PSRR 70 V+ = +5V - V = -5V -PSRR 50 + V = +1.35V - V = -1.35V 30 40 +PSRR + 10 20 V = +1.35V - V = -1.35V 0 10 100 1k 10k 100k 1M -10 10 10M 1k 100 Figure 14. Input Bias Current vs. VCM Input Bias Current vs. VCM + 100 - 95 V = +2.7V 95 V = 0V 125°C + - V = 0V 125°C 85 80 IBIAS (nA) IBIAS (nA) 10M V = +10V 90 85 25°C 75 70 65 -40°C 80 70 65 60 55 55 0 0.2 0.4 0.6 0.8 1 25°C 75 60 50 6 1M 100k Figure 13. 100 90 10k FREQUENCY (Hz) FREQUENCY (Hz) -40°C 50 1.2 1.4 1.6 1.8 0 1 2 3 4 5 6 VCM (V) VCM (V) Figure 15. Figure 16. Submit Documentation Feedback 7 8 9 Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LMV641 LMV641 www.ti.com SNOSAW3C – SEPTEMBER 2007 – REVISED FEBRUARY 2013 Typical Performance Characteristics (continued) Unless otherwise specified, TA = 25°C, V+ = 10V, V− = 0V, VCM = VS/2. 180 PHASE 120 GAIN 60 CL = 50 pF 30 30 + V = +1.35V - -30 V = -1.35V RL = 2 k: -60 100 10k 1k GAIN (dB) 90 CL = 100 pF 0 150 120 CL = 20 pF 90 60 150 PHASE (°) GAIN (dB) 120 180 0 100k 120 CL = 20 pF 90 CL = 100 pF 60 GAIN 30 0 + V = +5V - -30 V = -5V RL = 2 k: -60 100 10k 1k -60 100M FREQUENCY (Hz) CL = 100 pF 100k 10M 1M 180 150 PHASE Open Loop Gain and Phase with Supply Voltage 180 180 150 150 120 120 90 90 180 150 + V = +5V PHASE - V = -5V 60 60 RL = 10 k: 0 30 0 + V = +6V - GAIN (dB) 90 PHASE (°) GAIN (dB) RL = 2 k: GAIN -30 V = -6V CL = 20 pF -60 100 10k 1k 120 90 60 60 GAIN 30 30 0 0 RL = 10 k: + 10M 1M -30 RL = 2 k: CL = 20 pF -60 100 10k 1k -30 RL = 2 k: 100k -60 100M Figure 18. Open Loop Gain and Phase with Resistive Load 30 -30 CL = 50 pF FREQUENCY (Hz) Figure 17. 120 60 CL = 50 pF 30 0 -30 10M 1M 150 PHASE 90 CL = 100 pF CL = 50 pF 180 PHASE (°) 150 Open Loop Gain and Phase with Capacitive Load 180 PHASE (°) Open Loop Gain and Phase with Capacitive Load -60 100M FREQUENCY (Hz) V = +1.35V -30 - V = -1.35V 100k 10M 1M -60 100M FREQUENCY (Hz) Figure 19. Figure 20. Input Referred Noise Voltage vs. Frequency Close Loop Output Impedance vs. Frequency 1000 1000 + V = +5V 100 AV = +1 100 ZOUT (:) VOLTAGE NOISE (nV/ Hz) - V = -5V NOISE VOLTAGE 10 1 10 0.1 1 0.10 1 10 100 1k 10k 100k 0.01 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) Figure 21. Figure 22. Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LMV641 7 LMV641 SNOSAW3C – SEPTEMBER 2007 – REVISED FEBRUARY 2013 www.ti.com Typical Performance Characteristics (continued) Unless otherwise specified, TA = 25°C, V+ = 10V, V− = 0V, VCM = VS/2. THD+N vs. Frequency THD+N vs. Frequency 0.1 0.1 + V = +5V - V = -5V VIN = 1 VPP 0.01 AV = +2 THD+N (%) THD+N (%) RL = 2 k: 0.01 RL = 10 k: RL = 2 k: + 0.001 V = +1.35V RL = 10 k: - V = -1.35V VIN = 1 VPP AV = +2 0.001 10 100 10k 1k 100k 0.0001 10 100 FREQUENCY (Hz) 1k 10k Figure 23. Figure 24. THD+N vs. VOUT THD+N vs. VOUT 0.1 0.1 THD+N (%) 1 THD+N (%) 1 RL = 100 k: RL = 2 k: 0.01 V+ = +1.35V RL = 2 k: 0.01 V+ = +5V - - V = -1.35V V = -5V VIN = 1 kHz SINE WAVE VIN = 1 kHz SINE WAVE AV = +2 0.001 0.001 100k FREQUENCY (Hz) 0.01 0.1 1 RL = 10 k: AV = +2 0.001 0.001 0.01 10 0.1 VOUT (V) 1 10 VOUT (V) Figure 25. Figure 26. Sourcing Current vs. Supply Voltage Sinking Current vs. Supply Voltage 35 120 + + VOUT = V /2 VOUT = V /2 30 100 25°C 80 20 -40°C 15 -40°C 60 40 125°C 10 8 ISINK (mA) ISOURCE (mA) 25 5 20 0 0 25°C 125°C 2 3 4 5 6 7 8 9 10 11 12 2 3 4 5 6 7 8 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) Figure 27. Figure 28. Submit Documentation Feedback 9 10 Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LMV641 LMV641 www.ti.com SNOSAW3C – SEPTEMBER 2007 – REVISED FEBRUARY 2013 Typical Performance Characteristics (continued) Unless otherwise specified, TA = 25°C, V+ = 10V, V− = 0V, VCM = VS/2. Sourcing Current vs. VOUT 25 45 + V = +1.35V 40 V = -1.35V 20 + V = +1.35V 25°C - - V = -1.35V 35 -40°C 30 -40°C 15 10 ISINK (mA) ISOURCE (mA) Sinking Current vs. VOUT 125°C 25 25°C 20 125°C 15 10 5 5 0 0 0 0.5 1 1.5 2 2.5 1.5 2 2.5 VOUT FROM RAIL (V) Figure 29. Figure 30. Sourcing Current vs. VOUT 35 1 0.5 0 VOUT FROM RAIL (V) Large Signal Transient 1.5 + V = +5V - 30 V = -5V 1 25°C 0.5 -40°C 20 VOUT (mV) ISOURCE (mA) 25 15 125°C + V = +5V - V = -5V 0 CL = 15 pF, AV = +1 VIN = 2 VPP, 20 kHz -0.5 10 -1 5 0 0 1 2 3 4 5 6 7 8 9 -1.5 10 20 40 60 TIME (Ps) Figure 31. Figure 32. Small Signal Transient Response 30 0 VOUT FROM RAIL (V) CL = 125 pF, AV = +1 25 V = +5V 20 V = -5V 100 Small Signal Transient Response 30 + 80 + CL = 15 pF, AV = +1 V = +5V 25 - VIN = 20 mVPP, 20 kHz VIN = 20 mVPP, 20 kHz V = -5V 20 15 15 VOUT (mV) VOUT (mV) 10 5 0 -5 -10 5 0 -5 -15 -10 -20 -15 -25 -30 10 0 20 40 -20 60 70 80 0 20 40 60 TIME (Ps) TIME (Ps) Figure 33. Figure 34. 80 100 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LMV641 9 LMV641 SNOSAW3C – SEPTEMBER 2007 – REVISED FEBRUARY 2013 www.ti.com Typical Performance Characteristics (continued) Unless otherwise specified, TA = 25°C, V+ = 10V, V− = 0V, VCM = VS/2. Output Swing High vs. Supply Voltage Output Swing Low vs. Supply voltage 100 100 RL = 2 k: RL = 2 k: 90 125°C VOUT FROM RAIL (mV) VOUT FROM RAIL (mV) 90 80 70 25°C 60 50 80 125°C 70 25°C 60 -40°C 50 -40°C 40 40 30 30 2 3 4 5 6 7 8 9 10 11 12 2 4 5 6 7 8 9 10 11 12 SUPPLY VOLTAGE (V) Figure 35. Figure 36. Output Swing High vs. Supply Voltage Output Swing Low and Supply Voltage 50 50 RL = 10 k: RL = 10 k: 45 45 125°C VOUT FROM RAIL (mV) VOUT FROM RAIL (mV) 3 SUPPLY VOLTAGE (V) 25°C 40 35 30 -40°C 25 40 125°C 35 25°C 30 -40°C 25 20 20 15 15 2 3 4 5 6 7 8 9 10 11 12 2 3 4 5 6 7 8 9 10 11 12 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) Figure 37. Figure 38. Slew Rate vs. Supply Voltage 3 RISING SLEW RATE (V/Ps) 2.5 2 1.5 FALLING 1 0.5 RL = 1 M: CL = 20 pF 0 2 3 4 5 6 7 8 9 10 SUPPLY VOLTAGE (V) Figure 39. 10 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LMV641 LMV641 www.ti.com SNOSAW3C – SEPTEMBER 2007 – REVISED FEBRUARY 2013 APPLICATION INFORMATION ADVANTAGES OF THE LMV641 Low Voltage and Low Power Operation The LMV641 has performance guaranteed at supply voltages of 2.7V and 10V. It is guaranteed to be operational at all supply voltages between 2.7V and 12.0V. The LMV641 draws a low supply current of 138 µA. The LMV641 provides the low voltage and low power amplification which is essential for portable applications. Wide Bandwidth Despite drawing the very low supply current of 138 µA, the LMV641 manages to provide a wide unity gain bandwidth of 10 MHz. This is easily one of the best bandwidth to power ratios ever achieved, and allows this op amp to provide wideband amplification while using the minimum amount of power. This makes the LMV641 ideal for low power signal processing applications such as portable media players and other accessories. Low Input Referred Noise The LMV641 provides a flatband input referred voltage noise density of 14 nV/ , which is significantly better than the noise performance expected from a low power op amp. This op amp also feature exceptionally low 1/f noise, with a very low 1/f noise corner frequency of 4 Hz. Because of this the LMV641 is ideal for low power applications which require decent noise performance, such as PDAs and portable sensors. Ground Sensing and Rail-to-Rail Output The LMV641 has a rail-to-rail output stage, which provides the maximum possible output dynamic range. This is especially important for applications requiring a large output swing. The input common mode range of this part includes the negative supply rail which allows direct sensing at ground in a single supply operation. Small Size The small footprint of the packages for the LMV641 saves space on printed circuit boards, and enables the design of smaller and more compact electronic products. Long traces between the signal source and the op amp make the signal path susceptible to noise. By using a physically smaller package, these op amps can be placed closer to the signal source, reducing noise pickup and enhancing signal integrity. STABILITY OF OP AMP CIRCUITS GAIN If the phase margin of the LMV641 is plotted with respect to the capacitive load (CL) at its output, and if CL is increased beyond 100 pF then the phase margin reduces significantly. This is because the op amp is designed to provide the maximum bandwidth possible for a low supply current. Stabilizing the LMV641 for higher capacitive loads would have required either a drastic increase in supply current, or a large internal compensation capacitance, which would have reduced the bandwidth. Hence, if this device is to be used for driving higher capacitive loads, it will have to be externally compensated. STABLE ROC ± 20 dB/decade UNSTABLE ROC = 40 dB/decade 0 FREQUENCY (Hz) Figure 40. Gain vs. Frequency for an Op Amp Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LMV641 11 LMV641 SNOSAW3C – SEPTEMBER 2007 – REVISED FEBRUARY 2013 www.ti.com An op amp, ideally, has a dominant pole close to DC which causes its gain to decay at the rate of 20 dB/decade with respect to frequency. If this rate of decay, also known as the rate of closure (ROC), remains the same until the op amp's unity gain bandwidth, then the op amp is stable. If, however, a large capacitance is added to the output of the op amp, it combines with the output impedance of the op amp to create another pole in its frequency response before its unity gain frequency (Figure 40). This increases the ROC to 40 dB/decade and causes instability. In such a case, a number of techniques can be used to restore stability to the circuit. The idea behind all these schemes is to modify the frequency response such that it can be restored to an ROC of 20 dB/decade, which ensures stability. In The Loop Compensation Figure 41 illustrates a compensation technique, known as in the loop compensation, that employs an RC feedback circuit within the feedback loop to stabilize a non-inverting amplifier configuration. A small series resistance, RS, is used to isolate the amplifier output from the load capacitance, CL, and a small capacitance, CF, is inserted across the feedback resistor to bypass CL at higher frequencies. VIN + RS ROUT - CL RL CF RF RIN Figure 41. In the Loop Compensation The values for RS and CF are decided by ensuring that the zero attributed to CF lies at the same frequency as the pole attributed to CL. This ensures that the effect of the second pole on the transfer function is compensated for by the presence of the zero, and that the ROC is maintained at 20 dB/ decade. For the circuit shown in Figure 41 the values of RS and CF are given by Equation 1. Values of RS and CF required for maintaining stability for different values of CL, as well as the phase margins obtained, are shown in Table 1. RF and RIN are 10 kΩ, RL is 2 kΩ, while ROUT is 680Ω. RS = ROUTRIN RF § RF + 2RIN © 2 RF § ¨ ¨ © CF = ¨¨ CLROUT (1) Table 1. CL (nF) RS (Ω) CF (pF) Phase Margin (°) 0.5 680 10 17.4 1 680 20 12.4 1.5 680 30 10.1 The LMV641 is capable of driving heavy capacitive loads of up to 1 nF without oscillating, however it is recommended to use compensation should the load exceed 1 nF. Using this methodology will reduce any excessive ringing and help maintain the phase margin for stability. The values of the compensation network tabulated above illustrate the phase margin degradation as a function of the capacitive load. Although this methodology provides circuit stability for any load capacitance, it does so at the price of bandwidth. The closed loop bandwidth of the circuit is now limited by RF and CF. 12 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LMV641 LMV641 www.ti.com SNOSAW3C – SEPTEMBER 2007 – REVISED FEBRUARY 2013 Compensation by External Resistor In some applications it is essential to drive a capacitive load without sacrificing bandwidth. In such a case, in the loop compensation is not viable. A simpler scheme for compensation is shown in Figure 42. A resistor, RISO, is placed in series between the load capacitance and the output. This introduces a zero in the circuit transfer function, which counteracts the effect of the pole formed by the load capacitance, and ensures stability. The value of RISO to be used should be decided depending on the size of CL and the level of performance desired. Values ranging from 5Ω to 50Ω are usually sufficient to ensure stability. A larger value of RISO will result in a system with less ringing and overshoot, but will also limit the output swing and the short circuit current of the circuit. Figure 42. Compensation by Isolation Resistor TYPICAL APPLICATIONS ANISOTROPIC MAGNETORESISTIVE SENSOR The low operating current of the LMV641 makes it a good choice for battery operated applications. Figure 43 shows two LMV641s in a portable application with a magnetic field sensor. The LMV641s condition the output from an anisotropic magnetoresistive (AMR) sensor. The sensor is arranged in the form of a Wheatstone bridge. This type of sensor can be used to accurately measure the current (either DC or AC) flowing in a wire by measuring the magnetic flux density, B, emanating from the wire. BRIDGE TEMPCO COMPENSATION NETWORK RA RB STANDOFF DISTANCE x 580: 1% + V x 24.5 k: 1% - B + LMV641 + + x FROM mAs TO 20A HONEYWELL HMC1051Z or EQUIVALENT CONDUCTOR TO BE CURRENT MEASURED VOUT G = 23.2 BW-3 dB = 431 kHz 568 k: 1% I(AC or DC) U2 TO ADC or METER CIRCUITRY 24.5 k: 1% x RTH - U1 LMV641 x V + V 0.1 PF + V 9V ALKALINE BATTERY x 20 k: 5 k: 20 k: OFFSET TRIM Figure 43. A Battery Operated System for Contact-Less Current Sensing Using an Anisotropic Magnetoresistive Sensor Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LMV641 13 LMV641 SNOSAW3C – SEPTEMBER 2007 – REVISED FEBRUARY 2013 www.ti.com In this circuit, the use of a 9-volt alkaline battery exploits the LMV641’s high voltage and low supply current for a low power, portable current sensing application. The sensor converts an incident magnetic field (via the magnetic flux linkage) in the sensitive direction, to a balanced voltage output. The LMV641 can be utilized for moderate to high current sensing applications (from a few milliamps and up to 20A) using a nearby external conductor providing the sensed magnetic field to the bridge. The circuit shows a Honeywell HMC1051Z used as a current sensor. Note that the circuit must be calibrated based on the final displacement of the sensed conductor relative to the measurement bridge. Typically, once the sensor has been oriented properly, with respect to the conductor to be measured, the conductor can be placed about one centimeter away from the bridge and have reasonable capability of measuring from tens of milliamperes to beyond 20 amperes. In Figure 43, U1 is configured as a single differential input amplifier. Its input impedance is relatively low, however, and requires that the source impedance of the sensor be considered in the gain calculations. Also, the asymmetrical loading on the bridge will produce a small offset voltage that can be cancelled out with the offset trim circuit shown in Figure 43. Figure 44 shows a typical magnetoresistive Wheatstone bridge and the Thevenin equivalent of its resistive elements. As we shall see, the Thevenin equivalent model of the sensor is useful in calculating the gain needed in the differential amplifier. VEXC R + 'R R - 'R SIG - SIG + R + 'R R - 'R (a) R/2 SIG + + R/2 SIG - + - WITH 'R << R, THEN RTH | R/2 THUS, VEXC ± VSIG VTH± = 2 (b) Figure 44. Anisotropic Magnetoresistive Wheatstone Bridge Sensor, (a), and Thevenin Equivalent Circuit, (b) Using Thevenin’s Theorem, the bridge can be reduced to two voltage sources with series resistances. ΔR is normally very small in comparison to R, thus the Thevenin equivalent resistance, commonly called the source resistance, can be taken to be R. When a bias voltage is applied between VEXC and ground, in the absence of a magnetic field, all of the resistances are considered equal. The voltage at Sig+ and Sig− is half VEXC, or 4.5V, and Sig+ - Sig− = 0. Bridges are designed such that, when immersed in a magnetic field, opposite resistances in the bridge change by ±ΔR with an amount proportional to the strength of the magnetic field. This causes the bridge's output differential voltage, to change from its half VEXC value. Thus Sig+ - Sig− = Vsig ≠ 0. With four active elements, the output voltage is: 14 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LMV641 LMV641 www.ti.com VSIG = VEXC x SNOSAW3C – SEPTEMBER 2007 – REVISED FEBRUARY 2013 'R R (2) Since ΔR is proportional to the field strength, BS, the amount of output voltage from the sensor is a function of sensor sensitivity, S. This expression can rewritten as VSIG = VEXC · S · BS, where S = material constant (nominally 1 mV/V/gauss) BS = magnetic flux in gauss A simplified schematic of a single op amp, differential amplifier is shown in Figure 45. The Thevenin equivalent circuit of the sensor can be used to calculate the gain of this amplifier. R4 R2 - SIG - VO = [(SIG + ) ± (SIG -)] + SIG + R4 R2 R1 R3 R1 = R2 = R3 = R4 Figure 45. Differential Input Amplifier The Honeywell HMC1051Z AMR sensor has nominal 1 kΩ elements and a sensitivity of 1 mV/V/gauss and is being used with 9V of excitation with a full scale magnetic field range of ±6 gauss. At full-scale, the resistors will have ΔR ≈ 12Ω and 108 mV will be seen from Sig− to Sig+ (refer to Figure 46). 9V 1012: 988: SIG + = 4.554V 988: 1012: VSIG = 108 mV SIG - = 4.446V Figure 46. Sensor Output with No Load Referring to the simplified diagram in Figure 45, and assuming that required full scale at the output of the amplifier is 2.5V, a gain of 23.2 is needed for U1. It is clear from the Thevenin equivalent circuit in Figure 47 that a sensor Thevenin equivalent source resistance, RTHEV, of 500Ω will be in series with both the inverting and noninverting inputs of the LMV641. Therefore, the required gain is: R4 = 23.2 AVCL = RTHEV + R2 (3) Choosing R1 = R2 = 24.5 kΩ, then R4 will be approximately 580 kΩ. The actual values chosen will depend on the full-scale needs of the succeeding circuitry as well as bandwidth requirements. The values shown here provide a −3 dB bandwidth of approximately 431 kHz, and are found as follows. Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LMV641 15 LMV641 SNOSAW3C – SEPTEMBER 2007 – REVISED FEBRUARY 2013 BW-3 dB = www.ti.com GAIN-BANDWIDTH PRODUCT AVCL = 10 MHz = 431 kHz 23.2 580 k: SENSOR 500: 24.5 k: 4.446V - 4.554V + LMV641 500: VO = 2.50V 24.5 k: 580 k: Figure 47. Thevenin Equivalent Showing Required Gain By choosing input resistor values for R1 and R2 that are four to ten times the bridge element resistance, the bridge is minimally loaded and the offset errors induced by the op amp stages are minimized. These resistors should have 1% tolerance, or better, for the best noise rejection and offset minimization. Referring once again to Figure 43, U2 is an additional gain stage with a thermistor element, RTH, in the feedback loop. It performs a temperature compensation function for the bridge so that it will have greater accuracy over a wide range of operational temperatures. With mangetoresistive sensors, temperature drift of the bridge sensitivity is negative and linear, and in the case of the sensor used here, is nominally −3000 PP/M. Thus the gain of U2 needs to increase proportionally with increasing temperature, suggesting a thermistor with a positive temperature coefficient. Selection of the temperature compensation resistor, RTH, depends on the additional gain required, on the thermistor chosen, and is dependent on the thermistor’s %/°C shift in resistance. For best op amp compatibility, the thermistor resistance should be greater than 1000Ω. RTH should also be much less than RA, the feedback resistor. Because the temperature coefficient of the AMR bridge is largely linear, RTH also needs to behave in a linear fashion with temperature, thus RA is placed in parallel with RTH, which acts to linearize the thermistor. Gain Error and Bandwidth Consideration if Using an Analog to Digital Converter The bandwidth available from Figure 43 is dependent on the system closed loop gain required and the maximum gain-error allowed if driving an analog to digital converter (ADC). If the output from the sensor is intended to drive an ADC, the bandwidth will be considerably reduced from the closed-loop corner frequency. This is because the gain error of the pre-amplifier stage needs to be taken into account when calculating total error budget. Good practice dictates that the gain error of the amplifier be less than or equal to half LSB (preferably less in order to allow for other system errors that will eat up a portion of the available error budget) of the ADC. However, at the −3 dB corner frequency the gain error for any amplifier is 29.3%. In reality, the gain starts rolling off long before the −3 dB corner is reached. For example, if the amplifier is driving an 8-bit ADC, the minimum gain error allowed for half LSB would be approximately 0.2%. To achieve this gain error with the op amp, the maximum frequency of interest can be no higher than 1 - 1 2 n+1 § ¨ ¨ © § ¨ ¨1 © 2 - 1 x f-3 dB (4) where n is the bit resolution of the ADC and f−3 dB is the closed loop corner frequency. Given that the LMV641 has a GBW of 10 MHz, and is operating with a closed loop gain of 26.3, its closed loop bandwidth is 380 kHZ, therefore 16 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LMV641 LMV641 www.ti.com SNOSAW3C – SEPTEMBER 2007 – REVISED FEBRUARY 2013 1 § ¨ ¨1 © - 1 2 n+1 § ¨ ¨ © MAX FREQ = 2 - 1 = 0.062 x f-3 dB = 0.062 x 380 kHz = 23.56 kHz (5) which is the highest frequency that can be measured with required accuracy. VOICEBAND FILTER The majority of the energy of recognizable speech is within a band of frequencies between 200 Hz and 4 kHz. Therefore it is beneficial to design circuits which transmit telephone signals that pass only certain frequencies and eliminate unwanted signals (noise) that could interfere with conversations and introduce error into control signals. The pass band of these circuits is defined as the ranges of frequencies that are passed. A telephone system voice frequency (VF) channel has a pass band of 0 Hz to 4 kHz. Specifically for human voices most of the energy content is found from 300 Hz to 3 kHz and any signal within this range is considered an in-band signal. Alternatively, any signal outside this range but within the VF channel is considered an out-of-band signal. To properly recover a voice signal in applications such as cellular phones, cordless phones, and voice pagers, a low power bandpass filter that is matched to the human voice spectrum can be implemented using an LMV641 op amp. Figure 48 shows a multi-feedback, multi-pole filter (2nd order response) with a gain of −1. The lower 3 dB cutoff frequency which is set by the DC blocking capacitor C1 and resistor R1 is 60 Hz and the upper cutoff frequency is 3.5 kHz. The total current consumption is a mere 138 µA. The LV641 is operating with a gain of −1, but the circuit is easily modified to add gain. The op amp is powered from a single supply, hence the need for offset (common-mode) adjustment of its output, which is set to ½ VS via its non-inverting input. This filter is also useful in applications for battery operated talking toys and games. R3 5.23 k: C3 2.2 nF VOICE IN C1 0.5 PF R1 5.23 k: VS R2 12.1 k: LMV641 C2 15 nF VOUT + VS/2 Figure 48. Low Power Voice In-Band Receive Filter for Battery-Powered Portable Use Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LMV641 17 LMV641 SNOSAW3C – SEPTEMBER 2007 – REVISED FEBRUARY 2013 www.ti.com REVISION HISTORY Changes from Revision B (February 2013) to Revision C • 18 Page Changed layout of National Data Sheet to TI Format ........................................................................................................ 17 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LMV641 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) LMV641MA/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LMV64 1MA LMV641MAE/NOPB ACTIVE SOIC D 8 250 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LMV64 1MA LMV641MAX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LMV64 1MA LMV641MF/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM AB9A LMV641MFE/NOPB ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM AB9A LMV641MFX/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM AB9A LMV641MG/NOPB ACTIVE SC70 DCK 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 A99 LMV641MGE/NOPB ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 A99 LMV641MGX/NOPB ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 A99 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com (3) 11-Apr-2013 MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 29-Jan-2016 TAPE AND REEL INFORMATION *All dimensions are nominal Device LMV641MAE/NOPB Package Package Pins Type Drawing SOIC SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant D 8 250 178.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LMV641MAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LMV641MF/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LMV641MFE/NOPB SOT-23 DBV 5 250 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LMV641MFX/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LMV641MG/NOPB SC70 DCK 5 1000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3 LMV641MGE/NOPB SC70 DCK 5 250 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3 LMV641MGX/NOPB SC70 DCK 5 3000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 29-Jan-2016 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMV641MAE/NOPB SOIC D LMV641MAX/NOPB SOIC D 8 250 210.0 185.0 35.0 8 2500 367.0 367.0 35.0 LMV641MF/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0 LMV641MFE/NOPB SOT-23 DBV 5 250 210.0 185.0 35.0 LMV641MFX/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 LMV641MG/NOPB SC70 DCK 5 1000 210.0 185.0 35.0 LMV641MGE/NOPB SC70 DCK 5 250 210.0 185.0 35.0 LMV641MGX/NOPB SC70 DCK 5 3000 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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