Intersil HC4P5509A1-9 Slic subscriber line interface circuit Datasheet

HC-5509A1
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1- 88
PRELIMINARY
May 1997
Features
SLIC
Subscriber Line Interface Circuit
Description
• DI Monolithic High Voltage Process
• Compatible with Worldwide PBX and CO Performance
Requirements
• Controlled Supply of Battery Feed Current with Programmable
Current Limit
• Operates with 5V Positive Supply (VB+)
• Internal Ring Relay Driver and a Utility Relay Driver
• High Impedance Mode for Subscriber Loop
• High Temperature Alarm Output
• Low Power Consumption During Standby Functions
• Switch Hook, Ground Key, and Ring Trip Detection
• Selective Power Denial to Subscriber
• Voice Path Active During Power Denial
• On Chip Op-Amp for 2 Wire Impedance Matching
The HC-5509A1 telephone Subscriber Line Interface Circuit
integrates most of the BORSCHT functions on a monolithic
IC. The device is manufactured in a Dielectric Isolation (DI)
process and is designed for use as a high voltage interface
between the traditional telephone subscriber pair (Tip and
Ring) and the low voltage filtering and coding/decoding functions of the line card. Together with a secondary protection
diode bridge and “feed” resistors, the device will withstand
1000V lightning induced surges, in plastic packages. The
SLIC also maintains specified transmission performance in
the presence of externally induced longitudinal currents. The
BORSCHT functions that the SLIC provides are:
Applications
• Battery Feed with Subscriber Loop Current Limiting
• Solid State Line Interface Circuit for PBX or Central Office
Systems, Digital Loop Carrier Systems
• Hotel/Motel Switching Systems
• Direct Inward Dialing (DID) Trunks
• Voice Messaging PBX’s
• High Voltage 2W/4W, 4W/2W Hybrid
• Overvoltage Protection
• Ring Relay Driver
• Supervisory Signaling Functions
• Hybrid Functions (with External Op-Amp)
• Test (or Battery Reversal) Relay Driver
In addition, the SLIC provides selective denial of power to
subscriber loops, a programmable subscriber loop current
limit from 20 to 60mA, a thermal shutdown with an alarm output and line fault protection. Switch hook detection, ring trip
detection and ground key detection functions are also incorporated in the SLIC device.
Ordering Information
PART NUMBER
TEMP. RANGE
PACKAGE
HC1-5509A1-5
0o to +75oC
HC1-5509A1-9
-40o to +85oC
HC3-5509A1-5
0o to +75oC
HC3-5509A1-9
-40o to +85oC
HC4P5509A1-5
0o to +75oC
HC4P5509A1-9
-40o to +85oC
44 Lead PLCC
HC9P5509A1-5
0o to +75oC
28 Lead SOIC
28 Lead Ceramic DIP
28 Lead Ceramic DIP
28 Lead Plastic DIP
The HC-5509A1 SLIC is ideally suited for line card designs
in PBX and CO systems, replacing traditional transformer
solutions.
28 Lead Plastic DIP
44 Lead PLCC
Pinouts
0
1
RD Active
1
0
Power Down Latch
RESET
21 PR
1
0
Power on RESET
9
20 PRI
1
1
ALM 10
19 VTX
Loop Power
Denial Active
RS
6
23 RD
SHD
7
22 BG
GKD
8
TST
ILMT 11
18 LAO
OUT 1 12
17 VRX
-IN 1 13
16 RFS
TIP 14
15 RING
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
8-131
,
N/C
7
F1
8
F0
TF1
RF1
24 VFB
Normal Loop Feed
RF2
5
0
3 2
1 44 43 42 41 40
39
TF2
VFB
9
38
37
RS
SHD
10
36
11
35
BG
DG
GKD
TST
ALM
N/C
12
34
13
33
PR
PRI
14
15
32
31
VTX
LAO
N/C
16
30
N/C
N/C
17
29
N/C
X
RD
18 19 20 21 22 23 24 25 26 27 28
VRX
N/C
F0
0
4
C2
VB-
25 TF
6 5
ACTION
RFS
N/C
4
F0
N/C
F1
F1
RING
26 RF
AG
3
TIP
N/C
C1
TRUTH TABLE
C1
VB+
27 VB-
N/C
28 C2
2
ILMT
1
OUT 1
-IN 1
N/C
AG
VB+
N/C
HC-5509A1 (PLCC)
TOP VIEW
HC-5509A1 (PDIP, CDIP, SOIC)
TOP VIEW
File Number
3567.1
Specifications HC-5509A1
Absolute Maximum Ratings (Note 1)
Operating Conditions
Relay Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +15V
Maximum Supply Voltages
(V B+) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V
(V B+)-(VB-). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +75V
Junction Temperature Ceramic . . . . . . . . . . . . . . . . . . . . . . +175oC
Junction Temperature Plastic . . . . . . . . . . . . . . . . . . . . . . . . +150oC
Lead Temperature (Soldering 10 Sec.) . . . . . . . . . . . . . . . . +300oC
Operating Temperature Range
HC-5509A1-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to +75oC
HC-5509A1-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
Storage Temperature Range . . . . . . . . . . . . . . . . . -65oC to +150oC
Relay Drivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V to +12V
Positive Power Supply (VB+) . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%
Negative Power Supply (V B-) . . . . . . . . . . . . . . . . . . . . -42V to -58V
Loop Resistance (R L) . . . . . . . . . . . . . . . . . 200Ω to 1750Ω (Note 2)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications
Unless Otherwise Specified, Typical Parameters are at TA = +25oC, Min-Max Parameters are over
Operating Temperature Range, VB- = -48V, VB+ = +5V, AG = DG = BG = 0V. All A.C. Parameters are
specified at 600Ω 2-Wire terminating impedance.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
A.C. TRANSMISSION PARAMETERS
RX Input Impedance
300Hz to 3.4kHz (Note 3)
-
100
-
kΩ
TX Output Impedance
300Hz to 3.4kHz (Note 3)
-
-
20
Ω
4W Input Overload Level
300Hz to 3.4kHz R L = 1200Ω,
600Ω Reference
+1.5
-
-
VPEAK
2W Return Loss
Matched for 600Ω (Note 3)
SRL LO
26
35
-
dB
ERL
30
40
-
dB
SRL HI
30
40
-
dB
2W Longitudinal to Metallic Balance
Off Hook
Per ANSI/IEEE STD 455-1976 (Note 3)
300Hz to 3400Hz
58
63
-
dB
4W Longitudinal Balance
Off Hook
300Hz to 3400Hz (Note 3)
50
55
-
dB
Low Frequency Longitudinal Balance
R.E.A. Test Circuit
-
-
-67
dBmp
ILINE = 40mA TA = +25oC (Note 3)
-
-
23
dBrnC
Longitudinal Current Capability
ILINE = 40mA TA = +25oC (Note 3)
-
-
30
mArms
Insertion Loss
0dBm at 1kHz, Referenced 600Ω
2W/4W
-
±0.05
±0.2
dB
4W/2W
-
±0.05
±0.2
dB
4W/4W
-
-
±0.12
dB
-
±0.02
±0.05
dB
+3 to -40dBm
-
-
±0.05
dB
-40 to -50dBm
-
-
±0.1
dB
-50 to -55dBm
-
-
±0.3
dB
Frequency Response
300Hz to 3400Hz (Note 3) Referenced to
Absolute Level at 1kHz, 0dBm Referenced
600Ω
Level Linearity
Referenced to -10dBm (Note 3)
2W to 4W and 4W to 2W
Absolute Delay
(Note 3)
8-132
Specifications HC-5509A1
Electrical Specifications
Unless Otherwise Specified, Typical Parameters are at TA = +25oC, Min-Max Parameters are over
Operating Temperature Range, VB- = -48V, VB+ = +5V, AG = DG = BG = 0V. All A.C. Parameters are
specified at 600Ω 2-Wire terminating impedance. (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
2W/4W
300Hz to 3400Hz
-
-
1
µs
4W/2W
300Hz to 3400Hz
-
-
1
µs
4W/4W
300Hz to 3400Hz
-
-
1.5
µs
Transhybrid Loss, THL
(Note 3) See Figure 1
-
40
-
dB
Total Harmonic Distortion
2W/4W, 4W/2W, 4W/4W
Reference Level 0dBm at 600Ω
300Hz to 3400Hz (Note 3)
-
-
-52
dB
Idle Channel Noise
(Note 3)
C-Message
-
-
5
dBrnC
Psophometric
-
-
-85
dBmp
3kHz Flat
-
-
15
dBrn
20
29
-
dB
VB+ to 4W
20
29
-
dB
VB- to 2W
20
29
-
dB
VB- to 4W
20
29
-
dB
30
-
-
dB
30
-
-
dB
VB- to 4W
20
25
-
dB
VB- to 4W
20
25
-
dB
50
-
500
µs
Limit Range
20
40
60
mA
Accuracy
10
-
-
%
-
±3
±5
mA
TIP to Ground
-
30
-
mA
RING to Ground
-
60
-
mA
TIP and RING to Ground
-
90
-
mA
Switch Hook Detection Threshold
-
12
15
mA
Ground Key Detection Threshold
8
12
16
mA
2W and 4W
Power Supply Rejection Ratio
VB+ to 2W
VB+ to 4W
VB- to 2W
(Note 3)
30Hz to 200Hz, RL = 600Ω
(Note 3)
200Hz to 16kHz, R L = 600Ω
Ring Sync Pulse Width
D.C. PARAMETERS
Loop Current Programming
Loop Current During Power Denial
RL = 200Ω
Fault Currents
Thermal ALARM Output
Safe Operating Die Temperature Exceeded
140
-
160
o
Ring Trip Comparator Threshold
See Typical Applications for more information
9.5
13.5
17.5
mA
-
0.1
0.5
ms
Dial Pulse Distortion
8-133
C
Specifications HC-5509A1
Unless Otherwise Specified, Typical Parameters are at TA = +25oC, Min-Max Parameters are over
Operating Temperature Range, VB- = -48V, VB+ = +5V, AG = DG = BG = 0V. All A.C. Parameters are
specified at 600Ω 2-Wire terminating impedance. (Continued)
Electrical Specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Relay Driver Outputs
On Voltage VOL
IOL (PR) = 60mA, IOL (RD) = 30mA
-
0.2
0.5
V
Off Leakage Current
VOH = 13.2V
-
±10
±100
µA
Logic ‘0’ V IL
-
-
0.8
V
Logic ‘1’ V IH
2.0
-
5.5
V
0V ≤ VIN ≤ 5V
-
-
±100
µA
Logic ‘0’ V OL
ILOAD = 800µA
-
0.1
0.5
V
Logic ‘1’ V OH
ILOAD = 40µA
2.7
-
-
V
-
200
-
mW
TTL/CMOS Logic Inputs (F0, F1, RS, TEST,
PRI)
Input Current (F0, F1, RS, TEST, PRI)
Logic Outputs
Power Dissipation On Hook
Relay Drivers Off
IB+
VB+ = +5.25V, VB- = -58V, RLOOP =
∞
-
-
6
mA
IB-
VB+ = +5.25V, VB- = -58V, RLOOP =
∞
-6
-
-
mA
Input Offset Voltage
-
±5
-
mV
Input Offset Current
-
±10
-
nA
UNCOMMITED OP AMP PARAMETERS
Differential Input Resistance
(Note 2)
-
1
-
MΩ
Output Voltage Swing
RL = 10kΩ
-
±3
-
VP-P
Small Signal GBW
(Note 2)
-
1
-
MHz
NOTES:
1. Absolute maximum ratings are limiting values, applied individually, beyond which the serviceability of the circuit may be impaired. Functional operability under any of these conditions is not necessarily implied.
2. May Be Extended to 1900Ω With Application Circuit.
3. These parameters are controlled by design or process parameters and are not directly tested. These parameters are characterized upon
initial design release, upon design changes which would affect these characteristics, and at intervals to assure product quality and specification compliance.
Pin Descriptions
DIP/SOIC
PLCC
SYMBOL
DESCRIPTION
1
2
AG
Analog Ground - To be connected to zero potential. Serves as a reference for the transmit output
and receive input terminals.
2
3
VB+
Positive Voltage Source - Most Positive Supply.
3
4
C1
Capacitor #C1 - An external capacitor to be connected between this terminal and analog ground.
Required for proper operation of the loop current limiting function.
4
8
F1
Function Address #1 - A TTL and CMOS compatible input used with F0 function address line to
externally select logic functions. The three selectable functions are mutually exclusive. See Truth
Table on page1. F1 should be toggled high after power is applied.
8-134
HC-5509A1
Pin Descriptions (Continued)
DIP/SOIC
PLCC
SYMBOL
DESCRIPTION
5
9
F0
Function Address #0 - A TTL and CMOS compatible input used with F1 function address line to
externally select logic functions. The three selectable functions are mutually exclusive. See Truth
Table on page 1.
6
10
RS
Ring Synchronization Input - A TTL - compatible clock input. The clock is arranged such that a
positive pulse (50 - 500µs) occurs on the zero crossing of the ring voltage source, as it appears
at the RFS terminal. For Tip side injected systems, the RS pulse should occur on the negative
going zero crossing and for Ring injected systems, on the positive going zero crossing. This ensures that the ring delay activates and deactivates when the instantaneous ring voltage is near
zero. If synchronization is not required, the pin should be tied to +5.
7
11
SHD
Switch Hook Detection - An active low LS TTL compatible logic output. A line supervisory output.
8
12
GKD
Ground Key Detection - An active low LS TTL compatible logic output. A line supervisory output.
9
13
TST
A TTL logic input. A low on this pin will set a latch and keep the SLIC in a power down mode until
the proper F1, F0 state is set and will keep ALM low. See Truth Table on page 1.
10
14
ALM
A LS TTL compatible active low output which responds to the thermal detector circuit when a safe
operating die temperature has been exceeded. When TST is forced low by an external control
signal, ALM is latched low until the proper F1, F0 state and TST input is brought high. The ALM
can be tied directly to the TST pin to power down the part when a thermal fault is detected and
then reset with F0, F1. See Truth Table on page 1. It is possible to ignore transient thermal overload conditions in the SLIC by delaying the response to the TST pin from the ALM. Care must be
exercised in attempting this as continued thermal overstress may reduced component life.
11
18
ILMT
Loop Current Limit - Voltage on this pin sets the short loop current limiting conditions using a resistive voltage divider.
12
19
OUT1
The analog output of the spare operational amplifier.
13
20
-IN1
The inverting analog input of the spare operational amplifier.
14
22
TIP
An analog input connected to the TIP (more positive) side of the subscriber loop through a feed
resistor and ring relay contact. Functions with the RING terminal to receive voice signals from
the telephone and for loop monitoring purpose.
15
24
RING
An analog input connected to the RING (more negative) side of the subscriber loop through a
feed resistor. Functions with the TIP terminal to receive voice signals from the telephone and for
loop monitoring purposes.
16
25
RFS
Ring Feed Sense - Senses RING side of the loop for Ground Key Detection. During Ring injected
ringing the ring signal at this node is isolated from RF via the ring relay. For Tip injected ringing,
the RF and RFS pins must be shorted.
17
27
VRX
Receive Input, Four Wire Side - A high impedance analog input. AC signals appearing at this input drive the Tip Feed and Ring Feed amplifiers differentially.
18
31
LAO
Longitudinal Amplifier Output - A low impedance output to be connected to C2 through a low pass
filter. Output is proportional to the difference in ITIP and IRING.
19
32
VTX
Transmit Output, Four Wire Side - A low impedance analog output which represents the differential voltage across TIP and RING. Transhybrid balancing must be performed beyond this output to completely implement two to four wire conversion. This output is referenced to analog
ground. Since the D.C. level of this output varies with loop current, capacitive coupling to the next
stage is necessary.
20
33
PRI
A TTL compatible input used to control PR. PRI active High = PR active low.
21
34
PR
An active low open collector output. Can be used to drive a Polarity Reversal Relay.
NA
35
DG
Digital Ground - To be connected to zero potential - serves as reference for all digital inputs and
outputs on the SLIC.
22
36
BG
Battery Ground - Tube connected to zero potential. All loop current and some quiescent current
flows into this terminal.
8-135
HC-5509A1
Pin Descriptions (Continued)
DIP/SOIC
PLCC
SYMBOL
DESCRIPTION
23
37
RD
Ring Relay Driver - An active low open collector output. Used to drive a relay that switches ringing signals onto the 2-Wire line.
24
38
VFB
Feedback input to the tip feed amplifier; may be used in conjunction with transmit output signal
and the spare op-amp to accommodate 2W line impedance matching.
25
39
TF2
Tip Feed - A low impedance analog output connected to the TIP terminal through a feed resistor.
Functions with the RF terminal to provide loop current, and to feed voice signals to the telephone
set and to sink longitudinal currents. Must be tied to TF1.
NA
40
TF1
Tie directly to TF2 in the PLCC application.
26
41
RF1
Ring Feed - A low impedance analog output connected to the RING terminal through a feed resistor. Functions with the TF terminal to provide loop current, feed voice signals to the telephone
set, and to sink longitudinal currents. Tie directly to RF2.
NA
42
RF2
Tie directly to RF1 in the PLCC application.
27
43
VB-
The battery voltage source. The most negative supply.
28
44
C2
Capacitor #2 - An external capacitor to be connected between this terminal and ground. It prevents false ring trip detection from occurring when longitudinal currents are induced onto the subscriber loop from power lines and other noise sources. This capacitor should be nonpolarized.
1, 5, 6, 7,
15, 16,
17, 21,
23, 26,
28, 29, 30
NC
No internal connection.
NOTE:
1. All grounds (AG, BG, DG) must be applied before V B+ or VB-. Failure to do so may result in premature failure of the part. If a user wishes
to run separate grounds off a line card, the AG must be applied first.
8-136
HC-5509A1
Functional Diagram
DIP OR SOIC
VRX
R
-IN 1
OUT 1
17
12
VFB
13
2R
VTX
VB
19
OP AMP
+
R/2
24
RF1
2R
2R
SHD
TA
+
2R
THERM
LTD
25k
RTD
GKD
LA
+
25k
FAULT
DET
90k
VB/2
REF
3
C1
18
LAO
GM
+
28
C2
RF2
11
ILMT
High voltage surge conditions are as specified in Table 1.
Die Characteristics
Transistor Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Diode Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Die Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 x 120
Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . Connected
Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bipolar-DI
Thermal Constants (oC/W)
θJA
θJC
Ceramic DIP . . . . . . . . . . . . . . . . . . . .
48
12
Plastic DIP . . . . . . . . . . . . . . . . . . . . . .
51
21
PLCC . . . . . . . . . . . . . . . . . . . . . . . . . .
47
17
SOIC . . . . . . . . . . . . . . . . . . . . . . . . . .
72
22
Overvoltage Protection and Longitudinal
Current Protection
The SLIC device, in conjunction with an external protection
bridge, will withstand high voltage lightning surges and
power line crosses.
The SLIC will withstand longitudinal currents up to a maximum or 30mArms, 15mArms per leg, without any performance degradation
.
TABLE 1.
PARAMETER
TEST
CONDITION
PERFORMANCE
(MAX)
UNITS
Longitudinal
Surge
10µs Rise/
±1000 (Plastic)
V PEAK
1000µs Fall
±500 (Ceramic)
V PEAK
Metallic Surge
10µs Rise/
±1000 (Plastic)
V PEAK
1000µs Fall
±500 (Ceramic)
V PEAK
T/GND
10µs Rise/
±1000 (Plastic)
V PEAK
R/GND
1000µs Fall
±500 (Ceramic)
V PEAK
50/60Hz Current
8-137
T/GND
11 Cycles
700 (Plastic)
V RMS
R/GND
Limited to
10Arms
350 (Ceramic)
V RMS
HC-5509A1
Functional Diagram (Continued)
PLCC
VRX
OUT 1
27
R
-IN 1
19
VFB
20
2R
VTX
VB
32
OP AMP
+
R/2
38
RF1
2R
2R
SHD
TA
+
2R
THERM
LTD
25k
RTD
GKD
LA
+
25k
FAULT
DET
90k
RF2
VB/2
REF
4
C1
31
LAO
GM
44
C2
+
18
ILMT
8-138
HC-5509A1
Logic Diagram
RELAY
DRIVER
THERMAL
SHUT DOWN
RMAL
T
WN
CH
INJ
A
B
A
B
C
C
KEY
NOTE: PRI is an independent switch driven by TTL input lev-
8-139
HC-5509A1
Applications Diagram
+5V
SYSTEM CONTROLLER
+5V
K1
K2
R S1 C S1
K1A
TIP
RB1
RB2
RL2
PR
ILIMIT
TIP
VRX+
TF1**
*SECONDARY
PROTECTION
C5
PRIMARY
PROTECTION
SHD GKD PRI RS TEST F1 ALARM F0
RD
VFB
VB-
R S2
C S2
R B3
RING
Z1
FROM PCM
FILTER/CODER
TF2**
CAC
SLIC
HC-5509A1
VTX
KR F
RF2**
KIB
RL1
RB4
V RING
150VPEAK(MAX)
-IN1
RF1**
KZ0
RFS
OUT1
TO HYBIRD
BALANCE
NETWORK
LAO
RING
VB-
BG
C2
***
DG AG VB+ C1
PTC
C3
CF2
C4
RF1
+5V
RF2
CF1
FIGURE 1. TYPICAL LINE CIRCUIT APPLICATION WITH THE MONOLITHIC SLIC
TYPICAL COMPONENT VALUES
C1 = 0.5µF, 30V
KRF = 20kΩ, RF = 2(RB2 + RB4), K = Scaling Factor = 100)
RB1 = RB2 = RB3 = RB4 = 50Ω (1% absolute, matching
requirements covered in a Tech Brief)
RF1 = RF2 = 210kΩ, 1%
CF1 = CF2 = 0.22µF, 10%, 20V Nonpolarized
C3 = 0.01µF, 100V, ±20%
RS1 = RS2 = 1kΩ typically
C4 = 0.01µF, 100V, ±20%
CS1 = CS2 = 0.1µF, 200V typically, depending on VRing and
line length.
C5 = 0.01µF, 100V, ±20%
Z1 = 150V to 200V transient protector. PTC used as ring
generator ballast.
CAC = 0.5µF, 20V
KZ0 = 60kΩ, (Z0 = 600Ω, K = Scaling Factor = 100)
* Secondary protection diode bridge recommended is 3A, 200V
type.
RL1, RL2; Current Limit Setting Resistors:
RL1 + RL2 > 90kΩ → offset
ILIMIT = (0.6) (RL1 + RL2)/(200 x RL2), RL1 typically 100kΩ
**TF1, TF2 and RF1, RF2 are on PLCC only and should be connected together as shown.
***Not Present on DIP or SOIC packages.
NOTES:
1. All grounds (AG, BG, & DG) must be applied before VB+ or VB-. Failure to do so may result in premature failure of the part. If a user wishes
to run separate grounds off a line card, the AG must be applied first.
2. Application shows Ring Injected Ringing, a Balanced or Tip injected configuration may be used.
Additional information is contained in Application Note 549, “The HC-550X Telephone SLICs” By Geoff Phillips
8-140
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