AD ADRF6820 Internal lo frequency range Datasheet

695 MHz to 2700 MHz, Quadrature Demodulator
with Integrated Fractional-N PLL and VCO
ADRF6820
Data Sheet
SCLK
SDIO
ENBL
FUNCTIONAL BLOCK DIAGRAM
15
14
13
24
2
3
8
9
23 25 26 28 38
DC/PHASE
CORRECTION
SERIAL PORT
INTERFACE
4
I+
5
I–
POLYPHASE
FILTER
RFIN0 29
35 LOIN+
RFIN1 22
34 LOIN–
QUAD
DIVIDER
LDO
2.5V
1
19
LDO
VCO
30 31
VPOS_3P3
36
PLL
DC/PHASE
CORRECTION
10
27
33
40
DECL1 TO
DECL4
11
39 REFIN
6
Q–
7
Q+
21
VPOS_5V
11990-001
I/Q demodulator with integrated fractional-N PLL
RF input frequency range: 695 MHz to 2700 MHz
Internal LO frequency range: 356.25 MHz to 2850 MHz
Input P1dB: 14.5 dBm at 1900 MHz RF
Input IP3: 35 dBm at 1900 MHz RF
Programmable HD3/IP3 trim
Single pole, double throw (SPDT) RF input switch
RF digital step attenuation range: 0 dB to 15 dB
Integrated RF tunable balun for single-ended 50 Ω input
Multicore integrated VCO
Demodulated 1 dB bandwidth: 600 MHz
Demodulated 3 dB bandwidth: 1400 MHz
4 selectable baseband gain and bandwidth modes
Digital programmable LO phase offset and dc nulling
Programmable via 3-wire serial port interface (SPI)
40-lead, 6 mm × 6 mm LFCSP
CS
FEATURES
Figure 1.
APPLICATIONS
Cellular W-CDMA/GSM/LTE
Digital predistortion (DPD) receivers
Microwave point-to-point radios
GENERAL DESCRIPTION
The ADRF6820 is a highly integrated demodulator and synthesizer
ideally suited for next generation communication systems. The
feature rich device consists of a high linearity broadband I/Q
demodulator, an integrated fractional-N phase-locked loop (PLL),
and a low phase noise multicore, voltage controlled oscillator
(VCO). The ADRF6820 also integrates a 2:1 RF switch, an on-chip
tunable RF balun, a programmable RF attenuator, and two low
dropout (LDO) regulators. This highly integrated device fits
within a small 6 mm × 6 mm footprint.
The high isolation 2:1 RF switch and on-chip tunable RF balun
enable the ADRF6820 to support two single-ended, 50 Ω
terminated RF inputs. A programmable attenuator ensures
an optimal differential RF input level to the high linearity
demodulator core. The integrated attenuator offers an
attenuation range of 0 dB to 15 dB with a step size of 1 dB.
The ADRF6820 offers two alternatives for generating the
differential local oscillator (LO) input signal: externally via a
high frequency, low phase noise LO signal or internally via the
Rev. C
on-chip fractional-N synthesizer. The integrated synthesizer
enables continuous LO coverage from 356.25 MHz to 2850 MHz.
The PLL reference input can support a wide frequency range
because the divide or multiplication blocks can increase or
decrease the reference frequency to the desired value before it
is passed to the phase frequency detector (PFD).
When selected, the output of the internal fractional-N synthesizer
is applied to a divide-by-2 quadrature phase splitter. From the
external LO path, a 1× LO signal can be applied to the built-in
polyphase filter, or a 2× LO signal can be used with the divideby-2 quadrature phase splitter to generate the quadrature LO
inputs to the mixers.
The ADRF6820 is fabricated using an advanced silicon-germanium
BiCMOS process. It is available in a 40-lead, RoHS-compliant,
6 mm × 6 mm LFCSP package with an exposed paddle.
Performance is specified over the −40°C to +85°C temperature
range.
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ADRF6820
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
LO Generation Block ................................................................. 15
Applications ....................................................................................... 1
Active Mixers .............................................................................. 17
Functional Block Diagram .............................................................. 1
Baseband Buffers ........................................................................ 17
General Description ......................................................................... 1
Serial Port Interface (SPI) ......................................................... 17
Revision History ............................................................................... 2
Power Supply Sequencing ......................................................... 17
Specifications..................................................................................... 3
Applications Information .............................................................. 18
System Specifications ................................................................... 3
Basic Connections ...................................................................... 18
Dynamic Performance ................................................................. 3
RF Balun Insertion Loss Optimization ................................... 20
Synthesizer/PLL Specifications ................................................... 5
Bandwidth Select Modes ........................................................... 21
Digital Logic Specifications ......................................................... 6
IP3 and Noise Figure Optimization ......................................... 23
Absolute Maximum Ratings ............................................................ 7
I/Q Output Loading ................................................................... 26
Thermal Resistance ...................................................................... 7
Image Rejection .......................................................................... 27
ESD Caution .................................................................................. 7
I/Q Polarity.................................................................................. 28
Pin Configuration and Function Descriptions ............................. 8
Layout .......................................................................................... 29
Typical Performance Characteristics ............................................. 9
Register Map ................................................................................... 30
Theory of Operation ...................................................................... 14
Register Address Descriptions .................................................. 31
RF Input Switch .......................................................................... 14
Outline Dimensions ....................................................................... 45
Tunable Balun ............................................................................. 14
Ordering Guide .......................................................................... 45
RF Attenuator .............................................................................. 15
REVISION HISTORY
8/2016—Rev. B to Rev. C
Changes to Figure 3 .......................................................................... 8
Updated Outline Dimensions ....................................................... 45
4/2015—Rev. A to Rev. B
Changes to Features Section and Figure 1..................................... 1
Changes to Table 1 ............................................................................ 3
Changes to Figure 3 .......................................................................... 8
Changes to Figure 15 and Figure 16............................................. 11
Changes to Figure 25 ...................................................................... 12
Added Power Supply Sequencing Section ................................... 17
Changes to Figure 33 and Table 14............................................... 18
Changes to Figure 38 ...................................................................... 21
Changes to Figure 51 ...................................................................... 27
Changes to Address: 0x00, Reset: 0x0000, Name: SOFT_RESET
Section .............................................................................................. 31
Changes to Address: 0x33, Reset: 0x0000, Name: MOD_CTL1
Section and Table 31....................................................................... 40
3/2014—Rev. 0 to Rev. A
Changes to Features Section ............................................................1
Added LO Harmonic Rejection Parameter and DSA Attenuation
Accuracy Parameter, Table 1 ............................................................3
Changes to Table 2.............................................................................3
Changes to Table 3.............................................................................5
Changes to Figure 5 and Figure 8 ....................................................9
Changes to Figure 21 and Figure 22 ............................................ 12
Changes to Table 17 ....................................................................... 30
Added Address: 0x44, Reset: 0x0000, Name: DIV_SM_CTL
Section and Table 36; Renumbered Sequentially ....................... 43
Changes to Address: 0x45, Reset: 0x0000, Name: VCO_CTL2
Section and Table 37 ...................................................................... 44
Added Address: 0x46, Reset: 0x0000, Name: VCO_RB Section
and Table 38 .................................................................................... 44
12/2013—Revision 0: Initial Version
Rev. C | Page 2 of 45
Data Sheet
ADRF6820
SPECIFICATIONS
SYSTEM SPECIFICATIONS
VPOS_5V = 5 V, VPOS_3P3 = 3.3 V, ambient temperature (TA) = 25°C, high-side LO injection, internal LO mode, RF attenuation range =
0 dB, input IP2/input IP3 tone spacing = 5 MHz and −5 dBm per tone, fIF = 40 MHz for BWSEL = 0 and fIF = 200 MHz for BWSEL = 2.
Table 1.
Parameter
RF INPUT
RF Frequency Range
Return Loss
Input Impedance
Input Power
LO FREQUENCY
Internal LO Frequency Range
External LO Frequency Range
LO Input Level
LO Input Impedance
LO Harmonic Rejection 1
SUPPLY VOLTAGE 2
VPOS_3P3
VPOS_5V
RF ATTENUATION RANGE
Digital Step Attenuator (DSA)
IF OUTPUTS
Gain Flatness
Quadrature Phase Error
I/Q Amplitude Imbalance
Output DC Offset
Output Common Mode
I/Q Output Impedance
TOTAL POWER CONSUMPTION
1
2
Test Conditions/Comments
Min
Typ
695
Max
2700
15
50
18
356.25
350
−6
50
−30
2× LO at output of external LO (LO = 1900 MHz)
Step size = 1 dB
Step error between two adjacent DSA code
Attenuation accuracy
2850
6000
+6
3.1
4.7
0
3.3
5.0
3.5
5.25
15
±0.5
±1.0
Across any 20 MHz bandwidth
No correction applied
No correction applied
No correction applied
0.2
1
0.1
20
1.5
Differential
External LO, polyphase filter LO path
Internal PLL/VCO, 2× LO path
2.4
50
1100
1400
Unit
MHz
MHz
dB
Ω
dBm
MHz
MHz
MHz
dBm
Ω
dBc
V
V
V
dB
dB
dB
dB
Degrees
dB
mV
V
Ω
mW
mW
Measured with a nominal device with normal supply and temperature.
For information about power supply sequencing, see the Power Supply Sequencing section.
DYNAMIC PERFORMANCE
Table 2.
Parameter
DEMODULATION BANDWIDTH
fRF = 900 MHz
Conversion Gain
Input P1dB
Input IP3
Input IP2
Noise Figure
Test Conditions/Comments
1 dB bandwidth, fLO = 2100 MHz
3 dB bandwidth, fLO = 2100 MHz
Voltage gain
Min
BWSEL0 1
Typ
Max
240
480
+3.5
11
34
65
17
16
Internal LO
External LO
Rev. C | Page 3 of 45
Min
BWSEL21
Typ
Max
600
1400
−2.5
14
38
61
19
18.5
Unit
MHz
MHz
dB
dBm
dBm
dBm
dB
dB
ADRF6820
Parameter
LO to RF Leakage
RF to LO Leakage
LO to IF Leakage
RF to IF Leakage
Isolation 2
fRF = 1900 MHz
Conversion Gain
Input P1dB
Input IP3
Input IP2
Noise Figure
LO to RF Leakage
RF to LO Leakage
LO to IF Leakage
RF to IF Leakage
Isolation2
fRF = 2100 MHz
Conversion Gain
Input P1dB
Input IP3
Input IP2
Noise Figure
LO to RF Leakage
RF to LO Leakage
LO to IF Leakage
RF to IF Leakage
Isolation2
fRF = 2650 MHz
Conversion Gain
Input P1dB
Input IP3
Input IP2
Noise Figure
LO to RF Leakage
RF to LO Leakage
LO to IF Leakage
RF to IF Leakage
Isolation2
1
2
Data Sheet
Test Conditions/Comments
With respect to −5 dBm RF input power
With respect to −5 dBm RF input power
Isolation between RFIN0 to RFIN1
Isolation between RFIN1 to RFIN0
Voltage gain
Internal LO
External LO
With respect to −5 dBm RF input power
With respect to −5 dBm RF input power
Isolation between RFIN0 to RFIN1
Isolation between RFIN1 to RFIN0
Voltage gain
Internal LO
External LO
With respect to −5 dBm RF input power
With respect to −5 dBm RF input power
Isolation between RFIN0 to RFIN1
Isolation between RFIN1 to RFIN0
Voltage gain
Internal LO
External LO
With respect to −5 dBm RF input power
With respect to −5 dBm RF input power
Isolation between RFIN0 to RFIN1
Isolation between RFIN1 to RFIN0
Min
BWSEL0 1
Typ
Max
−82
−67
−78.5
−49
−55
−55
Min
BWSEL21
Typ
Max
−82
−67
−78.5
−49
−55
−55
Unit
dBm
dBm
dBc
dBc
dBc
dBc
+3
12
33
58
18
17.5
−75
−64
−64.5
−43.5
−51
−39
−3
14.5
35
57
20
19.5
−75
−64
−64.5
−43.5
−51
−39
dB
dBm
dBm
dBm
dB
dB
dBm
dBm
dBc
dBc
dBc
dBc
+2.5
12
37
58
18
18
−72.5
−62
−71
−45
−48.5
−36.5
−3
15.5
34
55
20.5
20
−72.5
−62
−71
−45
−48.5
−36.5
dB
dBm
dBm
dBm
dB
dB
dBm
dBm
dBc
dBc
dBc
dBc
+1.5
13
33
64
19.5
19.5
−70
−57
−76
−46
−40.5
−33
−4
16.5
33
55
22
21.5
−70
−57
−76
−46
−40.5
−33
dB
dBm
dBm
dBm
dB
dB
dBm
dBm
dBc
dBc
dBc
dBc
See Table 15.
This is the isolation between the RF inputs. An input signal was applied to RFIN0, while RFIN1 was terminated with 50 Ω. The IF signal amplitude was measured at the
baseband output. Next, the internal switch was configured for RFIN1, and the feedthrough was measured as a delta from the fundamental. This difference is recorded
as the isolation between RFIN0 and RFIN1.
Rev. C | Page 4 of 45
Data Sheet
ADRF6820
SYNTHESIZER/PLL SPECIFICATIONS
VPOS_5V = 5 V, VPOS_3P3 = 3.3 V, ambient temperature (TA) = 25°C, fREF = 153.6 MHz, fREF power = 4 dBm, fPFD = 38.4 MHz, loop filter
bandwidth = 20 kHz, measured at LO output, unless otherwise noted.
Table 3.
Parameter
PLL REFERENCE
Frequency
Amplitude
PLL Step Size 1
PLL Lock Time 2
PFD FREQUENCY
INTERNAL VCO RANGE
REFERENCE SPURS
INTEGRATED PHASE NOISE 3
CLOSED-LOOP PERFORMANCE
20 kHz Loop Filter
Test Conditions/Comments
Min
Typ
Max
Unit
4
320
14
MHz
dBm
Hz
ms
40
5700
MHz
MHz
12
PFD = 30.72 MHz
PFD = 30.72 MHz, charge pump = 500 µA,
loop bandwidth = 40 kHz, antibacklash delay = 0.5 ns,
charge pump bleed current = 78.125 µA down
468.76
5
24
2850
fREF = 153.6 MHz, fPFD = 38.4 MHz, fLO = 1809.6 MHz
fPFD/4
fPFD/2
fPFD × 1
fPFD × 2
fPFD × 3
fPFD × 4
fPFD × 5
1 kHz to 40 MHz integration bandwidth, PFD = 38.4 MHz,
fREF = 153.6 MHz, divide by 4, charge pump = 250 µA,
loop bandwidth = 20 kHz, antibacklash delay = 0 ns,
charge pump bleed current = 46.8 µA down,
LO frequency = 1562.5 MHz
fLO = 1809.6, fREF = 153.6 MHz, fPFD = 38.4 MHz
10 kHz offset
20 kHz offset
100 kHz offset
200 kHz offset
600 kHz offset
1 MHz offset
10 MHz offset
40 MHz offset
<−100
<−100
−90.67
−95
−97
<−100
<−100
0.6
dBc
dBc
dBc
dBc
dBc
dBc
dBc
°rms
−94.7
−95.8
−113
−122.4
−136.5
−141.5
−153.3
−154.6
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Minimum PLL step size is a function of PFD. Value shown is based on PFD = 30.72 MHz, LO_DIV = 2, and the formula fPFD/65535 × 2/LO_DIV.
Lock time is defined as the time it takes from the end of a register write for a change in frequency to the point where the frequency of the output is within 500 Hz of
the intended frequency.
3
Measured with a nominal device with normal supply and temperature.
1
2
Rev. C | Page 5 of 45
ADRF6820
Data Sheet
DIGITAL LOGIC SPECIFICATIONS
Table 4.
Parameter
Input Voltage High, VIH
Input Voltage Low, VIL
Output Voltage High, VOH
Output Voltage Low, VOL
Serial Clock Period
Setup Time Between Data and Rising Edge of SCLK
Hold Time Between Data and Rising Edge of SCLK
Setup Time Between Falling Edge of CS and SCLK
Hold Time Between Rising Edge of CS and SCLK
Minimum Period SCLK in a Logic High State
Minimum Period SCLK in a Logic Low State
Maximum Time Delay Between Falling Edge of SCLK and Output Data Valid for
a Read Operation
Maximum Time Delay Between CS Deactivation and SDIO Bus Return to
High Impedance
Test Conditions/Comments
Min
1.4
IOH = −100 µA
IOL = 100 µA
tSCLK
tDS
tDH
tS
tH
tHIGH
tLOW
tACCESS
2.3
0.2
38
8
8
10
10
10
10
Typ
Max
231
Unit
V
V
V
V
ns
ns
ns
ns
ns
ns
ns
ns
5
ns
0.70
tZ
Timing Diagram
tHIGH
tDS
tS
tH
tSCLK
tACCESS
tLOW
tDH
CS
DON'T CARE
DON'T CARE
tZ
SDIO
DON'T CARE
A6
A5
A4
A3
A2
A1
A0
R/W
D15
D14
D13
Figure 2. Setup and Hold Timing Measurements
Rev. C | Page 6 of 45
D3
D2
D1
D0
DON'T CARE
11990-002
SCLK
Data Sheet
ADRF6820
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 5.
Parameter
VPOS_5V
VPOS_3P3
VOCM
CS, SCLK, SDIO
RFSW
RFIN0, RFIN1
ENBL
VTUNE
LOIN−, LOIN+
REFIN
Operating Temperature Range
Storage Temperature Range
Maximum Junction Temperature
Rating
−0.5 V to +5.5 V
−0.3 V to +3.6 V
−0.3 V to +3.6 V
−0.3 V to +3.6 V
−0.3 V to +3.6 V
2.5 V peak, ac-coupled
−0.3 V to +3.6 V
−0.3 V to +3.6 V
16 dBm, differential
−0.3 V to +3.6 V
−40°C to +85°C
−65°C to +150°C
150°C
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 6. Thermal Resistance
Package Type
40-Lead LFCSP
ESD CAUTION
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. C | Page 7 of 45
θJA
31.93
θJC
1.12
Unit
°C/W
ADRF6820
Data Sheet
40
39
38
37
36
35
34
33
32
31
DECL4
REFIN
GND
CP
VPOS_3P3
LOIN+
LOIN–
DECL3
VTUNE
VPOS_3P3
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
ADRF6820
TOP VIEW
(Not to Scale)
30
29
28
27
26
25
24
23
22
21
VPOS_3P3
RFIN0
GND
DECL2
GND
GND
ENBL
GND
RFIN1
VPOS_5V
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED TO A
GROUND PLANE WITH LOW THERMAL IMPEDANCE.
11990-003
VPOS_5V
VOCM
SDIO
SCLK
CS
MUXOUT
LOOUT+
LOOUT–
VPOS_3P3
RFSW
11
12
13
14
15
16
17
18
19
20
VPOS_3P3
GND
GND
I+
I–
Q–
Q+
GND
GND
DECL1
Figure 3. Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
1, 19, 30, 31, 36
2, 3, 8, 9, 23, 25, 26, 28, 38
4, 5
6, 7
10
11, 21
12
13
14
15
16
Mnemonic
VPOS_3P3
GND
I+, I−
Q−, Q+
DECL1
VPOS_5V
VOCM
SDIO
SCLK
CS
MUXOUT
17, 18
20
22, 29
24
27, 33
32
34, 35
37
39
40
LOOUT+, LOOUT−
RFSW
RFIN1, RFIN0
ENBL
DECL2, DECL3
VTUNE
LOIN−, LOIN+
CP
REFIN
DECL4
EPAD
Description
3.3 V Power Supply.
Ground.
Differential Baseband Outputs, I Channel.
Differential Baseband Outputs, Q Channel.
Decoupling for Mixer Load. Connect a 0.22 µF capacitor from DECL1 to GND.
5 V Power Supply.
Reference Voltage Input. This pin sets the output common-mode level.
SPI Data.
SPI Clock.
Chip Select, Active Low.
Multiplexer Output. Output pin providing the PLL reference signal or the PLL lock
detect.
Differential LO Outputs.
RF Switch Select. Selects between RFIN0 and RFIN1.
RF Inputs. Single pole, double throw switch input.
Enable, Active High.
VCO LDO Decoupling.
VCO Tuning Voltage Input.
Differential LO Inputs.
PLL Charge Pump Output.
PLL Reference Input.
2.5 V LDO Decoupling.
Exposed Pad. The exposed pad must be connected to a ground plane with low thermal
impedance.
Rev. C | Page 8 of 45
Data Sheet
ADRF6820
TYPICAL PERFORMANCE CHARACTERISTICS
VPOS_5V = 5 V, VPOS_3P3 = 3.3 V, RFDSA_SEL = 0, RFSW = 0 (RFIN0), high-side LO, −5 dB per tone for two-tone measurement with
5 MHz tone spacing, unless otherwise noted. For BWSEL0, fIF = 40 MHz, and for BWSEL2, fIF = 200 MHz. For BAL_CIN, BAL_COUT,
MIX_BIAS, DEMOD_RDAC, and DEMOD_CDAC, refer to Table 16.
20
6
EXTERNAL LO
INTERNAL LO
EXTERNAL LO
INTERNAL LO
18
4
16
INPUT P1dB (dBm)
2
0
BWSEL = 2
–2
–4
BWSEL = 2
14
12
10
BWSEL = 0
8
6
4
TA = –40°C
TA = +25°C
TA = +85°C
–8
640
1140
2
1640
2140
2640
0
640
RF FREQUENCY (MHz)
TA = –40°C
TA = +25°C
TA = +85°C
1140
90
BWSEL = 0
80
80
70
70
IIP3 (dBm), IIP2 (dBm)
60
IIP2
50
40
BWSEL = 2
60
50
IIP2
40
30
IIP3
IIP3
20
–40°C
+25°C
+85°C
800 1000 1200 1400 1600 1800 2000 2200 2400 2600 2800
LO FREQUENCY (MHz)
10
800
11990-226
10
600
Figure 8. Input IP3 (IIP3) and Input IP2 (IIP2) vs. LO Frequency over
Temperature, BWSEL = 2
EXTERNAL 2× LO NF
EXTERNAL LO NF
INTERNAL LO NF
750
1000 1250 1500 1750 2000 2250 2500 2750
LO FREQUENCY (MHz)
11990-222
NOISE FIGURE (dB)
TA = –40°C
TA = +25°C
TA = +85°C
1000 1200 1400 1600 1800 2000 2200 2400 2600 2800
LO FREQUENCY (MHz)
Figure 5. Input IP3 (IIP3) and Input IP2 (IIP2) vs. LO Frequency over
Temperature, BWSEL = 0
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
500
–40°C
+25°C
+85°C
11990-227
20
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
500
TA = –40°C
TA = +25°C
TA = +85°C
750
EXTERNAL 2× LO NF
EXTERNAL LO NF
INTERNAL LO NF
1000 1250 1500 1750 2000 2250 2500 2750
LO FREQUENCY (MHz)
Figure 6. Noise Figure vs. LO Frequency, BWSEL = 0
Figure 9. Noise Figure vs. LO Frequency, BWSEL = 2
Rev. C | Page 9 of 45
11990-204
IIP3 (dBm), IIP2 (dBm)
2640
Figure 7. Input P1dB vs. LO Frequency
30
NOISE FIGURE (dB)
2140
LO FREQUENCY (MHz)
Figure 4. Voltage Conversion Gain vs. RF Frequency over Temperature
90
1640
11990-208
–6
11990-207
VOLTAGE CONVERSION GAIN (dB)
BWSEL = 0
ADRF6820
EXTERNAL LO
INTERNAL LO
0.09
–20
–30
–40
LO_DRV_LVL = 11
–50
–60
–70
–80
–90
LO_DRV_LVL = 00
–100
1140
640
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
1640
2640
2140
LO FREQUENCY (MHz)
0
640
1640
1890
2140
2390
2640
–87
–10
–20
RF FEEDTHROUGH
–30
–40
–50
–70
600 800 1000 1200 1400 1600 1800 2000 2200 2400 2600 2700
FREQUENCY (MHz)
11990-223
LO FEEDTHROUGH
Figure 11. RF and LO Feedthrough to IF Output, RF Input = −5 dBm
70
60
55
50
45
40
35
30
25
20
15
10
RF FREQUENCY (MHz)
11990-110
5
0
600 800 1000 1200 1400 1600 1800 2000 2200 2400 2600 2700 2800
–89
–90
–91
–92
640
890
1140
1390
1640
1890
2140
2390
2640
LO FREQUENCY (MHz)
Figure 14. Quadrature Phase Mismatch vs. LO Frequency
RFIN0 TO RFIN1
RFIN1 TO RFIN0
65
–88
Figure 12. Switch Isolation vs. RF Frequency
Rev. C | Page 10 of 45
11990-313
QUADRATURE PHASE MISMATCH (Degrees)
EXTERNAL LO
INTERNAL LO
FEEDTHROUGH (dBm)
1390
Figure 13. I/Q Amplitude Mismatch vs. LO Frequency
0
ISOLATION (dBc)
1140
LO FREQUENCY (MHz)
Figure 10. LO to RF Feedthrough vs. LO Frequency
–60
890
11990-312
LO DRIVER DISABLED
11990-210
LO TO RF FEEDTHROUGH (dBm)
–10
0.10
TA = –40°C
TA = +25°C
TA = +85°C
I/Q AMPLITUDE MISMATCH (dB)
0
Data Sheet
Data Sheet
ADRF6820
0
8
900MHz
1900MHz
2100MHz
2650MHz
6
5
–20
4
3
2
1
0
–1
TA = –40°C
TA = +25°C
TA = +85°C
1kHz OFFSET
–40
BWSEL = 0
PHASE NOISE (dBc/Hz)
VOLTAGE CONVENTION GAIN (dB)
7
BWSEL = 2
–2
–60
10kHz OFFSET
–80
50kHz OFFSET
–100
–120
1MHz OFFSET
–140
–3
–4
–160
10MHz OFFSET
1.85
2.05
2.25
VCM (V)
–180
2.85
900MHz
1900MHz
2100MHz
2650MHz
PHASE NOISE (dBc/Hz)
17
IP1dB (dBm)
16
15
14
13
12
11
BWSEL = 0
1.65
1.85
2.05
2.25
VCM (V)
–80
–85
–90
–95
–100
–105
–110
–115
–120
–125
–130
–135
–140
–145
–150
–155
–160
–165
2.85
4.85
5.35
TA = –40°C
TA = +25°C
TA = +85°C
100kHz OFFSET
500kHz OFFSET
800kHz OFFSET
40MHz OFFSET
3.35
11990-220
10
9
1.45
4.35
Figure 18. Open-Loop Phase Noise for 1 kHz, 10 kHz, 50 kHz, 1 MHz, and
10 MHz Offsets
19
BWSEL = 2
3.85
VCO FREQUENCY (GHz)
Figure 15. Gain vs. Common-Mode Voltage (VCM) for fRF = 900 MHz, fRF =
1900 MHz, fRF = 2100 MHz, and fRF = 2650 MHz for BWSEL = 0 and BWSEL = 2
18
3.35
Figure 16. Input P1dB (IP1dB) vs. Common-Mode Voltage (VCM) for fRF =
900 MHz, fRF = 1900 MHz, fRF = 2100 MHz, and fRF = 2650 MHz
3.85
4.35
4.85
5.35
VCO FREQUENCY (GHz)
11990-224
1.65
11990-219
–6
1.45
11990-225
–5
Figure 19. Open-Loop Phase Noise for 100 kHz, 500 kHz, 800 kHz, and
40 MHz Offsets
–90
350
–95
–100
300
PHASE NOISE (dBc/Hz)
ICC (3.3V), INTERNAL LO
200
ICC (3.3V), EXTERNAL LO
150
100
–110
–120
200kHz OFFSET
–125
–130
500kHz OFFSET
–135
–140
–145
1MHz OFFSET
–150
ICC (5V)
50
100kHz OFFSET
–115
–155
1.55
1.65
1.75
1.85
VCM (V)
1.95
2.05
2.15
2.25
11990-221
40MHz OFFSET
–160
1425 1550 1675 1800 1925 2050 2175 2300 2425 2550 2675 2800
Figure 17. Current Consumption (ICC) vs. Common-Mode Voltage (VCM),
Internal and External LO, fRF = 900 MHz, fRF = 1900 MHz, fRF = 2100 MHz,
fRF = 2100 MHz, and fRF = 2650 MHz
LO FREQUENCY (MHz)
11990-214
ICC (mA)
50kHz OFFSET
–105
250
0
1.45
TA = –40°C
TA = +25°C
TA = +85°C
Figure 20. Closed-Loop Phase Noise vs. LO Frequency, 20 kHz Bandwidth
Loop Filter, Measured with DIV4_EN = 1 (Divide by 2)
Rev. C | Page 11 of 45
ADRF6820
Data Sheet
–60
400
–80
–85
–90
–95
–100
–105
–110
–120
1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9
LO FREQUENCY (GHz)
200
150
100
50
TA = –40°C
TA = +25°C
TA = +85°C
1140
1640
2140
Figure 24. VPOS_3P3 Power Supply Current vs. LO Frequency
0
–60
TA = –40°C
TA = +25°C
TA = +85°C
–65
–70
–5
–80
–85
–90
–95
–100
–10
–15
–20
–105
–25
–110
1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9
LO FREQUENCY (GHz)
–30
11990-212
–120
Figure 22. 2× PFD Spurs vs. LO Frequency, Measured with
DIV4_EN = 1 (Divide by 2)
1.0
1.5
2.0
2.5
COUT
COUT
COUT
COUT
COUT
COUT
COUT
COUT
3.0
3.5
=0
=1
=2
=3
=4
=5
=6
=7
4.0
FREQUENCY (GHz)
Figure 25. RFIN0/RFIN1 Return Loss for Multiple BAL_CIN and BAL_COUT
Combinations
0
–60
–65
0.5
CIN = 0,
CIN = 1,
CIN = 2,
CIN = 3,
CIN = 4,
CIN = 5,
CIN = 6,
CIN = 7,
11990-016
RETURN LOSS (dB)
–75
–115
TA = –40°C
TA = +25°C
TA = +85°C
–5
–70
RETURN LOSS (dB)
–75
–80
–85
–90
–95
–10
–15
–20
–25
–100
–105
–30
–110
–115
1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9
LO FREQUENCY (GHz)
11990-213
REFERENCE SPURS, 3× PFD (dBc)
2640
LO FREQUENCY (MHz)
Figure 21. 1× PFD Spurs vs. LO Frequency, Measured with
DIV4_EN = 1 (Divide by 2)
REFERENCE SPURS, 2× PFD (dBc)
250
0
640
11990-211
–115
300
11990-209
–75
EXTERNAL LO
INTERNAL LO
350
Figure 23. 3× PFD Spurs vs. LO Frequency, Measured with
DIV4_EN = 1 (Divide by 2)
–35
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
FREQUENCY (GHz)
Figure 26. Return Loss of Unused RFINx Port vs. Frequency
Rev. C | Page 12 of 45
11990-035
REFERENCE SPURS, 1× PFD (dBc)
–70
VPOS 3.3V POWER SUPPLY CURRENT (mA)
TA = –40°C
TA = +25°C
TA = +85°C
–65
Data Sheet
ADRF6820
0
0
–2
–5
RETURN LOSS (dB)
RETURN LOSS (dB)
–4
–6
–8
–10
–12
–10
–15
–20
–25
–14
1500
2500
3500
4500
5500
FREQUENCY (MHz)
–35
11990-036
–18
500
0
–10
–15
–20
–25
3500
4500
5500
FREQUENCY (MHz)
11990-037
RETURN LOSS (dB)
–5
2500
300
400
500
600
700
800
Figure 29. I/Q Return Loss vs. Frequency
0
1500
200
FREQUENCY (MHz)
Figure 27. LO Input Return Loss vs. Frequency
–30
500
100
Figure 28. LO Output Return Loss vs. Frequency
Rev. C | Page 13 of 45
900
1000
11990-038
–30
–16
ADRF6820
Data Sheet
THEORY OF OPERATION
The different sections of the ADRF6820 are controlled through
registers programmable via a serial port interface (SPI).
RFIN0 29
50Ω
RFIN1
22
0.1µF
50Ω
Figure 30. Terminating Unused RF Input Ports
TUNABLE BALUN
The ADRF6820 integrates a programmable balun operating
over a 695 MHz to 2700 MHz frequency range. The tunable
balun offers the benefit of ease of drivability with single-ended,
50 Ω RF inputs, and the single-ended-to-differential conversion
of the integrated balun provides additional common-mode
noise rejection.
RFINx
BAL_CIN
REG 0x30[3:1]
RF INPUT SWITCH
The ADRF6820 integrates a SPDT switch where one of two RF
inputs is selected. Selection of the desired RF input is achieved
externally via a control pin or serially via register writes to the
SPI. When compared to the serial write approach, pin control
allows faster switching between the RF inputs. Using the RFSW
pin (Pin 20), the RF input can switch within 100 ns. When serial
port control is used, the switching time is dominated by the latency
of the SPI programming, which is 2.4 µs minimum for a 10 MHz
serial clock.
The RFSW_MUX bit (Register 0x23, Bit 11) selects whether the
RF input switch is controlled via the external pins or via the SPI
(see Table 8). By default at power-up, the device is configured for
pin control. Connecting RFSW to GND selects RFIN0, and
11990-039
Putting all the building blocks of the ADRF6820 together, the
signal path through the device starts at one of two RF inputs
selected by the input multiplexer (mux) and is converted to a
differential signal via a tunable balun. The differential RF signal
is attenuated to an optimal input level via the digital step attenuator
with 15 dB of attenuation range in 1 dB steps. The RF signal is
then mixed with the LO signal in the Gilbert cell mixers down
to an intermediate frequency (IF) or baseband. The emitter
followers further buffer the outputs of the mixers with an
adjustable output common-mode level.
connecting RFSW to VPOS_3P3 selects RFIN1. In serial mode
control, writing to the RFSW_SEL bit (Register 0x23, Bit 9)
allows selection of one of the two RF inputs. If only one RFINx port
is used, the unused RF input must be properly terminated to
improve isolation. The RFIN0/REFIN1 ports are internally
terminated with 50 Ω resistors, and the dc level is 2.5 V. To avoid
disrupting the dc level, the recommended termination is a dc
blocking capacitor to GND. Figure 30 shows the recommended
configuration when only RFIN0 is selected.
BAL_COUT
REG 0x30[7:5]
11990-040
The ADRF6820 integrates many of the essential building blocks
for a high bandwidth quadrature demodulator and receiver,
especially for the feedback downconverter path for the digital
predistortion in cellular base stations. The main features include a
single pole, double throw (SPDT) RF input switch, a variable RF
attenuator, a tunable balun, a pair of active mixers, and two
baseband buffers. Additionally, the local oscillator (LO) signals for
the mixers are generated by a fractional-N synthesizer and a
multicore voltage controlled oscillator (VCO), covering an octave
frequency range with low phase noise. A pair of flip-flops then
divides the LO frequency by two and generates the in-phase and
quadrature phase LO signals to drive the mixers. The synthesizer
uses a fractional-N phase-locked loop (PLL) with additional
frequency dividers to enable continuous LO coverage from
356.25 MHz to 2850 MHz. Alternatively, a polyphase phase splitter
is also available to generate LO signals in quadrature from an
external LO source.
Figure 31. Integrated Tunable Balun
To accomplish RF balun tuning, switch the parallel capacitances
on the primary and secondary sides of the balun by writing to
Register 0x30. The added capacitance in parallel with the inductive
windings of the balun changes the resonant frequency of the
inductor capacitor (LC) tank. Therefore, selecting the proper
combination of BAL_CIN (Register 0x30, Bits[3:1]) and
BAL_COUT (Register 0x30, Bits[7:5]) sets the desired frequency
and optimizes gain. Under most circumstances, the input and
output capacitances are tuned together; however, sometimes for
matching reasons, it is advantageous to tune them independently.
Table 8. RF Input Selection Table
RFSW_MUX (Register 0x23, Bit 11)
0
0
1
1
1
RFSW_SEL SPI Control (Register 0x23, Bit 9)
0
1
X1
X1
X = don’t care.
Rev. C | Page 14 of 45
RFSW Pin Control (Pin 20)
X1
X1
0
1
RF Input
RFIN0
RFIN1
RFIN0
RFIN1
Data Sheet
ADRF6820
RF ATTENUATOR
Internal LO Mode
The RF digital step attenuator (RFDSA) follows the tunable
balun, and the attenuation range is 0 dB to 15 dB with a step
size of 1 dB. The RFDSA_SEL bits (Register 0x23, Bits[8:5]) in
the DGA_CTL register determine the setting of the RFDSA.
For internal LO mode, the ADRF6820 uses the on-chip PLL and
VCO to synthesize the frequency of the LO signal. The PLL,
shown in Figure 32, consists of a reference path, phase and
frequency detector (PFD), charge pump, and a programmable
integer divider with prescaler. The reference path takes in a
reference clock and divides it down by a factor of 2, 4, or 8 or
multiplies it by a factor of 1 or a factor of 2, and then passes it to
the PFD. The PFD compares this signal to the divided down
signal from the VCO. Depending on the PFD polarity selected,
the PFD sends an up/down signal to the charge pump if the
VCO signal is slow/fast compared to the reference frequency.
The charge pump sends a current pulse to the off-chip loop
filter to increase or decrease the tuning voltage (VTUNE).
LO GENERATION BLOCK
The ADRF6820 supports the use of both internal and external
LO signals for the mixers. The internal LO is generated by an
on-chip VCO, which is tunable over an octave frequency range
of 2850 MHz to 5700 MHz. The output of the VCO is phase
locked to an external reference clock through a fractional-N
PLL that is programmable through the SPI control registers.
To produce in-phase and quadrature phase LO signals over the
356.25 MHz to 2850 MHz frequency range to drive the mixers,
steer the VCO outputs through a combination of frequency
dividers, as shown in Figure 32.
The ADRF6820 integrates four VCO cores covering an octave
range of 2.85 GHz to 5.7 GHz.
Table 9 lists the frequency range covered by each VCO. The
desired VCO can be selected by addressing the VCO_SEL bits
(Register 0x22, Bits[2:0]).
Alternatively, an external signal can be used with the dividers or
a polyphase phase splitter to generate the LO signals in quadrature
to the mixers. In demanding applications that require the lowest
possible phase noise performance, it may be necessary to source
the LO signal externally. The different methods in quadrature
LO generation and the control register programming needed
are listed in Table 9.
POLYPHASE
FILTER
I+
REFSEL
REG 0x21[2:0]
÷8
÷4
REFIN 39
÷2
×1
I–
EXTERNAL
LOOP
FILTER
PFD_POLARITY
REG 0x21[3]
PFD
+
×2
CHARGE
PUMP
LOIN+
QUAD_DIV_EN
REG 0x01[9]
35
LOIN– 34
CP
VTUNE
37
32
TO MIXER
Q+
÷1, ÷2,
÷4
QUAD
DIVIDER
Q–
LPF
DIV8 _EN/
DIV4_EN
REG 0x22[4:3]
CP_CTRL
REG 0x20[13:0]
N = INT +
FRAC
MOD
÷2
VCO_SEL
REG 0x22[2:0]
11990-041
DIV_MODE: REG 0x02[11]
INT_DIV: REG 0x02[10:0]
FRAC_DIV: REG 0x03[15:0]
MOD_DIV: REG 0x04[15:0]
Figure 32. LO Generation Block Diagram
Table 9. LO Mode Selection
LO Selection
Internal (VCO)
External (2× LO)
External (1× LO)
fVCO or fEXT (GHz)
2.85 to 3.5
3.5 to 4.02
4.02 to 4.6
4.6 to 5.7
0.7 to 6.0
0.35 to 3.5
Quadrature Generation
Divide by 2
Divide by 2
Divide by 2
Divide by 2
Divide by 2
Polyphase
QUAD_DIV_EN,
Register 0x01[9]
1
1
1
1
1
0
Rev. C | Page 15 of 45
LO Enables,
Register 0x01[6:0]
111 111X
111 111X
111 111X
111 111X
101 000X
000 000X
VCO_SEL,
Register 0x22[2:0]
011
010
001
000
1XX
XXX
ADRF6820
Data Sheet
LO Frequency and Dividers
The signal coming from the VCO or the external LO inputs
goes through a series of dividers before it is buffered to drive
the active mixers. Two programmable divide-by-two stages
divide the frequency of the incoming signal by 1, 2, or 4 before
reaching the quadrature divider that further divides the signal
frequency by 2 to generate the in-phase and quadrature-phase
LO signals for the mixers. The control bits (Register 0x22,
Bits[4:3]) needed to select the different LO frequency ranges
are listed in Table 10.
Table 10. LO Frequency and Dividers
LO Frequency
Range (MHz)
1425 to 2850
712.5 to 1425
356.25 to 712.5
fVCO/fLO or
fEXT LO/fLO
2
4
8
DIV8_EN
(Register 0x22,
Bit 4)
0
0
1
DIV4_EN
(Register 0x22,
Bit 3)
0
1
1
PLL Frequency Programming
The N divider divides down the differential VCO signal to the
PFD frequency. The N divider can be configured for fractional or
integer mode by addressing the DIV_MODE bit (Register 0x02,
Bit 11). The default configuration is set for fractional mode. Use
the following equations to determine the N value and PLL
frequency:
f PFD
f
= VCO
2× N
N = INT +
f LO =
FRAC
MOD
f PFD × 2 × N
LO_DIVIDER
where:
fPFD is the phase frequency detector frequency.
fVCO is the VCO frequency.
N is the fractional divide ratio (INT + FRAC/MOD).
INT is the integer divide ratio programmed in Register 0x02.
FRAC is the fractional divider programmed in Register 0x03.
MOD is the modulus divide ratio programmed in Register 0x04.
fLO is the LO frequency going to the mixer core when the loop is
locked.
LO_DIVIDER is the final frequency divider ratio that divides
the frequency of the VCO or the external LO signal down by 2,
4, or 8 before it reaches the mixer, as shown in Table 10.
PLL Lock Time
The time it takes to lock the PLL after the last register is written
breaks down into two parts: VCO band calibration and loop
settling.
After writing to the last register, the PLL automatically performs
a VCO band calibration to choose the correct VCO band. This
calibration takes approximately 94,208 PFD cycles. For a 40 MHz
fPFD, this corresponds to 2.36 ms. After calibration completes,
the feedback action of the PLL causes the VCO to lock to the
correct frequency eventually. The speed with which this lock
occurs depends on the nonlinear cycle slipping behavior, as well
as the small signal settling of the loop. For an accurate estimation
of the lock time, download the ADIsimPLL tool to capture these
effects correctly. In general, higher bandwidth loops tend to
lock more quickly than lower bandwidth loops.
The lock detect signal is available as one of the selectable outputs
through the MUXOUT pin, with a logic high signifying that the
loop is locked. The control for the MUXOUT pin is located in
the REF_MUX_SEL bits (Register 0x21, Bits[6:4]), and the
default configuration is for PLL lock detect.
Buffered LO Outputs
A buffered version of the internal LO signal is available
differentially at the LOOUT+ and LOOUT− pins (Pin 17 and
Pin 18). When the quadrature LO signals are generated using
the quadrature divider, the output signal is available at either 2×
or 1× the frequency of the LO signal at the mixer. Set the output
to different drive levels by accessing the LO_DRV_LVL bits
(Register 0x22, Bits[7:6]), as shown in Table 11.
The availability of the LO signal makes it possible to daisy-chain
many devices synchronously. One ADRF6820 device can serve
as the master where the LO signal is sourced, and the subsequent
slave devices share the same LO output signal from the master.
This flexibility substantially eases the LO requirements of a
system requiring multiple LOs.
Table 11. LO Output Level
LO_DRV_LVL
(Register 0x22, Bits[7:6])
00
01
10
11
Amplitude (dBm)
−5
−1
+2
+4
DC Level (V)
3.0
2.85
2.7
2.5
External LO Mode
Use the VCO_SEL bits (Register 0x22, Bits[2:0]) to select external
or internal LO mode. To configure for external LO mode, set
Register 0x22, Bits[2:0] to 4 decimal and apply the differential LO
signals to Pin 34 (LOIN−) and Pin 35 (LOIN+). The external LO
frequency range is 350 MHz to 6 GHz. When the polyphase phase
splitter is selected, a 1× LO signal is required for the active mixer,
or a 2× LO signal can be used with the internal quadrature
divider, as shown in Table 9.
The LOIN+ and LOIN− input pins must be ac-coupled. When
not in use, leave the LOIN+ and LOIN− pins unconnected.
Rev. C | Page 16 of 45
Data Sheet
ADRF6820
Required PLL/VCO Settings and Register Write Sequence
Table 13. Baseband Buffer Bias
In addition to writing to the necessary registers to configure the
PLL and VCO for the desired LO frequency and phase noise
performance, the registers in Table 12 are required register writes.
BB_BIAS (Register 0x34, Bits[11:10])
00
01
10
11
To ensure that the PLL locks to the desired frequency, follow the
proper write sequence of the PLL registers. Configure the PLL
registers accordingly to achieve the desired frequency, and the
last writes must be to Register 0x02 (INT_DIV), Register 0x03
(FRAC_DIV), or Register 0x04 (MOD_DIV). When Register 0x02,
Register 0x03, and Register 0x04 are programmed, an internal
VCO calibration initiates, which is the last step to locking the PLL.
Table 12. Required PLL/VCO Register Writes
Address[Bits]
0x21[3]
0x49[15:0]
Bit Name
PFD_POLARITY
RESERVED,
SET_1, SET_0
Setting
0x1
0x14B4
Description
Negative polarity
Internal settings
ACTIVE MIXERS
The signal from the RFDSA is split to drive a pair of double
balanced, Gilbert cell active mixers, to be downconverted by the
LO signals to baseband. Program the current in the mixers by
changing the value of the MIX_BIAS bits (Register 0x31,
Bits[12:10]) for trade-off between output noise and linearity.
The active mixers employ a distortion correction circuit for
cancelling the third-order distortions coming from the mixers.
Determine the amplitude and phase of the correction signals by
the combination of control register entries DEMOD_RDAC and
DEMOD_CDAC (Register 0x31, Bits[8:5] and Register 0x31,
Bits[3:0], respectively). Refer to the IP3 and Noise Figure
Optimization section for more information.
Demodulator gain and bandwidth are set by the resistance and
capacitance in the mixer loads, which are controlled by the
BWSEL bits (Register 0x34, Bits[9:8]) according to Table 15. Refer
to the Bandwidth Select Modes section for more information.
BASEBAND BUFFERS
Emitter followers buffer the signals at the mixer loads and drive
the baseband output pins (I+, I−, Q−, and Q+). Bias currents of
the emitter followers are controlled by the BB_BIAS bits
(Register 0x34, Bits[11:10]), as shown in Table 13. Set the bias
current according to the load driving capabilities needed (that
is, BB_BIAS = 1 for the specified 200 Ω load, and BB_BIAS = 2
for the 50 Ω or 100 Ω loads are recommended). The differential
impedance of the baseband outputs is 50 Ω; however, the
ADRF6820 output load must be high (that is, 200 Ω) for
optimized linearity performance. Refer to the I/Q Output
Loading section for supporting data.
Bias Current (mA)
0
4.5
9
13.5
SERIAL PORT INTERFACE (SPI)
The SPI of the ADRF6820 allows the user to configure the device
for specific functions or operations through a structured register
space provided inside the chip. This interface provides users with
added flexibility and customization. Addresses are accessed via
the serial port interface and can be written to or read from the
serial port interface.
The serial port interface consists of three control lines: SCLK,
SDIO, and CS. SCLK (serial clock) is the serial shift clock, and it
synchronizes the serial interface reads and writes. SDIO is the
serial data input or the serial data output depending on the
instruction sent and the relative position in the timing frame.
CS (chip select bar) is an active low control that gates the read
and write cycles. The falling edge of CS in conjunction with the
rising edge of SCLK determines the start of the frame. When CS
is high, all SCLK and SDIO activity is ignored. See Table 4 for
the serial timing and its definitions.
The ADRF6820 protocol consists of 7 register address bits,
followed by a read/write and 16 data bits. Both the address and
data fields are organized with the most significant bit (MSB)
first and end with the least significant bit (LSB).
On a write cycle, up to 16 bits of serial write data is shifted in,
MSB to LSB. If the rising edge of CS occurs before the LSB of
the serial data is latched, only the bits that were latched are
written to the device. If more than 16 data bits are shifted in, the
16 most recent bits are written to the device. The ADRF6820
input logic level for the write cycle supports an interface as low
as 1.8 V.
On a read cycle, up to 16 bits of serial read data is shifted out,
MSB first. Data shifted out beyond 16 bits is undefined. Read
back content at a given register address does not necessarily
correspond with the write data of the same address. The output
logic level for a read cycle is 2.5 V.
POWER SUPPLY SEQUENCING
The ADRF6820 operates from two nominal supply voltages,
3.3 V and 5 V. Careful consideration must be exercised to
ensure that the voltage on all pins connected to VPOS_3P3
never exceed the voltage on all pins connected to VPOS_5V.
Rev. C | Page 17 of 45
ADRF6820
Data Sheet
APPLICATIONS INFORMATION
BASIC CONNECTIONS
VPOS_3P3
VPOS_3P3
0Ω
(0402)
0Ω
(0402)
RFIN0
1000pF
(0402)
RFIN1
14
13
ENBL
15
PWR_DWN
24
2
3
8
SERIAL PORT
INTERFACE
9
TC4-1W+
23 25 26 28 38
4
DC/PHASE
CORRECTION
29
5
3
4
LOOUT–
18
7
4
6
1
Q+
6
2
3
Q–
÷1, ÷2
POLYPHASE
FILTER
100pF
(0402)
÷8
÷4
÷2
×1
×2
100pF
(0402) REFIN
39
49.9Ω
(0402)
PFD
+
CHARGE
PUMP
34
DIV 2
PHASE
SPLITTER
÷1, ÷2,
0°
÷4
90°
CP
35
32
37
N = INT +
FRAC
MOD
÷2
LOIN–
4
LOCK_DET
VPTAT
SCAN
1
19
30
36
31
27
100pF
(0402)
100pF
(0402)
100pF
(0402)
100pF
(0402)
100pF
(0402)
0.1µF
(0402)
0.1µF
(0402)
0.1µF
(0402)
0.1µF
(0402)
10µF
(0805)
33
100pF
(0402)
12
40
10
100pF
(0402)
10µF
(0805)
DECL2
VPOS_3P3
MIXER BUFFER
3.3/5.0V
LDO
VCO
LDO
2.5V
VTUNE
100pF
(0402)
10µF
(0805)
10µF
(0805)
0.22µF
(0402)
100pF
(0402)
0.1µF
(0805)
6
1
4
3
100pF
(0402)
10kΩ
(0402)
CP
22pF
(0402)
3kΩ
(0402)
2.7nF
(0402)
5.1kΩ
VOCM (0402)
21
11
100pF
(0402) TC1-1-43A+
LOIN+
16
DECL3
MUXOUT
3
17
DECL1
6
I–
TC4-1W+
DECL4
1
LOOUT+
6
2
22
DC/PHASE
CORRECTION
100pF
(0402)
1
I+
100pF
(0402)
10kΩ
(0402)
6.8pF
(0402)
22pF
(0402)
VPOS_3P3
49.9Ω
(0402)
10µF
(0805)
VPOS_5V
11990-042
1000pF
(0402)
SDIO
20
ENABLE
SCLK
RFIN0
CS
RFSW
RFIN1
Figure 33. Basic Connections
Table 14.
Pin No.
5 V Power
11
Mnemonic
Description
Basic Connection
VPOS_5V
Mixer power supply
VPOS_5V
RF front-end power supply
1
VPOS_3P3
Digital power supply
19
VPOS_3P3
LO power supply
30
VPOS_3P3
LO power supply
31
VPOS_3P3
VCO power supply
36
VPOS_3P3
PLL power supply
Decouple this power supply pin via a 100 pF and a
0.1 µF capacitor to ground. Ensure that the decoupling
capacitors are located close to the pin.
Decouple this power supply pin via a 100 pF and a 10 µF
(0805) capacitor to ground. Ensure that the decoupling
capacitors are located close to the pin.
The voltage on any and all pins connected to VPOS_3P3
must never exceed the voltage on any and all pins
connected to VPOS_5V.
Decouple this pin via a 100 pF and a 0.1 µF capacitor to
ground.
Decouple this pin via a 100 pF and a 0.1 µF capacitor to
ground.
Decouple this pin via a 100 pF and a 0.1 µF capacitor to
ground.
Decouple this pin via a 100 pF and a 10 µF capacitor to
ground.
Decouple this pin via a 100 pF and a 0.1 µF capacitor to
ground.
21
3.3 V Power
Rev. C | Page 18 of 45
Data Sheet
Pin No.
PLL/VCO
37
39
ADRF6820
Mnemonic
Description
Basic Connection
CP
REFIN
Synthesizer charge pump output voltage
Synthesizer reference frequency input
17, 18
LOOUT+,
LOOUT−
Differential LO outputs
34, 35
Differential LO inputs
16
LOIN−,
LOIN+
MUXOUT
32
VTUNE
VCO tuning voltage
Connect to the VTUNE pin through the loop filter.
Nominal input level is 1 V p-p. Input range is 12 MHz to
320 MHz. This pin is internally biased to VPOS_3P3/2
and must be ac-coupled.
The differential output impedance is 50 Ω. These pins
are internally biased and must be ac-coupled. The dc
level varies with LO output drive level. See Table 11.
Differential input impedance of 50 Ω. These pins are
internally biased and must be ac-coupled.
This output pin provides the PLL reference signal or the
PLL lock detect signal.
This pin is driven by the output of the loop filter, and the
nominal input voltage range is 1 V to 2.8 V.
RFIN1,
RFIN0
RF inputs
RFSW
Pin control of the RF inputs
I+, I−, Q−,
Q+
I and Q channel mixer baseband outputs
12
VOCM
Mixer output common-mode voltage
Enable
24
ENBL
External enable pin control
Set this pin high for enable and low for power-down of
the internal blocks. To specify the internal blocks, write
to Register 0x10, PWRDWN_MSK.
Serial Port Interface
13
14
15
SDIO
SCLK
CS
SPI data input and output
SPI clock
SPI chip select
3.3 V tolerant logic levels.
3.3 V tolerant logic levels.
Active low. 3.3 V tolerant logic levels.
LDO Decoupling
10
DECL1
Mixer LDO decoupling
27
DECL2
VCO2 LDO decoupling
33
DECL3
VCO LDO decoupling
40
DECL4
2.5V LDO decoupling
Decouple this pin via a 0.22 µF capacitor to ground. Ensure
the decoupling capacitor is located close to the pin.
Decouple this power supply pin via 100 pF and 10 µF
(0805) capacitors to ground. Ensure that the decoupling
capacitors are located close to the pin.
Decouple this power supply pin via 100 pF and 10 µF
(0805) capacitors to ground. Ensure that the decoupling
capacitors are located close to the pin.
Decouple this power supply pin via 100 pF and 10 µF
capacitors to ground. Ensure that the decoupling
capacitors are located close to the pin.
GND
Ground
Connect these pins to the GND of the PCB.
EPAD
Exposed pad (EPAD)
The exposed thermal pad is on the bottom of the
package. Solder the exposed pad to ground.
RF Inputs
22, 29
20
Demodulator Outputs
4, 5, 6, 7
GND
2, 3, 8, 9, 23, 25, 26,
28, 38
PLL multiplex output
Rev. C | Page 19 of 45
The single-ended RF inputs have a 50 Ω input impedance.
These pins are internally biased to VPOS_5V/2. AC-couple
the RF inputs. Refer to the Layout section for the
recommended printed circuit board (PCB) layout for
improved channel-to-channel isolation. Terminate
unused RF inputs with a dc blocking capacitor to GND
to improve isolation.
For RFIN0, set RFSW to logic low, and for RFIN1, set RFSW
to logic high. For logic high, connect this pin to 3.3 V.
The I and Q mixer outputs have a 50 Ω differential
output impedance (25 Ω per pin). The VOCM pin sets
the output common-mode level.
This input pin sets the common-mode voltage of the I and
Q complex outputs. VOCM needs a clean voltage source
within the 1.5 V to 2.4 V range. Linearity performance
degrades when the voltage is outside this range.
ADRF6820
Data Sheet
0
RF BALUN INSERTION LOSS OPTIMIZATION
–2
–3
GAIN (dB)
As shown in Figure 34 to Figure 37, the gain of the ADRF6820
mixer was characterized for every combination of BAL_CIN and
BAL_COUT (Register 0x30, Bits[7:0]). As shown, a range of
BAL_CIN and BAL_COUT values can be used to optimize the
gain of the ADRF6820. The optimized values do not change with
temperature. After the values are chosen, the absolute gain changes
over temperature; however, the signature of the BAL_CIN and
BAL_COUT values is fixed.
–40°C
+25°C
+85°C
–1
–4
–5
–6
–7
–8
0
0123456701234567012345670123456701234567012345670123456701234567
0
1
2
3
4
5
6
7
COUT
CIN
CIN/COUT
11990-026
–10
Figure 36. Gain vs. BAL_CIN and BAL_COUT at fRF = 1900 MHz
0
–40°C
+25°C
+85°C
–2
–4
–6
–8
–10
–1.0
–12
–1.5
–14
–2.0
–16
0123456701234567012345670123456701234567012345670123456701234567
0
1
2
3
4
5
6
7
COUT
CIN
CIN/COUT
–2.5
11990-028
GAIN (dB)
–0.5
–40°C
+25°C
+85°C
–9
GAIN (dB)
At lower input frequencies, more capacitance is needed. This
capacitance increase is achieved by programming higher codes into
BAL_CIN and BAL_COUT. At higher frequencies, less capacitance
is required; therefore, lower BAL_CIN and BAL_COUT codes
are appropriate. Figure 38 shows the change in gain over frequency
for various BAL_CIN and BAL_COUT codes. Use Figure 34 to
Figure 38 only as guides; do not interpret them in the absolute
sense because every application and PCB design varies. Additional
fine-tuning may be necessary to achieve the maximum gain.
Table 16 shows the recommended BAL_CIN and BAL_COUT
settings for various RF frequencies.
Figure 37. Gain vs. BAL_CIN and BAL_COUT at fRF = 2600 MHz
–3.0
0
–3.5
–2
0
1
2
3
4
5
6
7
COUT
CIN
CIN/COUT
0
–40°C
+25°C
+85°C
–6
–2
–8
–4
–10
–12
500
–6
CIN =
CIN =
CIN =
CIN =
CIN =
CIN =
CIN =
CIN =
700
0,
1,
2,
3,
4,
5,
6,
7,
900
COUT
COUT
COUT
COUT
COUT
COUT
COUT
COUT
=
=
=
=
=
=
=
=
0
1
2
3
4
5
6
7
1100 1300 1500 1700 1900 2200 2400 2600
RF FREQUENCY (MHz)
Figure 38. Gain vs. RF Frequency for Various BAL_CIN and BAL_COUT Codes
–8
–10
–12
0123456701234567012345670123456701234567012345670123456701234567
0
1
2
3
4
5
6
7
COUT
CIN
CIN/COUT
11990-027
GAIN (dB)
–4
GAIN (dB)
Figure 34. Gain vs. BAL_CIN and BAL_COUT at fRF = 900 MHz
11990-029
0123456701234567012345670123456701234567012345670123456701234567
11990-025
–4.0
Figure 35. Gain vs. BAL_CIN and BAL_COUT at fRF = 2200 MHz
Rev. C | Page 20 of 45
Data Sheet
ADRF6820
BANDWIDTH SELECT MODES
The ADRF6820 offers four bandwidth select modes, as specified
in Table 15. The bandwidth select modes include either high gain
and low bandwidth or low gain and high bandwidth. The selection
of the resistance and capacitance in the mixer load determines
the IF gain and bandwidth. Use Register 0x34, Bits[9:8] to select
one of the four modes.
The high gain modes, BWSEL0 and BWSEL1, have equivalent
performance in terms of gain, noise figure, and linearity. Similarly,
the low gain modes, BWSEL2 and BWSEL3, share the same
performance specifications. However, the factor that distinguishes
the different modes is the IF bandwidth. Figure 39 to Figure 42
show the voltage gain, pass-band flatness, and 1 dB bandwidth
of the bandwidth modes for the various LO frequencies. Table 15
summarizes the results of Figure 39 to Figure 42.
Table 15. Mixer Gain and Bandwidth Select Modes1
Voltage
Gain (dB)
+2
+2
−3
−3
1 dB BW
(MHz)
240
180
600
500
3 dB BW
(MHz)
480
340
1400
900
fLO = 2100 MHz, high-side LO injection.
LO = 1800 MHz
LO = 2100 MHz
LO = 2700 MHz
VOLTAGE GAIN (dB)
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
–300
Figure 39 to Figure 42 show data for both positive and negative
IF frequencies; positive IF frequencies represent low-side LO
injection, and negative frequencies represent high-side LO
injection.
–200
–100
0
100
IF FREQUENCY (MHz)
200
300
11990-013
VOLTAGE GAIN (dB)
1
Mode
BWSEL0
BWSEL1
BWSEL2
BWSEL3
It is very difficult to accurately measure the voltage gain flatness
of the ADRF6820 because the signal generators and spectrum
analyzers introduce their own amplitude inaccuracies.
Additionally, at higher frequencies, the board traces are not as
well matched, resulting in signal reflections. With the amplitude
errors/inaccuracies from the signal generators and spectrum
analyzers included in the measurement, the gain flatness of the
ADRF6820 is approximately 0.3 dB for any 100 MHz bandwidth,
or approximately 0.2 dB for any 20 MHz bandwidth. By design,
the gain flatness of the ADRF6820 is substantially better than
this; however, the measurement approach is the limiting factor,
and the result is quoted as such.
Figure 39. Voltage Gain vs. IF Frequency, BWSEL = 0, LO Fixed and RF Swept
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
–300
LO = 1800MHz
LO = 2100MHz
LO = 2700MHz
–200
–100
0
100
IF FREQUENCY (MHz)
200
300
11990-012
BWSEL
(Reg. 0x34[9:8])
00
01
10
11
The LO frequency was set to 1800 MHz, 2100 MHz, and
2700 MHz, and the RF frequency was swept. With this
measurement approach, Figure 39 to Figure 42 show the effects
of both the RF and IF roll-off. The RF roll-off is determined by
the integrated RF balun, and the IF roll-off is set by the bandwidth
select mode. The effect of both the RF roll-off and IF roll-off is
most evident in the widest bandwidth mode (BWSEL2), as shown
in Figure 41. Figure 41 shows the flattest and widest bandwidth
when the LO frequency is at 2700 MHz because the RF frequency
is farthest from the roll-off of the integrated RF balun. In the fLO =
1800 MHz and fLO = 2100 MHz sweeps, the effect of the RF
balun becomes evident, resulting in a narrower 1 dB bandwidth.
Figure 40. Voltage Gain vs. IF Frequency, BWSEL = 1, LO Fixed and RF Swept
Rev. C | Page 21 of 45
–600
–400
–200
0
200
IF FREQUENCY (MHz)
400
600
800
Figure 41. Voltage Gain vs. IF Frequency, BWSEL = 2, LO Fixed and RF Swept
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
–4.5
–5.0
–5.5
–6.0
–6.5
–7.0
–7.5
–8.0
–800
LO = 1800MHz
LO = 2100MHz
LO = 2700MHz
–600
–400
–200
0
200
IF FREQUENCY (MHz)
400
600
800
11990-010
LO = 1800MHz
LO = 2100MHz
LO = 2700MHz
VOLTAGE GAIN (dB)
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
–4.5
–5.0
–5.5
–6.0
–6.5
–7.0
–7.5
–8.0
–800
Data Sheet
11990-011
VOLTAGE GAIN (dB)
ADRF6820
Figure 42. Voltage Gain vs. IF Frequency, BWSEL = 3, LO Fixed and RF Swept
Rev. C | Page 22 of 45
Data Sheet
ADRF6820
IP3 AND NOISE FIGURE OPTIMIZATION
The ADRF6820 can be configured for either improved
performance or reduced power consumption. In applications
where performance is critical, the ADRF6820 offers IP3 or noise
figure optimization. However, if power consumption is the priority,
the mixer bias current can be reduced to save on overall power
at the expense of degraded performance. Depending on the
application specific needs, the ADRF6820 offers configurability
that balances performance and power consumption.
Adjustments to the mixer bias setting have the most impact on
performance and power. For this reason, first adjust the mixer
bias. The active mixer core of the ADRF6820 is a linearized
transconductor. With increased bias current, the transconductor
becomes more linear, resulting in higher IP3. The higher IP3,
however, is at the expense of degraded noise figure and
increased power consumption. For a 1-bit change of the mixer
bias (MIX_BIAS, Register 0x31, Bits[12:10]), the total mixer
current increases by 8 mA.
Inevitably, there is a limit on how much the bias current can
increase before the improvement in linearity no longer justifies
the increase in power and noise. The mixer core reaches a point
where further increases in bias current do not translate to
improved linearity performance. When that point is reached,
decrease the bias current to a level where the desired performance
is achieved. Depending on the system specifications of the
customer, a balance between linearity, noise figure, and power
can be attained.
In addition to bias optimization, the ADRF6820 also has
configurable distortion cancellation circuitry. The linearized
transconductor input of the ADRF6820 is composed of a main
path and a secondary path. Through adjustments of the amplitude
and phase of the secondary path, the distortion generated by the
main path can be canceled, resulting in improved IP3 performance.
The amplitude and phase adjustments are located in the following
serial interface bits: DEMOD_RDAC (Register 0x31, Bits[8:5])
and DEMOD_CDAC (Register 0x31, Bits[3:0]).
Figure 43 to Figure 46 show the input IP3 and noise figure
sweeps for all DEMOD_RDAC, DEMOD_CDAC, and
MIX_BIAS combinations. The input IP3 vs. DEMOD_RDAC
and DEMOD_CDAC figures show both a surface and a contour
plot in one figure. The contour plot is located directly underneath
the surface plot. The best approach for reading the figures is to
locate the peaks on the surface plot, which indicate maximum
input IP3, and to follow the same color pattern to the contour
plot to determine the optimized DEMOD_RDAC and
DEMOD_CDAC values. The overall shape of the input IP3
plot does not vary with the MIX_BIAS setting; therefore, only
MIX_BIAS = 011 is displayed. Table 16 shows the recommended
MIX_BIAS, DEMOD_RDAC, and DEMOD_CDAC settings for
various RF frequencies. Use Table 16 and Figure 43 to Figure 46
as guides only; do not interpret them in the absolute sense
because every application and input signal varies.
38
40
36
40
34
35
36
34
32
30
30
25
28
30
26
32
20
0
5
RD
10
AC
30
25
20
28
10
5
RDAC
15
26
11990-031
AC
CD
0
15
0
CDAC
24
Figure 44. IIP3 vs. DEMOD_CDAC and DEMOD_RDAC, MIX_BIAS = 2 at
fRF = 1900 MHz
10
0
15
10
5
11990-032
IIP3 (dBm)
35
IIP3 (dBm)
38
Figure 43. IIP3 vs. DEMOD_CDAC and DEMOD_RDAC, MIX_BIAS = 3 at
fRF = 900 MHz
Rev. C | Page 23 of 45
ADRF6820
Data Sheet
40
38
36
36
35
34
32
34
IIP3 (dBm)
34
IIP3 (dBm)
38
36
32
30
30
28
30
32
30
25
26
28
28
24
26
20
0
22
24
0
5
10
CDAC
22
24
10
11990-033
15
15
AC
RD
5
RDA 10
C
Figure 45. IIP3 vs. DEMOD_CDAC and DEMOD_RDAC, MIX_BIAS = 2 at
fRF = 2100 MHz
20
0
15
10
5
22
CDAC
Figure 46. IIP3 vs. DEMOD_CDAC and DEMOD_RDAC, MIX_BIAS = 2 at
fRF = 2700 MHz
Recommended Settings for BAL_CIN, BAL_COUT, MIX_BIAS, DEMOD_RDAC, and DEMOD_CDAC Settings
Table 16. Recommended Settings
BWSEL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
fRF (MHz)
500
600
700
800
900
1000
1100
1200
1300
1400
1500
1600
1700
1800
1900
2000
2100
2200
2300
2400
2500
2600
2700
2800
BAL_CIN
7
7
7
7
6
5
3
3
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
BAL_COUT
7
7
7
3
2
1
2
1
1
1
1
1
0
1
0
0
0
0
0
0
0
0
0
0
11990-034
20
0
26
MIX_BIAS
2
2
2
2
1
1
1
1
2
2
2
1
1
1
1
2
2
2
2
2
2
2
1
1
Rev. C | Page 24 of 45
DEMOD_RDAC
9
9
8
9
8
8
9
8
8
9
9
8
8
8
8
8
8
9
9
7
7
7
8
8
DEMOD_CDAC
10
10
11
4
7
9
6
8
7
3
4
5
5
6
5
4
4
2
3
3
3
3
4
4
Data Sheet
BWSEL
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
ADRF6820
fRF (MHz)
500
600
700
800
900
1000
1100
1200
1300
1400
1500
1600
1700
1800
1900
2000
2100
2200
2300
2400
2500
2600
2700
2800
BAL_CIN
7
7
7
7
6
5
3
3
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
BAL_COUT
7
7
7
3
2
1
2
1
1
1
1
1
0
1
0
0
0
0
0
0
0
0
0
0
MIX_BIAS
3
3
2
3
3
3
2
2
2
3
3
2
2
2
2
3
2
2
3
3
3
3
2
2
Rev. C | Page 25 of 45
DEMOD_RDAC
5
5
4
8
9
7
6
8
3
8
8
8
8
8
5
5
4
4
8
8
9
9
8
8
DEMOD_CDAC
7
7
9
4
5
7
9
9
9
5
6
5
5
7
6
7
6
6
6
6
6
6
5
5
ADRF6820
Data Sheet
The output load on the differential I/Q outputs has a direct
impact on the voltage gain where the gain decreases with lighter
loads. The 50 Ω differential source impedance (RS) of the
ADRF6820 forms a voltage divider with the external load
resistor (RL). The performance of the ADRF6820 was optimized
for and specified with a differential load termination of 200 Ω.
For a 200 Ω differential load termination, the voltage divider
ratio is given by
VOUT/VIN = RL/(RL + RS)
where RS = 50 Ω.
80
70
60
IF FREQUENCY (MHz)
Figure 48 shows input IP3 and input IP2 performance vs. IF
frequency for 50 Ω, 100 Ω, and 200 Ω loads. For the 100 Ω and
200 Ω load impedance, the bias current was configured to its
default of 9 mA, whereas for the 50 Ω load, the current was
increased to the maximum to achieve the same level of input
IP3 performance as the higher output loads.
0
–1
–2
VOLTAGE GAIN (dB)
RL = 200Ω
RL = 100Ω
–5
–6
RL = 50Ω
–8
–9
–10
–11
11990-140
10
30
50
70
90
110
130
150
170
190
210
230
250
270
290
310
330
350
370
390
410
430
450
470
490
510
530
550
570
590
610
630
650
670
690
710
730
750
770
790
810
830
850
870
–12
IF FREQUENCY (MHz)
50Ω
100Ω
200Ω
50Ω
100Ω
200Ω
Figure 48. IIP3 and IIP2 vs. IF Frequency for fLO = 1840 MHz and BWSEL = 2
The conversion gain of the ADRF6820 at fRF = 2100 MHz and
fIF = 200 MHz is −3.2 dB. For the same test conditions with a
100 Ω load, the gain decreases by 20log(5/6) = −1.58 dB to a
voltage gain of −4.6 dB. Figure 47 shows the voltage gain vs. IF
frequency for fLO = 1840 MHz and BWSEL = 2 for common
output loads.
–13
IIP3 =
IIP3 =
IIP3 =
IIP2 =
IIP2 =
IIP2 =
10
0
where:
RL1 = 200 Ω.
RL2 is the new load impedance.
–7
30
10
30
50
70
90
110
130
150
170
190
210
230
250
270
290
310
330
350
370
390
410
430
450
470
490
510
530
550
570
590
610
630
650
670
690
710
RL2
Gain (RL2 ) (RL2 + RS )
=
RL1
Gain (RL1 )
(RL1 + RS )
–4
40
20
The change in gain due to different load impedance is given by
–3
50
11990-141
The I and Q baseband outputs of the ADRF6820 have a 50 Ω
differential impedance. However, voltage gain and linearity
performance are optimized with the use of a 200 Ω differential
load. This may not be the most favorable termination for every
application; therefore, performance trade-offs can be made for
lower output loads.
In addition to the lower conversion gain, the effect of lower
output load impedance is degraded linearity performance.
The degraded performance is a result of the emitter follower
buffers, after the mixers, needing to deliver more load current;
therefore, they operate closer to their nonlinear region. To
improve performance with lighter loads, such as 50 Ω, increase
the bias current of the emitter follower by increasing BB_BIAS
(Register 0x34, Bits[11:10]) to its maximum of 13.5 mA. Refer
to Table 13 for the bias current settings.
IIP3 (dBm), IIP2 (dBm)
I/Q OUTPUT LOADING
Figure 47. Voltage Gain vs. IF Frequency for LO = 1840 MHz, BWSEL = 2
Rev. C | Page 26 of 45
Data Sheet
ADRF6820
IMAGE REJECTION
45
The amplitude and phase mismatch of the baseband I and Q
paths directly translates to degradations in image rejection, and
for direct conversion systems, maximizing image rejection is
key to achieving performance and optimizing bandwidth. The
ADRF6820 offers phase adjustment of the I and Q paths
independently to allow quadrature correction. The quadrature
correction can be accessed by writing to Register 0x32, Bits[3:0]
for the I path correction and Register 0x32, Bits[7:4] for the Q
path correction. Figure 49 shows the available correction range
for various LO frequencies.
43
IMAGE REJECTION (dB)
41
35
33
31
27
25
700
= 740MHz
= 940MHz
= 1940MHz
= 2540MHz
900
1100 1300 1500 1700 1900 2100 2300 2500 2700
RF FREQUENCY (MHz)
Figure 50. Image Rejection vs. RF Frequency, fIF = 200 MHz
45
LOW-SIDE LO: INT 2× LO
HIGH-SIDE LO: INT 2× LO
LOW-SIDE LO: EXT 1× LO, POLYPHASE
HIGH-SIDE LO: EXT 1× LO, POLYPHASE
1.5
43
2.5°
1.0
1.1°
0.9°
2.9°
–1.0
–1.5
ILO ADJUST
QLO ADJUST
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
ILO OR QLO SETTING
35
33
31
29
Figure 49. Quadrature Correction Range
27
25
–10
Use the following equation to translate the gain and quadrature
phase mismatch to image rejection ratio (IRR) performance.
–8
–6
–4
–2
0
2
4
6
8
10
RF SIGNAL LEVEL (dBm)
Figure 51. Image Rejection vs. RF Signal Level, IF = 200 MHz, for High-Side LO
Injection fLO = 2000 MHz and fRF = 1800 MHz and Vice Versa for Low-Side Injection
1 + Ae 2 + 2 Ae cos(ϕe )
1 + Ae − 2 Ae cos(ϕe )
2
45
where:
Ae is the amplitude error.
φe is the phase error.
43
EXTERNAL LO: POLYPHASE
41
One of the dominant sources of phase error in a system
originates from the demodulator where the quadrature phase
split of the LO signal occurs. Figure 50 to Figure 52 show the
level of image rejection achievable from the ADRF6820 across
different sweep parameters with no correction applied.
IMAGE REJECTION (dB)
IRR (dB ) = 10 log
37
11990-148
–0.5
39
39
37
35
33
INTERNAL 2× LO
31
29
27
25
0
100
200
300
400
500
600
IF FREQUENCY (MHz)
Figure 52. Image Rejection vs. IF Frequency, fLO = 1800 MHz
Rev. C | Page 27 of 45
11990-049
0
IMAGE REJECTION (dB)
41
0.5
11990-113
PHASE ERROR (Degrees)
2.0
37
11990-047
2.5
39
29
3.0
LO
LO
LO
LO
HIGH-SIDE LO: INT 2× LO
HIGH-SIDE LO: EXT. 1× LO, POLYPHASE
LOW-SIDE LO: INT 2× LO
LOW-SIDE LO: EXT. 1× LO, POLYPHASE
ADRF6820
Data Sheet
At power up, depending on whether high-side or low-side
injection of the LO frequency is applied, the I channel can
either lead or lag the Q channel by 90°. When the RF frequency
is greater than the LO frequency (low-side LO injection), the
I channel leads the Q channel (see Figure 53). On the contrary,
if the RF frequency is less than the LO frequency (high-side LO
injection), the Q channel leads the I channel by 90° (see Figure 54).
0.10
0.10
0.06
0.04
–0.06
–0.08
–0.10
–5
–3
–2
–1
0.10
0
1
2
3
4
5
Q CHANNEL
I CHANNEL
0.08
0.02
0.06
0
0.04
–0.02
TRIGGER
–0.06
–0.08
0.02
0
–0.02
–2
–1
0
1
2
3
4
5
TIME (ns)
–0.06
–0.08
Figure 53. POLI = 1, POLQ = 2, I Channel Normal Polarity, Q Channel Normal
Polarity, fRF = 2040 MHz, and fLO = 1840 MHz
I CHANNEL
–0.10
–5
–4
–3
–2
–1
0
1
2
3
4
5
TIME (ns)
Q CHANNEL
11990-138
–3
11990-135
–0.04
–4
Figure 56. POLI = 1, POLQ = 1, I Channel Normal Polarity, Q Channel Invert
Polarity, fRF = 2040 MHz, and fLO = 2240 MHz
0.08
0.06
0.10
0.04
I CHANNEL
Q CHANNEL
0.08
0.02
0.06
0
0.04
TRIGGER
–0.02
–0.04
–0.06
–0.08
0.02
0
–0.02
–3
–2
–1
0
TIME (ns)
1
2
3
4
5
11990-136
–0.04
–4
–0.06
–0.08
Figure 54. POLI = 1, POLQ = 2, I Channel Normal Polarity, Q Channel Normal
Polarity, fRF = 2040 MHz, and fLO = 2240 MHz
–0.10
–5
–4
–3
–2
–1
0
TIME (ns)
1
2
3
4
5
11990-139
TRIGGER
–4
Figure 55. POLI = 2, POLQ = 2, I Channel Invert Polarity, Q Channel Normal
Polarity, fRF = 2040 MHz, and fLO = 2240 MHz
–0.04
TRIGGER
–0.02
–0.04
0.04
–0.10
–5
0
TIME (ns)
0.06
0.10
0.02
Q CHANNEL I CHANNEL
0.08
–0.10
–5
Q CHANNEL I CHANNEL
0.08
11990-137
The ADRF6820 offers the flexibility of specifying the polarity of
the I/Q outputs, where I can lead Q or vice versa. By addressing
POLI (Register 0x32, Bits[9:8]) or POLQ (Register 0x32,
Bits[11:10]), both the I and Q outputs can be inverted from
their default configuration. The flexibility of specifying the
polarity becomes important when the I and Q outputs are
processed simultaneously in the complex domain, I + jQ.
Both the I and Q channels can be inverted to achieve the desired
polarity, as shown in Figure 55 to Figure 57, by writing to POLI
(Register 0x32, Bits[9:8]) or POLQ (Register 0x32, Bits[11:10]).
TRIGGER
I/Q POLARITY
Figure 57. POLI = 2, POLQ = 1, I Channel Invert Polarity, Q Channel Invert
Polarity, fRF = 2040 MHz, and fLO = 2240 MHz
Rev. C | Page 28 of 45
Data Sheet
ADRF6820
LAYOUT
The input impedance of the RF inputs is 50 Ω, and the traces
leading to the pin must also have a 50 Ω characteristic impedance.
For unused RF inputs, terminate the pins with a dc blocking
capacitor to ground.
Rev. C | Page 29 of 45
RFIN0
GND
GND
GND
RFIN1
11990-048
Careful layout of the ADRF6820 is necessary to optimize
performance and minimize stray parasitics. The ADRF6820
supports two RF inputs; therefore, the layout of the RF section
is critical in achieving isolation between each channel. Figure 58
shows the recommended layout for the RF inputs. Each RF input,
RFIN0 and RFIN1, is isolated between ground pins, and the
best layout approach is to keep the traces short and direct. To
achieve this, connect the pins directly to the center ground pad
of the exposed pad of the ADRF6820. This approach minimizes
the trace inductance and promotes better isolation between the
channels. In addition, for improved isolation, do not route the
RFIN0 and RFIN1 traces in parallel to each other; split the
traces immediately after each one leaves the pins. Keep the
traces as far away from each other as possible to prevent cross
coupling.
Figure 58. Recommended RF Input Layout
ADRF6820
Data Sheet
REGISTER MAP
Table 17.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Hex
Addr. Name
Bits Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
00
SOFT_RESET [15:8]
RESERVED
[7:0]
RESERVED
SOFT_RESET
01
Enables
[15:8]
RESERVED
DMOD_EN QUAD_DIV_EN LO_DRV2X_EN
[7:0] LO_DRV1X_EN VCO_MUX_ REF_BUF_EN VCO_EN
DIV_EN
CP_EN
VCO_LDO_EN RESERVED
EN
02
INT_DIV
[15:8]
RESERVED
DIV_MODE
INT_DIV
[7:0]
INT_DIV
03
FRAC_DIV [15:8]
FRAC_DIV
[7:0]
FRAC_DIV
04
MOD_DIV [15:8]
MOD_DIV
[7:0]
MOD_DIV
PWRDWN_ [15:8]
DMOD_ QUAD_DIV_ LO_DRV2X_
10
RESERVED
MASK
MASK
MASK
MASK
VCO_MUX_ REF_BUF_
VCO_
[7:0] LO_DRV1X_
DIV_MASK
CP_MASK VCO_LDO_
RESERVED
MASK
MASK
MASK
MASK
MASK
20
CP_CTL
[15:8] RESERVED
CPSEL
CSCALE
RESERVED
[7:0]
RESERVED
BLEED
21
PFD_CTL
[15:8]
RESERVED
[7:0] RESERVED
REF_MUX_SEL
PFD_POLARITY
REFSEL
22
VCO_CTL
[15:8]
RESERVED
RESERVED
[7:0]
LO_DRV_LVL
DRVDIV2_EN DIV8_EN
DIV4_EN
VCO_SEL
23
DGA_CTL
[15:8]
RESERVED
RFSW_MUX
RESERVED RFSW_SEL
RFDSA_SEL
[7:0]
RFDSA_SEL
RESERVED
30
BALUN_CTL [15:8]
RESERVED
[7:0]
BAL_COUT
RESERVED
BAL_CIN
RESERVED
31
MIXER_CTL [15:8]
RESERVED
MIX_BIAS
RESERVED
DEMOD_RDAC
[7:0]
DEMOD_RDAC
RESERVED
DEMOD_CDAC
32
MOD_CTL0 [15:8]
RESERVED
POLQ
POLI
[7:0]
QLO
ILO
33
MOD_CTL1 [15:8]
DCOFFI
[7:0]
DCOFFQ
34
MOD_CTL2 [15:8]
RESERVED
BB_BIAS
BWSEL
[7:0]
RESERVED
RESERVED
40
PFD_CTL2 [15:8]
RESERVED
[7:0] RESERVED
ABLDLY
CPCTRL
CLKEDGE
42
DITH_CTL1 [15:8]
RESERVED
[7:0]
RESERVED
DITH_EN
DITH_MAG
DITH_VAL
43
DITH_CTL2 [15:8]
DITH_VAL
[7:0]
DITH_VAL
DIV_SM_
44
[15:8]
RESERVED
CTL
BANDCAL_
[7:0]
RESERVED
DIVD_CLR
45
VCO_CTL2 [15:8]
RESERVED
[7:0] VCO_BAND_SRC
BAND
46
VCO_RB
[15:8]
RESERVED
[7:0]
RESERVED
VCO_BAND
49
VCO_CTL3 [15:8]
RESERVED
SET_1
SET_0
[7:0]
SET_0
Rev. C | Page 30 of 45
Reset RW
0x0000 W
0xFE7F RW
0x002C RW
0x0128 RW
0x0600 RW
0xFE7F RW
0x0C26 RW
0x0003 RW
0x2A03 RW
0x0000 RW
0x0000 RW
0x1101 RW
0x0900 RW
0x0000 RW
0x0B00 RW
0x0010 RW
0x000E RW
0x0001 RW
0x0000 RW
0x0000 RW
0x0000 R
0x16BD RW
Data Sheet
ADRF6820
REGISTER ADDRESS DESCRIPTIONS
Address: 0x00, Reset: 0x0000, Name: SOFT_RESET
Table 18. Bit Descriptions for SOFT_RESET
Bits
0
Bit Name
SOFT_RESET
Settings
Description
Soft reset
Reset
0x0000
Access
W
Reset
0x1
0x1
0x0
0x0
0x1
0x1
0x1
0x1
0x1
0x1
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Address: 0x01, Reset: 0xFE7F, Name: Enables
Table 19. Bit Descriptions for Enables
Bits
10
9
8
7
6
5
4
3
2
1
Bit Name
DMOD_EN
QUAD_DIV_EN
LO_DRV2X_EN
LO_DRV1X_EN
VCO_MUX_EN
REF_BUF_EN
VCO_EN
DIV_EN
CP_EN
VCO_LDO_EN
Settings
Description
DMOD enable
Quadrature divider path enable (2×/4×/8× LO)
External 2× LO driver enable—before quad divider
External 1× LO driver enable—after quad divider
VCO mux enable
Reference buffer enable
Power up VCOs
Power up dividers
Power up charge pump
Power up VCO LDO
Rev. C | Page 31 of 45
ADRF6820
Data Sheet
Address: 0x02, Reset: 0x002C, Name: INT_DIV
Table 20. Bit Descriptions for INT_DIV
Bits
11
Bit Name
DIV_MODE
Settings
0
1
[10:0]
INT_DIV
Description
Divide mode
Fractional
Integer
Set divider INT value
Integer mode range: 21 to 123
Fractional mode range: 24 to 119
Reset
0x0
Access
RW
0x2C
RW
Reset
0x128
Access
RW
Reset
0x600
Access
RW
Address: 0x03, Reset: 0x0128, Name: FRAC_DIV
Table 21. Bit Descriptions for FRAC_DIV
Bits
[15:0]
Bit Name
FRAC_DIV
Settings
Description
Set divider FRAC value
Address: 0x04, Reset: 0x0600, Name: MOD_DIV
Table 22. Bit Descriptions for MOD_DIV
Bits
[15:0]
Bit Name
MOD_DIV
Settings
Description
Set divider MOD value
Rev. C | Page 32 of 45
Data Sheet
ADRF6820
Address: 0x10, Reset: 0xFE7F, Name: PWRDWN_MASK
Table 23. Bit Descriptions for PWRDWN_MASK
Bits
10
9
8
7
6
5
4
3
2
1
Bit Name
DMOD_MASK
QUAD_DIV_MASK
LO_DRV2X_MASK
LO_DRV1X_MASK
VCO_MUX_MASK
REF_BUF_MASK
VCO_MASK
DIV_MASK
CP_MASK
VCO_LDO_MASK
Settings
Description
Demodulator (DMOD) enable
Quadrature divider path enable (2×/4×/8× LO)
External 2× LO driver enable—before quad divider
External 1× LO driver enable—after quad divider
VCO mux enable
Reference buffer enable
Power up VCOs
Power up dividers
Power up charge pump
Power up VCO LDO
Rev. C | Page 33 of 45
Reset
0x1
0x1
0x0
0x0
0x1
0x1
0x1
0x1
0x1
0x1
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
ADRF6820
Data Sheet
Address: 0x20, Reset: 0x0C26, Name: CP_CTL
Table 24. Bit Descriptions for CP_CTL
Bits
14
Bit Name
CPSEL
Settings
0
1
[13:10]
CSCALE
0001
0011
0111
1111
[5:0]
BLEED
000000
000001
000010
000011
...
011111
100000
100001
100010
100011
...
111111
Description
Charge pump reference current select
Internal charge pump
External charge pump
Charge pump coarse scale current
250 µA
500 µA
750 µA
1000 µA
Charge pump bleed
0 µA
15.625 µA sink
31.25 µA sink
46.875 µA sink
484.375 µA sink
0 µA
15.625 µA source
31.25 µA source
46.875 µA source
484.375 µA source
Rev. C | Page 34 of 45
Reset
0x0
Access
RW
0x3
RW
0x26
RW
Data Sheet
ADRF6820
Address: 0x21, Reset: 0x0003, Name: PFD_CTL
Table 25. Bit Descriptions for PFD_CTL
Bits
[6:4]
Bit Name
REF_MUX_SEL
Settings
000
001
010
011
100
101
110
111
3
PFD_POLARITY
0
1
[2:0]
REFSEL
000
001
010
011
100
Description
Reference (REF) mux select
LOCK_DET
VPTAT
REFCLK
REFCLK/2
REFCLK × 2
REFCLK/8
REFCLK/4
SCAN
Set PFD polarity
Positive
Negative
Set REF input multiply/divide ratio
×2
×1
Divide by 2
Divide by 4
Divide by 8
Rev. C | Page 35 of 45
Reset
0x0
Access
RW
0x0
RW
0x3
RW
ADRF6820
Data Sheet
Address: 0x22, Reset: 0x2A03, Name: VCO_CTL
Table 26. Bit Descriptions for VCO_CTL
Bits
[7:6]
Bit Name
LO_DRV_LVL
Settings
00
01
10
11
5
DRVDIV2_EN
0
1
4
DIV8_EN
0
1
3
DIV4_EN
0
1
[2:0]
VCO_SEL
000
001
010
011
100
Description
External LO amplitude
−5 dBm
−1 dBm
+2 dBm
+4 dBm
Divide by 2 for external LO driver enable
Disable
Enable
Divide by 2 in LO path for total of division of 8
Disable
Enable
Divide by 2 in LO path for total of division of 4
Disable
Enable
Select VCO core/external LO
4.6 GHz to 5.7 GHz
4.02 GHz to 4.6 GHz
3.5 GHz to 4.02 GHz
2.85 GHz to 3.5 GHz
External LO/VCO
Rev. C | Page 36 of 45
Reset
0x0
Access
RW
0x0
RW
0x0
RW
0x0
RW
0x3
RW
Data Sheet
ADRF6820
Address: 0x23, Reset: 0x0000, Name: DGA_CTL
Table 27. Bit Descriptions for DGA_CTL
Bits
11
Bit Name
RFSW_MUX
Settings
0
1
9
RFSW_SEL
0
1
[8:5]
RFDSA_SEL
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Description
RF switch mux
Pin control (CNTRL)
Serial control (CNTRL)
RF switch select
RFIN0
RFIN1
RFDSA selection
0 dB
1 dB
2 dB
3 dB
4 dB
5 dB
6 dB
7 dB
8 dB
9 dB
10 dB
11 dB
12 dB
13 dB
14 dB
15 dB
Rev. C | Page 37 of 45
Reset
0x0
Access
RW
0x0
RW
0x0
RW
ADRF6820
Data Sheet
Address: 0x30, Reset: 0x0000, Name: BALUN_CTL
Table 28. Bit Descriptions for BALUN_CTL
Bits
[7:5]
Bit Name
BAL_COUT
Settings
000
111
[3:1]
BAL_CIN
000
111
Description
Balun output capacitance
Minimum capacitance value
Maximum capacitance value
Balun input capacitance
Minimum capacitance value
Maximum capacitance value
Reset
0x0
Access
RW
0x0
RW
Reset
0x4
0x8
0x1
Access
RW
RW
RW
Address: 0x31, Reset: 0x1101, Name: MIXER_CTL
Table 29. Bit Descriptions for MIXER_CTL
Bits
[12:10]
[8:5]
[3:0]
Bit Name
MIX_BIAS
DEMOD_RDAC
DEMOD_CDAC
Settings
Description
Demodulator (demod) bias value
Demodulator linearizer RDAC value
Demodulator linearizer CDAC value
Rev. C | Page 38 of 45
Data Sheet
ADRF6820
Address: 0x32, Reset: 0x0900, Name: MOD_CTL0
Table 30. Bit Descriptions for MOD_CTL0
Bits
[11:10]
Bit Name
POLQ
Settings
01
10
[9:8]
POLI
01
10
[7:4]
[3:0]
QLO
ILO
Description
Quadrature polarity switch, Q channel
Invert Q channel polarity
Normal polarity
Quadrature polarity switch, I channel
Normal polarity
Invert I channel
Upper side band nulling, Q channel
Upper side band nulling, I channel
Rev. C | Page 39 of 45
Reset
0x2
Access
RW
0x1
RW
0x0
0x0
RW
RW
ADRF6820
Data Sheet
Address: 0x33, Reset: 0x0000, Name: MOD_CTL1
Table 31. Bit Descriptions for MOD_CTL1
Bits
[15:8]
Bit Name
DCOFFI
Settings
00000000
00000001
00000010
00000011
01111110
01111111
10000000
10000001
10000010
10000011
11111110
11111111
[7:0]
DCOFFQ
00000000
00000001
00000010
00000011
01111110
01111111
10000000
10000001
10000010
10000011
11111110
11111111
Description
Baseband DC LO nulling, I channel
0 µA
+5 µA
+10 µA
+15 µA
+630 µA
+635 µA
0 µA
−5 µA
−10 µA
−15 µA
−630 µA
−635 µA
Baseband DC LO nulling, Q channel
0 µA
+5 µA
+10 µA
+15 µA
+630 µA
+635 µA
0 µA
−5 µA
−10 µA
−15 µA
−630 µA
−635 µA
Rev. C | Page 40 of 45
Reset
0x00
Access
RW
0x00
RW
Data Sheet
ADRF6820
Address: 0x34, Reset: 0x0B00, Name: MOD_CTL2
Table 32. Bit Descriptions for MOD_CTL2
Bits
[11:10]
Bit Name
BB_BIAS
Settings
00
01
10
11
[9:8]
BWSEL
00
01
10
11
Description
Baseband bias select
0 mA
4.5 mA
9 mA
13.5 mA
Baseband gain and bandwidth select
High gain, high bandwidth (refer to Table 15)
High gain, low bandwidth (refer to Table 15)
Low gain, high bandwidth (refer to Table 15)
Low gain, low bandwidth (refer to Table 15)
Rev. C | Page 41 of 45
Reset
0x2
Access
RW
0x3
RW
ADRF6820
Data Sheet
Address: 0x40, Reset: 0x0010, Name: PFD_CTL2
Table 33. Bit Descriptions for PFD_CTL2
Bits
[6:5]
Bit Name
ABLDLY
Settings
00
01
10
11
[4:2]
CPCTRL
000
001
010
011
100
[1:0]
CLKEDGE
00
01
10
11
Description
Set antibacklash delay
0 ns
0.5 ns
0.75 ns
0.9 ns
Set charge pump control
Both on
Pump down
Pump up
Tristate
PFD
Set PFD edge sensitivity
Div and REF down edge
Div down edge, REF up edge
Div up edge, REF down edge
Div and REF up edge
Rev. C | Page 42 of 45
Reset
0x0
Access
RW
0x4
RW
0x0
RW
Data Sheet
ADRF6820
Address: 0x42, Reset: 0x000E, Name: DITH_CTL1
Table 34. Bit Descriptions for DITH_CTL1
Bits
3
Bit Name
DITH_EN
Settings
0
1
[2:1]
0
DITH_MAG
DITH_VAL
Description
Set dither enable
Disable
Enable
Set dither magnitude
Set dither value
Reset
0x1
Access
RW
0x3
0x0
RW
RW
Reset
0x1
Access
RW
Reset
0x0
Access
RW
Address: 0x43, Reset: 0x0001, Name: DITH_CTL2
Table 35. Bit Descriptions for DITH_CTL2
Bits
[15:0]
Bit Name
DITH_VAL
Settings
Description
Set dither value
Address: 0x44, Reset: 0x0000, Name: DIV_SM_CTL
Table 36. Bit Descriptions for DIV_SM_CTL
Bits
0
Bit Name
BANDCAL_DIVD_CLR
Settings
Description
Set to 1 to disable autocal
Rev. C | Page 43 of 45
ADRF6820
Data Sheet
Address: 0x45, Reset: 0x0000, Name: VCO_CTL2
Table 37. Bit Descriptions for VCO_CTL2
Bits
7
[6:0]
Bit Name
VCO_BAND_SRC
BAND
Settings
Description
VCO band source (SIF or BANDCAL algorithm)
VCO band selection
Reset
0x0
0x00
Access
RW
RW
Reset
0x00
Access
R
Reset
0xB
Access
RW
0xBD
RW
Address: 0x46, Reset: 0x0000, Name: VCO_RB
Table 38. Bit Descriptions for VCO_RB
Bits
[5:0]
Bit Name
VCO_BAND
Settings
Description
Read back output of BANDCAL mux
Address: 0x49, Reset: 0x16BD, Name: VCO_CTL3
Table 39. Bit Descriptions for VCO_CTL3
Bits
[13:9]
Bit Name
SET_1
[8:0]
SET_0
Settings
Description
Internal settings (refer to the Required PLL/VCO Settings and Register Write
Sequence section)
Internal settings (refer to the Required PLL/VCO Settings and Register Write
Sequence section)
Rev. C | Page 44 of 45
Data Sheet
ADRF6820
OUTLINE DIMENSIONS
6.10
6.00 SQ
5.90
31
30
40
1
0.50
BSC
4.70
4.60 SQ
4.50
EXPOSED
PAD
TOP VIEW
0.80
0.75
0.70
END VIEW
PKG-005131
SEATING
PLANE
0.45
0.40
0.35
21
11
20
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.203 REF
BOTTOM VIEW
PIN 1
INDICATOR
10
0.20 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WJJD-5
03-08-2016-A
PIN 1
INDICATOR
0.30
0.25
0.18
Figure 59. 40-Lead Lead Frame Chip Scale Package [LFCSP]
6mm × 6mm Body and 0.75 mm Package Height
(CP-40-7)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
ADRF6820ACPZ-R7
ADRF6820-EVALZ
1
Temperature Range
−40°C to +85°C
Package Description
40-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Board
Z = RoHS Compliant Part.
©2013–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D11990-0-8/16(C)
Rev. C | Page 45 of 45
Package Option
CP-40-7