ON NCP5173 1.5 a 560 khz-1.0 mhz boost regulator Datasheet

NCP5173
1.5 A 560 kHz−1.0 MHz
Boost Regulator
The NCP5173 is a switching regulator with a high efficiency, 1.5 A
integrated switch. It runs at a base frequency of 560 kHz and can be
synchronized to an external clock up to 1.0 MHz. This part operates
over a wide input voltage range, from 2.7 V to 30 V. The flexibility of
the design allows the chip to operate in most power supply
configurations, including boost, flyback, forward, inverting, and
SEPIC. The IC uses current mode architecture, which allows excellent
load and line regulation, as well as a practical means for limiting
current. Combining high frequency operation with a highly integrated
regulator circuit results in an extremely compact power supply
solution. The circuit design includes provisions for features such as
frequency synchronization, shutdown, and feedback controls for
positive voltage regulation.
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MARKING
DIAGRAM
1
NCP5173
AWLYYWW
5x6 QFN
MN SUFFIX
CASE 505AC
Features
•
•
•
•
•
•
•
•
•
•
Integrated Power Switch: 1.5 A Guaranteed
Wide Input Range: 2.7 V to 30 V
High Frequency Allows for Small Components
Minimum External Components
Easy External Synchronization
Built−in Overcurrent Protection
Frequency Foldback Reduces Component Stress During an
Overcurrent Condition
Thermal Shutdown with Hysteresis
Low 1.0 mm Maximum Profile
Shut Down Current: 50 A Maximum
Applications
• Flat Panel Displays
• Systems Requiring Low Profile Components
 Semiconductor Components Industries, LLC, 2004
September, 2004 − Rev. 1
NCP5173 = Specific Device Code
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
NOTE:
Thermal pad is electrically isolated from IC
and all pins.
ORDERING INFORMATION
Package
Shipping†
NCP5173MN
QFN
95 Units/Rail
NCP5173MNR2
QFN
2500 Tape & Reel
Device
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
1
Publication Order Number:
NCP5173/D
NCP5173
R2
3.72 k
2
C1
0.01 F
3
D1
VSW
VC
FB
Test
PGND
NCP5173
1
AGND
VOUT
8
5V
MBRS120T3
7
6
L1
4
SS
VCC
SS
5
+
22 H
C3
22 F
3.3 V
R3
R1
5k
+
C2
22 F
1.28 k
Figure 1. Applications Diagram
MAXIMUM RATINGS*
Rating
Value
Unit
Junction Temperature Range, TJ
−40 to +150
°C
Storage Temperature Range, TSTORAGE
−65 to +150
°C
35
°C/W
230 Peak
°C
1.2
kV
Package Thermal Resistance: Junction−to−Ambient, RJA
Lead Temperature Soldering: Reflow (Note 1)
ESD, Human Body Model
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. 60 second maximum above 183°C.
*The maximum package power dissipation must be observed.
MAXIMUM RATINGS
Pin Name
Pin Symbol
VMAX
VMIN
ISOURCE
ISINK
IC Power Input
VCC
30 V
−0.3 V
N/A
200 mA
Shutdown/Sync
SS
30 V
−0.3 V
1.0 mA
1.0 mA
Loop Compensation
VC
6.0 V
−0.3 V
10 mA
10 mA
Voltage Feedback Input
FB
10 V
−0.3 V
1.0 mA
1.0 mA
Test Pin
Test
6.0 V
−0.3 V
1.0 mA
1.0 mA
Power Ground
PGND
0.3 V
−0.3 V
4A
10 mA
Analog Ground
AGND
0V
0V
N/A
10 mA
Switch Input
VSW
40 V
−0.3 V
10 mA
3.0 A
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NCP5173
ELECTRICAL CHARACTERISTICS (2.7 V < VCC < 30 V; 0°C < TJ < 125°C; for all specifications unless otherwise stated.)
Test Conditions
Min
Typ
Max
Unit
VC tied to FB; measure at FB
1.246
1.276
1.300
V
FB = VREF
−1.0
0.1
1.0
A
VC = FB
−
0.01
0.03
%/V
IVC = 25 A
300
550
800
Mho
(Note 2)
200
500
−
V/V
VC Source Current
FB = 1.0 V or NFB = −1.9 V, VC = 1.25 V
25
50
90
A
VC Sink Current
FB = 1.5 V or NFB = −3.1 V, VC = 1.25 V
200
625
1500
A
VC High Clamp Voltage
FB = 1.0 V or NFB = −1.9 V;
VC sources 25 A
1.5
1.7
1.9
V
VC Low Clamp Voltage
FB = 1.5 V or NFB = −3.1 V, VC sinks 25 A
0.25
0.50
0.65
V
VC Threshold
Reduce VC from 1.5 V until switching stops
0.75
1.05
1.30
V
FB = 1.0 V
460
560
620
kHz
FB = 0 V
60
104
160
kHz
−
82
90
−
%
Frequency drops to reduced operating
frequency
0.36
0.40
0.44
V
−
640
−
1000
kHz
Rise time = 20 ns
2.5
−
−
V
SS = 0 V
SS = 3.0 V
−15
−
−3.0
3.0
−
8.0
A
−
0.50
0.85
1.20
V
2.7 V ≤ VCC ≤ 12 V
12 V < VCC ≤ 30 V
12
12
80
36
350
200
s
ISWITCH = 1.5 A (Note 2)
ISWITCH = 1.0 A, 0°C TJ ≤ 85°C
ISWITCH = 1.0 A, −40°C ≤ TJ 0°C
ISWITCH = 10 mA
−
−
−
−
0.8
0.55
0.75
0.09
1.4
−
−
0.45
V
50% Duty cycle (Note 2)
80% Duty cycle (Note 2)
1.6
1.5
1.9
1.7
2.4
2.2
A
FB = 0 V, ISW = 4.0 A (Note 2)
200
250
300
ns
2.7 V ≤ VCC ≤ 12 V, 10 mA ≤ ISW ≤ 1.0 A
12 V < VCC ≤ 30 V, 10 mA ≤ ISW ≤ 1.0 A
2.7 V ≤ VCC ≤ 12 V, 10 mA ≤ ISW ≤ 1.5 A
(Note 2)
12 V < VCC ≤ 30 V, 10 mA ≤ ISW ≤ 1.5 A
(Note 2)
−
−
−
10
−
17
30
100
30
mA/A
−
−
100
VSW = 40 V, VCC = 0V
−
2.0
100
Characteristic
Positive and Negative Error Amplifiers
FB Reference Voltage
FB Input Current
FB Reference Voltage Line Regulation
Error Amp Transconductance
Error Amp Gain
Oscillator
Base Operating Frequency
Reduced Operating Frequency
Maximum Duty Cycle
FB Frequency Shift Threshold
Sync/Shutdown
Sync Range
Sync Pulse Transition Threshold
SS Bias Current
Shutdown Threshold
Shutdown Delay
Power Switch
Switch Saturation Voltage
Switch Current Limit
Minimum Pulse Width
ICC/ IVSW
Switch Leakage
2. Guaranteed by design, not 100% tested in production.
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A
NCP5173
ELECTRICAL CHARACTERISTICS (continued) (2.7 V < VCC < 30 V; 0°C < TJ < 125°C; for all specifications unless otherwise stated.)
Test Conditions
Characteristic
Min
Typ
Max
Unit
General
Operating Current
ISW = 0
−
5.5
8.0
mA
Shutdown Mode Current
VC < 0.8 V, SS = 0 V, 2.7 V ≤ VCC ≤ 12 V
VC < 0.8 V, SS = 0 V, 12 V ≤ VCC ≤ 30 V
−
−
12
−
60
100
A
Minimum Operation Input Voltage
VSW switching, maximum ISW = 10 mA
−
2.45
2.70
V
Thermal Shutdown
(Note 3)
150
180
210
°C
Thermal Hysteresis
(Note 3)
−
25
−
°C
3. Guaranteed by design, not 100% tested in production.
PIN FUNCTION DESCRIPTION
Pin Number
Symbol
Function
1
VC
Loop compensation pin. The VC pin is the output of the error amplifier and is used for loop compensation, current limit and soft−start. Loop compensation can be implemented by a simple RC
network as shown in the application diagram on Page 2 as R1 and C1.
2
FB
Positive regulator feedback pin. This pin senses a positive output voltage and is referenced to
1.276 V. When the voltage at this pin falls below 0.4 V, chip switching frequency reduces to 20% of
the nominal frequency.
3
Test
These pins are connected to internal test logic and should either be left floating or tied to ground.
Connection to a voltage between 2.0 V and 6.0 V shuts down the internal oscillator and leaves the
power switch running.
4
SS
Synchronization and shutdown pin. This pin may be used to synchronize the part to nearly twice
the base frequency. A TTL low will shut the part down and put it into low current mode. If synchronization is not used, this pin should be either tied high or left floating for normal operation.
5
VCC
Input power supply pin. This pin supplies power to the part and should have a bypass capacitor
connected to AGND.
6
AGND
Analog ground. This pin provides a clean ground for the controller circuitry and should not be in the
path of large currents. The output voltage sensing resistors should be connected to this ground pin.
This pin is connected to the IC substrate.
7
PGND
Power ground. This pin is the ground connection for the emitter of the power switching transistor.
Connection to a good ground plane is essential.
8
VSW
High current switch pin. This pin connects internally to the collector of the power switch. The open
voltage across the power switch can be as high as 40 V. To minimize radiation, use a trace as short
as practical.
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NCP5173
VCC
Thermal
Shutdown
Shutdown
2.0 V
Regulator
VSW
Oscillator
Delay
Timer
S PWM
Latch
R
Q
Switch
Driver
Sync
SS
Frequency
Shift 5:1
×5
Slope
Compensation
0.4 V Detector
63 m
−
FB
Ramp
Summer
+
1.276 V
Positive
Error Amp
PWM
Comparator
+
AGND
VC
Figure 2. Block Diagram
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5
−
PGND
NCP5173
TYPICAL PERFORMANCE CHARACTERISTICS
7.2
70
7.0
VCC = 12 V
40
30
6.2
VCC = 12 V
20
6.0
5.8
5.6
ISW = 1.5 A
50
(mA/A)
Current (mA)
6.6
6.4
VCC = 30 V
60
VCC = 30 V
6.8
0
50
Temperature (°C)
VCC = 2.7 V
10
VCC = 2.7 V
0
100
0
100
Figure 4. ICC/ IVSW vs. Temperature
Figure 3. ICC (No Switching) vs. Temperature
1.9
1200
−40 °C
1000
1.8
85 °C
800
600
VIN (V)
VCE(SAT) (mV)
50
Temperature (°C)
1.7
25 °C
400
1.6
200
0
500
1.5
1000
0
ISW (mA)
100
fOSC (% of Typical)
fOSC (kHz)
100
Figure 6. Minimum Input Voltage vs. Temperature
Figure 5. VCE(SAT) vs. ISW
570
565
560
555
550
545
540
535
530
525
520
50
Temperature (°C)
VCC = (12 V)
−40°C
75
85°C
50
25°C
25
0
0
50
Temperature (°C)
350
100
Figure 7. Switching Frequency vs. Temperature
380
400
VFB (mV)
420
Figure 8. Switching Frequency vs. VFB
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450
NCP5173
TYPICAL PERFORMANCE CHARACTERISTICS
0.20
1.280
VCC = 12 V
0.18
1.276
IFB (A)
Voltage (V)
1.278
1.274
VCC = 2.7 V
1.272
0.16
VCC = 12 V
0.14
0.12
VCC = 30 V
0.10
1.270
VCC = 2.7 V
0.08
1.268
0
50
Temperature (°C)
0
100
Figure 9. Reference Voltage vs. Temperature
50
Temperature (°C)
Figure 10. IFB vs. Temperature
2.60
99
VCC = 30 V
2.50
Duty Cycle (%)
Current (A)
98
2.40
VCC = 2.7 V
2.30
VCC = 12 V
2.20
0
100
VCC = 12 V
97
96
VCC = 2.7 V
95
94
VCC = 30 V
50
Temperature (°C)
93
100
0
50
Temperature (°C)
100
Figure 12. Maximum Duty Cycle vs. Temperature
Figure 11. Current Limit vs. Temperature
1.1
1.7
Voltage (V)
Voltage (V)
1.0
VC High Clamp Voltage
1.5
1.3
1.1
0.9
0.7
VC Threshold
0
50
Temperature (°C)
0.9
0.8
0.7
0.6
0.5
0.4
100
0
Figure 13. VC Threshold and High Clamp
Voltage vs. Temperature
50
Temperature (°C)
100
Figure 14. Shutdown Threshold vs. Temperature
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NCP5173
TYPICAL PERFORMANCE CHARACTERISTICS
40
160
25°C
VCC = 2.7 V
140
30
85°C
100
ISS (A)
Delay (s)
120
VCC = 12 V
80
20
−40°C
10
VCC = 30 V
60
0
40
0
50
Temperature (°C)
−10
100
gm (mho)
ICC (A)
7
9
600
−40°C
30
25°C
20
5
VSS (V)
Figure 16. ISS vs. VSS
Figure 15. Shutdown Delay vs. Temperature
40
3
1
85°C
550
500
10
0
450
10
VIN (V)
50
Temperature (°C)
100
Figure 18. Error Amplifier Transconductance
vs. Temperature
Figure 17. ICC vs. VIN During Shutdown
100
2.6
2.5
Current (A)
60
IOUT (A)
0
20
−20
2.4
2.3
2.2
2.1
−60
−255 −175 −125
−75
−25
VREF − VFB (mV)
0
2.0
25
0
50
Temperature (°C)
100
Figure 20. Switch Leakage vs. Temperature
Figure 19. Error Amplifier IOUT vs. VFB
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NCP5173
APPLICATIONS INFORMATION
THEORY OF OPERATION
The oscillator is trimmed to guarantee an 18% frequency
accuracy. The output of the oscillator turns on the power
switch at a frequency of 600 kHz, as shown in Figure 21.
The power switch is turned off by the output of the PWM
Comparator.
A TTL−compatible sync input at the SS pin is capable of
syncing up to 1.8 times the base oscillator frequency. As
shown in Figure 22, in order to sync to a higher frequency,
a positive transition turns on the power switch before the
output of the oscillator goes high, thereby resetting the
oscillator. The sync operation allows multiple power
supplies to operate at the same frequency.
A sustained logic low at the SS pin will shut down the IC
and reduce the supply current.
An additional feature includes frequency shift to 20% of
the nominal frequency when the FB pin triggers the
threshold. During power up, overload, or short circuit
conditions, the minimum switch on−time is limited by the
PWM comparator minimum pulse width. Extra switch
off−time reduces the minimum duty cycle to protect external
components and the IC itself.
As previously mentioned, this block also produces a ramp
for the slope compensation to improve regulator stability.
Current Mode Control
VCC
Oscillator
S
VC
−
+
Q
L
R
D1
Power Switch
VSW
PWM
Comparator
In Out
X5
CO
Driver
RLOAD
SUMMER
Slope Compensation
63 m
Figure 21. Current Mode Control Scheme
The NCP5173 incorporates a current mode control
scheme, in which the PWM ramp signal is derived from the
power switch current. This ramp signal is compared to the
output of the error amplifier to control the on−time of the
power switch. The oscillator is used as a fixed−frequency
clock to ensure a constant operational frequency. The
resulting control scheme features several advantages over
conventional voltage mode control. First, derived directly
from the inductor, the ramp signal responds immediately to
line voltage changes. This eliminates the delay caused by the
output filter and error amplifier, which is commonly found
in voltage mode controllers. The second benefit comes from
inherent pulse−by−pulse current limiting by merely
clamping the peak switching current. Finally, since current
mode commands an output current rather than voltage, the
filter offers only a single pole to the feedback loop. This
allows both a simpler compensation and a higher
gain−bandwidth over a comparable voltage mode circuit.
Without discrediting its apparent merits, current mode
control comes with its own peculiar problems, mainly,
subharmonic oscillation at duty cycles over 50%. The
NCP5173 solves this problem by adopting a slope
compensation scheme in which a fixed ramp generated by
the oscillator is added to the current ramp. A proper slope
rate is provided to improve circuit stability without
sacrificing the advantages of current mode control.
Error Amplifier
VC
1.276 V +
−
FB
1M
120 pF
Voltage
Clamp
C1
0.01 F
R1
5 k
positive error−amp
Figure 23. Error Amplifier Equivalent Circuit
The FB pin is directly connected to the inverting input of
the positive error amplifier, whose non−inverting input is
fed by the 1.276 V reference. The transconductance
amplifier has a high output impedance of approximately
1.0 M, as shown in Figure 23. The VC pin is connected to
the output of the error amplifier and is internally clamped
between 0.5 V and 1.7 V. A typical connection at the VC pin
includes a capacitor in series with a resistor to ground,
forming a pole/zero for loop compensation.
An external shunt can be connected between the VC pin
and ground to reduce its clamp voltage. Consequently, the
current limit of the internal power transistor current is
reduced from its nominal value.
Oscillator and Shutdown
Sync
Current
Ramp
VSW
Figure 22. Timing Diagram of Sync and Shutdown
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NCP5173
Switch Driver and Power Switch
output through the inductor and diode. Once VCC reaches
approximately 1.5 V, the internal power switch briefly turns
on. This is a part of the NCP5173’s normal operation. The
turn−on of the power switch accounts for the initial current
swing.
When the VC pin voltage rises above the threshold, the
internal power switch starts to switch and a voltage pulse can
be seen at the VSW pin. Detecting a low output voltage at the
FB pin, the built−in frequency shift feature reduces the
switching frequency to a fraction of its nominal value,
reducing the minimum duty cycle, which is otherwise
limited by the minimum on−time of the switch. The peak
current during this phase is clamped by the internal current
limit.
When the FB pin voltage rises above 0.4 V, the frequency
increases to its nominal value, and the peak current begins
to decrease as the output approaches the regulation voltage.
The overshoot of the output voltage is prevented by the
active pull−on, by which the sink current of the error
amplifier is increased once an overvoltage condition is
detected. The overvoltage condition is defined as when the
FB pin voltage is 50 mV greater than the reference voltage.
The switch driver receives a control signal from the logic
section to drive the output power switch. The switch is
grounded through emitter resistors (63 m total) to the
PGND pin. PGND is not connected to the IC substrate so that
switching noise can be isolated from the analog ground. The
peak switching current is clamped by an internal circuit. The
clamp current is guaranteed to be greater than 1.5 A and
varies with duty cycle due to slope compensation. The
power switch can withstand a maximum voltage of 40 V on
the collector (VSW pin). The saturation voltage of the switch
is typically less than 1.0 V to minimize power dissipation.
Short Circuit Condition
When a short circuit condition happens in a boost circuit,
the inductor current will increase during the whole
switching cycle, causing excessive current to be drawn from
the input power supply. Since control ICs don’t have the
means to limit load current, an external current limit circuit
(such as a fuse or relay) has to be implemented to protect the
load, power supply and ICs.
In other topologies, the frequency shift built into the IC
prevents damage to the chip and external components. This
feature reduces the minimum duty cycle and allows the
transformer secondary to absorb excess energy before the
switch turns back on.
COMPONENT SELECTION
Frequency Compensation
The goal of frequency compensation is to achieve
desirable transient response and DC regulation while
ensuring the stability of the system. A typical compensation
network, as shown in Figure 25, provides a frequency
response of two poles and one zero. This frequency response
is further illustrated in the Bode plot shown in Figure 26.
IL
VOUT
VCC
VC
R1
VC
NCP5173
C2
C1
GND
Figure 24. Startup Waveforms of Circuit Shown in
the Application Diagram. Load = 400 mA.
Figure 25. A Typical Compensation Network
The NCP5173 can be activated by either connecting the
VCC pin to a voltage source or by enabling the SS pin.
Startup waveforms shown in Figure 24 are measured in the
boost converter demonstrated in the Application Diagram
on the Page 2 of this document. Recorded after the input
voltage is turned on, this waveform shows the various
phases during the power up transition.
When the VCC voltage is below the minimum supply
voltage, the VSW pin is in high impedance. Therefore,
current conducts directly from the input power source to the
The high DC gain in Figure 26 is desirable for achieving
DC accuracy over line and load variations. The DC gain of
a transconductance error amplifier can be calculated as
follows:
GainDC GM RO
where:
GM = error amplifier transconductance;
RO = error amplifier output resistance ≈ 1.0 M.
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NCP5173
The low frequency pole, fP1, is determined by the error
amplifier output resistance and C1 as:
1
fP1 2C1R
where:
VF = output diode forward voltage.
In the flyback topology, peak VSW voltage is governed by:
VSW(MAX) VCC(MAX)(VOUTVF) N
O
The first zero generated by C1 and R1 is:
where:
N = transformer turns ratio, primary over secondary.
When the power switch turns off, there exists a voltage
spike superimposed on top of the steady−state voltage.
Usually this voltage spike is caused by transformer leakage
inductance charging stray capacitance between the VSW and
PGND pins. To prevent the voltage at the VSW pin from
exceeding the maximum rating, a transient voltage
suppressor in series with a diode is paralleled with the
primary windings. Another method of clamping switch
voltage is to connect a transient voltage suppressor between
the VSW pin and ground.
1
fZ1 2C1R1
The phase lead provided by this zero ensures that the loop
has at least a 45° phase margin at the crossover frequency.
Therefore, this zero should be placed close to the pole
generated in the power stage which can be identified at
frequency:
1
fP 2CORLOAD
where:
CO = equivalent output capacitance of the error amplifier
≈120 pF;
RLOAD= load resistance.
The high frequency pole, fP2, can be placed at the output
filter’s ESR zero or at half the switching frequency. Placing
the pole at this frequency will cut down on switching noise.
The frequency of this pole is determined by the value of C2
and R1:
Magnetic Component Selection
When choosing a magnetic component, one must consider
factors such as peak current, core and ferrite material, output
voltage ripple, EMI, temperature range, physical size and
cost. In boost circuits, the average inductor current is the
product of output current and voltage gain (VOUT/VCC),
assuming 100% energy transfer efficiency. In continuous
conduction mode, inductor ripple current is:
1
fP2 2C2R1
V (V
VCC)
IRIPPLE CC OUT
(f)(L)(VOUT)
DC Gain
One simple method to ensure adequate phase margin is to
design the frequency response with a −20 dB per decade
slope, until unity−gain crossover. The crossover frequency
should be selected at the midpoint between fZ1 and fP2 where
the phase margin is maximized.
where:
f = 560 kHz
The peak inductor current is equal to average current plus
half of the ripple current, which should not cause inductor
saturation. The above equation can also be referenced when
selecting the value of the inductor based on the tolerance of
the ripple current in the circuits. Small ripple current
provides the benefits of small input capacitors and greater
output current capability. A core geometry like a rod or
barrel is prone to generating high magnetic field radiation,
but is relatively cheap and small. Other core geometries,
such as toroids, provide a closed magnetic loop to prevent
EMI.
fP1
Gain (dB)
fZ1
fP2
Input Capacitor Selection
In boost circuits, the inductor becomes part of the input
filter, as shown in Figure 28. In continuous mode, the input
current waveform is triangular and does not contain a large
pulsed current, as shown in Figure 27. This reduces the
requirements imposed on the input capacitor selection.
During continuous conduction mode, the peak to peak
inductor ripple current is given in the previous section. As
we can see from Figure 27, the product of the inductor
current ripple and the input capacitor’s effective series
resistance (ESR) determine the VCC ripple. In most
applications, input capacitors in the range of 10 F to
100F with an ESR less than 0.3 work well up to a full
1.5 A switch current.
Frequency (LOG)
Figure 26. Bode Plot of the Compensation Network
Shown in Figure 25
VSW Voltage Limit
In the boost topology, VSW pin maximum voltage is set by
the maximum output voltage plus the output diode forward
voltage. The diode forward voltage is typically 0.5 V for
Schottky diodes and 0.8 V for ultrafast recovery diodes:
VSW(MAX) VOUT(MAX)VF
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NCP5173
By examining the waveforms shown in Figure 29, we can
see that the output voltage ripple comes from two major
sources, namely capacitor ESR and the charging/
discharging of the output capacitor. In boost circuits, when
the power switch turns off, IL flows into the output capacitor
causing an instant V = IIN × ESR. At the same time, current
IL − IOUT charges the capacitor and increases the output
voltage gradually. When the power switch is turned on, IL is
shunted to ground and IOUT discharges the output capacitor.
When the IL ripple is small enough, IL can be treated as a
constant and is equal to input current IIN. Summing up, the
output voltage peak−peak ripple can be calculated by:
VCC ripple
IIN
IL
(I IOUT)(1 D)
VOUT(RIPPLE) IN
(COUT)(f)
I
D
OUT
IIN ESR
(COUT)(f)
Figure 27. Boost Input Voltage and Current
Ripple Waveforms
IL
IIN
VCC
+
−
The equation can be expressed more conveniently in
terms of VCC, VOUT and IOUT for design purposes as
follows:
I
(V
VCC)
1
VOUT(RIPPLE) OUT OUT
(COUT)(f)
(COUT)(f)
CIN
(I
)(V
)(ESR)
OUT OUT
VCC
RESR
The capacitor RMS ripple current is:
IRIPPLE (IIN IOUT)2(1 D)(IOUT)2(D)
IOUT
Figure 28. Boost Circuit Effective Input Filter
The situation is different in a flyback circuit. The input
current is discontinuous and a significant pulsed current is
seen by the input capacitors. Therefore, there are two
requirements for capacitors in a flyback regulator: energy
storage and filtering. To maintain a stable voltage supply to
the chip, a storage capacitor larger than 20 F with low ESR
is required. To reduce the noise generated by the inductor,
insert a 1.0F ceramic capacitor between VCC and ground
as close as possible to the chip.
VOUT VCC
VCC
Although the above equations apply only for boost
circuits, similar equations can be derived for flyback
circuits.
Reducing the Current Limit
In some applications, the designer may prefer a lower
limit on the switch current than 1.5 A. An external shunt can
be connected between the VC pin and ground to reduce its
clamp voltage. Consequently, the current limit of the
internal power transistor current is reduced from its nominal
value.
The voltage on the VC pin can be evaluated with the
equation:
Output Capacitor Selection
VC ISWREAV
where:
RE = .063 , the value of the internal emitter resistor;
AV = 5.0 V/V, the gain of the current sense amplifier.
Since RE and AV cannot be changed by the end user, the
only available method for limiting switch current below
1.5 A is to clamp the VC pin at a lower voltage. If the
maximum switch or inductor current is substituted into the
equation above, the desired clamp voltage will result.
VOUT ripple
IL
Figure 29. Typical Output Voltage Ripple
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NCP5173
A simple diode clamp, as shown in Figure 30, clamps the
VC voltage to a diode drop above the voltage on resistor R3.
Unfortunately, such a simple circuit is not generally
acceptable if VIN is loosely regulated.
The improved circuit does not require a regulated voltage
to operate properly. Unfortunately, a price must be paid for
this convenience in the overall efficiency of the circuit. The
designer should note that the input and output grounds are
no longer common. Also, the addition of the current sense
resistor, RSENSE, results in a considerable power loss which
increases with the duty cycle. Resistor R2 and capacitor C3
form a low−pass filter to remove noise.
VIN
VCC
R2
Subharmonic Oscillation
Subharmonic oscillation (SHM) is a problem found in
current−mode control systems, where instability results
when duty cycle exceeds 50%. SHM only occurs in
switching regulators with a continuous inductor current.
This instability is not harmful to the converter and usually
does not affect the output voltage regulation. SHM will
increase the radiated EM noise from the converter and can
cause, under certain circumstances, the inductor to emit
high−frequency audible noise.
SHM is an easily remedied problem. The rising slope of
the inductor current is supplemented with internal “slope
compensation” to prevent any duty cycle instability from
carrying through to the next switching cycle. In the
NCP5173, slope compensation is added during the entire
switch on−time, typically in the amount of 180 mA/s.
In some cases, SHM can rear its ugly head despite the
presence of the onboard slope compensation. The simple
cure to this problem is more slope compensation to avoid the
unwanted oscillation. In that case, an external circuit, shown
in Figure 32, can be added to increase the amount of slope
compensation used. This circuit requires only a few
components and is “tacked on” to the compensation
network.
VC
D1
R3
R1
C1
C2
Figure 30. Current Limiting Using a Diode Clamp
Another solution to the current limiting problem is to
externally measure the current through the switch using a
sense resistor. Such a circuit is illustrated in Figure 31.
VCC
PGND AGND
VSW
−
+
VIN
VC
VC
R1
Q1
R2
VSW
C1
C2
C3
RSENSE
R1
Output
Ground
R2
C1
Figure 31. Current Limiting using a Current Sense
Resistor
C2
The switch current is limited to:
VBE(Q1)
ISWITCH(PEAK) RSENSE
C3
where:
VBE(Q1) = the base−emitter voltage drop of Q1, typically
0.65 V.
R3
Figure 32. Technique for Increasing Slope
Compensation
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NCP5173
The dashed box contains the normal compensation
circuitry to limit the bandwidth of the error amplifier.
Resistors R2 and R3 form a voltage divider off of the VSW
pin. In normal operation, VSW looks similar to a square
wave, and is dependent on the converter topology. Formulas
for calculating VSW in the boost and flyback topologies are
given in the section “VSW Voltage Limit.” The voltage on
VSW charges capacitor C3 when the switch is off, causing
the voltage at the VC pin to shift upwards. When the switch
turns on, C3 discharges through R3, producing a negative
slope at the VC pin. This negative slope provides the slope
compensation.
The amount of slope compensation added by this circuit is:
R3
I V
SW R R
T
2
3
1 (1D)
e R3C3fSW
VIN
VCC
SS
SS
VC
D2
D1
R1
C1
C3
fSW
(1 D)REAV
where:
I/T = the amount of slope compensation added (A/s);
VSW = the voltage at the switch node when the transistor
is turned off (V);
fSW = the switching frequency, typically 560 kHz;
D = the duty cycle;
RE = 0.063 , the value of the internal emitter resistor;
AV = 5.0 V/V, the gain of the current sense amplifier.
In selecting appropriate values for the slope compensation
network, the designer is advised to choose a convenient
capacitor, then select values for R2 and R3 such that the
amount of slope compensation added is 100 mA/s. Then
R2 may be increased or decreased as necessary. Of course,
the series combination of R2 and R3 should be large enough
to avoid drawing excessive current from VSW. Additionally,
to ensure that the control loop stability is improved, the time
constant formed by the additional components should be
chosen such that:
C2
Figure 33. Soft−Start
Resistor R1 and capacitors C1 and C2 form the
compensation network. At turn on, the voltage at the VC pin
starts to come up, charging capacitor C3 through Schottky
diode D2, clamping the voltage at the VC pin such that
switching begins when VC reaches the VC threshold,
typically 1.05 V (refer to graphs for detail over
temperature).
VC VF(D2)VC3
Therefore, C3 slows the startup of the circuit by limiting
the voltage on the VC pin. The soft−start time increases with
the size of C3.
Diode D1 discharges C3 when SS is low. If the shutdown
function is not used with this part, the cathode of D1 should
be connected to VIN.
R3C3 1 D
fSW
Calculating Junction Temperature
Finally, it is worth mentioning that the added slope
compensation is a trade−off between duty cycle stability and
transient response. The more slope compensation a designer
adds, the slower the transient response will be, due to the
external circuitry interfering with the proper operation of the
error amplifier.
To ensure safe operation, the designer must calculate the
on−chip power dissipation and determine its expected
junction temperature. Internal thermal protection circuitry
will turn the part off once the junction temperature exceeds
180°C ± 30°. However, repeated operation at such high
temperatures will reduce operating life.
Calculation of the junction temperature is an imprecise
but simple task. First, the power losses must be quantified.
There are three major sources of power loss on the
NCP5173:
• biasing of internal control circuitry, PBIAS
• switch driver, PDRIVER
• switch saturation, PSAT
Soft−Start
Through the addition of an external circuit, a soft−start
function can be added to the NCP5173. Soft−start circuitry
prevents the VC pin from slamming high during startup,
thereby inhibiting the inductor current from rising at a high
slope.
This circuit, shown in Figure 33, requires a minimum
number of components and allows the soft−start circuitry to
activate any time the SS pin is used to restart the converter.
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NCP5173
or junction−to−ambient thermal resistance. The on−chip
junction temperature can be calculated if JA, the air
temperature near the surface of the IC, and the on−chip
power dissipation are known.
The internal control circuitry, including the oscillator and
linear regulator, requires a small amount of power even
when the switch is turned off. The specifications section of
this datasheet reveals that the typical operating current, IQ,
due to this circuitry is 5.5 mA. Additional guidance can be
found in the graph of operating current vs. temperature. This
graph shows that IQ is strongly dependent on input voltage,
VIN, and temperature. Then:
TJ TA(PDJA)
where:
TJ = IC or FET junction temperature (°C);
TA = ambient temperature (°C);
PD = power dissipated by part in question (W);
JA = junction−to−ambient thermal resistance (°C/W).
PBIAS VINIQ
Since the onboard switch is an NPN transistor, the base
drive current must be factored in as well. This current is
drawn from the VIN pin, in addition to the control circuitry
current. The base drive current is listed in the specifications
as ICC/ISW, or switch transconductance. As before, the
designer will find additional guidance in the graphs. With
that information, the designer can calculate:
For the NCP5173, JA = 35°C/W.
Once the designer has calculated TJ, the question of
whether the IC can be used in an application is settled. If TJ
exceeds 150°C, the absolute maximum allowable junction
temperature, the NCP5173 is not suitable for that
application.
If TJ approaches 150°C, the designer should consider
possible means of reducing the junction temperature.
Perhaps another converter topology could be selected to
reduce the switch current. Increasing the airflow across the
surface of the chip might be considered to reduce TA. A
copper “landing pad” can be connected to the ground pin −
Designers are referred to ON Semiconductor Application
Note AND8036/D for more information on properly sizing
a copper area.
I
PDRIVER VINISW CC D
ISW
where:
ISW = the current through the switch;
D = the duty cycle or percentage of switch on−time.
ISW and D are dependent on the type of converter. In a
boost converter,
1
ISW(AVG) ILOAD D Efficiency
V
VIN
D OUT
VOUT
Circuit Layout Guidelines
In any switching power supply, circuit layout is very
important for proper operation. Rapidly switching currents
combined with trace inductance generates voltage
transitions that can cause problems. Therefore the following
guidelines should be followed in the layout.
In a flyback converter,
V
I
1
ISW(AVG) OUT LOAD VIN
Efficiency
D
VOUT
1.
N
VOUT NSP VIN
The switch saturation voltage, V(CE)SAT, is the last major
source of on−chip power loss. V(CE)SAT is the
collector−emitter voltage of the internal NPN transistor
when it is driven into saturation by its base drive current. The
value for V(CE)SAT can be obtained from the specifications
or from the graphs, as “Switch Saturation Voltage.” Thus,
PSAT V(CE)SATISW D
Finally, the total on−chip power losses are:
PD PBIASPDRIVERPSAT
2.
Power dissipation in a semiconductor device results in the
generation of heat in the junctions at the surface of the chip.
This heat is transferred to the surface of the IC package, but
a thermal gradient exists due to the resistive properties of the
package molding compound. The magnitude of the thermal
gradient is expressed in manufacturers’ data sheets as JA,
3.
In boost circuits, high AC current circulates within the
loop composed of the diode, output capacitor, and
on−chip power transistor. The length of associated
traces and leads should be kept as short as possible. In
the flyback circuit, high AC current loops exist on both
sides of the transformer. On the primary side, the loop
consists of the input capacitor, transformer, and
on−chip power transistor, while the transformer,
rectifier diodes, and output capacitors form another
loop on the secondary side. Just as in the boost circuit,
all traces and leads containing large AC currents
should be kept short.
Separate the low current signal grounds from the
power grounds. Use single point grounding or ground
plane construction for the best results.
Locate the voltage feedback resistors as near the IC as
possible to keep the sensitive feedback wiring short.
Connect feedback resistors to the low current analog
ground.
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NCP5173
MBRS140T3
VCC
−12 V
P6KE−15A
+
T1
1.0 F
22 F
+
47 F
GND
VCC (5)
GND
1N4148
+
1:2
47 F
PGND (7)
VSW (8)
AGND (6)
NCP5173
VC (1 )
+12 V
MBRS140T3
FB (2)
47 nF
10.72 k
1.28 k
4.7 nF
2.0 k
Figure 34. Additional Application Diagram, 2.7 to 13 V Input, 12 V/ 200 mA Output Flyback Converter
GND
VCC (5)
VC (1 )
GND
5.0 k
2.2 F
1.1 k
22 F
NCP5173
200 pF
.01 F
VIN
Low
ESR
15 H
VSW (8)
AGND (6)
−5.0
VOUT
FB (2)
PGND (7)
300
Figure 35. Additional Application Diagram, −9.0 V to −28 V Input, −5.0 V/700 mA Output Inverted Buck Converter
R1
R2
1.245 k/0.1 W, 1%
99.755 k/0.1 W, 1%
GND
C1
D1
C11
.01 R3
2.0 k
3 Test
4 SS
VSW 8
PGND 7
NCP5173
C10
.1 1 V
C
2 FB
AGND
VCC
.1 50 V
D1
D1
C3
.1 50 V
D1
D1
.1 50 V
D1
D1
100 VO
1N4148 1N4148
6
5
C2
C8
10 C9
.1 C7
.1 50 V
C4
.1 50 V
1N4148 1N4148 1N4148 1N4148 1N4148
C5
.1 50 V
C6
.1 50 V
4.0 V
Figure 36. Additional Application Diagram, 4.0 V Input, 100 V/ 10 mA Output Boost Converter with
Output Voltage Multiplier
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GND
NCP5173
PACKAGE DIMENSIONS
5x6 QFN
MN SUFFIX
CASE 505AC−01
ISSUE A
D
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
A
B
PIN ONE
LOCATION
E
2X
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
0.15 C
TOP VIEW
0.15 C
2X
(A3)
0.10 C
A
0.08 C
SIDE VIEW
A1
C
SEATING
PLANE
D2
8X
L
e
1
4
E2
8X
K
8
5
b
BOTTOM VIEW
8X
NOTE 3
0.10 C A
B
0.05 C
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MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.20 REF
0.35
0.50
6.00 BSC
3.95
4.25
5.00 BSC
2.95
3.25
1.27 BSC
0.20
−−−
0.45
0.65
NCP5173
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
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For additional information, please contact your
local Sales Representative.
NCP5173/D