Fairchild FM24C256YYX 256 kbit 2-wire bus interface serial eeprom with write protect Datasheet

FM24C256
256 KBit 2-Wire Bus Interface
Serial EEPROM with Write Protect
General Description
Features
The FM24C256/C256L/C256LZ devices are 256 Kbits CMOS
nonvolatile electrically erasable memory. These devices offer the
designer different low voltage and low power options. They
conform to all requirements in the Extended IIC 2-wire protocol.
Furthermore, they are designed to minimize device pin count and
simplify PC board layout requirements.
■ Extended Operating Voltages
— C256: 4.5V - 5.5V
— C256L: 2.7V - 5.5V
— C256LZ: 2.7V - 5.5V
■ Low Power CMOS
— 1mA active current typical
— C256/C256L: 10µA standby current typical
— C256LZ: less than 1µA standby current
The entire memory array can be write disabled (Write Protection)
by connecting the WP pin to VCC.
■ 2-wire IIC serial interface
Functional address lines allow up to eight devices on the same
bus, for up to a total of 2 Mbit address space.
■ 64 byte page write mode
■ Max write cycle time of 6ms byte/page
The IIC communication protocol uses CLOCK (SCL) and DATA
I/O (SDA) lines to synchronously clock data between the master
(for example a microprocessor) and the slave EEPROM device(s).
■ 40 years data retention
■ Endurance: 100,000 data changes
■ Hardware write protect for entire array
Fairchild EEPROMs are designed and tested for applications
requiring high endurance, high reliability, and low power consumption.
■ Schmitt trigger inputs for noise suppression
■ Electrostatic discharge protection > 4000V
■ 8-pin DIP and 8-pin SO (150 mil) packages. Contact factory
for CSP package availability
Block Diagram
WRITE
LOCKOUT
VCC
WP
START CYCLE
H.V. GENERATION
TIMING &CONTROL
START
STOP
LOGIC
SDA
CONTROL
LOGIC
SLAVE ADDRESS
REGISTER &
COMPARATOR
SCL
XDEC
LOAD
A2
A1
A0
E2PROM
ARRAY
INC
WORD
ADDRESS
COUNTER
R/W
YDEC
CK
DATA REGISTER
DIN
DOUT
DS800023-1
© 2000 Fairchild Semiconductor International
FM24C256 rev. B.3
1
www.fairchildsemi.com
FM24C256 256 KBit 2-Wire Bus Interface Serial EEPROM with Write Protect
June 2000
FM24C256 256 KBit 2-Wire Bus Interface Serial EEPROM with Write Protect
Connection Diagram
Dual-In-Line Package (N)
and 8-Pin SO Package (M8)
A0
1
A1
2
8
VCC
7
WP
FM24C256
A2
3
6
SCL
VSS
4
5
SDA
DS800023-2
Top View
See Package Number N08E and M08A
Pin Names
A0, A1, A2
Device Address Input
VSS
Ground
SDA
Data I/O
SCL
Clock Input
WP
Write Protect
VCC
Power Supply
2
FM24C256 rev. B.3
www.fairchildsemi.com
Commercial Temperature Range: 0° to +70°C
Part Number
Clock Frequency
FM24C256YYX
FM24C256LYYX
100KHz
VCC
Standby Current
4.5V - 5.5V
10µA typical
2.7V - 5.5V
FM24C256LZYYX
1µA max
FM24C256FYYX
4.5V - 5.5V
FM24C256FLYYX
400KHz
10µA typical
2.7V - 5.5V
FM24C256FLZYYX
1µA max
Industrial Temperature Range: -40° to +85°C
Part Number
Clock Frequency
FM24C256EYYX
FM24C256LEYYX
100KHz
VCC
Standby Current
4.5V - 5.5V
10µA typical
2.7V - 5.5V
FM24C256LZEYYX
1µA max
FM24C256FEYYX
4.5V - 5.5V
FM24C256FLEYYX
400KHz
10µA typical
2.7V - 5.5V
FM24C256FLZEYYX
FM
24
C
XX
F
1µA max
LZ
E
YY
X
Letter
Description
Blank
X
Tube
Tape and Reel
N
M8
8-pin DIP
8-pin SO8
Temp. Range
Blank
E
0 to 70°C
-40 to +85°C
Voltage Operating Range
Blank
L
LZ
4.5V to 5.5V
2.7V to 5.5V
2.7V to 5.5V and
<1µA Standby Current
SCL Clock Frequency
Blank
F
100KHz
400KHz
256
256K with write protect
C
CMOS
24
IIC - 2 Wire
FM
Fairchild Non-Volatile
Memory
Package
Density
Interface
3
FM24C256 rev. B.3
www.fairchildsemi.com
FM24C256 256 KBit 2-Wire Bus Interface Serial EEPROM with Write Protect
Ordering Information
Ambient Storage Temperature
Operating Conditions
–65°C to +150°C
All Input or Output Voltages
with Respect to Ground
6.5V to –0.3V
Lead Temperature
(Soldering, 10 seconds)
+300°C
ESD Rating
Ambient Operating Temperature
FM24C256/L/LZ
FM24C256F/FL/FLZ
FM24C256E/LE/LZE
FM24C256FE/FLE/FLZE
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
Positive Power Supply
FM24C256/E
FM24C256F/FE
FM24C256L/LZ
FM24C256FL/FLZ
FM24C256LE/LZE
FM24C256FLE/FLZE
4000V min.
4.5V to 5.5V
4.5V to 5.5V
2.7V to 5.5V
2.7V to 5.5V
2.7V to 5.5V
2.7V to 4.5V
Standard VCC (4.5V to 5.5V) DC Electrical Characteristics
Symbol
Parameter
Test Conditions
Min
Limits
Typ
Max
Units
ICCA
Active Power Supply Current
fSCL = 100 kHz
fSCL = 400 kHz
0.5
1.0
mA
ISB
Standby Current
VIN = GND or VCC
10
50
µA
ILI
Input Leakage Current
VIN = GND to VCC
0.1
1
µA
ILO
Output Leakage Current
VOUT = GND to VCC
0.1
1
µA
VIL
Input Low Voltage
–0.3
VCC x 0.3
V
VIH
Input High Voltage
VCC x 0.7
VCC + 0.5
V
VOL
Output Low Voltage
0.4
V
IOL = 2.1 mA
Low VCC (2.7V to 5.5V) DC Electrical Characteristics
Symbol
Parameter
Test Conditions
Min
ICCA
ISB
(Note 1)
Limits
Typ
Max
Units
Active Power Supply Current
fSCL = 100 kHz
fSCL = 400 kHz
0.5
1.0
mA
Standby Current for L
VIN = GND or VCC = 4.5V - 5.5V
VIN = GND or VCC = 2.7V - 4.5V
VIN = GND or VCC = 4.5V - 5.5V
VIN = GND or VCC = 2.7V - 4.5V
10
1
10
0.1
50
10
50
1
µA
Standby Current for LZ
ILI
Input Leakage Current
VIN = GND to VCC
0.1
1
µA
ILO
Output Leakage Current
VOUT = GND to VCC
0.1
1
µA
VIL
Input Low Voltage
–0.3
VCC x 0.3
V
VIH
Input High Voltage
VCC x 0.7
VCC + 0.5
V
VOL
Output Low Voltage
0.4
V
IOL = 2.1 mA
Capacitance TA = +25°C, f = 100/400 KHz, VCC = 5V
Symbol
Test
Conditions
Max
Units
CI/O
Input/Output Capacitance (SDA)
VI/O = 0V
8
pF
CIN
Input Capacitance (A0, A1, A2, SCL)
VIN = 0V
6
pF
Note 1: Typical values are for TA = 25°C and nominal supply voltage (5V).
4
FM24C256 rev. B.3
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FM24C256 256 KBit 2-Wire Bus Interface Serial EEPROM with Write Protect
Absolute Maximum Ratings
Input Pulse Levels
VCC x 0.1 to VCC x 0.9
Input Rise and Fall Times
10 ns
Input & Output Timing Levels
VCC x 0.5
Output Load
1 TTL Gate and CL = 100 pF
Read and Write Cycle Limits (Standard and Low VCC Range - 2.7V-5.5V)
Symbol
fSCL
TI
Parameter
100 kHz
Min
Max
400 kHz
Min
Max
Units
SCL Clock Frequency
100
400
kHz
Noise Suppression Time Constant at
SCL, SDA Inputs (Minimum VIN
Pulse width)
100
50
ns
1.2
µs
tAA
SCL Low to SDA Data Out Valid
0.3
tBUF
Time the Bus Must Be Free before
a New Transmission Can Start
4.7
1.3
µs
Start Condition Hold Time
4.0
0.6
µs
tLOW
Clock Low Period
4.7
1.5
µs
tHIGH
Clock High Period
4.0
0.6
µs
tSU:STA
Start Condition Setup Time
(for a Repeated Start Condition)
4.7
0.6
µs
tHD:DAT
Data in Hold Time
0
0
µs
tSU:DAT
Data in Setup Time
250
100
ns
tHD:STA
3.5
0.3
tR
SDA and SCL Rise Time
1
0.3
µs
tF
SDA and SCL Fall Time
300
300
ns
tSU:STO
tDH
tWR
(Note 2)
Stop Condition Setup Time
4.7
0.6
µs
Data Out Hold Time
100
100
ns
Write Cycle Time
6
6
ms
Note 2: The write cycle time (tWR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle, the
FM24C256 bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and the device does not respond to its slave address
5
FM24C256 rev. B.3
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FM24C256 256 KBit 2-Wire Bus Interface Serial EEPROM with Write Protect
AC Conditions of Test
tR
tF
tHIGH
tLOW
tLOW
SCL
;;
tSU:STA
SDA
tHD:STA
tHD:DAT
tSU:DAT
tSU:STO
IN
tBUF
tAA
tDH
SDA
OUT
Note 3: SCL = Serial Clock Data
SDA = Serial Data I/O
DS800023-3
BACKGROUND INFORMATION (IIC Bus)
SERIAL DATA (SDA)
The IIC bus allows synchronous bidirectional communication between Transmitter/Receiver using the SCL (clock) and SDA (Data
I/O) lines. All communication must be started with a valid START
condition, concluded with a STOP condition and acknowledged by
the Receiver with an ACKNOWLEDGE condition.
SDA is a bidirectional pin used to transfer data to and from the
device. It is an open drain output and may be wire-ORed with any
number of open drain or open collector outputs.
In addition, since the IIC bus is designed to support other devices
such as RAM, EPROM, etc., the device type identifier string, or
control byte, must follow the START condition. For EEPROMs, the
first 4-bit of the control byte is 1010 binary for READ and WRITE
operations. This is then followed by the device selection bits A2, A1
and A0, and acts as the three most significant bits of the word
address.The final bit in the control byte determines the type of
operation performed (READ/WRITE). A "1" signifies a READ while
a "0" signifies a WRITE. The control byte is then followed by two bytes
that define the word address, which is then followed by the data byte.
Device address pins A0, A1, and A2 are connected to VCC or VSS
to configure the EEPROM address for multiple device configuration. A total of eight different devices can be attached to the same
SDA bus.
Device Address Inputs (A0, A1, A2)
Write Protection (WP)
If WP is tied to VCC, program WRITE operations onto the entire
array of the memory will not be executed. READ operations are
always available.
If WP is tied to VSS or left floating (unconnected), normal memory
operation is enabled for READ/WRITE over the entire 256K bit
memory array.
The EEPROMs on the IIC bus may be configured in any manner
required, providing the total memory addressed does not exceed
512K bits (64K bytes). EEPROM memory addressing is controlled
by hardware configuring the A2, A1, and A0 pins (Device Address
pins) with pull-up or pull-down resistors. ALL UNUSED PINS
MUST BE GROUNDED (tied to VSS).
This feature allows the user to assign the entire array of the memory
as ROM, which can be protected against accidental programming
writes. When WRITE is disabled, slave address and word address
will be acknowledged but data will not be acknowledged.
Addressing an EEPROM memory location involves sending a
command string with the following information:
Device Operation
The FM24C256xxx supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the bus as a
transmitter and the receiving devices as the receiver. The device
controlling the transfer is the master and the device that is controlled is the slave. The master will always initiate data transfers and
provide the clock for both transmit and receive operations. Therefore, the FM24C256xxx is considered a slave in all applications.
[DEVICE TYPE]-[DEVICE ADDRESS]-[PAGE BLOCK ADDRESS]-[BYTE ADDRESS]
Pin Description
SERIAL CLOCK (SCL)
Definitions
Word
8 bits (byte) of data
Page
64 sequential addresses (one byte each) that
may be programmed during a "Page Write"
programming cycle.
Master
Any IIC device CONTROLLING the transfer of
data (such as a microcontroller).
Slave
Device being controlled (EEPROMS are
always considered Slaves).
Transmitter
Device currently SENDING data on the bus
(may be either a Master or Slave).
Receiver
Device currently receiving data on the bus
(Master or Slave).
CLOCK AND DATA CONVENTIONS
Data states on the SDA line can change only during SCL LOW.
SDA state changes during SCL HIGH and are reserved for
indication of start and stop conditions. Refer to Figures 1 and 2.
START CONDITION
All commands are preceded by the start condition, which is a
HIGH to LOW transition of SDA when SCL is HIGH. The
FM24C256xxx continuously monitors the SDA and SCL lines for
the start condition and will not respond to any command until this
condition has been met.
STOP CONDITION
All communications are terminated by a stop condition, which is a
LOW to HIGH transition of SDA when SCL is HIGH. The stop
condition is also used by the FM24C256xxx to place the device in
the standby power mode.
The SCL input is used to clock all data into and out of the device.
6
FM24C256 rev. B.3
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FM24C256 256 KBit 2-Wire Bus Interface Serial EEPROM with Write Protect
Bus Timing
both the device and a WRITE operation have been selected, the
FM24C256xxx will respond with an acknowledge after the receipt
of each subsequent eight bit word.
ACKNOWLEDGE
ACK (acknowledge) is a software convention used to indicate
successful data transfers. The transmitting device, either master or
slave, will release the bus after transmitting eight bits. During the ninth
clock cycle the receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data. Refer to Figure 3.
In the READ mode the FM24C256xxx slave will transmit eight bits
of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is
generated by the master, the slave will continue to transmit data.
If an acknowledge is not detected, the slave will terminate further
data transmissions and await the stop condition to return to the
standby power mode.
The FM24C256xxx device will always respond with an acknowledge after recognition of a start condition and its slave address. If
Write Cycle Timing:
SCL
SDA
8th BIT
ACK
WORD n
tWR
START
CONDITION
STOP
CONDITION
DS800023-4
Data Validity (Figure 1)
SCL
DATA
CHANGE
DATA STABLE
SDA
DS800023-5
Definition of Start and Stop (Figure 2)
SCL
SDA
START CONDITION
STOP CONDITION
DS800023-6
Acknowledge Response from Receiver (Figure 3)
SCL FROM
MASTER
1
8
9
Data Output
from Transmitter
Data Output
from Receiver
START
ACKNOWLEDGE
7
FM24C256 rev. B.3
DS800023-7
www.fairchildsemi.com
FM24C256 256 KBit 2-Wire Bus Interface Serial EEPROM with Write Protect
Write Cycle Timing
Following a start condition the master must output the address of
the slave it is accessing. The most significant four bits of the slave
address are those of the device type identifier. This is fixed as
1010 for all different FM24C256xxx devices.
The next three bits identify the device address. Address from 000
to 111 are acceptable thus allowing up to eight devices to be
connected to the IIC bus.
PAGE WRITE
The FM24C256xxx is capable of 64 byte page write operation. It
is initiated in the same manner as the byte write operation; but
instead of terminating the write cycle after the first data word is
transferred, the master can transmit up to 63 more words. After
the receipt of each word, the device responds with an acknowledge.
The last bit of the slave address defines whether a write or read
condition is requested by the master. A "1" indicates that a READ
operation is to be executed and a "0" initiates the WRITE mode.
A simple review: After the FM24C256xxx recognizes the start
condition, the device interfaced to the IIC bus waits for a slave
address to be transmitted over the SDA line. If the transmitted
slave address matches an address of one of the devices, the
designated slave pulls the SDA line LOW with an acknowledge
signal and awaits further transmissions.
After the receipt of each word, the internal address counter
increments to the next address and the next SDA data is accepted. If the master should transmit more than 64 words prior to
generating the stop condition, the address counter will "roll over"
and the previous written data will be overwritten. As with the byte
write operation, all inputs are disabled until completion of the
internal write cycle. Refer to Figure 6 for the address, acknowledge and data transfer sequence.
Write Operations
BYTE WRITE
For a WRITE operation, two additional address fields are required
after the control byte acknowledge. These are the word addresses
and comprise fifteen bits to provide access to any one of the 32K
words. The first byte indicates the high-order byte of the word
address. Only the seven least signicant bits can be changed, the
most significant bit is pre-assigned the value "0". Following the
acknowledgement from the first word address, the next byte
indicates the low-order byte of the word address. Upon receipt of
the word address, the FM24C256xxx responds with another
acknowledge and waits for the next eight bits of data, again,
responding with an acknowledge. The master then terminates the
Acknowledge Polling
Once the stop condition is isssued to indicate the end of the host's
write operation, the FM24C256xxx initiates the internal write
cycle. ACK polling can be initiated immediately. This involves
issuing the start condition followed by the slave address for a write
operation. If the FM24C256xxx is still busy with the write operation, no ACK will be returned. If the device has completed the write
operation, an ACK will be returned and the host can then proceed
with the next read or write operation.
Byte Write (Figure 5)
S
T
Bus Activity: A
Master R
T
SDA Line
Bus Activity
SLAVE
ADDRESS
WORD
ADDRESS (1)
1 0 1 0
WORD
ADDRESS (0)
S
T
O
P
DATA
0
A
C
K
A
C
K
A
C
K
A
C
K
DS800023-8
8
FM24C256 rev. B.3
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FM24C256 256 KBit 2-Wire Bus Interface Serial EEPROM with Write Protect
transfer by generating a stop condition, at which time the
FM24C256xxx begins the internal write cycle to the nonvolatile
memory. While the internal write cycle is in progress, the device's
inputs are disabled and the device will not respond to any requests
from the master. Refer to Figure 5 for the address, acknowledge
and data transfer sequence.
DEVICE ADDRESSING
Programming of the memory array will not take place if the WP pin
is connected to VCC. The device will accept control and word
addresses; but if the memory accessed is write protected by the
WP pin, the FM24C256xxx will not generate an acknowledge after
the first byte of data has been received, and thus the program
cycle will not be started when the stop condition is asserted.
Read Operation
Read operations are initiated in the same manner as write
operations, with the exception that the R/W bit of the slave address
is set to "1". There are three basic read operations: current
address read, random read and sequential read.
SEQUENTIAL READ
Sequential reads can be initiated as either a current address read
or random access read. The first word is transmitted in the same
manner as the other read modes; however, the master now
responds with an acknowledge, indicating it requires additional
data. The FM24C256xxx continues to output data for each acknowledge received. The read operation is terminated by the
master not responding with an acknowledge or by generating a
stop condition.
CURRENT ADDRESS READ
Internally the FM24C256xxx contains an address counter that
maintains the address of the last word accessed, incremented by
one. Therefore, if the last access (either a read or write) was to
address n, the next read operation would access data from
address n+1. Upon receipt of the slave address with R/W set to
"1," the FM24C256xxx issues an acknowledge and transmits the
eight bit word. The master will not acknowledge the transfer but
does generate a stop condition, and therefore discontinues transmission. Refer to Figure 7 for the sequence of address, acknowledge and data transfer.
The data output is sequential, with the data from address n,
followed by the data n+1. The address counter for read operations
increments all word address bits, allowing the entire memory
contents to be serially read during one operation. After the entire
memory has been read, the counter "rolls over" and the
FM24C256xxx continues to output data for each acknowledge
received. Refer to Figure 9 for the address, acknowledge, and
data transfer sequence.
RANDOM READ
Random read operations allow the master to access any memory
location in a random manner. Prior to issuing the slave address
Page Write (Figure 6)
S
T
Bus Activity: A
Master R
T
SDA Line
Bus Activity
SLAVE
ADDRESS
WORD
ADDRESS (1)
1 0 1 0
WORD
ADDRESS (0)
DATA n
S
T
O
P
DATA n+63
0
A
C
K
A
C
K
A
C
K
A
C
K
DS800023-9
9
FM24C256 rev. B.3
www.fairchildsemi.com
FM24C256 256 KBit 2-Wire Bus Interface Serial EEPROM with Write Protect
with the R/W bit set to "1", the master must first perform a "dummy"
write operation. The master issues a start condition, a slave
address, and then the word address to be read. After the word
address acknowledge, the master immediately reissues the start
condition and the slave address with the R/W bit set to "1". This will
be followed by an acknowledge from the FM24C256xxx and then
by the eight bit word. The master will not acknowledge the transfer
but does generate the stop condition, and therefore the
FM24C256xxx discontinues transmission. Refer to Figure 8 for
the address, acknowledge, and data transfer sequence.
Write Protection
S
T
A
R SLAVE ADDRESS
T
S
T
O
P
DATA
1 0 1 0
A
C
K
NO
A
C
K
DS800023-10
Random Read (Figure 8)
S
T
A
Bus Activity: R
Master T
SDA Line
SLAVE
ADDRESS
WORD
ADDRESS (1)
1 0 1 0
S
T
A
R
T
WORD
ADDRESS (0)
0
1 0 1 0
A
C
K
Bus Activity
SLAVE
ADDRESS
A
C
K
A
C
K
DATA n
S
T
O
P
1 0
A
C
K
NO
A
C
K
DS800023-11
Sequential Read (Figure 9)
S
T
Bus Activity: A
Master R
T
SDA Line
Bus Activity
SLAVE
ADDRESS
DATA n
DATA n + 1
DATA n + x
S
T
O
P
1 0 1 0
A
C
K
A
C
K
A
C
K
A
C
K
NO
A
C
K
DS800023-12
10
FM24C256 rev. B.3
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FM24C256 256 KBit 2-Wire Bus Interface Serial EEPROM with Write Protect
Current Address Read (Figure 7)
FM24C256 256 KBit 2-Wire Bus Interface Serial EEPROM with Write Protect
Physical Dimensions inches (millimeters) unless otherwise noted
0.189 - 0.197
(4.800 - 5.004)
8 7 6 5
0.228 - 0.244
(5.791 - 6.198)
1 2 3 4
Lead #1
IDENT
0.010 - 0.020
x 45¡
(0.254 - 0.508)
0.0075 - 0.0098
(0.190 - 0.249)
Typ. All Leads
0.150 - 0.157
(3.810 - 3.988)
8¡ Max, Typ.
All leads
0.004
(0.102)
All lead tips
0.053 - 0.069
(1.346 - 1.753)
0.004 - 0.010
(0.102 - 0.254)
Seating
Plane
0.014
(0.356)
0.016 - 0.050
(0.406 - 1.270)
Typ. All Leads
0.050
(1.270)
Typ
0.014 - 0.020 Typ.
(0.356 - 0.508)
Molded Small Out-Line Package (M8)
Order Number FM24C256xxxM8 or FM24C256xxxEM8
Package Number M08A
11
FM24C256 rev. B.3
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0.373 - 0.400
(9.474 - 10.16)
0.090
(2.286)
8
0.092
DIA
(2.337)
7
6
0.250 - 0.005
(6.35 ± 0.127)
+
Pin #1 IDENT
0.032 ± 0.005
(0.813 ± 0.127)
RAD
5
1
1
2
3
0.040 Typ.
(1.016)
0.300 - 0.320
(7.62 - 8.128)
7
Pin #1
IDENT
Option 1
0.280 MIN
(7.112)
8
0.030
MAX
(0.762)
20° ± 1°
4
Option 2
0.145 - 0.200
(3.683 - 5.080)
0.039
(0.991)
0.130 ± 0.005
(3.302 ± 0.127)
95° ± 5°
0.009 - 0.015
(0.229 - 0.381)
+0.040
0.325 -0.015
+1.016
8.255 -0.381
0.125
(3.175)
DIA
NOM
0.125 - 0.140
(3.175 - 3.556)
0.065
(1.651)
90° ± 4°
Typ
0.018 ± 0.003
(0.457 ± 0.076)
0.100 ± 0.010
(2.540 ± 0.254)
0.045 ± 0.015
(1.143 ± 0.381)
0.020
(0.508)
Min
0.060
(1.524)
0.050
(1.270)
Molded Dual-In-Line Package (N)
Order Number FM24C256xxxN or FM24C256xxxEN
Package Number N08E
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(a) are intended for surgical implant into the body, or (b) support
or sustain life, and whose failure to perform, when properly
used in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a significant
injury to the user.
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2. A critical component is any component of a life support device
or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system,
or to affect its safety or effectiveness.
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12
FM24C256 rev. B.3
www.fairchildsemi.com
FM24C256 256 KBit 2-Wire Bus Interface Serial EEPROM with Write Protect
Physical Dimensions inches (millimeters) unless otherwise noted