(Rev. 1.0) MITSUBISHI LSIs M5M467400/465400DJ,DTP -5,-6,-5S,-6S M5M467800/465800DJ,DTP -5,-6,-5S,-6S M5M465160DJ,DTP -5,-6,-5S,-6S FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM PRELIMINARY Some of contents are subject to change without notice. DESCRIPTION The M5M467400/465400DJ,DTP is a 16777216-word by 4-bit, M5M467800/465800DJ,DTP is a 8388608-word by 8-bit, and M5M465160DJ,DTP is a 4194304-word by 16-bit dynamic RAMs, fabricated with the high performance CMOS process, and are suitable for large-capacity memory systems with high speed and low power dissipation. FEATURES Address Power RAS OE CAS Cycle access access access access dissipatime tion time time time time (max.ns) (max.ns) (max.ns) (max.ns) (min.ns) (typ.mW) Type name M5M467400DXX-5,5S M5M467800DXX-5,5S 50 13 25 13 90 300 M5M467400DXX-6,6S M5M467800DXX-6,6S 60 15 30 15 110 250 M5M465400DXX-5,5S M5M465800DXX-5,5S 50 13 25 13 90 390 M5M465400DXX-6,6S M5M465800DXX-6,6S 60 15 30 15 110 325 Type name Power Address RAS CAS OE Cycle dissipaaccess access access access time time tion time time time (max.ns) (max.ns) (max.ns) (max.ns) (min.ns) (typ.mW) M5M465160DXX-5,5S 50 13 25 13 90 420 M5M465160DXX-6,6S 60 15 30 15 110 390 XX=J,TP Standard 32 pin SOJ, 32 pin TSOP (M5M467400Dxx/M5M465400Dxx/M5M467800Dxx/M5M465800Dxx) Standard 50 pin SOJ, 50 pin TSOP (M5M465160Dxx) Single 3.3 ± 0.3V supply Low stand-by power dissipation 1.8mW (Max) LVCMOS input level Low operating power dissipation M5M467400Dxx-5,5S / M5M467800Dxx-5,5S 360.0mW (Max) M5M467400Dxx-6,6S / M5M467800Dxx-6,6S 324.0mW (Max) M5M465400Dxx-5,5S / M5M465800Dxx-5,5S 468.0mW (Max) M5M465400Dxx-6,6S / M5M465800Dxx-6,6S 432.0mW (Max) M5M465160Dxx-5,5S 504.0mW (Max) M5M465160Dxx-6,6S 468.0mW (Max) Self refresh capability* Self refresh current 400µA (Max) Fast-page mode , Read-modify-write, CAS before RAS refresh, Hidden refresh capabilities Early-write mode and OE to control output buffer impedance All inputs, outputs LVTTL compatible and low capacitance * :Applicable to self refresh version(M5M467400/465400/467800/465800/465160DJ,DTP-5S,-6S:option) only ADDRESS Part No. Row Add. Col. Add. Refresh Refresh Cycle Normal S-version RAS Only Ref,Normal R/W 8192/64ms 8192/128ms M5M467400Dxx A0-A12 A0-A10 CBR Ref,Hidden Ref M5M465400Dxx A0-A11 A0-A11 M5M467800Dxx A0-A12 A0-A9 4096/64ms 4096/128ms RAS Only Ref,Normal R/W 4096/64ms 4096/128ms CBR Ref,Hidden Ref RAS Only Ref,Normal R/W 8192/64ms 8192/128ms CBR Ref,Hidden Ref 4096/64ms 4096/128ms M5M465800Dxx A0-A11 A0-A10 RAS Only Ref,Normal R/W 4096/64ms 4096/128ms CBR Ref,Hidden Ref M5M465160Dxx A0-A11 A0-A9 RAS Only Ref,Normal R/W 4096/64ms 4096/128ms CBR Ref,Hidden Ref APPLICATION Main memory unit for computers, Microcomputer memory, Refresh memory for CRT Aug. 1999 1 MITSUBISHI ELECTRIC (Rev. 1.0) MITSUBISHI LSIs M5M467400/465400DJ,DTP -5,-6,-5S,-6S M5M467800/465800DJ,DTP -5,-6,-5S,-6S M5M465160DJ,DTP -5,-6,-5S,-6S FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM PIN DESCRIPTION M5M467400Dxx / M5M465400Dxx Pin Name Function A0-A12 DQ1-DQ4 RAS M5M467800Dxx / M5M465800Dxx Pin Name Function Address Inputs A0-A12 Address Inputs Data Inputs / Outputs DQ1-DQ8 Data Inputs / Outputs Row Address Strobe Input Column Address Strobe Input RAS Row Address Strobe Input Column Address Strobe Input W OE Vcc Write Control Input Write Control Input Output Enable Input Power Supply (+3.3V) W OE Vcc Vss NC Ground (0V) No Connection Vss NC Ground (0V) No Connection CAS CAS Output Enable Input Power Supply (+3.3V) M5M465160Dxx Pin Name Function A0-A11 Address Inputs DQ1-DQ16 Data Inputs / Outputs Row Address Strobe Input RAS Upper byte control UCAS Column Address Strobe Input Lower byte control LCAS Column Address Strobe Input Write Control Input W OE Vcc Output Enable Input Vss NC Ground (0V) No Connection Power Supply (+3.3V) XX=J, TP M5M467400/465400DJ, DTP 3 30 4 29 5 28 6 7 8 9 10 11 27 26 25 24 23 22 12 21 13 20 14 19 15 18 16 17 Vss DQ4 DQ3 NC NC NC CAS OE A12/NC(Note) A11 A10 A9 A8 A7 A6 Vss Outline 32P0N (400mil SOJ) Vcc DQ1 DQ2 NC NC NC NC W RAS A0 A1 A2 A3 A4 A5 Vcc 1 32 2 31 3 30 4 29 5 28 6 7 8 9 10 11 12 M5M467400DTP 31 M5M465400DTP 32 2 M5M467400DJ 1 M5M465400DJ Vcc DQ1 DQ2 NC NC NC NC W RAS A0 A1 A2 A3 A4 A5 Vcc PIN CONFIGURATION (TOP VIEW) 27 26 25 24 23 22 21 13 20 14 19 15 18 16 17 Vss DQ4 DQ3 NC NC NC CAS OE A12/NC(Note) A11 A10 A9 A8 A7 A6 Vss Outline 32P3N (400mil TSOP Normal Bend) Note : A12...M5M467400Dxx, NC...M5M465400Dxx : NO CONNECTION NC 2 Aug. 1999 MITSUBISHI ELECTRIC (Rev. 1.0) MITSUBISHI LSIs M5M467400/465400DJ,DTP -5,-6,-5S,-6S M5M467800/465800DJ,DTP -5,-6,-5S,-6S M5M465160DJ,DTP -5,-6,-5S,-6S FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM M5M467800/465800DJ, DTP PIN CONFIGURATION (TOP VIEW) 3 30 DQ3 DQ4 NC Vcc 4 29 5 28 W RAS A0 A1 A2 A3 A4 A5 Vcc 8 6 7 9 10 11 27 26 25 24 23 22 12 21 13 20 14 19 15 18 16 17 Vss DQ8 DQ7 DQ6 DQ5 Vss CAS Vcc DQ1 DQ2 DQ3 DQ4 NC Vcc 1 32 2 31 3 30 4 29 5 28 OE A12/NC(Note) A11 A10 A9 A8 A7 A6 Vss W RAS A0 A1 A2 A3 A4 A5 Vcc 8 Outline 32P0N (400mil SOJ) 6 7 9 10 11 12 M5M467800DTP 31 M5M465800DTP 32 2 M5M467800DJ 1 M5M465800DJ Vcc DQ1 DQ2 27 26 25 24 23 22 21 13 20 14 19 15 18 16 17 Vss DQ8 DQ7 DQ6 DQ5 Vss CAS OE A12/NC(Note) A11 A10 A9 A8 A7 A6 Vss Outline 32P3N (400mil TSOP Normal Bend) Note : A12...M5M467800Dxx, NC...M5M465800Dxx : NO CONNECTION NC PIN CONFIGURATION (TOP VIEW) M5M465160DJ, DTP Vcc 1 50 Vss Vcc 1 50 Vss DQ1 2 49 DQ16 DQ1 2 49 DQ16 DQ2 3 48 DQ15 DQ2 3 48 DQ15 DQ3 4 47 DQ14 DQ3 4 47 DQ14 DQ4 5 46 DQ13 DQ4 5 46 DQ13 Vcc 6 45 Vss Vcc 6 45 Vss 44 DQ12 DQ5 7 44 DQ12 8 43 DQ11 DQ6 8 43 DQ11 DQ7 9 42 DQ10 DQ7 9 42 DQ10 DQ8 10 41 DQ9 DQ8 10 41 DQ9 NC Vcc 11 40 NC Vcc 11 40 39 NC Vss 39 NC Vss 38 LCAS LCAS UCAS W RAS NC 38 37 15 12 12 13 12 12 13 M5M465160DTP 7 M5M465160DJ DQ5 DQ6 W RAS NC 15 NC 16 35 OE NC NC 16 35 OE NC NC 17 34 NC NC 17 34 NC NC 18 33 NC NC 18 33 NC A0 19 32 A11 A0 19 32 A11 A1 20 31 A10 A1 20 31 A2 21 30 A9 A2 21 30 A10 A9 A3 22 29 A8 A3 22 29 A8 23 28 A7 A4 23 28 A7 A4 14 36 14 37 36 UCAS A5 24 27 A6 A5 24 27 A6 Vcc 25 26 Vss Vcc 25 26 Vss Outline 50P0G (400mil SOJ) Outline 50P3G (400mil TSOP Normal Bend) NC : NO CONNECTION 3 Aug. 1999 MITSUBISHI ELECTRIC (Rev. 1.0) MITSUBISHI LSIs M5M467400/465400DJ,DTP -5,-6,-5S,-6S M5M467800/465800DJ,DTP -5,-6,-5S,-6S M5M465160DJ,DTP -5,-6,-5S,-6S FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM FUNCTION The M5M467400(800)/465400(800,160)DJ, DTP provide, in addition to normal read, write, and read-modify-write operations, a number of other functions, e.g., fast page mode, CAS before RAS refresh, and delayed-write. The input conditions for each are shown in Table 1. Table 1 Input conditions for each mode M5M467400Dxx / M5M465400Dxx / M5M467800Dxx / M5M465800Dxx Inputs Input/Output Operation Column address APD Refresh RAS CAS W OE Read ACT ACT NAC ACT Row address APD OPN VLD NO Write (Early write) ACT ACT ACT DNC APD APD VLD OPN NO Write (Delayed write) ACT ACT ACT DNC APD APD VLD IVD NO Read-modify-write ACT ACT ACT ACT APD APD VLD VLD NO RAS-only refresh ACT NAC DNC DNC APD DNC OPN OPN YES Hidden refresh ACT ACT NAC ACT DNC DNC OPN VLD YES CAS before RAS refresh ACT ACT NAC DNC DNC DNC DNC OPN YES Standby NAC DNC DNC DNC DNC DNC DNC OPN NO Column address APD Input Output Remark FAST PAGE mode identical M5M465160Dxx Inputs Input/Output Operation RAS LCAS UCAS W OE Lower byte read ACT ACT NAC NAC ACT Row address APD Upper byte read ACT NAC ACT NAC ACT APD APD Word read ACT ACT ACT NAC ACT APD APD Lower byte write ACT ACT NAC ACT NAC APD Upper byte write ACT NAC ACT ACT NAC APD Word write ACT ACT ACT ACT NAC RAS-only refresh ACT NAC NAC DNC Hidden refresh ACT ACT ACT CAS before RAS refresh ACT ACT ACT Stand-by NAC DNC DNC Refresh DQ1~DQ8 DQ9~DQ16 VLD OPN NO OPN VLD NO VLD VLD NO APD DIN DNC NO APD DNC DIN NO APD APD DIN DIN NO DNC APD DNC OPN OPN YES NAC ACT DNC DNC VLD VLD YES DNC DNC DNC DNC OPN OPN YES DNC DNC DNC DNC OPN OPN NO Remark FAST PAGE mode identical Note : ACT : active, NAC : nonactive, DNC : don' t care, VLD : valid, IVD : Invalid, APD : applied, OPN : open 4 Aug. 1999 MITSUBISHI ELECTRIC (Rev. 1.0) MITSUBISHI LSIs M5M467400/465400DJ,DTP -5,-6,-5S,-6S M5M467800/465800DJ,DTP -5,-6,-5S,-6S M5M465160DJ,DTP -5,-6,-5S,-6S FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM M5M467400Dxx / M5M465400Dxx BLOCK DIAGRAM Vcc (3.3V) CAS RAS WRITE CONTROL INPUT W A0~A11 (Note) A0 COLUMN DECODER A1 A4 A5 ADDRESS INPUTS A6 A7 A8 A9 DQ2 DQ3 A0~ A12 (Note) A10 A11 DQ1 SENSE REFRESH AMPLIFIER & I /O CONTROL ROW DECODER A3 ROW & COLUMN ADDRESS BUFFER A2 Vss (0V) (4) DATA IN BUFFERS ROW ADDRESS STROBE INPUT CLOCK GENERATOR CIRCUIT MEMORY CELL (67108864 BITS) (4) DATA OUT BUFFERS COLUMN ADDRESS STROBE INPUT DATA INPUTS / OUTPUTS DQ4 OE OUTPUT ENABLE INPUT A12 (Note) Note : Refer to Page 1 (ADDRESS) M5M467800Dxx / M5M465800Dxx BLOCK DIAGRAM Vcc (3.3V) CAS RAS WRITE CONTROL INPUT W CLOCK GENERATOR CIRCUIT A0~A10 A0 (Note) COLUMN DECODER A1 A4 A5 ADDRESS INPUTS A6 A7 A8 A9 DQ4 A0~ A12 MEMORY CELL (67108864 BITS) DATA INPUTS / OUTPUTS DQ6 DQ7 DQ8 OE OUTPUT ENABLE INPUT A11 A12 (Note) Note 5 DQ2 DQ5 (Note) A10 DQ1 DQ3 SENSE REFRESH AMPLIFIER & I /O CONTROL ROW DECODER A3 ROW & COLUMN ADDRESS BUFFER A2 Vss (0V) (8) DATA IN BUFFERS ROW ADDRESS STROBE INPUT (8) DATA OUT BUFFERS COLUMN ADDRESS STROBE INPUT : Refer to Page 1 (ADDRESS) Aug. 1999 MITSUBISHI ELECTRIC (Rev. 1.0) MITSUBISHI LSIs M5M467400/465400DJ,DTP -5,-6,-5S,-6S M5M467800/465800DJ,DTP -5,-6,-5S,-6S M5M465160DJ,DTP -5,-6,-5S,-6S FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM M5M465160Dxx BLOCK DIAGRAM ROW ADDRESS RAS STROBE INPUT LOWER BYTE CONTROL LCAS COLUMN ADDRESS STROBE INPUT UPPER BYTE CONTROL UCAS COLUMN ADDRESS STROBE INPUT CIRCUIT DATA IN BUFFERS BUFFERS BUFFERS (8)LOWER W DATA OUT UPPER DATA IN LOWER (8)LOWER VSS (0V) (8)UPPER WRITE CONTROL INPUT VCC (3.3V) CLOCK GENERATOR DQ1 DQ2 LOWER DATA INPUTS / OUTPUTS DQ8 A0~A9 6 SENSE REFRESH AMPLIFIER & I /O DQ9 DQ10 UPPER DATA INPUTS / OUTPUTS (67108864BITS) BUFFERS A11 MEMORY CELL (8)UPPER A0 ~ DATA OUT CONTROL ROW DECODER ROW & COLUMN COLUMN DECODER ADDRESS BUFFER ADDRESS INPUTS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 DQ16 OE OUTPUT ENABLE INPUT Aug. 1999 MITSUBISHI ELECTRIC (Rev. 1.0) MITSUBISHI LSIs M5M467400/465400DJ,DTP -5,-6,-5S,-6S M5M467800/465800DJ,DTP -5,-6,-5S,-6S M5M465160DJ,DTP -5,-6,-5S,-6S FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM ABSOLUTE MAXIMUM RATINGS Symbol Parameter Vcc Supply voltage VI Input voltage V0 Output voltage I0 Output current Pd Power dissipation Topr Operating temperature Tstg Storage temperature Conditions Unit ~ 4.6 -0.5 ~ 4.6 -0.5 ~ 4.6 With respect to Vss Ta=25 C V V V 50 mA 1000 mW ~ 70 -65 ~ 150 0 RECOMMENDED OPERATING CONDITIONS Symbol Ratings -0.5 (Ta=0 ~ 70 C, unless Min Nom Max C otherwise noted) (Note 1) Limits Parameter C Unit Vcc Supply voltage 3.0 3.3 3.6 V Vss Supply voltage 0 0 0 V VIH High-level input voltage, all inputs 2.0 Vcc+0.3 V VIL Low-level input voltage, all inputs -0.3 0.8 V Note 1 : All voltage values are with respect to Vss. ELECTRICAL CHARACTERISTICS [M5M467400D / M5M467800D] Symbol (Ta=0 ~ 70 C , Vcc=3.3 ± 0.3V, Vss=0V, unless Parameter Test conditions VOH High-level output voltage IOH=-2mA VOL Low-level output voltage IOZ Off-state output current IOL=2mA Q floating 0V ≤ VOUT II Input current ICC1 (AV) Average supply current from Vcc operating (Note 3,4,5) ICC2 (AV) ICC4 (AV) ICC6 (AV) Average supply current from Vcc (Note 6) stand-by otherwise noted) (Note 2) ≤ Vcc 0V≤VIN ≤ Vcc+0.3V, Other input pins=0V M5M467400D-5,5S M5M467800D-5,5S M5M467400D-6,6S M5M467800D-6,6S M5M467400D-5,5S -6,6S M5M467800D-5,5S -6,6S Average supply current from Vcc Fast-Page-Mode (Note 3,4,5) M5M467400D-5,6 M5M467800D-5,6 M5M467400D-5S,6S M5M467800D-5S,6S M5M467400D-5,5S M5M467800D-5,5S M5M467400D-6,6S M5M467800D-6,6S Average supply current from Vcc CAS before RAS refresh (Note 3,5) mode M5M467400D-5,5S M5M467800D-5,5S M5M467400D-6,6S M5M467800D-6,6S RAS, CAS cycling tRC=tWC=min. output open RAS= CAS =VIH, output open Limits Min Typ Max Unit 2.4 Vcc 0 0.4 V -10 10 -10 10 µA µA V 100 mA 90 1 mA 0.5 RAS= CAS ≥Vcc -0.2V,output open 0.3 RAS=VIL, CAS cycling tPC=min. output open 100 CAS before RAS refresh cycling tRC=min. output open 130 mA 90 mA 120 Note 2: Current flowing into an IC is positive, out is negative. 3: Icc1 (AV) , Icc4 (AV) and Icc6 (AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate. 4: Icc1 (AV) and Icc4 (AV) are dependent on output loading. Specified values are obtained with the output open. 5: Column Address can be changed once or less while RAS=VIL and CAS=VIH. 7 Aug. 1999 MITSUBISHI ELECTRIC (Rev. 1.0) MITSUBISHI LSIs M5M467400/465400DJ,DTP -5,-6,-5S,-6S M5M467800/465800DJ,DTP -5,-6,-5S,-6S M5M465160DJ,DTP -5,-6,-5S,-6S FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM ELECTRICAL CHARACTERISTICS [M5M465400D / M5M465800D] Symbol (Ta=0 ~ 70 C, Vcc=3.3 ± 0.3V, Vss=0V, unless Parameter Test conditions VOH High-level output voltage IOH=-2mA VOL Low-level output voltage IOZ Off-state output current IOL=2mA Q floating 0V ≤ VOUT II Input current ICC1 (AV) Average supply current from Vcc operating (Note 3,4,5) ICC2 (AV) ICC4 (AV) ICC6 (AV) otherwise noted) (Note 2) ≤ Vcc 0V≤VIN ≤ Vcc+0.3V, Other input pins=0V Average supply current from Vcc (Note 6) stand-by M5M465400D-5,5S M5M465800D-5,5S M5M465400D-6,6S M5M465800D-6,6S M5M465400D-5,5S -6,6S M5M465800D-5,5S -6,6S Limits Min Typ Vcc 0 0.4 V -10 10 µA µA -10 10 Average supply current from Vcc CAS before RAS refresh (Note 3,5) mode M5M465400D-5,5S M5M465800D-5,5S M5M465400D-6,6S M5M465800D-6,6S V 130 mA 120 RAS= CAS =VIH, output open Average supply current from Vcc Fast-Page-Mode (Note 3,4,5) Unit 2.4 RAS, CAS cycling tRC=tWC=min. output open M5M465400D-5,6 M5M465800D-5,6 RAS= CAS ≥Vcc -0.2V,output open M5M465400D-5S,6S M5M465800D-5S,6S M5M465400D-5,5S RAS=VIL, CAS cycling M5M465800D-5,5S tPC=min. M5M465400D-6,6S output open M5M465800D-6,6S Max 1 mA 0.5 0.3 100 mA 90 130 CAS before RAS refresh cycling tRC=min. output open mA 120 [M5M465160D] Symbol Parameter Test conditions VOH High-level output voltage IOH=-2mA VOL Low-level output voltage IOL=2mA IOZ Off-state output current II Input current ICC1 (AV) Average supply current M5M465160D-5,5S from Vcc (Note 3,4,5) M5M465160D-6,6S operating ICC2 (AV) ICC4 (AV) ICC6 (AV) Average supply current from Vcc (Note 6) stand-by M5M465160D-5,5S -6,6S M5M465160D-5,6 M5M465160D-5S,6S Average supply current M5M465160D-5,5S from Vcc Fast-Page-Mode (Note 3,4,5) M5M465160D-6,6S Average supply current from Vcc CAS before RAS refresh (Note 3,5) mode M5M465160D-5,5S M5M465160D-6,6S Limits Min Typ Max Unit 2.4 Vcc 0 0.4 Q floating 0V ≤ VOUT ≤ Vcc V -10 10 0V -10 µA µA ≤ VIN ≤ Vcc+0.3V, Other input pins=0V RAS, CAS cycling tRC=tWC=min. output open RAS= CAS =VIH, output open 10 V 140 130 mA 1 RAS= CAS ≥ Vcc -0.2V, output open 0.5 RAS=VIL, CAS cycling tPC=min. output open 105 CAS before RAS refresh cycling tRC=min. output open 140 mA 0.3 95 mA mA 130 Aug. 1999 8 MITSUBISHI ELECTRIC (Rev. 1.0) MITSUBISHI LSIs M5M467400/465400DJ,DTP -5,-6,-5S,-6S M5M467800/465800DJ,DTP -5,-6,-5S,-6S M5M465160DJ,DTP -5,-6,-5S,-6S FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM CAPACITANCE Symbol (Ta=0 ~ 70 C , Vcc=3.3 ± 0.3V, Vss=0V, unless Parameter otherwise noted) Limits Test conditions CI (A) Input capacitance,address inputs CI (OE) Input capacitance, OE input CI (W) Input capacitance, write control input CI (RAS) Input capacitance, RAS input CI (CAS) CI / O Min Max 5 Typ Unit pF 7 pF 7 pF 7 pF Input capacitance, CAS input 7 pF Input/Output capacitance, data ports 7 pF SWITCHING CHARACTERISTICS VI=Vss f=1MHZ Vi=25mVrms (Ta=0 ~ 70 C , Vcc=3.3 ± 0.3V, Vss=0V, unless otherwise noted , see notes 6,13,14) Limits Symbol M5M46X400D-5,5S M5M46X400D-6,6S M5M46X800D-5,5S M5M46X800D-6,6S M5M465160D-5,5S M5M465160D-6,6S Parameter Min Max Min Unit Max tCAC Access time from CAS (Note 7,8) 13 15 ns tRAC Access time from RAS (Note 7,9) 50 60 ns tAA Column address access time (Note 7,10) 25 30 ns tCPA Access time from CAS precharge (Note 7,11) 30 35 ns tOEA Access time from OE (Note 7) 13 15 ns tCLZ Output low impedance time from CAS low (Note 7) 5 tOFF Output disable time after CAS high (Note 12) 0 13 0 15 ns tOEZ Output disable time after OE high (Note 12) 0 13 0 15 ns ns 5 Note 6: An initial pause of 500µs is required after power-up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS-only refresh or CAS before RAS refresh). Note the RAS may be cycled during the initial pause. And any eight initialization cycles are required after prolonged periods (greater than 64 ms) of RAS inactivity before proper device operation is achieved. 7: Measured with a load circuit equivalent to VOH=2.4V(IOH=-2mA) / VOL=0.4V(IOL=2mA) loads and 100pF. The reference levels for measuring of output signals are VOH=2.0V and VOL=0.8V. 8: Assumes that tRCD ≥ tRCD(max) and tASC ≥ tASC(max) and tCP ≥ tCP(max). 9: Assumes that tRCD ≤ tRCD(max) and tRAD ≤ tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC will increase by amount that tRCD exceeds the value shown. 10: Assumes that tRAD ≥ tRAD(max) and tASC ≤ tASC(max). 11: Assumes that tCP ≤ tCP(max) and tASC ≥ tASC(max). 12: tOFF(max) and tOEZ(max) defines the time at which the output achieves the high impedance state (IOUT ≤ ± 10 µA) and is not reference to VOH(min) or VOL(max). Aug. 1999 9 MITSUBISHI ELECTRIC (Rev. 1.0) MITSUBISHI LSIs M5M467400/465400DJ,DTP -5,-6,-5S,-6S M5M467800/465800DJ,DTP -5,-6,-5S,-6S M5M465160DJ,DTP -5,-6,-5S,-6S FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write ,Refresh, and Fast-Page Mode Cycles) (Ta=0 ~ 70 C , Vcc=3.3 ± 0.3V, Vss=0V, unless otherwise noted See notes 13,14) Symbol Limits M5M46X400D-5,5S M5M46X400D-6,6S Unit M5M46X800D-5,5S M5M46X800D-6,6S M5M465160D-5,5S M5M465160D-6,6S Parameter Min Max Min Max tREF Refresh cycle time tREF Refresh cycle time (S-version only) tRP RAS high pulse width tRCD Delay time, RAS low to CAS low tCRP Delay time, CAS high to RAS low 5 10 ns tRPC Delay time, RAS high to CAS low CAS high pulse width 0 8 0 10 ns tCPN tRAD Column address delay time from RAS low tASR Row address setup time before RAS low tASC Column address setup time before CAS low tRAH Row address hold time after RAS low tCAH Column address hold time after CAS low tDZC Delay time, data to CAS low tDZO 64 64 ms 128 128 ms 30 (Note15) (Note16) 40 18 37 25 13 45 ns ns 15 0 (Note17) ns 20 30 ns 10 ns ns 0 7 0 0 8 10 ns 13 15 ns (Note18) 0 0 ns Delay time, data to OE low (Note18) 0 0 ns tCDD Delay time, CAS high to data (Note19) 13 15 ns tODD Delay time, OE high to data Transition time (Note19) 13 15 (Note20) 1 tT 50 ns ns 50 1 Note 13: The timing requirements are assumed tT =5ns. 14: VIH(min) and VIL(max) are reference levels for measuring timing of input signals. VIH(min) and VIL(max) of the switching characteristics are 2.0V and 0.8V respectively. 15: tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than tRCD(max), access time is controlled exclusively by tCAC or tAA. tRCD(min) is specified as tRCD(min) =tRAH(min) +2tT+tASC(min). 16: tRAD(max) is specified as a reference point only. If tRAD ≥ tRAD(max) and tASC ≤ tASC(max), access time is controlled exclusively by tAA. 17: tASC(max) is specified as a reference point only. If tRCD ≥ tRCD(max) and tASC ≥ tASC(max), access time is controlled exclusively by tCAC. 18: Either tDZC or tDZO must be satisfied. 19: Either tCDD or tODD must be satisfied. 20: tT is measured between VIH(min) and VIL(max). Read and Refresh Cycles Symbol Limits M5M46X400D-5,5S M5M46X400D-6,6S M5M46X800D-5,5S M5M46X800D-6,6S M5M465160D-5,5S M5M465160D-6,6S Parameter Min Max Min Unit Max tRC Read cycle time 90 tRAS RAS low pulse width 50 10000 60 10000 ns tCAS CAS low pulse width 13 10000 15 10000 ns tCSH CAS hold time after RAS low 50 60 ns tRSH RAS hold time after CAS low 13 15 ns tRCS Read Setup time before CAS low 0 0 ns tRCH Read hold time after CAS high (Note 21) 0 0 ns tRRH Read hold time after RAS high (Note 21) 10 10 ns tRAL Column address to RAS hold time 25 30 ns tOCH CAS hold time after OE low 13 15 ns tORH RAS hold time after OE low 13 15 ns 110 ns Note 21: Either tRCH or tRRH must be satisfied for a read cycle. Aug. 1999 10 MITSUBISHI ELECTRIC (Rev. 1.0) MITSUBISHI LSIs M5M467400/465400DJ,DTP -5,-6,-5S,-6S M5M467800/465800DJ,DTP -5,-6,-5S,-6S M5M465160DJ,DTP -5,-6,-5S,-6S FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM Write Cycle (Early Write and Delayed Write) Symbol Limits M5M46X400D-5,5S M5M46X400D-6,6S M5M46X800D-5,5S M5M46X800D-6,6S M5M465160D-5,5S M5M465160D-6,6S Parameter Min Max Min Unit Max tWC Write cycle time 90 tRAS RAS low pulse width 50 10000 60 10000 ns tCAS CAS low pulse width 13 10000 15 10000 ns tCSH CAS hold time after RAS low 50 60 ns tRSH RAS hold time after CAS low 13 15 ns tWCS Write setup time before CAS low 0 0 ns tWCH Write hold time after CAS low 8 10 ns tCWL CAS hold time after W low 13 15 ns tRWL RAS hold time after W low 13 15 ns tWP Write pulse width 8 10 ns tDS Data setup time before CAS low or W low 0 0 ns tDH Data hold time after CAS low or W low 8 10 ns tOEH OE hold time after W low 13 15 ns (Note 23) 110 ns Read-Write and Read-Modify-Write Cycles Limits Symbol M5M46X400D-5,5S M5M46X400D-6,6S M5M46X800D-5,5S M5M46X800D-6,6S M5M465160D-5,5S M5M465160D-6,6S Parameter Min Max 126 Min Unit Max 150 tRWC Read write/read modify write cycle time tRAS RAS low pulse width 85 10000 95 10000 ns tCAS CAS low pulse width 50 10000 50 10000 ns tCSH CAS hold time after RAS low 85 95 ns tRSH RAS hold time after CAS low 50 50 ns tRCS Read setup time before CAS low 0 0 ns tCWD Delay time, CAS low to W low (Note23) 30 30 ns tRWD Delay time, RAS low to W low (Note23) 65 75 ns tAWD Delay time, address to W low (Note23) 40 45 ns tCWL CAS hold time after W low 13 15 ns tRWL RAS hold time after W low 13 15 ns tWP Write pulse width 8 10 ns tDS tDH Data setup time before CAS low or W low Data hold time after CAS low or W low 0 8 0 10 ns ns tOEH OE hold time after W low 13 15 ns (Note22) ns Note 22: tRWC is specified as tRWC(min)=tRAC(max)+tODD(min)+tRWL(min)+tRP(min)+4tT. 23: tWCS, tCWD, tRWD and tAWD and, tCPWD are specified as reference points only. If tWCS ≥ tWCS(min) the cycle is an early write cycle and the DQ pins will remain high impedance throughout the entire cycle. If tCWD ≥ tCWD(min), tRWD ≥ tRWD (min), tAWD ≥ tAWD(min) and tCPWD ≥ tCPWD(min) (for Fast Page mode cycle only), the cycle is a read-modify-write cycle and the DQ will contain the data read from the selected address. If neither of the above condition (delayed write) is satisfied, the DQ (at access time and until CAS or OE goes back to VIH ) is indeterminate. Aug. 1999 11 MITSUBISHI ELECTRIC (Rev. 1.0) MITSUBISHI LSIs M5M467400/465400DJ,DTP -5,-6,-5S,-6S M5M467800/465800DJ,DTP -5,-6,-5S,-6S M5M465160DJ,DTP -5,-6,-5S,-6S FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM Fast-Page Mode Cycle (Read, Early Write, Read-Write, Read-Modify-Write Cycle) Symbol (Note 24) Limits M5M46X400D-5,5S M5M46X400D-6,6S M5M46X800D-5,5S M5M46X800D-6,6S M5M465160D-5,5S M5M465160D-6,6S Parameter Min Max Min Unit Max tPC Fast page mode read/write cycle time 35 40 tPRWC Fast page mode read write/read modify write cycle time 70 75 tRAS RAS low pulse width for read write cycle (Note25) 85 125000 100 tCP CAS high pulse width (Note26) 8 12 10 tCPRH RAS hold time after CAS precharge 30 35 ns tCPWD Delay time, CAS precharge to W low (Note23) 30 35 ns ns ns 125000 15 ns ns Note 24: All previously specified timing requirements and switching characteristics are applicable to their respective Fast page mode cycle. 25: tRAS(min) is specified as two cycles of CAS input are performed. 26: tCP(max) is specified as a reference point only. If tCP ≥ tCP(max) , access time is controlled exclusively by tCAC. CAS before RAS Refresh Cycle Symbol Parameter (Note 27) Limits M5M46X400D-5,5S M5M46X400D-6,6S M5M46X800D-5,5S M5M46X800D-6,6S Unit M5M465160D-5,5S M5M465160D-6,6S Min tCSR CAS setup time before RAS low tCHR Max Min Max 5 5 ns CAS hold time after RAS low 10 10 ns tRSR Read setup time before RAS low 10 10 ns tRHR Read hold time after RAS low 10 10 ns Note 27: Eight or more CAS before RAS cycles instead of eight RAS cycles are necessary for proper operation of CAS before RAS refresh mode. Aug. 1999 12 MITSUBISHI ELECTRIC (Rev. 1.0) MITSUBISHI LSIs M5M467400/465400DJ,DTP -5,-6,-5S,-6S M5M467800/465800DJ,DTP -5,-6,-5S,-6S M5M465160DJ,DTP -5,-6,-5S,-6S FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM SELF REFRESH SPECIFICATIONS Self refresh devices are denoted by "S" after speed item, like -5S / -6S . The other characteristics and requirements than the below are same as normal devices. ELECTRICAL CHARACTERISTICS Symbol ICC8 (AV) ICC9 (AV) (Ta=0 ~ 70 C , Vcc=3.3V Parameter otherwise noted) (Note 2) Test conditions Average supply current from Vcc Self - Refresh cycle (note 6) Min Limits Typ CAS before RAS refresh cycling input high level ≥ Vcc-0.2V input low level ≤ 0.2V output = OPEN , tRC = 31.25µs tRAS = tRAS(min) ~ 300ns Average supply current M5M46X400D-5S,6S from Vcc M5M46X800D-5S,6S Extended - Refresh cycle M5M465160D-5S,6S (note 5,6) M5M46X400D-5S,6S M5M46X800D-5S,6S M5M465160D-5S,6S RAS = CAS ≤ 0.2V output = OPEN (Ta=0 ~ 70 C, Vcc=3.3V TIMING REQUIREMENTS ± 0.3V, Vss=0V, unless ± 0.3V, Vss=0V, unless Max Unit 500 µA 400 µA otherwise noted See notes 13,14) Limits Symbol Parameter M5M46X400D-5S M5M46X400D-6S M5M46X800D-5S M5M46X800D-6S M5M465160D-5S M5M465160D-6S Min Max Min Unit Max 100 100 µS tRPS Self Refresh RAS low pulse width Self Refresh RAS high precharge time 90 110 ns tCHS Self Refresh CAS hold time - 50 - 50 ns tRASS SELF REFRESH ENTRY & EXIT CONDITIONS (1) In case of CBR distributed refresh The last / first full refresh cycles must be made within on the condition of tNS ≤ 128 ms and tSN ≤ 128 ms. tNS / tSN before / after self refresh , tSN tNS Self refresh period DISTRIBUTED REFRESH < 128 ms > DISTRIBUTED REFRESH < 128 ms > (2) In case of burst refresh The last / first full refresh cycles must be made within tNS / tSN before / after self refresh , on the condition of tNS ≤ 16 ms and tSN ≤ 16 ms. tSN tNS Self refresh period BURST REFRESH < 128 ms > BURST REFRESH < 128 ms > 13 Aug. 1999 MITSUBISHI ELECTRIC (Rev. 1.0) MITSUBISHI LSIs M5M467400/465400DJ,DTP -5,-6,-5S,-6S M5M467800/465800DJ,DTP -5,-6,-5S,-6S M5M465160DJ,DTP -5,-6,-5S,-6S FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM Timing Diagrams Read Cycle (Note 28) tRC tRAS tRP VIH tRSH RAS VIL tRPC tCRP tCSH tCRP CAS VIH LCAS / UCAS VIL tRCD tCAS tCPN tRAD (at M5M465160Dxx only) tASR VIH Address tCAH tRAH COLUMN ADDRESS ROW ADDRESS VIL tASR tRAL tASC ROW ADDRESS tRRH tRCS VIH W tRCH VIL tDZC DQ1 ~ DQ4 (8,16) (INPUTS) tCDD VIH Hi-Z tCAC VIL tAA tOFF tCLZ VOH DQ1 ~ DQ4 (8,16) (OUTPUTS) VOL Hi-Z Hi-Z DATA VALID tRAC tDZO tOEZ tOEA tODD tOCH VIH tORH OE VIL Note 28: Indicates the don't care input. VIH(min) ≤ VIN ≤ VIH(max) or VIL(min) ≤ VIN ≤ VIL(max) Indicates the invalid output. Indicates the skew of the two inputs. (at M5M465160xx only) 14 Aug. 1999 MITSUBISHI ELECTRIC (Rev. 1.0) MITSUBISHI LSIs M5M467400/465400DJ,DTP -5,-6,-5S,-6S M5M467800/465800DJ,DTP -5,-6,-5S,-6S M5M465160DJ,DTP -5,-6,-5S,-6S FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM Write Cycle (Early Write) tWC tRAS tRP VIH RAS VIL tRPC tCSH tCRP CAS VIH LCAS / UCAS VIL tRSH tRCD tCRP tCAS (at M5M465160Dxx only) tASR Address VIH VIL tRAH tASC ROW ADDRESS tCAH tASR COLUMN ADDRESS tWCS ROW ADDRESS tWCH VIH W VIL tDS VIH DQ1 ~ DQ4 (8,16) (INPUTS) VIL VOH DQ1 ~ DQ4 (8,16) (OUTPUTS) VOL tDH DATA VALID Hi-Z VIH OE VIL 15 Aug. 1999 MITSUBISHI ELECTRIC (Rev. 1.0) MITSUBISHI LSIs M5M467400/465400DJ,DTP -5,-6,-5S,-6S M5M467800/465800DJ,DTP -5,-6,-5S,-6S M5M465160DJ,DTP -5,-6,-5S,-6S FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM Write Cycle (Delayed Write) tWC tRAS tRP VIH RAS VIL tRPC tCSH tCRP tRCD tCRP tRSH tCAS VIH CAS LCAS / UCAS VIL (at M5M465160Dxx only) tASR Address VIH VIL tRAH tASC ROW ADDRESS tCAH tASR COLUMN ADDRESS ROW ADDRESS tCWL tRWL VIH tWP W VIL tWCH tRCS tDZC VIH DQ1 ~ DQ4 (8,16) (INPUTS) VIL tDS Hi-Z tDH DATA VALID tCLZ VOH DQ1 ~ DQ4 (8,16) (OUTPUTS) VOL tDZO Hi-Z tOEZ tODD tOEH VIH OE VIL 16 Aug. 1999 MITSUBISHI ELECTRIC (Rev. 1.0) MITSUBISHI LSIs M5M467400/465400DJ,DTP -5,-6,-5S,-6S M5M467800/465800DJ,DTP -5,-6,-5S,-6S M5M465160DJ,DTP -5,-6,-5S,-6S FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM Read-Write, Read-Modify-Write Cycle tRWC tRAS RAS tRP VIH VIL tCSH tCRP CAS VIH LCAS / UCAS VIL tRAD tASR VIH VIL tCRP tRSH tCAS (at M5M465160Dxx only) Address tRPC tRCD tRAH tASC tCAH ROW ADDRESS tASR COLUMN ADDRESS ROW ADDRESS tCWD tCWL tAWD tRWD tRWL VIH W tRCS VIL tRAC tWP tDZC tCAC tDS tAA DQ1 ~ DQ4 (8,16) (INPUTS) VIH Hi-Z tDH DATA VALID VIL tCLZ VOH DQ1 ~ DQ4 (8,16) (OUTPUTS) VOL Hi-Z Hi-Z DATA VALID tOEA tDZO tODD tOEH tOEZ VIH OE VIL 17 Aug. 1999 MITSUBISHI ELECTRIC (Rev. 1.0) MITSUBISHI LSIs M5M467400/465400DJ,DTP -5,-6,-5S,-6S M5M467800/465800DJ,DTP -5,-6,-5S,-6S M5M465160DJ,DTP -5,-6,-5S,-6S FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM Fast Page Mode Read Cycle tRAS tRP tCSH tCPRH tPC VIH tRSH RAS VIL tRPC tCRP tRCD tCAS tCP tCAS tCP tCRP tCAS VIH CAS LCAS / UCAS VIL (at M5M465160Dxx only) tRAD tASR Address VIH VIL tRAH tRAL tASC tASC tCAH COLUMN ADDRESS-1 ROW ADDRESS tASC tCAH COLUMN ADDRESS-2 COLUMN ADDRESS-3 tRCH tRCS ROW ADDRESS tRRH tAA tAA tRCS tASR tCAH tRCH tRCS VIH W tRCH VIL tDZC tCDD VIH tCAC tCAC tOFF tCLZ Hi-Z tCLZ DATA VALID-1 tCAC tOFF tAA DATA VALID-3 tCPA tCPA tORH tOEZ tOEZ tDZO tDZO tOCH tDZO tOEA tOEA tOEA tODD tOFF tCLZ DATA VALID-2 tRAC VIH tCDD tDZC Hi-Z DQ1 ~ DQ4 (8,16) (INPUTS) VIL VOH DQ1 ~ DQ4 (8,16) (OUTPUTS) VOL tCDD tDZC tOCH tODD tOEZ tODD tOCH OE VIL 18 Aug. 1999 MITSUBISHI ELECTRIC (Rev. 1.0) MITSUBISHI LSIs M5M467400/465400DJ,DTP -5,-6,-5S,-6S M5M467800/465800DJ,DTP -5,-6,-5S,-6S M5M465160DJ,DTP -5,-6,-5S,-6S FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM Fast Page Mode Write Cycle (Early Write) tRAS tCSH tRP tPC VIH tRSH RAS VIL tRPC tCRP tRCD tCAS tCP tCAS tCP tCRP tCAS VIH CAS LCAS / UCAS VIL (at M5M465160Dxx only) tASR Address VIH VIL VIH W tRAH ROW ADDRESS tASC tCAH tASC COLUMN ADDRESS-1 tCAH tASC tCAH COLUMN ADDRESS-3 COLUMN ADDRESS-2 tWCS tWCH tWCS tWCH tWCS tWCH tDS tDH tDS tDH tDS tDH tASR ROW ADDRESS VIL VIH DQ1 ~ DQ4 (8,16) (INPUTS) VIL VOH DQ1 ~ DQ4 (8,16) (OUTPUTS) VOL DATA VALID-1 DATA VALID-2 DATA VALID-3 Hi-Z VIH OE VIL 19 Aug. 1999 MITSUBISHI ELECTRIC (Rev. 1.0) MITSUBISHI LSIs M5M467400/465400DJ,DTP -5,-6,-5S,-6S M5M467800/465800DJ,DTP -5,-6,-5S,-6S M5M465160DJ,DTP -5,-6,-5S,-6S FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM Fast Page Mode Write Cycle (Delayed Write) tRSH tRAS tRP tCSH RAS tPC VIH VIL tRPC tCRP tCP tCAS tRCD tCRP tCAS VIH CAS tRAD LCAS / UCAS VIL (at M5M465160Dxx only) tASR VIH Address VIL tRAH tASC tCAH tASC tRCS tRWL tASR COLUMN ADDRESS-2 COLUMN ADDRESS-1 ROW ADDRESS tCAH tWCH ROW ADDRESS tRCS tWCH tCWL VIH tCWL tWP W tWP VIL tDS tDZC VIH DQ1 ~ DQ4 (8,16) (INPUTS) VIL tDH tDS tDZC DATA VALID-1 tDH DATA VALID-2 tDZO tCLZ tCLZ VOH Hi-Z DQ1 ~ DQ4 (8,16) (OUTPUTS) VOL tOEZ tOEZ tDZO tODD tOEH tOEH tODD VIH OE VIL 20 Aug. 1999 MITSUBISHI ELECTRIC (Rev. 1.0) MITSUBISHI LSIs M5M467400/465400DJ,DTP -5,-6,-5S,-6S M5M467800/465800DJ,DTP -5,-6,-5S,-6S M5M465160DJ,DTP -5,-6,-5S,-6S FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM Fast Page Mode Read-Write, Read-Modify-Write Cycle tRAS tRP tCSH VIH tRSH RAS VIL tPRWC tCRP tRCD tCP tCAS tRPC tCAS tCRP VIH CAS VIL LCAS / UCAS (at M5M465160Dxx only) Address VIH VIL tRAD tASR tRAH tASC tASC tCAH COLUMN ADDRESS-1 ROW ADDRESS tRWL tCAH tASR COLUMN ADDRESS-2 ROW ADDRESS tRWD tRCS tWCH tAWD VIH W tAWD tWP tCWD VIL tCAC VIH tDS tDH VIL tDS tDZC DATA VALID-1 (8,16) (INPUTS) tWP tCPA tAA tAA DQ1 ~ DQ4 tCWL tCWD tCPWD tRAC tDZC tWCH tRCS tCWL tDH DATA VALID-2 tCAC tDZO tCLZ tCLZ DATA VALID-1 DQ1 ~ DQ4 VOH (8,16) (OUTPUTS) VOL tOEA tDZO tOEZ tODD DATA VALID-2 Hi-Z tOEH tOEA tOEZ tOEH tODD VIH OE VIL 21 Aug. 1999 MITSUBISHI ELECTRIC (Rev. 1.0) MITSUBISHI LSIs M5M467400/465400DJ,DTP -5,-6,-5S,-6S M5M467800/465800DJ,DTP -5,-6,-5S,-6S M5M465160DJ,DTP -5,-6,-5S,-6S FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM RAS-only Refresh Cycle tRC tRAS VIH RAS VIL tRP tRPC tCRP CAS VIH LCAS / UCAS VIL tCRP (at M5M465160Dxx only) tASR Address VIH VIL tRAH tASR ROW ADDRESS ROW ADDRESS VIH W VIL DQ1 ~ DQ4 (8,16) VIH (INPUTS) VIL VOH DQ1 ~ DQ4 (8,16) (OUTPUTS) VOL Hi-Z VIH OE VIL 22 Aug. 1999 MITSUBISHI ELECTRIC (Rev. 1.0) MITSUBISHI LSIs M5M467400/465400DJ,DTP -5,-6,-5S,-6S M5M467800/465800DJ,DTP -5,-6,-5S,-6S M5M465160DJ,DTP -5,-6,-5S,-6S FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM CAS before RAS Refresh Cycle tRC tRC tRP tRP tRAS VIH RAS tRAS VIL tRPC tCSR tCPN tRPC tCSR tRPC tCRP tCHR tCHR VIH CAS LCAS / UCAS VIL (at M5M465160Dxx only) tASR Address VIH ROW ADDRESS VIL tRCH tRSR tRHR tRSR tRHR tRCS VIH W VIL tOFF tCDD DQ1 ~ DQ4 (8,16) (INPUTS) VIH DQ1 ~ DQ4 (8,16) (OUTPUTS) VOH VIL Hi-Z VOL tOEZ tODD VIH OE VIL 23 Aug. 1999 MITSUBISHI ELECTRIC (Rev. 1.0) MITSUBISHI LSIs M5M467400/465400DJ,DTP -5,-6,-5S,-6S M5M467800/465800DJ,DTP -5,-6,-5S,-6S M5M465160DJ,DTP -5,-6,-5S,-6S FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM Hidden Refresh Cycle (Read) (Note 29) tRC tRC tRP tRAS tRAS tRP VIH RAS VIL tRPC tRCD tCRP CAS tCRP tCHR VIH LCAS / UCAS VIL tRAD (at M5M465160Dxx only) tASR Address tRSH VIH VIL tASC tRAH tCAH tASR COLUMN ADDRESS ROW ADDRESS ROW ADDRESS tRAL tRRH tRSR tRCS tRHR VIH W VIL tDZC tCDD DQ1 ~ DQ4 (8,16) (INPUTS) VIH Hi-Z VIL tAA tCAC tOFF tRAC tCLZ DQ1 ~ DQ4 (8,16) (OUTPUTS) VOH Hi-Z Hi-Z DATA VALID VOL tOEZ tDZO VIH tOEA tODD tORH OE VIL Note 29: Early write, delayed write, read write, or read modify write cycle is applicable instead of read cycle. Timing requirements and output state are the same as that of each cycle shown above. 24 Aug. 1999 MITSUBISHI ELECTRIC (Rev. 1.0) MITSUBISHI LSIs M5M467400/465400DJ,DTP -5,-6,-5S,-6S M5M467800/465800DJ,DTP -5,-6,-5S,-6S M5M465160DJ,DTP -5,-6,-5S,-6S FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM Self Refresh Cycle tRASS tRP tRPS VIH RAS VIL tRPC tRPC tCSR tCHS tCRP VIH CAS LCAS / UCAS VIL (at M5M465160Dxx only) tCPN tASR Address VIH ROW ADDRESS VIL tRCH tRSR tRHR VIH W VIL DQ1 ~ DQ4 (8,16) (INPUTS) VIH VIL tOFF VOH DQ1 ~ DQ4 (8,16) (OUTPUTS) VOL Hi-Z tOEZ VIH OE VIL 25 Aug. 1999 MITSUBISHI ELECTRIC (Rev. 1.0) MITSUBISHI LSIs M5M467400/465400DJ,DTP -5,-6,-5S,-6S M5M467800/465800DJ,DTP -5,-6,-5S,-6S M5M465160DJ,DTP -5,-6,-5S,-6S FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM Upper / (Lower) Byte Read Cycle (at M5M465160Dxx only) tRC tRAS tRP VIH tRSH RAS VIL tCSH tCRP UCAS (or LCAS) tRCD tCAS tRPC tCRP tCPN VIL tCAH VIH tRAD tRAL VIL tASR Address tCRP VIH tCRP LCAS (or UCAS) tRPC VIH VIL tRAH tASC ROW ADDRESS tASR COLUMN ADDRESS ROW ADDRESS tRRH tRCS tRCH VIH W VIL VIH DQ1 ~ DQ8 (or DQ9 ~ DQ16) (INPUTS) VIL DQ1 ~ DQ8 VOH (or DQ9 ~ DQ16) (OUTPUTS) VOL Hi-Z tDZC tCDD tCAC VIH DQ9 ~ DQ16 (or DQ1 ~ DQ8) (INPUTS) VIL Hi-Z tAA tOFF tCLZ VOH DQ9 ~ DQ16 (or DQ1 ~ DQ8) (OUTPUTS) VOL Hi-Z DATA VALID tRAC tDZO VIH tOEZ tODD tOEA tOCH OE VIL tORH 26 Aug. 1999 MITSUBISHI ELECTRIC (Rev. 1.0) MITSUBISHI LSIs M5M467400/465400DJ,DTP -5,-6,-5S,-6S M5M467800/465800DJ,DTP -5,-6,-5S,-6S M5M465160DJ,DTP -5,-6,-5S,-6S FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM Upper / (Lower) Byte Write Cycle (Early Write) (at M5M465160Dxx only) tWC tRAS tRP VIH RAS VIL tCSH tCRP tRCD tRSH tRPC tCRP tRPC tCRP tCAS UCAS (or LCAS) VIH VIL tCRP LCAS (or UCAS) VIH VIL tASR Address VIH VIL tRAH tASC ROW ADDRESS tCAH tASR COLUMN ADDRESS tWCS ROW ADDRESS tWCH VIH W VIL DQ1 ~ DQ8 VIH (or DQ9 ~ DQ16) (INPUTS) VIL DQ1 ~ DQ8 VOH (or DQ9 ~ DQ16) (OUTPUTS) VOL Hi-Z tDS DQ9 ~ DQ16 VIH (or DQ1 ~ DQ8) (INPUTS) VIL DQ9 ~ DQ16 VOH (or DQ1 ~ DQ8) (OUTPUTS) VOL tDH DATA VALID Hi-Z VIH OE VIL 27 Aug. 1999 MITSUBISHI ELECTRIC (Rev. 1.0) MITSUBISHI LSIs M5M467400/465400DJ,DTP -5,-6,-5S,-6S M5M467800/465800DJ,DTP -5,-6,-5S,-6S M5M465160DJ,DTP -5,-6,-5S,-6S FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM Upper / (Lower) Byte Write Cycle (Delayed Write) (at M5M465160Dxx only) tWC tRAS tRP VIH RAS VIL tCSH tCRP UCAS (or LCAS) tRCD tRPC tRSH tCRP tCAS VIH VIL tRPC tCRP LCAS (or UCAS) VIH VIL tASR Address tCRP VIH VIL tRAH tASC ROW ADDRESS tCAH tASR COLUMN ADDRESS ROW ADDRESS tCWL tRWL VIH tWP W VIL tRCS tWCH DQ1 ~ DQ8 VIH (or DQ9 ~ DQ16) (INPUTS) VIL DQ1 ~ DQ8 VOH (or DQ9 ~ DQ16) (OUTPUTS) VOL Hi-Z tDZC VIH DQ9 ~ DQ16 (or DQ1 ~ DQ8) (INPUTS) VIL tDS Hi-Z tDH DATA VALID tCLZ DQ9 ~ DQ16 VOH (or DQ1 ~ DQ8) (OUTPUTS) VOL Hi-Z tOEZ tDZO tOEH tODD VIH OE VIL 28 Aug. 1999 MITSUBISHI ELECTRIC (Rev. 1.0) MITSUBISHI LSIs M5M467400/465400DJ,DTP -5,-6,-5S,-6S M5M467800/465800DJ,DTP -5,-6,-5S,-6S M5M465160DJ,DTP -5,-6,-5S,-6S FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM Upper/(Lower) Byte Read-Write, Upper/(Lower) Byte Read-Modify-Write Cycle (at M5M465160Dxx only) tRWC tRAS tRP VIH RAS VIL tCSH tRPC tCRP tRCD tCRP tRSH tCAS UCAS (or LCAS) VIH VIL tCRP LCAS (or UCAS) tCRP VIH VIL tASR Address tRPC VIH VIL tRAH tASC ROW ADDRESS tASR tCAH COLUMN ADDRESS ROW ADDRESS tCWD tCWL tAWD tRWL tRWD VIH W VIL tRCS tWP DQ1 ~ DQ8 VIH (or DQ9 ~ DQ16) (INPUTS) VIL tRAC VOH DQ1 ~ DQ8 (or DQ9 ~ DQ16) VOL (OUTPUTS) Hi-Z tDZC tDS tAA VIH DQ9 ~ DQ16 (or DQ1 ~ DQ8) (INPUTS) VIL Hi-Z tDH DATA VALID tCAC tCLZ DQ9 ~ DQ16 (or DQ1 ~ DQ8) VOH (OUTPUTS) VOL Hi-Z Hi-Z DATA VALID tOEA tDZO tOEZ tOEH tODD VIH OE VIL 29 Aug. 1999 MITSUBISHI ELECTRIC (Rev. 1.0) MITSUBISHI LSIs M5M467400/465400DJ,DTP -5,-6,-5S,-6S M5M467800/465800DJ,DTP -5,-6,-5S,-6S M5M465160DJ,DTP -5,-6,-5S,-6S FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM Fast Page Mode Upper / (Lower) Byte Read Cycle (at M5M465160Dxx only) tRAS tRP tCPRH tCSH tPC tRSH VIH RAS VIL tRPC tCRP tRCD tCAS tCP tCAS tCP tCRP tCAS VIH UCAS (or LCAS) VIL tRPC tCRP tCRP VIH LCAS (or UCAS) VIL tRAD tASR VIH Address VIL tRAH tRAL tASC tCAH tASC COLUMN ADDRESS-1 ROW ADDRESS tASC tCAH COLUMN ADDRESS-2 tASR tCAH COLUMN ADDRESS-3 ROW ADDRESS tRRH tAA tRCS W tRCH tAA tRCH tRCS tRCS VIH tRCH VIL VIH DQ1 ~ DQ8 (or DQ9 ~ DQ16) (INPUTS) VIL DQ1 ~ DQ8 VOH (or DQ9 ~ DQ16) (OUTPUTS) VOL Hi-Z tDZC tCDD tDZC DQ9 ~ DQ16 VIH (or DQ1 ~ DQ8) (INPUTS) VIL tCAC tOFF tCLZ Hi-Z DATA VALID-3 DATA VALID-2 tCPA tRAC tOEZ tDZO tOEA tOCH tODD tOFF tCLZ DATA VALID-1 tDZO tCAC tOFF tCLZ tAA VIH tCDD Hi-Z tCAC DQ9 ~ DQ16 VOH (or DQ1 ~ DQ8) (OUTPUTS) VOL tCDD tDZC tCPA tOEZ tDZO tORH tOEA tOEZ tOEA tOCH tODD tODD tOCH OE VIL 30 Aug. 1999 MITSUBISHI ELECTRIC (Rev. 1.0) MITSUBISHI LSIs M5M467400/465400DJ,DTP -5,-6,-5S,-6S M5M467800/465800DJ,DTP -5,-6,-5S,-6S M5M465160DJ,DTP -5,-6,-5S,-6S FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM Fast Page Mode Upper / (Lower) Byte Write Cycle (Early Write) (at M5M465160Dxx only) tRAS tRP tCSH tPC VIH tRSH RAS VIL tCRP UCAS (or LCAS) tRCD tCAS tCP tCAS tCP VIH tRPC tCRP tCAS VIL tCRP LCAS (or UCAS) VIL VIH VIL VIH W tCRP VIH tASR Address tRPC tRAH ROW ADDRESS tASC tCAH tASC COLUMN ADDRESS-1 tWCS tWCH tCAH tASC COLUMN ADDRESS-3 COLUMN ADDRESS-2 tWCS tWCH tCAH tWCS tWCH tDS tDH tASR ROW ADDRESS VIL DQ1 ~ DQ8 VIH (or DQ9 ~ DQ16) (INPUTS) VIL VOH DQ1 ~ DQ8 (or DQ9 ~ DQ16) (OUTPUTS) VOL Hi-Z tDS VIH DQ9 ~ DQ16 (or DQ1 ~ DQ8) VIL (INPUTS) DQ9 ~ DQ16 VOH (or DQ1 ~ DQ8) (OUTPUTS) VOL tDH DATA VALID-1 tDS tDH DATA VALID-2 DATA VALID-3 Hi-Z VIH OE VIL 31 Aug. 1999 MITSUBISHI ELECTRIC (Rev. 1.0) MITSUBISHI LSIs M5M467400/465400DJ,DTP -5,-6,-5S,-6S M5M467800/465800DJ,DTP -5,-6,-5S,-6S M5M465160DJ,DTP -5,-6,-5S,-6S FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM Fast Page Mode Upper / (Lower) Byte Write Cycle (Delayed Write) (at M5M465160Dxx only) tRSH tRAS tCSH tRP tPC VIH RAS VIL tRPC tCRP UCAS (or LCAS) tRCD tCAS tCP tCRP tCAS VIH VIL tRPC tCRP tCRP LCAS (or UCAS) VIH VIL tRAD tASR Address VIH VIL tRAH ROW ADDRESS tASC tCAH tASC tRWL tWCH ROW ADDRESS tWCH tRCS tCWL VIH W tASR COLUMN ADDRESS-2 COLUMN ADDRESS-1 tRCS tCAH tCWL tWP tWP VIL DQ1 ~ DQ8 VIH (or DQ9 ~ DQ16) (INPUTS) VIL DQ1 ~ DQ8 VOH (or DQ9 ~ DQ16) (OUTPUTS) VOL Hi-Z tDS tDZC VIH DQ9 ~ DQ16 (or DQ1 ~ DQ8) (INPUTS) VIL tDH tDS tDZC DATA VALID-1 tDH DATA VALID-2 tDZO tDZO tCLZ tCLZ VOH DQ9 ~ DQ16 (or DQ1 ~ DQ8) (OUTPUTS) VOL Hi-Z tOEZ tOEZ tODD tOEH tOEH tODD VIH OE VIL 32 Aug. 1999 MITSUBISHI ELECTRIC (Rev. 1.0) MITSUBISHI LSIs M5M467400/465400DJ,DTP -5,-6,-5S,-6S M5M467800/465800DJ,DTP -5,-6,-5S,-6S M5M465160DJ,DTP -5,-6,-5S,-6S FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM Fast Page Mode Upper / (Lower) Byte Read-Write, Upper/(Lower) Byte Read-Modefy-Write Cycle (at M5M465160Dxx only) tRAS tRP tCSH VIH tRSH RAS VIL tRPC tPRWC tCRP tRCD tCAS tCP tCRP tCAS VIH UCAS (or LCAS) VIL tRPC tCRP tCRP VIH LCAS (or UCAS) VIL tRAD tASR Address VIH VIL tRAH tRWL tASC tCAH tASC tASR COLUMN ADDRESS-2 COLUMN ADDRESS-1 ROW ADDRESS tCAH ROW ADDRESS tRWD tWCH tWCH tRCS tRCS tAWD tCWL tWP tCWD W tAWD tCWL VIH tWP tCWD VIL tCPWD VIH DQ1 ~ DQ8 (or DQ9 ~ DQ16) (INPUTS) VIL tCPA DQ1 ~ DQ8 VOH (or DQ9 ~ DQ16) (OUTPUTS) VOL Hi-Z tAA tCAC tDZC tRAC DQ9 ~ DQ16 VIH (or DQ1 ~ DQ8) (INPUTS) VIL tAA tDS tDZC tDH DATA VALID-1 tDH DATA VALID-2 tDZO tDZO tCLZ tCLZ DQ9 ~ DQ16 VOH (or DQ1 ~ DQ8) (OUTPUTS) VOL tDS tCAC DATA VALID-1 DATA VALID-2 Hi-Z tOEA tOEA tOEZ tODD tOEH tOEZ tOEH tODD VIH OE VIL 33 Aug. 1999 MITSUBISHI ELECTRIC (Rev. 1.0) MITSUBISHI LSIs M5M467400/465400DJ,DTP -5,-6,-5S,-6S M5M467800/465800DJ,DTP -5,-6,-5S,-6S M5M465160DJ,DTP -5,-6,-5S,-6S FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM Upper / (Lower) CAS before RAS Refresh Cycle (at M5M465160Dxx only) tRP tRC tRC tRAS VIH tRP tRAS RAS VIL tRPC tCSR tRPC UCAS VIH (or LCAS) VIL tRPC tCRP tCSR tCHR tCHR tCPN tRPC LCAS (or UCAS) tRPC tCRP tRPC tCRP tCRP VIH VIL tASR Address VIH ROW ADDRESS VIL tRSR tRCH tRHR tRSR tRHR tRCS VIH W VIL tOFF DQ1 ~ DQ8 VIH (or DQ9 ~ DQ16) (INPUTS) VIL tOEZ DQ1 ~ DQ8 VOH (or DQ9 ~ DQ16) (OUTPUTS) VOL Hi-Z tCDD tOFF DQ9 ~ DQ16 VIH (or DQ1 ~ DQ8) (INPUTS) VIL tOEZ VOH DQ9 ~ DQ16 (or DQ1 ~ DQ8) (OUTPUTS) VOL Hi-Z tODD VIH OE VIL 34 Aug. 1999 MITSUBISHI ELECTRIC (Rev. 1.0) MITSUBISHI LSIs M5M467400/465400DJ,DTP -5,-6,-5S,-6S M5M467800/465800DJ,DTP -5,-6,-5S,-6S M5M465160DJ,DTP -5,-6,-5S,-6S FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM Upper / (Lower) Hidden Refresh Cycle (Byte Read) (at M5M465160Dxx only) (Note 29) tRC tRC tRAS tRAS tRP tRP VIH tRPC RAS VIL tRPC tRCD tRSH tCRP tCRP tCHR VIH UCAS (or LCAS) VIL tCRP tCRP VIH LCAS (or UCAS) VIL tRAD tASR Address VIH VIL tASC tRAH ROW ADDRESS tASR tCAH ROW ADDRESS COLUMN ADDRESS tRCS tRRH tRAL tRSR tRHR VIH W VIL DQ1 ~ DQ8 VIH (or DQ9 ~ DQ16) (INPUTS) VIL DQ1 ~ DQ8 VOH (or DQ9 ~ DQ16) (OUTPUTS) VOL Hi-Z tDZC tCDD VIH DQ9 ~ DQ16 (or DQ1 ~ DQ8) (INPUTS) VIL Hi-Z tCAC tOFF tCLZ VOH DQ9 ~ DQ16 (or DQ1 ~ DQ8) (OUTPUTS) VOL Hi-Z DATA VALID tAA tOEZ tRAC tDZO tOEA tODD tORH VIH OE VIL 35 Aug. 1999 MITSUBISHI ELECTRIC (Rev. 1.0) MITSUBISHI LSIs M5M467400/465400DJ,DTP -5,-6,-5S,-6S M5M467800/465800DJ,DTP -5,-6,-5S,-6S M5M465160DJ,DTP -5,-6,-5S,-6S FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM Byte Self Refresh Cycle (at M5M465160Dxx only) tRASS tRP RAS tRPS VIH VIL tRPC tRPC UCAS VIH (or LCAS) VIL tCSR tCHS tCRP tCPN tCRP tRPC LCAS VIH (or UCAS) VIL tRPC tCRP tASR VIH Address ROW ADDRESS VIL tRSR tRCH tRHR VIH W VIL Å @ Å @ Å @ Å @ DQ1 ~ DQ8 VIH (or DQ9 ~ DQ16) (INPUTS) VIL tOFF tOHC tREZ tOHR VOH DQ1 ~ DQ8 (or DQ9 ~ DQ16) (OUTPUTS) VOL Hi-Z tOEZ tCDD tOFF VIH DQ9 ~ DQ16 (or DQ1 ~ DQ8) (INPUTS) VIL VOH DQ9 ~ DQ16 (or DQ1 ~ DQ8) (OUTPUTS) VOL Hi-Z tOEZ tODD VIH OE VIL 36 Aug. 1999 MITSUBISHI ELECTRIC (Rev. 1.0) MITSUBISHI LSIs M5M467400/465400DJ,DTP -5,-6,-5S,-6S M5M467800/465800DJ,DTP -5,-6,-5S,-6S M5M465160DJ,DTP -5,-6,-5S,-6S FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM Keep safety first in your circuit designs! • Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable,but there is always the possibility that trouble may occur with them. Trouble with semiconductors consideration to safety when making your circuit designs,with appropriate measures such as (i) placement of substitutive, auxiliary circuits,(ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials •These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer's application;they do not convey any license under any intellectual property rights,or any other rights,belonging to Mitsubishi Electric Corporation or a third party. •Mitsubishi Electric Corporation assumes no responsibility for any damage,or infringement of any third-party's rights,originating in the use of any product data,diagrams,charts or circuit application examples contained in these materials. • All information contained in these materials,including product data,diagrams and charts, represent information on products at the time of publication of these materials,and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. • Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for special applications,such as apparatus or systems for transportation,vehicular, medical,aerospace,nuclear,or undersea repeater use. •The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. •If these products or technologies are subject the Japanese export control restrictions,they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. •Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein. 37 Aug. 1999 MITSUBISHI ELECTRIC