ON NBC12429FAG 3.3v/5v programmable pll synthesized clock generator Datasheet

NBC12429, NBC12429A
3.3V/5V Programmable PLL
Synthesized Clock
Generator
25 MHz to 400 MHz
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Description
The NBC12429 and NBC12429A are general purpose,
Phase--Lock--Loop (PLL) based synthesized clock sources. The VCO
will operate over a frequency range of 200 MHz to 400 MHz. The
VCO frequency is sent to the N--output divider, where it can be
configured to provide division ratios of 1, 2, 4, or 8. The VCO and
output frequency can be programmed using the parallel or serial
interfaces to the configuration logic. Output frequency steps of
125 kHz, 250 kHz, 500 kHz, or 1.0 MHz can be achieved using a
16 MHz crystal, depending on the output dividers. The PLL loop filter
is fully integrated and does not require any external components.
MARKING
DIAGRAMS
1 28
NBC12429xG
AWLYYWW
PLCC--28
FN SUFFIX
CASE 776
Features
•
•
•
•
Best--in--Class Output Jitter Performance, ±20 ps Peak--to--Peak
•
•
•
•
•
Serial 3--Wire Programming Interface
25 MHz to 400 MHz Programmable Differential PECL Outputs
Fully Integrated Phase--Lock--Loop with Internal Loop Filter
Parallel Interface for Programming Counter and Output Dividers
During Powerup
• Minimal Frequency Overshoot
LQFP--32
FA SUFFIX
CASE 873A
1
1
Crystal Oscillator Interface
32
QFN32
MN SUFFIX
CASE 488AM
Operating Range: VCC = 3.135 V to 5.25 V
CMOS and TTL Compatible Control Inputs
Pin and Function Compatible with Motorola MC12429 and
MPC9229
• 0°C to 70°C Ambient Operating Temperature (NBC12429)
• --40°C to 85°C Ambient Operating Temperature (NBC12429A)
• Pb--Free Packages are Available
NBC12
429x
AWLYYWWG
NBC12
429x
AWLYYWWG
G
x
= Blank or A
A
= Assembly Location
WL, L = Wafer Lot
YY, Y
= Year
WW, W = Work Week
G or G = Pb--Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 17 of this data sheet.
© Semiconductor Components Industries, LLC, 2007
February, 2007 -- Rev. 10
1
Publication Order Number:
NBC12429/D
NBC12429, NBC12429A
÷ 16
4
10--20 MHz
+3.3 or 5.0 V
1
PLL_VCC
1 MHz FREF
with
16 MHz Crystal
PHASE
DETECTOR
VCO
VCC
XTAL1
9--BIT ÷ M
COUNTER
OSC
5
+3.3 or 5.0 V
XTAL2
200--400
MHz
21, 25
24
23
÷N
(1, 2, 4, 8)
FOUT
FOUT
20
6
OE
LATCH
TEST
LATCH
28
S_LOAD
LATCH
7
P_LOAD
0
27
S_DATA
1
0
1
2--BIT SR
9--BIT SR
3--BIT SR
26
S_CLOCK
17, 18
8 ¤ 16
22, 19
9
2
M[8:0]
N[1:0]
Figure 1. Block Diagram (PLCC--28)
Table 1. Output Division
Table 2. XTAL_SEL and OE
N[1:0]
Output Division
Input
0
1
00
01
10
11
1
2
4
8
OE
Outputs Disabled
Outputs Enabled
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2
VCC
FOUT
FOUT
GND
VCC
TEST
GND
NBC12429, NBC12429A
25
24
23
22
21
20
19
27
17
N[0]
S_LOAD
28
16
M[8]
PLL_VCC
1
15
M[7]
NC
2
14
M[6]
NC
3
13
M[5]
XTAL1
4
12
M[4]
6
OE
XTAL2
5
7
8
9
10
11
M[3]
S_DATA
M[2]
N[1]
M[1]
18
M[0]
26
P_LOAD
S_CLOCK
S_DATA
25
24
1
2
23
N/C
N[1]
GND
GND
26
TEST
TEST
27
VCC
VCC
28
VCC
VCC
29
GND
GND
30
FOUT
FOUT
31
FOUT
FOUT
32
VCC
S_CLOCK
VCC
Figure 2. PLCC--28 (Top View)
32
31
30
29
28
27
26
25
S_CLOCK
1
24
N/C
S_DATA
2
23
N[1]
S_LOAD
3
22
N[0]
M[8]
PLL_VCC
4
21
PLL_VCC
5
20
M[7]
N/C
6
19
M[6]
N/C
7
18
M[5]
XTAL1
8
17
M[4]
PLL_VCC
5
20
M[7]
N/C
6
19
M[6]
17
9
10
11
12
13
14
15
16
P_LOAD
M[0]
M[1]
M[2]
M[3]
N/C
8
OE
XTAL1
18
7
XTAL2
N/C
M[5]
M[4]
Exposed Pad (EP)
Figure 4. 32--Lead QFN (Top View)
9
10
11
12
13
14
15
16
N/C
M[8]
M[3]
21
M[2]
4
M[1]
PLL_VCC
M[0]
N[0]
P_LOAD
22
OE
3
XTAL2
S_LOAD
Figure 3. LQFP--32 (Top View)
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NBC12429, NBC12429A
The following gives a brief description of the functionality of the NBC12429 and NBC12429A Inputs and Outputs. Unless
explicitly stated, all inputs are CMOS/TTL compatible with either pullup or pulldown resistors. The PECL outputs are capable
of driving two series terminated 50 Ω transmission lines on the incident edge.
Table 3. PIN FUNCTION DESCRIPTION
Pin Name
Function
Description
INPUTS
XTAL1, XTAL2
Crystal Inputs
These pins form an oscillator when connected to an external series--resonant
crystal.
S_LOAD*
CMOS/TTL Serial Latch Input
(Internal Pulldown Resistor)
This pin loads the configuration latches with the contents of the shift registers. The
latches will be transparent when this signal is HIGH; thus, the data must be stable
on the HIGH--to--LOW transition of S_LOAD for proper operation.
S_DATA*
CMOS/TTL Serial Data Input
(Internal Pulldown Resistor)
This pin acts as the data input to the serial configuration shift registers.
S_CLOCK*
CMOS/TTL Serial Clock Input
(Internal Pulldown Resistor)
This pin serves to clock the serial configuration shift registers. Data from S_DATA
is sampled on the rising edge.
P_LOAD**
CMOS/TTL Parallel Latch Input
(Internal Pullup Resistor)
This pin loads the configuration latches with the contents of the parallel inputs.
The latches will be transparent when this signal is LOW; therefore, the parallel
data must be stable on the LOW--to--HIGH transition of P_LOAD for proper operation.
M[8:0]**
CMOS/TTL PLL Loop Divider
Inputs (Internal Pullup Resistor)
These pins are used to configure the PLL loop divider. They are sampled on the
LOW--to--HIGH transition of P_LOAD. M[8] is the MSB, M[0] is the LSB.
N[1:0]**
CMOS/TTL Output Divider Inputs
(Internal Pullup Resistor)
These pins are used to configure the output divider modulus. They are sampled
on the LOW--to--HIGH transition of P_LOAD.
OE**
CMOS/TTL Output Enable Input
(Internal Pullup Resistor)
Active HIGH Output Enable. The Enable is synchronous to eliminate possibility of
runt pulse generation on the FOUT output.
FOUT, FOUT
PECL Differential Outputs
These differential, positive--referenced ECL signals (PECL) are the outputs of the
synthesizer.
TEST
CMOS/TTL Output
The function of this output is determined by the serial configuration bits T[2:0].
VCC
Positive Supply for the Logic
The positive supply for the internal logic and output buffer of the chip, and is connected to +3.3 V or +5.0 V.
PLL_VCC
Positive Supply for the PLL
This is the positive supply for the PLL and is connected to +3.3 V or +5.0 V.
GND
Negative Power Supply
These pins are the negative supply for the chip and are normally all connected to
ground.
--
Exposed Pad for QFN--32 only
The Exposed Pad (EP) on the QFN--32 package bottom is thermally connected to
the die for improved heat transfer out of package. The exposed pad must be attached to a heat--sinking conduit. The pad is electrically connected to GND.
OUTPUTS
POWER
* When left Open, these inputs will default LOW.
** When left Open, these inputs will default HIGH.
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NBC12429, NBC12429A
Table 4. ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 kΩ
Internal Input Pullup Resistor
37.5 kΩ
ESD Protection
Human Body Model
Machine Model
Charged Device Model
Moisture Sensitivity (Note 1)
PLCC
LQFP
QFN
Flammability Rating
Oxygen Index: 28 to 34
> 2 kV
> 150 V
> 1 kV
Pb Pkg
Pb--Free Pkg
Level 1
Level 2
Level 1
Level 1
Level 2
Level 1
UL 94 V--0 @ 0.125 in
Transistor Count
2035
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 5. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
VCC
Positive Supply
GND = 0 V
VI
Input Voltage
GND = 0 V
Iout
Output Current
Continuous
Surge
TA
Operating Temperature Range
Tstg
Storage Temperature Range
θJA
Thermal Resistance (Junction--to--Ambient)
0 lfpm
500 lfpm
θJC
Thermal Resistance (Junction--to--Case)
θJA
Condition 2
VI ± VCC
Rating
Unit
6
V
6
V
50
100
mA
mA
0 to 70
--40 to +85
NBC12429
NBC12429A
°C
--65 to +150
°C
PLCC--28
PLCC--28
63.5
43.5
°C/W
°C/W
Standard Board
PLCC--28
22 to 26
°C/W
Thermal Resistance (Junction--to--Ambient)
0 lfpm
500 lfpm
LQFP--32
LQFP--32
80
55
°C/W
°C/W
θJC
Thermal Resistance (Junction--to--Case)
Standard Board
LQFP--32
12 to 17
°C/W
θJA
Thermal Resistance (Junction--to--Ambient)
0 lfpm
500 lfpm
QFN--32
QFN--32
31
27
°C/W
°C/W
θJC
Thermal Resistance (Junction--to--Case)
2S2P
QFN--32
12
°C/W
Tsol
Wave Solder
Pb
Pb--Free
<3 sec @ 248°C
<3 sec @ 260°C
265
265
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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NBC12429, NBC12429A
Table 6. DC CHARACTERISTICS (VCC = 3.3 V ± 5%; TA = 0°C to 70°C (NBC12429), TA = --40°C to 85°C (NBC12429A))
Condition
Min
VIH
LVCMOS/
LVTTL
Input HIGH Voltage
Characteristic
VCC = 3.3 V
2.0
VIL
LVCMOS/
LVTTL
Input LOW Voltage
VCC = 3.3 V
IIN
Input Current
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VOH
PECL
Output HIGH Voltage
FOUT
FOUT
VCC = 3.3 V
(Notes 2, 3)
VOL
PECL
Output LOW Voltage
FOUT
FOUT
VCC = 3.3 V
(Notes 2, 3)
ICC
Power Supply Current
Symbol
TEST
TEST
IOH = --0.8 mA
Typ
Max
V
0.8
V
1.0
mA
2.5
V
IOL = 0.8 mA
VCC
PLL_VCC
Unit
0.4
V
2.155
2.405
V
1.355
1.605
V
70
26
mA
mA
48
18
58
22
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
2. FOUT/FOUT output levels will vary 1:1 with VCC variation.
3. FOUT/FOUT outputs are terminated through a 50 Ω resistor to VCC -- 2.0 V.
Table 7. DC CHARACTERISTICS (VCC = 5.0 V ± 5%; TA = 0°C to 70°C (NBC12429), TA = --40°C to 85°C (NBC12429A))
Characteristic
Symbol
Condition
Min
2.0
VIH
CMOS/
TTL
Input HIGH Voltage
VCC = 5.0 V
VIL
CMOS/
TTL
Input LOW Voltage
VCC = 5.0 V
IIN
Input Current
VOH
Output HIGH Voltage
TEST
IOH = --0.8 mA
VOL
Output LOW Voltage
TEST
IOL = 0.8 mA
VOH
PECL
Output HIGH Voltage
FOUT
FOUT
VCC = 5.0 V
(Notes 4, 5)
VOL
PECL
Output LOW Voltage
FOUT
FOUT
VCC = 5.0 V
(Notes 4, 5)
ICC
Power Supply Current
VCC
PLL_VCC
Typ
Max
Unit
V
0.8
V
1.0
mA
2.5
V
0.4
V
3.855
4.105
V
3.055
3.305
V
75
27
mA
mA
50
19
60
23
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. FOUT/FOUT output levels will vary 1:1 with VCC variation.
5. FOUT/FOUT outputs are terminated through a 50 Ω resistor to VCC -- 2.0 V.
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NBC12429, NBC12429A
Table 8. AC CHARACTERISTICS (VCC = 3.125 V to 5.25 V; TA = 0°C to 70°C (NBC12429), TA = --40°C to 85°C (NBC12429A))
(Note 6)
Symbol
Characteristic
Condition
FMAXI
Maximum Input Frequency
S_CLOCK
Xtal Oscillator
FMAXO
Maximum Output Frequency
VCO (Internal)
FOUT
tjitter(pd)
Period Jitter @ 3.3 V
10000 WFMS
(See Table 13 for Typical Values)
Cycle--to--Cycle @ 3.3 V
1000 WFMS
(See Table 13 for Typical Values)
Cycle--to--Cycle @ 5.0 V
1000 WFMS
(See Table 13 for Typical Values)
tLOCK
Max
Unit
10
10
20
MHz
200
25
400
400
MHz
25 MHz < fOUT < 100 MHz, M = 200
25 MHz < fOUT < 100 MHz, M = 300
25 MHz < fOUT < 100 MHz, M = 400
100 MHz < fOUT < 400 MHz, M = 200
100 MHz < fOUT < 400 MHz, M = 300
100 MHz < fOUT < 400 MHz, M = 400
25
9.0
6.0
9.0
5.0
4.0
psRMS
25 MHz < fOUT < 100 MHz, M = 200
25 MHz < fOUT < 100 MHz, M = 300
25 MHz < fOUT < 100 MHz, M = 400
100 MHz < fOUT < 400 MHz, M = 200
100 MHz < fOUT < 400 MHz, M = 300
100 MHz < fOUT < 400 MHz, M = 400
146
71
53
125
60
54
psPP
25 MHz < fOUT < 100 MHz, M = 200
25 MHz < fOUT < 100 MHz, M = 300
25 MHz < fOUT < 100 MHz, M = 400
100 MHz < fOUT < 400 MHz, M = 200
100 MHz < fOUT < 400 MHz, M = 300
100 MHz < fOUT < 400 MHz, M = 400
25
9.0
6.0
10
6.0
5.0
psRMS
25 MHz < fOUT < 100 MHz, M = 200
25 MHz < fOUT < 100 MHz, M = 300
25 MHz < fOUT < 100 MHz, M = 400
100 MHz < fOUT < 400 MHz, M = 200
100 MHz < fOUT < 400 MHz, M = 300
100 MHz < fOUT < 400 MHz, M = 400
168
69
57
133
49
108
psPP
25 MHz < fOUT < 100 MHz, M = 200
25 MHz < fOUT < 100 MHz, M = 300
25 MHz < fOUT < 100 MHz, M = 400
100 MHz < fOUT < 400 MHz, M = 200
100 MHz < fOUT < 400 MHz, M = 300
100 MHz < fOUT < 400 MHz, M = 400
20
11
8.0
17
10
9.0
psRMS
25 MHz < fOUT < 100 MHz, M = 200
25 MHz < fOUT < 100 MHz, M = 300
25 MHz < fOUT < 100 MHz, M = 400
100 MHz < fOUT < 400 MHz, M = 200
100 MHz < fOUT < 400 MHz, M = 300
100 MHz < fOUT < 400 MHz, M = 400
150
105
77
208
94
89
psPP
25 MHz < fOUT < 100 MHz, M = 200
25 MHz < fOUT < 100 MHz, M = 300
25 MHz < fOUT < 100 MHz, M = 400
100 MHz < fOUT < 400 MHz, M = 200
100 MHz < fOUT < 400 MHz, M = 300
100 MHz < fOUT < 400 MHz, M = 400
25
12
8.0
18
11
10
psRMS
25 MHz < fOUT < 100 MHz, M = 200
25 MHz < fOUT < 100 MHz, M = 300
25 MHz < fOUT < 100 MHz, M = 400
100 MHz < fOUT < 400 MHz, M = 200
100 MHz < fOUT < 400 MHz, M = 300
100 MHz < fOUT < 400 MHz, M = 400
192
131
76
164
128
186
psPP
10
ms
(Note 7)
Period Jitter @ 5.0 V
10000 WFMS
(See Table 13 for Typical Values)
tjitter(cyc--cyc)
Min
Maximum PLL Lock Time
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
6. FOUT/FOUT outputs are terminated through a 50 Ω resistor to VCC -- 2.0 V.
7. 10 MHz is the maximum frequency to load the feedback divide registers. S_CLOCK can be switched at higher frequencies when used
as a test clock in TEST_MODE 6.
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NBC12429, NBC12429A
Table 8. AC CHARACTERISTICS (VCC = 3.125 V to 5.25 V; TA = 0°C to 70°C (NBC12429), TA = --40°C to 85°C (NBC12429A))
(Note 6)
Symbol
Characteristic
Condition
Min
Max
Unit
ts
Setup Time
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
M, N to P_LOAD
20
20
20
ns
th
Hold Time
S_DATA to S_CLOCK
M, N to P_LOAD
20
20
ns
tpwMIN
Minimum Pulse Width
S_LOAD
P_LOAD
50
50
ns
DCO
Output Duty Cycle
tr, tf
Output Rise/Fall
FOUT
20%--80%
47.5
52.5
%
175
425
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
6. FOUT/FOUT outputs are terminated through a 50 Ω resistor to VCC -- 2.0 V.
7. 10 MHz is the maximum frequency to load the feedback divide registers. S_CLOCK can be switched at higher frequencies when used
as a test clock in TEST_MODE 6.
FUNCTIONAL DESCRIPTION
The internal oscillator uses the external quartz crystal as
the basis of its frequency reference. The output of the
reference oscillator is divided by 16 before being sent to the
phase detector. With a 16 MHz crystal, this provides a
reference frequency of 1 MHz. Although this data sheet
illustrates functionality only for a 16 MHz crystal, Table 9,
any crystal in the 10 MHz -- 20 MHz range can be used,
Table 11.
The VCO within the PLL operates over a range of 200 to
400 MHz. Its output is scaled by a divider that is configured
by either the serial or parallel interfaces. The output of this
loop divider is also applied to the phase detector.
The phase detector and the loop filter force the VCO
output frequency to be M times the reference frequency by
adjusting the VCO control voltage. Note that for some
values of M (either too high or too low), the PLL will not
achieve loop lock.
The output of the VCO is also passed through an output
divider before being sent to the PECL output driver. This
output divider (N divider) is configured through either the
serial or the parallel interfaces and can provide one of four
division ratios (1, 2, 4, or 8). This divider extends the
performance of the part while providing a 50% duty cycle.
The output driver is driven differentially from the output
divider and is capable of driving a pair of transmission lines
terminated into 50 Ω to VCC -- 2.0 V. The positive reference
for the output driver and the internal logic is separated from
the power supply for the PLL to minimize noise induced
jitter.
The configuration logic has two sections: serial and
parallel. The parallel interface uses the values at the M[8:0]
and N[1:0] inputs to configure the internal counters.
Normally upon system reset, the P_LOAD input is held
LOW until sometime after power becomes valid. On the
LOW--to--HIGH transition of P_LOAD, the parallel inputs
are captured. The parallel interface has priority over the
serial interface. Internal pullup resistors are provided on the
M[8:0] and N[1:0] inputs to reduce component count in the
application of the chip.
The serial interface logic is implemented with a fourteen
bit shift register scheme. The register shifts once per rising
edge of the S_CLOCK input. The serial input S_DATA must
meet setup and hold timing as specified in the AC
Characteristics section of this document. With P_LOAD
held high, the configuration latches will capture the value of
the shift register on the HIGH--to--LOW edge of the
S_LOAD input. See the programming section for more
information.
The TEST output reflects various internal node values and
is controlled by the T[2:0] bits in the serial data stream. See
the programming section for more information.
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NBC12429, NBC12429A
Table 9. PROGRAMMING VCO FREQUENCY FUNCTION TABLE WITH 16 MHZ CRYSTAL
VCO
Frequency
(MHz)
MCount
Divisor
200
256
128
64
32
16
8
4
2
1
M8
M7
M6
M5
M4
M3
M2
M1
M0
200
0
1
1
0
0
1
0
0
0
201
201
0
1
1
0
0
1
0
0
1
202
202
0
1
1
0
0
1
0
1
0
203
203
0
1
1
0
0
1
0
1
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
397
397
1
1
0
0
0
1
1
0
1
398
398
1
1
0
0
0
1
1
1
0
399
399
1
1
0
0
0
1
1
1
1
400
400
1
1
0
0
1
0
0
0
0
PROGRAMMING INTERFACE
131 MHz was desired, the following steps would be taken to
identify the appropriate M and N values. 131 MHz falls
within the frequency range set by an N value of 2; thus, N
[1:0] = 01. For N = 2, FOUT = M ÷ 2 and M = 2 x FOUT.
Therefore,
Programming the NBC12429 and NBC12429A is
accomplished by properly configuring the internal dividers
to produce the desired frequency at the outputs. The output
frequency can by represented by this formula:
FOUT = (FXTAL ÷ 16) × M ÷ N
(eq. 1)
M = 131 × 2 = 262, soM[8 : 0] = 100000110.
where FXTAL is the crystal frequency, M is the loop divider
modulus, and N is the output divider modulus. Note that it
is possible to select values of M such that the PLL is unable
to achieve loop lock. To avoid this, always make sure that M
is selected to be 200 ≤ M ≤ 400 for a 16 MHz input reference.
Assuming that a 16 MHz reference frequency is used the
above equation reduces to:
FOUT = M ÷ N
Following this same procedure, a user can generate any
whole frequency desired between 25 and 400 MHz. Note
that for N > 2, fractional values of FOUT can be realized. The
size of the programmable frequency steps (and thus, the
indicator of the fractional output frequencies achievable)
will be equal to FXTAL ÷ 16 ÷ N.
For input reference frequencies other than 16 MHz, see
Table 11, which shows the usable VCO frequency and
M divider range.
The input frequency and the selection of the feedback
divider M is limited by the VCO frequency range and
FXTAL. M must be configured to match the VCO frequency
range of 200 MHz to 400 MHz in order to achieve stable
PLL operation.
(eq. 2)
Substituting the four values for N (1, 2, 4, 8) yields:
Table 10. Programmable Output Divider Function
N1
N0
N Divider
FOUT
Output
Frequency
Range (MHz)*
FOUT
Step
0
0
÷1
M
200--400
1 MHz
0
1
÷2
M÷2
100--200
500 kHz
1
0
÷4
M÷4
50--100
250 kHz
1
1
÷8
M÷8
25--50
125 kHz
M min = fVCOmin ÷ (fXTAL ÷ 16) and
(eq. 3)
M max = fVCOmax ÷ (fXTAL ÷ 16)
(eq. 4)
The value for M falls within the constraints set for PLL
stability. If the value for M fell outside of the valid range, a
different N value would be selected to move M in the
appropriate direction.
The M and N counters can be loaded either through a
parallel or serial interface. The parallel interface is
controlled via the P_LOAD signal such that a LOW to HIGH
transition will latch the information present on the M[8:0]
and N[1:0] inputs into the M and N counters. When the
P_LOAD signal is LOW, the input latches will be
transparent and any changes on the M[8:0] and N[1:0] inputs
will affect the FOUT output pair. To use the serial port, the
*For crystal frequency of 16 MHz.
The user can identify the proper M and N values for the
desired frequency from the above equations. The four output
frequency
ranges
established
by
N
are
200 MHz -- 400 MHz,
100 MHz -- 200 MHz,
50 MHz -- 100 MHz and 25 MHz -- 50 MHz, respectively.
From these ranges, the user will establish the value of N
required. The value of M can then be calculated based on
Equation 1. For example, if an output frequency of
http://onsemi.com
9
NBC12429, NBC12429A
again through the serial interface. This approach allows the
application to come up at one frequency and then change or
fine--tune the clock as the ability to control the serial
interface becomes available.
The TEST output provides visibility for one of the several
internal nodes as determined by the T[2:0] bits in the serial
configuration stream. It is not configurable through the
parallel interface. The T2, T1, and T0 control bits are preset
to ‘000’ when P_LOAD is LOW so that the PECL FOUT
outputs are as jitter--free as possible. Any active signal on the
TEST output pin will have detrimental affects on the jitter
of the PECL output pair. In normal operations, jitter
specifications are only guaranteed if the TEST output is
static. The serial configuration port can be used to select one
of the alternate functions for this pin.
S_CLOCK signal samples the information on the S_DATA
line and loads it into a 14 bit shift register. Note that the
P_LOAD signal must be HIGH for the serial load operation
to function. The Test register is loaded with the first three
bits, the N register with the next two, and the M register with
the final nine bits of the data stream on the S_DATA input.
For each register, the most significant bit is loaded first (T2,
N1, and M8). A pulse on the S_LOAD pin after the shift
register is fully loaded will transfer the divide values into the
counters. The HIGH to LOW transition on the S_LOAD
input will latch the new divide values into the counters.
Figures 5 and 6 illustrate the timing diagram for both a
parallel and a serial load of the device synthesizer.
M[8:0] and N[1:0] are normally specified once at
powerup through the parallel interface, and then possibly
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10
NBC12429, NBC12429A
Table 11. FREQUENCY OPERATING RANGE
Output Frequency for
FXTAL = 16 MHz and for N =
VCO Frequency Range for a Crystal Frequency of:
M
M[8:0]
10
12
14
16
18
20
160
010100000
170
010101010
180
010110100
202.5
225
190
010111110
213.75
237.5
200
011001000
200
225
210
011010010
210
220
011011100
230
011100110
240
250
÷1
÷2
÷4
÷8
250
200
100
50
25
236.25
262.5
210
105
52.5
26.25
220
247.5
275
220
110
55
27.5
201.25
230
258.75
287.5
230
115
57.5
28.75
011110000
210
240
270
300
240
120
60
30
011111010
218.75
250
281.25
312.5
250
125
62.5
31.25
260
100000100
227.5
260
292.5
325
260
130
65
32.5
270
100001110
202.5
236.25
270
303.75
337.5
270
135
67.5
33.75
280
100011000
210
245
280
315
350
280
140
70
35
290
100100010
217.5
253.75
290
326.25
362.5
290
145
72.5
36.25
300
100101100
225
262.5
300
337.5
375
300
150
75
37.5
310
100110110
232.5
271.25
310
348.75
387.5
310
155
77.5
38.75
320
101000000
200
240
280
320
360
400
320
160
80
40
330
101001010
206.25
247.5
288.75
330
371.25
330
165
82.5
41.25
340
101010100
212.5
255
297.5
340
382.5
340
170
85
42.5
350
101011110
218.75
262.5
306.25
350
393.75
350
175
87.5
43.75
360
101101000
225
270
315
360
360
180
90
45
370
101110010
231.25
277.5
323.75
370
370
185
92.5
46.25
380
101111100
237.5
285
332.5
380
380
190
95
47.5
390
110000110
243.75
292.5
341.25
390
390
195
97.5
48.75
400
110010000
250
300
350
400
400
200
100
50
410
110011010
256.25
307.5
358.75
420
110100100
262.5
315
367.5
430
110101110
268.75
322.5
376.25
440
110111000
275
330
385
450
111000010
281.25
337.5
393.75
460
111001100
287.5
345
470
111010110
293.75
352.5
480
111100000
300
360
490
111101010
306.25
367.5
500
111110100
312.5
375
510
111111110
318.75
382.5
200
212.5
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11
NBC12429, NBC12429A
Most of the signals available on the TEST output pin are
useful only for performance verification of the device itself.
However, the PLL bypass mode may be of interest at the
board level for functional debug. When T[2:0] is set to 110,
the device is placed in PLL bypass mode. In this mode the
S_CLOCK input is fed directly into the M and N dividers.
The N divider drives the FOUT differential pair and the M
counter drives the TEST output pin. In this mode the
S_CLOCK input could be used for low speed board level
functional test or debug. Bypassing the PLL and driving
FOUT directly gives the user more control on the test clocks
sent through the clock tree. Figure 7 shows the functional
setup of the PLL bypass mode. Because the S_CLOCK is a
CMOS level the input frequency is limited to 250 MHz or
less. This means the fastest the FOUT pin can be toggled via
the S_CLOCK is 250 MHz as the minimum divide ratio of
the N counter is 1. Note that the M counter output on the
TEST output will not be a 50% duty cycle due to the way the
divider is implemented.
T2
T1
T0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
TEST (Pin 20)
SHIFT REGISTER OUT
HIGH
FREF
M COUNTER OUT
FOUT
LOW
PLL BYPASS
FOUT ÷ 4
M[8:0]
N[1:0]
VALID
ts
th
P_LOAD
M, N to P_LOAD
Figure 5. Parallel Interface Timing Diagram
S_CLOCK
ts
S_DATA
C1
C2
th
T2
T1
C3
C4
C5
C6
C7
C8
M7
M6
C9
C10
C11
C12
C13
C14
M4
M3
M2
M1
M0
S_DATA to S_CLOCK
T0
N1
N0
M8
M5
Last
Bit
First
Bit
S_LOAD
th
ts
S_CLOCK to S_LOAD
Figure 6. Serial Interface Timing Diagram
FREF_EXT
MCNT
VCO_CLK
PLL 12430
0
1
SCLOCK
M COUNTER
DECODE
SDATA
SHIFT
REG T0
14--BIT T1
T2
FDIV4
MCNT
LOW
FOUT
MCNT
FREF
HIGH
FOUT
(VIA ENABLE GATE)
7
TEST
MUX
0
LATCH
SLOAD
•
•
N÷
(1, 2, 4, 8)
T2=T1=1, T0=0: Test Mode
Reset
PLOAD
SCLOCK is selected, MCNT is on TEST output, SCLOCK ÷ N is on FOUT pin.
PLOAD acts as reset for test pin latch. When latch reset, T2 data is shifted out TEST pin.
Figure 7. Serial Test Clock Block Diagram
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12
TEST
NBC12429, NBC12429A
APPLICATIONS INFORMATION
Using the On--Board Crystal Oscillator
Power Supply Filtering
The NBC12429 and NBC12429A feature a fully
integrated on--board crystal oscillator to minimize system
implementation costs. The oscillator is a series resonant,
multivibrator type design as opposed to the more common
parallel resonant oscillator design. The series resonant
design provides better stability and eliminates the need for
large on chip capacitors. The oscillator is totally self
contained so that the only external component required is the
crystal. As the oscillator is somewhat sensitive to loading on
its inputs, the user is advised to mount the crystal as close to
the device as possible to avoid any board level parasitics. To
facilitate co--location, surface mount crystals are
recommended, but not required. Because the series resonant
design is affected by capacitive loading on the crystal
terminals, loading variation introduced by crystals from
different vendors could be a potential issue. For crystals with
a higher shunt capacitance, it may be required to place a
resistance across the terminals to suppress the third
harmonic. Although typically not required, it is a good idea
to layout the PCB with the provision of adding this external
resistor. The resistor value will typically be between 500 Ω
and 1 kΩ.
The oscillator circuit is a series resonant circuit and thus,
for optimum performance, a series resonant crystal should
be used. Unfortunately, most crystals are characterized in a
parallel resonant mode. Fortunately, there is no physical
difference between a series resonant and a parallel resonant
crystal. The difference is purely in the way the devices are
characterized. As a result, a parallel resonant crystal can be
used with the device with only a minor error in the desired
frequency. A parallel resonant mode crystal used in a series
resonant circuit will exhibit a frequency of oscillation a few
hundred ppm lower than specified (a few hundred ppm
translates to kHz inaccuracies). In a general computer
application, this level of inaccuracy is immaterial. Table 12
below specifies the performance requirements of the
crystals to be used with the device.
The NBC12429 and NBC12429A are mixed
analog/digital products and as such, exhibit some
sensitivities that would not necessarily be seen on a fully
digital product. Analog circuitry is naturally susceptible to
random noise, especially if this noise is seen on the power
supply pins. The NBC12429 and NBC12429A provide
separate power supplies for the digital circuitry (VCC) and
the internal PLL (PLL_VCC) of the device. The purpose of
this design technique is to try and isolate the high switching
noise of the digital outputs from the relatively sensitive
internal analog PLL. In a controlled environment such as an
evaluation board, this level of isolation is sufficient.
However, in a digital system environment where it is more
difficult to minimize noise on the power supplies, a second
level of isolation may be required. The simplest form of
isolation is a power supply filter on the PLL_VCC pin for the
NBC12429 and NBC12429A.
Figure 8 illustrates a typical power supply filter scheme.
The NBC12429 and NBC12429A are most susceptible to
noise with spectral content in the 1 kHz to 1 MHz range.
Therefore, the filter should be designed to target this range.
The key parameter that needs to be met in the final filter
design is the DC voltage drop that will be seen between the
VCC supply and the PLL_VCC pin of the NBC12429 and
NBC12429A. From the data sheet, the PLL_VCC current
(the current sourced through the PLL_VCC pin) is typically
23 mA (27 mA maximum). Assuming that a minimum of
2.8 V must be maintained on the PLL_VCC pin, very little
DC voltage drop can be tolerated when a 3.3 V VCC supply
is used. The resistor shown in Figure 8 must have a
resistance of 10 -- 15 Ω to meet the voltage drop criteria. The
RC filter pictured will provide a broadband filter with
approximately 100:1 attenuation for noise whose spectral
content is above 20 kHz. As the noise frequency crosses the
series resonant point of an individual capacitor, it’s overall
impedance begins to look inductive and thus increases with
increasing frequency. The parallel capacitor combination
shown ensures that a low impedance path to ground exists
for frequencies well above the bandwidth of the PLL.
Table 12. Crystal Specifications
Parameter
Value
Crystal Cut
Fundamental AT Cut
Resonance
Series Resonance*
Frequency Tolerance
±75 ppm at 25°C
Frequency/Temperature Stability
±150 ppm 0 to 70°C
Operating Range
0 to 70°C
Shunt Capacitance
5--7 pF
Equivalent Series Resistance (ESR)
50 to 80 Ω
Correlation Drive Level
100 mW
Aging
5 ppm/Yr (First 3 Years)
3.3 V or
5.0 V
3.3 V or
5.0 V
RS = 10--15 Ω
PLL_VCC
22 mF
NBC12429
NBC12429A
0.01 mF
VCC
0.01 mF
*See accompanying text for series versus parallel resonant
discussion.
Figure 8. Power Supply Filter
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13
L=1000 mH
R=15 Ω
NBC12429, NBC12429A
A higher level of attenuation can be achieved by replacing
the resistor with an appropriate valued inductor. Figure 8
shows a 1000 mH choke. This value choke will show a
significant impedance at 10 kHz frequencies and above.
Because of the current draw and the voltage that must be
maintained on the PLL_VCC pin, a low DC resistance
inductor is required (less than 15 Ω). Generally, the
resistor/capacitor filter will be cheaper, easier to implement,
and provide an adequate level of supply filtering.
The
NBC12429
and
NBC12429A
provide
sub--nanosecond output edge rates and therefore a good
power supply bypassing scheme is a must. Figure 9 shows
a representative board layout for the NBC12429 and
NBC12429A. There exists many different potential board
layouts and the one pictured is but one. The important aspect
of the layout in Figure 9 is the low impedance connections
between VCC and GND for the bypass capacitors.
Combining good quality general purpose chip capacitors
with good PCB layout techniques will produce effective
capacitor resonances at frequencies adequate to supply the
instantaneous switching current for the NBC12429 and
NBC12429A outputs. It is imperative that low inductance
chip capacitors are used. It is equally important that the
board layout not introduce any of the inductance saved by
using the leadless capacitors. Thin interconnect traces
between the capacitor and the power plane should be
avoided and multiple large vias should be used to tie the
capacitors to the buried power planes. Fat interconnect and
large vias will help to minimize layout induced inductance
and thus maximize the series resonant point of the bypass
capacitors.
C1
Note the dotted lines circling the crystal oscillator
connection to the device. The oscillator is a series resonant
circuit and the voltage amplitude across the crystal is
relatively small. It is imperative that no actively switching
signals cross under the crystal as crosstalk energy coupled
to these lines could significantly impact the jitter of the
device. Special attention should be paid to the layout of the
crystal to ensure a stable, jitter free interface between the
crystal and the on--board oscillator. Note the provisions for
placing a resistor across the crystal oscillator terminals as
discussed in the crystal oscillator section of this data sheet.
Although the NBC12429 and NBC12429A have several
design features to minimize the susceptibility to power
supply noise (isolated power and grounds and fully
differential PLL), there still may be applications in which
overall performance is being degraded due to system power
supply noise. The power supply filter and bypass schemes
discussed in this section should be adequate to eliminate
power supply noise--related problems in most designs.
Jitter Performance
Jitter is a common parameter associated with clock
generation and distribution. Clock jitter can be defined as the
deviation in a clock’s output transition from its ideal
position.
Cycle--to--Cycle Jitter is the period variation between
two adjacent cycles over a defined number of observed
cycles. The number of cycles observed is application
dependent but the JEDEC specification is 1000 cycles. Both
Peak--to--Peak and RMS statistical values were measured.
Period Jitter is the edge placement deviation observed
over a long period of consecutive cycles compared to the
position of the perfect reference clock’s edge and is specified
by the number of cycles over which the jitter is measured.
The number of cycles used to look for the maximum jitter
varies by application but the JEDEC spec is 10,000 observed
cycles. Both Peak--to--Peak and RMS value statistical values
were measured.
C1
R1
1
C3
C2
T0
R1 = 10--15 Ω
C1 = 0.01 mF
C2 = 22 mF
C3 = 0.1 mF
Xtal
T1
TJITTER(cycle--cycle) = T1 -- T0
Figure 10. Cycle--to--Cycle Jitter
Table 13 shows the typical Period and Cycle--to--Cycle
jitter as a function of the output frequency for selected M and
N values using a 16 MHz crystal. Typical jitter values for
other M and N registers settings may be linearly
interpolated. The general trend is that as the VCO output
frequency is increased, primarily determined by the M
register setting, the output jitter will decrease. Alternate
combinations of M and N register values may produce the
same output frequency but with significantly different jitter
performance.
= VCC
= GND
= Via
Figure 9. PCB Board Layout (PLCC--28)
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14
NBC12429, NBC12429A
Table 13. TYPICAL JITTER PERFORMANCE, 3.3 V, 25°C with 16 MHz Crystal Input at Selected M and N Values
M Value
200
200
200
200
300
300
300
300
400
400
400
400
N Value
1
2
4
8
1
2
4
8
1
2
4
8
JITTER
FOUT in MHz
Cycle--to--Cycle (psPP)
25
106
37.5
67
50
91
44
75
55
100
105
51
150
200
59
98
52
300
58
400
Cycle--to--Cycle
(psRMS)
43
25
17
37.5
10
50
13
7
75
9
100
13
8
150
200
9
11
8
300
6
400
Period (psPP)
6
25
106
37.5
56
50
79
35
75
42
100
66
32
150
200
39
65
31
300
38
400
Period (psRMS)
33
25
14
37.5
7
50
10
75
6
100
4
150
200
5
7
5
6
4
300
4
400
4
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15
NBC12429, NBC12429A
S_DATA
S_CLOCK
tHOLD
tSETUP
Figure 11. Setup and Hold
S_DATA
S_LOAD
tHOLD
tSETUP
Figure 12. Setup and Hold
M[8:0]
N[1:0]
P_LOAD
tHOLD
tSETUP
Figure 13. Setup and Hold
FOUT
FOUT
Pulse Width
tPERIOD
Figure 14. Output Duty Cycle
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16
DCO =
τpw
τPERIOD
NBC12429, NBC12429A
Zo = 50 Ω
FOUT
D
Receiver
Device
Driver
Device
FOUT
D
Zo = 50 Ω
50 Ω
50 Ω
VTT
VTT = VCC -- 2.0 V
Figure 15. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D -- Termination of ECL Logic Devices.)
ORDERING INFORMATION
Package
Shipping†
NBC12429FA
LQFP--32
250 Units / Tray
NBC12429FAG
LQFP--32
(Pb--Free)
250 Units / Tray
NBC12429FAR2
LQFP--32
2000 / Tape & Reel
NBC12429FAR2G
LQFP--32
(Pb--Free)
2000 / Tape & Reel
NBC12429FN
PLCC--28
37 Units / Rail
NBC12429FNG
PLCC--28
(Pb--Free)
37 Units / Rail
NBC12429FNR2
PLCC--28
500 / Tape & Reel
NBC12429FNR2G
PLCC--28
(Pb--Free)
500 / Tape & Reel
NBC12429AFA
LQFP--32
250 Units / Tray
NBC12429AFAG
LQFP--32
(Pb--Free)
250 Units / Tray
NBC12429AFAR2
LQFP--32
2000 / Tape & Reel
NBC12429AFAR2G
LQFP--32
(Pb--Free)
2000 / Tape & Reel
NBC12429AFN
PLCC--28
37 Units / Rail
NBC12429AFNG
PLCC--28
(Pb--Free)
37 Units / Rail
NBC12429AFNR2
PLCC--28
500 / Tape & Reel
NBC12429AFNR2G
PLCC--28
(Pb--Free)
500 / Tape & Reel
NBC12429AMNG
QFN--32
(Pb--Free)
74 Units / Rail
NBC12429AMNR4G
QFN--32
(Pb--Free)
1000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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17
NBC12429, NBC12429A
Resource Reference of Application Notes
AN1405/D
-- ECL Clock Distribution Techniques
AN1406/D
-- Designing with PECL (ECL at +5.0 V)
AN1503/D
-- ECLinPSt I/O SPiCE Modeling Kit
AN1504/D
-- Metastability and the ECLinPS Family
AN1568/D
-- Interfacing Between LVDS and ECL
AN1672/D
-- The ECL Translator Guide
AND8001/D
-- Odd Number Counters Design
AND8002/D
-- Marking and Date Codes
AND8020/D
-- Termination of ECL Logic Devices
AND8066/D
-- Interfacing with ECLinPS
AND8090/D
-- AC Characteristics of ECL Devices
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18
NBC12429, NBC12429A
PACKAGE DIMENSIONS
PLCC--28
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 776--02
ISSUE E
--N--
0.007 (0.180)
B
Y BRK
M
T L--M
0.007 (0.180)
U
M
N
S
T L--M
S
S
N
S
D
Z
--M--
--L--
W
28
D
X
V
1
A
0.007 (0.180)
R
0.007 (0.180)
C
M
M
T L--M
T L--M
S
S
N
N
S
0.007 (0.180)
H
N
S
S
J
--T--
T L--M
S
N
S
N
S
K
SEATING
PLANE
F
VIEW S
G1
T L--M
K1
0.004 (0.100)
G
M
S
E
S
T L--M
S
VIEW D--D
Z
0.010 (0.250)
0.010 (0.250)
G1
VIEW S
S
NOTES:
1. DATUMS --L--, --M--, AND --N-- DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM --T--, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE
MOLD FLASH. ALLOWABLE MOLD FLASH IS
0.010 (0.250) PER SIDE.
4. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE
DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR
BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH
BETWEEN THE TOP AND BOTTOM OF THE
PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037
(0.940). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMENSION TO BE
SMALLER THAN 0.025 (0.635).
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
INCHES
MIN
MAX
0.485
0.495
0.485
0.495
0.165
0.180
0.090
0.110
0.013
0.019
0.050 BSC
0.026
0.032
0.020
-----0.025
-----0.450
0.456
0.450
0.456
0.042
0.048
0.042
0.048
0.042
0.056
-----0.020
2_
10_
0.410
0.430
0.040
------
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19
MILLIMETERS
MIN
MAX
12.32
12.57
12.32
12.57
4.20
4.57
2.29
2.79
0.33
0.48
1.27 BSC
0.66
0.81
0.51
-----0.64
-----11.43
11.58
11.43
11.58
1.07
1.21
1.07
1.21
1.07
1.42
-----0.50
2_
10_
10.42
10.92
1.02
------
0.007 (0.180)
M
T L--M
S
N
S
NBC12429, NBC12429A
PACKAGE DIMENSIONS
32
A1
A
--T--, --U--, --Z--
32 LEAD LQFP
CASE 873A--02
ISSUE C
4X
25
0.20 (0.008) AB T--U Z
1
AE
--U--
--T-B
P
V
17
8
BASE
METAL
DETAIL Y
V1
AC T--U Z
AE
DETAIL Y
N
--Z--
9
S1
4X
M
9
0.20 (0.008) AC T--U Z
F
D
S
8X
J
R
DETAIL AD
G
--AB--
SECTION AE--AE
C E
--AC--
H
W
K
X
DETAIL AD
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
MILLIMETER.
3. DATUM PLANE --AB-- IS LOCATED AT
BOTTOM OF LEAD AND IS COINCIDENT
WITH THE LEAD WHERE THE LEAD
EXITS THE PLASTIC BODY AT THE
BOTTOM OF THE PARTING LINE.
4. DATUMS --T--, --U--, AND --Z-- TO BE
DETERMINED AT DATUM PLANE --AB--.
5. DIMENSIONS S AND V TO BE
DETERMINED AT SEATING PLANE --AC--.
6. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.250 (0.010) PER SIDE.
DIMENSIONS A AND B DO INCLUDE
MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE --AB--.
7. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. DAMBAR
PROTRUSION SHALL NOT CAUSE THE
D DIMENSION TO EXCEED 0.520 (0.020).
8. MINIMUM SOLDER PLATE THICKNESS
SHALL BE 0.0076 (0.0003).
9. EXACT SHAPE OF EACH CORNER MAY
VARY FROM DEPICTION.
DIM
A
A1
B
B1
C
D
E
F
G
H
J
K
M
N
P
Q
R
S
S1
V
V1
W
X
http://onsemi.com
20
MILLIMETERS
MIN
MAX
7.000 BSC
3.500 BSC
7.000 BSC
3.500 BSC
1.400
1.600
0.300
0.450
1.350
1.450
0.300
0.400
0.800 BSC
0.050
0.150
0.090
0.200
0.450
0.750
12_ REF
0.090
0.160
0.400 BSC
1_
5_
0.150
0.250
9.000 BSC
4.500 BSC
9.000 BSC
4.500 BSC
0.200 REF
1.000 REF
INCHES
MIN
MAX
0.276 BSC
0.138 BSC
0.276 BSC
0.138 BSC
0.055
0.063
0.012
0.018
0.053
0.057
0.012
0.016
0.031 BSC
0.002
0.006
0.004
0.008
0.018
0.030
12_ REF
0.004
0.006
0.016 BSC
1_
5_
0.006
0.010
0.354 BSC
0.177 BSC
0.354 BSC
0.177 BSC
0.008 REF
0.039 REF
Q_
0.250 (0.010)
0.10 (0.004) AC
GAUGE PLANE
SEATING
PLANE
M_
0.20 (0.008)
B1
NBC12429, NBC12429A
PACKAGE DIMENSIONS
QFN32 5*5*1 0.5 P
CASE 488AM--01
ISSUE O
A
B
D
NOTES:
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM TERMINAL
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
PIN ONE
LOCATION
E
0.15 C
2X
2X
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
TOP VIEW
0.15 C
(A3)
0.10 C
A
32 X
0.08 C
C
L
32 X
9
D2
SEATING
PLANE
A1
SIDE VIEW
MILLIMETERS
MIN
NOM MAX
0.800 0.900 1.000
0.000 0.025 0.050
0.200 REF
0.180 0.250 0.300
5.00 BSC
2.950 3.100 3.250
5.00 BSC
2.950 3.100 3.250
0.500 BSC
0.200
----------0.300 0.400 0.500
SOLDERING FOOTPRINT*
EXPOSED PAD
16
K
5.30
32 X
17
3.20
8
32 X
E2
1
0.63
24
32
25
32 X b
0.10 C A B
e
3.20 5.30
0.05 C
BOTTOM VIEW
32 X
0.28
28 X
0.50 PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb--Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
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NBC12429/D