Lattice iCE40HX8K-CM225 Ice40â ¢ hx-series ultra low-power fpga family Datasheet

iCE40™ HX-Series
Ultra Low-Power
FPGA Family
October 03, 2012 (1.32)
Data Sheet
Figure 1: iCE40 HX-Series Family Architectural Features
 HX-Series - optimized for high
performance
 Low cost package offerings
 80% faster than iCE65
 Proven, high-volume 40 nm, low-power
I/O Bank 0
CMOS technology
8 Logic Cells = Programmable Logic Block
I/O Bank 1
PLB
PLB
PLB
PLB
SPI
Config
I/O Bank 2
Windows® and Linux® support
VHDL and Verilog logic synthesis
Place and route software
Design and IP core libraries
Low-cost iCEman40HX development board
Programmable Interconnect
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLL
NVCM
 Complete iCEcube™ development system
PLB
4Kbit RAM
4Kbit RAM
PLB
PLB
PLB
PLB
programmable interconnect fabric
 8K look-up tables (LUT4) and flip-flops
 Low-power logic and interconnect
PLB
 Flexible programmable logic and
PLB
methods and sources
Programmable Interconnect
 Up to 533 MHz PLL Output
 Reprogrammable from a variety of
PLB
I/O Bank 3
 Clock multiplication/division for display, SerDes,
and memory interface applications
PLB
Programmable Interconnect
 Integrated Phase-Locked Loop (PLL)





Programmable
Logic Block (PLB)
267 µA at f =0 kHz
(Typical)
Carry logic
Four-input
Table
Nonvolatile Configuration Look-Up(LUT4)
Memory (NVCM)
Phase-Locked
Loop
Flip-flop with enable
and reset controls
Table 1: iCE40HX Ultra Low-Power Programmable Logic Family Summary
Part Number
Logic Cells (LUT + Flip-Flop)
RAM4K Memory Blocks
RAM4K RAM bits
Phase-Locked Loops (PLLs)
Configuration bits (maximum)
Core Operating Power 0 KHz1
Maximum Programmable I/O Pins
Maximum Differential Input Pairs
HX1K
HX4K
HX8K
1,280
16
64K
1
245 Kb
267 µA
96
12
3,520
20
80K
2
533 Kb
667 µA
107
14
7,680
32
128K
2
1,057 Kb
1100 µA
206
26
Package
Code
Area mm
Pitch mm
225-ball ucBGA
CM225
7x7
0.4
132-ball csBGA
CB132
8x8
0.5
256-ball caBGA
CT256
14x14
0.8
100-pin VQFP2
VQ100
14x14
0.5
72(9)
TQ144
20x20
0.5
96(12)
144-pin TQFP
Note 1: At 1.2V VCC, 25°C
PIO: Max I/O (LVDS)
178(23)
95(11)
95(12)
95(12)
206(26)
107(14)
2: No PLL Available
© 2007-2012 by Lattice Semiconductor Corporation. All rights reserved.
www.latticesemi.com
(1.32, 03-OCT-2012)
1
iCE40 HX-Series Ultra-Low Power Family
Ordering Information
Figure 2 describes the iCE40HX ordering codes for all packaged components. See the separate DiePlus data sheets
when ordering die-based products. See the separate iCE40 Pinout Excel files for package and pinout specifications.
Figure 2: iCE40HX Ordering Codes (packaged, non-die components)
iCE40HX 8K - CM 225
High Performance
Series
Package Leads
Package Style
Logic Cells
1K, 4K, 8K
CM = ucBGA (0.4 mm pitch)
CB = csBGA (0.5 mm pitch)
CT = caBGA (0.8 mm pitch)
VQ = Very Thin Quad flat pack (0.5 mm pitch)
TQ = Thin Quad flat pack (0.5 mm pitch)
Part Number
LUTs
Supply Voltage
Temp.
iCE40HX1K-VQ100
iCE40HX1K-TQ144
iCE40HX1K-CB132
iCE40HX4K-CB132
iCE40HX4K-TQ144
iCE40HX8K-CB132
iCE40HX8K-CM225
iCE40HX8K-CT256
1,280
1,280
1,280
3,520
3,520
7,680
7,680
7,680
1.2V
1.2V
1.2V
1.2V
1.2V
1.2V
1.2V
1.2V
IND
IND
IND
IND
IND
IND
IND
IND
iCE40HX8K-CM225
225-ball Chip-Scale BGA Package
(7x7 mm footprint, 0.4 mm pitch)
Lattice Semiconductor Corporation
www.latticesemi.com/
(1.32, 03-OCT-2012)
2
iCE40 HX-Series Ultra-Low Power Family
Electrical Characteristics
All parameter limits are specified under worst-case supply voltage, junction temperature, and processing conditions.
Absolute Maximum Ratings
Stresses beyond those listed under Table 2 may cause permanent damage to the device. These are stress ratings only;
functional operation of the device at these or any other conditions beyond those listed under the Recommended
Operating Conditions is not implied. Exposure to absolute maximum conditions for extended periods of time
adversely affects device reliability.
Table 2: Absolute Maximum Ratings
Description
Minimum
Symbol
VCC
VPP_2V5
VPP_FAST
VCCIO_0
VCCIO_1
VCCIO_2
VCCIO_3
SPI_VCC
VIN_0
VIN_1
VIN_2
VIN_SPI
VIN_3
VCCPLL
IOUT
TJ
TSTG
Maximum
Units
Core supply Voltage
VPP_2V5 NVCM programming and operating supply
Optional fast NVCM programming supply
I/O bank supply voltage (I/O Banks 0, 1, 2 and 3 plus SPI
interface)
–0.5
1.42
–0.5
4.00
V
V
V
V
Voltage applied to PIO pin within a specific I/O bank (I/O
Banks 0, 1, 2 and 3 plus SPI interface)
–1.0
3.6
V
Analog voltage supply to the Phase Locked Loop (PLL)
DC output current per pin
Junction temperature
Storage temperature, no bias
–0.5
—
–55
–65
1.30
20
125
150
V
mA
°C
°C
Recommended Operating Conditions
Table 3: Recommended Operating Conditions
Symbol
VCC
VPP_2V51
VPP_FAST2
SPI_VCC
VCCIO_0
VCCIO_1
VCCIO_2
VCCIO_3
SPI_VCC
VCCPLL3
TA
TPROG
Notes:
Description
Core supply voltage
VPP_2V5 NVCM
programming and operating
supply
High Performance, low-power
Release from Power-on Reset
Configure from NVCM
NVCM programming
Optional fast NVCM programming supply
SPI interface supply voltage
I/O standards, all banks
LVCMOS33
LVCMOS25, LVDS
Minimum Nominal Maximum Units
1.14
1.20
1.26
V
1.30
—
3.47
V
2.30
—
3.47
V
2.30
—
3.00
V
Leave unconnected in application
1.71
—
3.47
V
2.70
3.30
3.47
V
2.38
2.50
2.63
V
LVCMOS18, SubLVDS
1.71
1.80
1.89
V
LVCMOS15
1.43
1.50
1.58
V
1.14
–40
10
1.20
—
25
1.26
85
30
V
°C
°C
Analog voltage supply to the Phase Locked Loop (PLL)
Ambient temperature
NVCM programming temperature
1.
VPP_2V5 must be connected to a valid voltage, when the iCE40HX device is active.
2.
VPP_FAST, used only for fast production programming, must be left floating or unconnected in application.
3.
VCCPLL must be tied to VCC when PLL is not used.
Lattice Semiconductor Corporation
www.latticesemi.com/
(1.32, 03-OCT-2012)
3
iCE40 HX-Series Ultra-Low Power Family
I/O Characteristics
Table 4: PIO Pin Electrical Characteristics
Symbol
Il
IOZ
CPIO
CGBIN
RPULLUP
VHYST
Description
Input pin leakage current
Three-state I/O pin (Hi-Z)
leakage current
PIO pin input capacitance
GBIN global buffer pin
input capacitance
Internal PIO pull-up
resistance during
configuration
Input hysteresis
Conditions
VIN = VCCIOmax to 0 V
VO = VCCIOmax to 0 V
Minimum
VCCIO = 3.3V
VCCIO = 2.5V
VCCIO = 1.8V
VCCIO = 1.5V
VCCIO = 1.5V to 3.3V
Nominal
Maximum
±10
±10
Units
µA
µA
6
6
pF
pF
60
80
120
160
50
kΩ
kΩ
kΩ
kΩ
mV
NOTE: All characteristics are characterized and may or may not be tested on each pin on each device.
Single-ended I/O Characteristics
Table 5: I/O Characteristics
I/O Standard
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
Nominal I/O
Bank Supply
Voltage
3.3V
2.5V
1.8V
1.5V
Lattice Semiconductor Corporation
www.latticesemi.com/
Input Voltage (V)
Output Voltage (V)
Output Current at
Voltage (mA)
VIL
VIH
VOL
VOH
IOL
IOH
0.80
0.70
2.00
1.70
35% VCCIO
35% VCCIO
65% VCCIO
65% VCCIO
0.4
0.4
0.4
0.4
2.40
2.00
1.40
1.20
8
6
4
2
8
6
4
2
(1.32, 03-OCT-2012)
4
iCE40 HX-Series Ultra-Low Power Family
Differential Inputs
Figure 3: Differential Input Specifications
VCCIO_3
Differential
input voltage
50%
DPxxB
1%
100Ω
Input common mode voltage
VIN_B
VID
VIN_A
DPxxA
VICM
iC40 Differential
Input
GND
Input common mode voltage:
|
Differential input voltage:
|
Table 6: Recommended Operating Conditions for Differential Inputs
VCCIO_3 (V)
VID (mV)
VICM (V)
I/O
Standard
Min
Nom
Max
Min
Nom
Max
LVDS
2.38
2.50
2.63
250
350
450
SubLVDS
1.71
1.80
1.89
100
150
200
Min
Nom
Max
Differential Outputs
Figure 4: Differential Output Specifications
VCCIO_x
RS 1%
RS
VOUT_B
Output common mode voltage
Differential
output voltage
50%
RP
VOD
VOUT_A
VOCM
iC40 Differential
Output Pair
GND
Output common mode voltage:
|
Differential output voltage:
|
Table 7: Recommended Operating Conditions for Differential Outputs
VCCIO_x (V)
Min
Nom
Max
RS
LVDS
2.38
2.50
2.63
SubLVDS
1.71
1.80
1.89
Lattice Semiconductor Corporation
www.latticesemi.com/
VOD (mV)
Ω
I/O
Standard
VOCM (V)
RP
Min
Nom
Max
150
140
300
350
400
270
120
100
150
200
Min
Nom
Max
(1.32, 03-OCT-2012)
5
iCE40 HX-Series Ultra-Low Power Family
AC Timing Guidelines
The following examples provide some guidelines of device performance. The actual performance depends on the
specific application and how it is physically implemented in the iCE40 FPGA using the Lattice iCEcube2 software.
The following guidelines assume typical conditions (VCC = 1.0 V or 1.2 V as specified, temperature = 25 ˚C). Apply
derating factors using the iCEcube2 timing analyzer to adjust to other operating regimes.
Programmable Logic Block (PLB) Timing
Table 8 provides timing information for the logic in a Programmable Logic Block (PLB), which includes the paths
shown in Figure 5 and Figure 6.
Figure 5 PLB Sequential Timing Circuit
PAD
PIO PAD
DFF
PIO
D
Q
LUT4
GBIN
Logic
Logic Cell
Cell
GBUF
Figure 6 PLB Combinational Timing Circuit
PAD
PIO PAD
PIO
LUT4
Logic Cell
Table 8: Typical Programmable Logic Block (PLB) Timing
Nominal VCC
Description
Sequential Logic Paths
FTOGGLE
GBIN
GBIN Flip-flop toggle frequency. DFF flip-flop output fed back to LUT4 input with
input
input 4-input XOR, clocked on same clock edge
Logic cell flip-flop (DFF) clock-to-output time, measured from the DFF CLK
tCKO
DFF
PIO
clock
output input to PIO output, including interconnect delay.
input
Global Buffer Input (GBIN) delay, though Global Buffer (GBUF) clock network
tGBCKLC
GBIN
DFF
input
clock to clock input on the logic cell DFF flip-flop.
input
tSULI
PIO
GBIN Minimum setup time on PIO input, through LUT4, to DFF flip-flop D-input
input
input before active clock edge on the GBIN input, including interconnect delay.
Minimum hold time on PIO input, through LUT4, to DFF flip-flop D-input
tHDLI
GBIN
PIO
input
input after active clock edge on the GBIN input, including interconnect delay.
Combinational Logic Paths
tLUT4IN
PIO
LUT4 Asynchronous delay from PIO input pad to adjacent PLB interconnect.
input
input
tILO
LUT4
LUT4 Logic cell LUT4 combinational logic propagation delay, regardless of logic
input
output complexity from input to output.
Asynchronous delay from adjacent PLB interconnect to PIO output
tLUT4IN
LUT4
PIO
output output pad.
Lattice Semiconductor Corporation
www.latticesemi.com/
1.2 V
Typ.
units
256
MHz
3.9
ns
1.5
ns
.67
ns
0
ns
1.8
ns
0.34
ns
3.7
ns
(1.32, 03-OCT-2012)
6
iCE40 HX-Series Ultra-Low Power Family
Programmable Input/Output (PIO) Block
Table 9 provides timing information for the logic in a Programmable Logic Block (PLB), which includes the paths
shown in Figure 7 and Figure 8. The timing shown is for the LVCMOS25 I/O standard in all I/O banks. The
iCEcube2 development software reports timing adjustments for other I/O standards.
Figure 7: Programmable I/O (PIO) Pad-to-Pad Timing Circuit
PAD
PIO PAD
PIO
Figure 8: Programmable I/O (PIO) Sequential Timing Circuit
PAD
PIO
PIO PAD
INFF
D
Q
GBIN
OUTFF
D
Q
GBUF
Table 9: Typical Programmable Input/Output (PIO) Timing (LVCMOS25)
Nominal VCC
1.2 V
Description
Synchronous Output Paths
OUTFF
Delay from clock input on OUTFF output flip-flop to PIO output
tOCKO
PIO
clock
output pad.
input
OUTFF
Global Buffer Input (GBIN) delay, though Global Buffer (GBUF)
tGBCKIO
GBIN
clock
clock network to clock input on the PIO OUTFF output flip-flop.
input
input
Synchronous Input Paths
Setup time on PIO input pin to INFF input flip-flop before active
tSUPDIN
PIO
GBIN
clock edge on GBIN input, including interconnect delay.
input
input
Hold time on PIO input to INFF input flip-flop after active clock
tHDPDIN
GBIN
PIO
edge on the GBIN input, including interconnect delay.
input
input
Pad to Pad
InterAsynchronous delay from PIO input pad to adjacent
tPADIN
PIO
connect interconnect.
input
InterAsynchronous delay from adjacent interconnect to PIO output
tPADO
PIO
connect
output pad including interconnect delay.
Lattice Semiconductor Corporation
www.latticesemi.com/
Typ.
units
3.1
ns
1.4
ns
0
ns
1.6
ns
1.8
ns
3.4
ns
(1.32, 03-OCT-2012)
7
iCE40 HX-Series Ultra-Low Power Family
RAM4K Block
Table 10 provides timing information for the logic in a RAM4K block, which includes the paths shown in Figure 9.
Figure 9: RAM4K Timing Circuit
PAD
GBIN
PIO
WDATA
RDATA
RAM4K
RAM Block
(256x16)
GBUF
WCLK
PIO PAD
GBUF
Table 10: Typical RAM4K Block Timing
Nominal VCC
Description
Write Setup/Hold Time
tSUWD
PIO
GBIN Minimum write data setup time on PIO inputs before active clock
input
input edge on GBIN input, include interconnect delay.
Minimum write data hold time on PIO inputs after active clock edge
tHDWD
GBIN
PIO
input
input on GBIN input, including interconnect delay.
Read Clock-Output-Time
Clock-to-output delay from RCLK input pin, through RAM4K RDATA
tCKORD
RCLK
PIO
clock
output output flip-flop to PIO output pad, including interconnect delay.
input
tGBCKRM
GBIN
RCLK Global Buffer Input (GBIN) delay, though Global Buffer (GBUF)
input
clock clock network to the RCLK clock input.
input
Write and Read Clock Characteristics
WCLK
WCLK
Write clock High time
tRMWCKH
RCLK
RCLK
Write clock Low time
tRMWCKL
Write clock cycle time
tRMWCYC
Sustained write clock frequency
FWMAX
Lattice Semiconductor Corporation
www.latticesemi.com/
GBIN
RCLK
1.2 V
Typ.
0.44
ns
0
ns
4.1
ns
1.4
ns
0.30
0.35
0.71
256
ns
ns
ns
MHz
(1.32, 03-OCT-2012)
8
iCE40 HX-Series Ultra-Low Power Family
Phase-Locked Loop (PLL) Block
Table 11 provides timing information for the Phase-Locked Loop (PLL) block shown in Figure 10.
Figure 10: Phase-Locked Loop (PLL)
PLL
LATCHINPUTVALUE
DYNAMICDELAY[3:0]
EXTFEEDBACK
BYPASS
RESET
REFERENCECLK
LOCK
PLLOUT
Table 11: Phase-Locked Loop (PLL) Block Timing
Nominal VCC
1.2 V
Symbol From
Frequency Range
FREF
FOUT
Duty Cycle
PLLIJ
TwHI
TwLOW
PLLOJ
Fine Delay
tFDTAP
PLLTAPS
PLLFDAM
Jitter
PLLIPJ
PLLOPJ
Lock/Reset Time
tLOCK
twRST
To
Description
Min.
Typical
Max.
Units
Input clock frequency range
Output clock frequency range (cannot exceed
maximum frequency supported by global
buffers)
10
16
—
—
133
533
MHz
MHz
Input duty cycle
Input clock high time
Input clock low time
Output duty cycle
35
2.5
2.5
45
—
—
—
—
65
—
—
55
%
ns
ns
%
Fine delay adjustment, per tap
Fine delay adjustment settings
Maximum delay adjustment
0
165
—
2.5
15
ps
taps
ns
Input clock period jitter
PLLOUT output period jitter
—
—
—
1% or
≤ 100
+/- 300
+/- 1.1%
output
period or
≥ 110
ps
ps
PLL lock time after receive stable, monotonic
REFERENCECLK input
Minimum reset pulse width
—
—
50
μs
20
—
—
ns
Notes:
1.
Output jitter performance is affected by input jitter. A clean reference clock < 100ps jitter must be used to ensure
best jitter performance.
2. The output jitter specification refers to the intrinsic jitter of the PLL.
Lattice Semiconductor Corporation
www.latticesemi.com/
(1.32, 03-OCT-2012)
9
iCE40 HX-Series Ultra-Low Power Family
Internal Configuration Oscillator Frequency
Table 12 shows the operating frequency for the iCE40’s internal configuration oscillator.
Table 12: Internal Oscillator Frequency at VCC = 1.2V
Symbol
fOSCD
fOSCL
fOSCH
Frequency (MHz)
Min.
Max.
7
10
Oscillator
Mode
Default
Low
Frequency
High
Frequency
Off
21
30
Description
Default oscillator frequency. Slow enough to safely operate
with any SPI serial PROM.
Supported by most SPI serial Flash PROMs
35
50
Supported by some high-speed SPI serial Flash PROMs
0
0
Oscillator turned off by default after configuration to save
power.
Configuration Timing
Table 13 shows the maximum time to configure an iCE40HX device, by oscillator mode. The calculations use the
slowest frequency for a given oscillator mode from Table 12 and the maximum configuration bitstream size from
Table 1, which includes full RAM4K block initialization. The configuration bitstream selects the desired oscillator
mode based on the performance of the configuration data source.
Table 13: Typical SPI Master or NVCM Configuration Timing by Oscillator Mode
Symbol
tCONFIGL
Description
Time from when minimum
Power-on Reset (POR)
threshold is reached until
user application starts.
Device
iCE40HX1K
Default
53
Low Freq.
25
High Freq.
11
Units
ms
iCE40HX4K
230
110
50
ms
iCE40HX8K
230
110
50
ms
Table 14 provides timing for the CRESET_B and CDONE pins.
Table 14: General Configuration Timing
Symbol
tCRESET_B
tDONE_IO
From
To
Description
CREST_B
CREST_B
CDONE
High
PIO pins
active
Minimum CRESET_B Low pulse width required to restart
configuration, from falling edge to rising edge
Number of configuration clock cycles after CDONE goes
High before the PIO pins are activated.
SPI Peripheral Mode (Clock = SPI_SCK, cycles measured
rising-edge to rising-edge)
All Grades
Min.
Max.
200
—
—
49
Units
ns
Clock
cycles
Depends on
SPI_SCK frequency
Table 15 provides various timing specifications for the SPI peripheral mode interface.
Table 15: SPI Peripheral Mode Timing
Symbol
tCR_SCK
From
To
CRESET_B
SPI_SCK
Description
Minimum time from a rising edge on CRESET_B until
the first SPI write operation, first SPI_SCK. During this
time, the iCE40HX FPGA is clearing its internal
configuration memory
SPI_SI
SPI_SCK Setup time on SPI_SI before the rising SPI_SCK clock
tSUSPISI
edge
SPI_SCK
SPI_SI
Hold time on SPI_SI after the rising SPI_SCK clock edge
tHDSPISI
SPI_SCK SPI_SCK SPI_SCK clock High time
tSPISCKH
SPI_SCK SPI_SCK SPI_SCK clock Low time
tSPISCKL
tSPISCKCYC SPI_SCK SPI_SCK SPI_SCK clock period*
SPI_SCK SPI_SCK Sustained SPI_SCK clock frequency*
FSPI_SCK
* = Applies after sending the synchronization pattern.
Lattice Semiconductor Corporation
www.latticesemi.com/
All Grades
Min.
Max.
300
—
Units
µs
12
—
ns
12
20
20
40
1
—
—
—
1,000
25
ns
ns
ns
ns
MHz
(1.32, 03-OCT-2012)
10
iCE40 HX-Series Ultra-Low Power Family
Power Consumption Characteristics
Core Power
Table 16 shows the power consumed on the internal VCC supply rail when the device is filled with 16-bit binary
counters, measured with a 32.768 kHz and at 32.0 MHz
Table 16: VCC Power Consumption for Device Filled with 16-Bit Binary Counters
Symbol
Description
VCC
ICC0K
ICC32K
ICC32M
f =0
f ≤ .768 kHz
f = 32.0 MHz
1.2V
1.2V
1.2V
iCE40HX1K
iCE40HX4K
iCE40HX8K
Typical1
Typical1
Typical1
Units
267
297
4
667
741
12
1100
1222
13
µA
µA
mA
Note 1: At 25°C
I/O Power
Table 17 provides the static current by I/O bank. The typical current for I/O Banks 0, 1, 2 and the SPI bank is not
measurable within the accuracy of the test environment. The PIOs in I/O Bank 3 use different circuitry and dissipate
a small amount of static current.
Table 17: I/O Bank Static Current (f = 0 MHz)
Symbol
ICCO_0
ICCO_1
ICCO_2
ICCO_3
ICCO_SPI
Description
I/O Bank 0
I/O Bank 1
I/O Bank 2
I/O Bank 3
SPI Bank
Static current consumption per I/O bank.
f = 0 MHz. No PIO pull-up resistors
enabled. All inputs grounded. All
outputs driving Low.
Typical
«
«
«
«
«
Maximum
1
1
1
1
1
Units
uA
uA
uA
uA
uA
NOTE: The typical static current for I/O Banks 0, 1, 2, and the SPI bank is less than the accuracy of the device tester.
Power Estimator
To estimate the power consumption for a specific application, please download and use the iCE40HX Power Estimator
Spreadsheet our use the power estimator built into the iCEcube2 software.
Lattice Semiconductor Corporation
www.latticesemi.com/
(1.32, 03-OCT-2012)
11
iCE40 HX-Series Ultra-Low Power Family
Revision History
Version
Date
1.32
03-OCT-2012
1.31
1.3
30-MAR-2012
22-MAR-2012
1.21
1.2
1.1
5-MAR-2012
13-FEB-2012
15-DEC-2011
1.01
1.0
31-OCT-2011
11-JUL-2011
Description
Updated Table 1 to remove iCE40HX640, add TQ144 package, note 1 to include 25°C,
and unified package nomenclature. Updated Figure 2 Ordering codes to include all part
numbers. Added Note 1: At 25°C to Table 16 VCC Power.
Updated Table 1
Production Release
Updated Notes on Table 3: Recommended Operating Conditions
Updated values in Table 4, Table 5 Table 12, Table 13 and Table 17
Updated Figure 3 and Figure 4 to specify iCE40
Updated company name
Moved package specifications to iCE40 Pinout Excel files.
Updated Table 1 maximum IOs.
Added 640, 1K and 4K to Table 13 configuration times. Updated Table 1 maximum IOs.
Initial Release
© 2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at
www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective
holders. The specifications and information herein are subject to change without notice.
Lattice Semiconductor Corporation
5555 N.E. Moore Court
Hillsboro, Oregon 97124-6421
United States of America
cumentati on s ervi ces by Prevail ing Technol ogy, Inc. ( www.pre vai ling-technol ogy.com )
Lattice Semiconductor Corporation
www.latticesemi.com/
Tel: +1 503 268 8000
Fax: +1 503 268 8347
(1.32, 03-OCT-2012)
12