AD EVAL-ADE7753ZEB Single-phase multifunction metering ic with di/dt sensor interface Datasheet

Single-Phase Multifunction Metering IC
with di/dt Sensor Interface
ADE7753
line-voltage period measurement, and rms calculation on the
voltage and current. The selectable on-chip digital integrator
provides direct interface to di/dt current sensors such as
Rogowski coils, eliminating the need for an external analog
integrator and resulting in excellent long-term stability and precise phase matching between the current and voltage channels.
FEATURES
High accuracy; supports IEC 60687/61036/61268 and
IEC 62053-21/62053-22/62053-23
On-chip digital integrator enables direct interface to current
sensors with di/dt output
A PGA in the current channel allows direct interface to
shunts and current transformers
Active, reactive, and apparent energy; sampled waveform;
current and voltage rms
Less than 0.1% error in active energy measurement over a
dynamic range of 1000 to 1 at 25°C
Positive-only energy accumulation mode available
On-chip user programmable threshold for line voltage surge
and SAG and PSU supervisory
Digital calibration for power, phase, and input offset
On-chip temperature sensor (±3°C typical)
SPI® compatible serial interface
Pulse output with programmable frequency
Interrupt request pin (IRQ) and status register
Reference 2.4 V with external overdrive capability
Single 5 V supply, low power (25 mW typical)
The ADE7753 provides a serial interface to read data, and a
pulse output frequency (CF), which is proportional to the active
power. Various system calibration features, i.e., channel offset
correction, phase calibration, and power calibration, ensure
high accuracy. The part also detects short duration low or high
voltage variations.
The positive-only accumulation mode gives the option to
accumulate energy only when positive power is detected. An
internal no-load threshold ensures that the part does not exhibit
any creep when there is no load. The zero-crossing output (ZX)
produces a pulse that is synchronized to the zero-crossing point
of the line voltage. This signal is used internally in the line cycle
active and apparent energy accumulation modes, which enables
faster calibration.
GENERAL DESCRIPTION
The ADE77531 features proprietary ADCs and DSP for high
accuracy over large variations in environmental conditions and
time. The ADE7753 incorporates two second-order 16-bit -Δ
ADCs, a digital integrator (on CH1), reference circuitry,
temperature sensor, and all the signal processing required to
perform active, reactive, and apparent energy measurements,
The interrupt status register indicates the nature of the interrupt,
and the interrupt enable register controls which event produces
an output on the IRQ pin, an open-drain, active low logic output.
The ADE7753 is available in a 20-lead SSOP package.
FUNCTIONAL BLOCK DIAGRAM
AVDD
DVDD
RESET
INTEGRATOR
PGA
WGAIN[11:0]
MULTIPLIER
V1P
DGND
ADE7753
LPF2
dt
ADC
V1N
HPF1
TEMP
SENSOR

2
PHCAL[5:0]
CFNUM[11:0]
APOS[15:0]
DFC

IRMSOS[11:0]
V2P
CFDEN[11:0]
VAGAIN[11:0]
x2
PGA
CF
VRMSOS[11:0]
|x|
ADC
VADIV[7:0]
V2N
%
%
WDIV[7:0]
LPF1
2.4V
REFERENCE
ZX
4k
SAG
REGISTERS AND
SERIAL INTERFACE
02875-A-001
AGND
REFIN/OUT
CLKIN CLKOUT
DIN DOUT SCLK
CS
IRQ
Figure 1.
1
U.S. Patents 5,745,323; 5,760,617; 5,862,069; 5,872,469.
Rev. C
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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Fax: 781.461.3113 ©2003–2010 Analog Devices, Inc. All rights reserved.
ADE7753
TABLE OF CONTENTS
Features .............................................................................................. 1
Energy Calculation..................................................................... 29
General Description ......................................................................... 1
Power Offset Calibration ........................................................... 31
Functional Block Diagram .............................................................. 1
Energy-to-Frequency Conversion............................................ 31
Revision History ............................................................................... 3
Line Cycle Energy Accumulation Mode ................................. 33
Specifications..................................................................................... 4
Positive-Only Accumulation Mode ......................................... 33
Timing Characteristics..................................................................... 6
No-Load Threshold.................................................................... 33
Absolute Maximum Ratings............................................................ 7
Reactive Power Calculation ...................................................... 33
ESD Caution .................................................................................. 7
Sign of Reactive Power Calculation ......................................... 35
Terminology ...................................................................................... 8
Apparent Power Calculation ..................................................... 35
Pin Configuration and Function Descriptions ............................. 9
Apparent Energy Calculation ................................................... 36
Typical Performance Characteristics ........................................... 11
Line Apparent Energy Accumulation ...................................... 37
Theory of Operation ...................................................................... 16
Energies Scaling .......................................................................... 38
Analog Inputs .............................................................................. 16
Calibrating an Energy Meter Based on the ADE7753 ........... 38
di/dt Current Sensor and Digital Integrator ............................... 17
CLKIN Frequency ...................................................................... 48
Zero-Crossing Detection ........................................................... 18
Suspending ADE7753 Functionality ....................................... 48
Period Measurement .................................................................. 19
Checksum Register..................................................................... 48
Power Supply Monitor ............................................................... 19
ADE7753 Serial Interface .......................................................... 49
Line Voltage Sag Detection ....................................................... 19
ADE7753 Registers ......................................................................... 52
Peak Detection ............................................................................ 20
ADE7753 Register Descriptions ................................................... 55
ADE7753 Interrupts ................................................................... 21
Communications Register ......................................................... 55
Temperature Measurement ....................................................... 22
Mode Register (0x09)................................................................. 55
ADE7753 Analog-to-Digital Conversion ................................ 22
Channel 1 ADC .......................................................................... 23
Interrupt Status Register (0x0B), Reset Interrupt Status
Register (0x0C), Interrupt Enable Register (0x0A) .............. 57
Channel 2 ADC .......................................................................... 25
CH1OS Register (0x0D) ............................................................ 58
Phase Compensation.................................................................. 27
Outline Dimensions ....................................................................... 59
Active Power Calculation .......................................................... 28
Ordering Guide .......................................................................... 59
Rev. C | Page 2 of 60
ADE7753
REVISION HISTORY
1/10—Rev. B to Rev C
6/04—Rev. 0 to Rev A
Changes to Figure 1........................................................................... 1
Changes to t6 Parameter (Table 2) ................................................... 6
Added Endnote 1 to Table 4............................................................. 9
Changes to Figure 32 ......................................................................16
Changes to Period Measurement Section ....................................19
Changes to Temperature Measurement Section .........................22
Changes to Figure 51 ......................................................................24
Changes to Channel 1 RMS Calculation Section ........................25
Added Table 7 ..................................................................................25
Changes to Channel 2 RMS Calculation Section ........................26
Added Table 8 ..................................................................................26
Changes to Figure 64 ......................................................................29
Changes to Apparent Power Calculation Section .......................35
Changes IEC Standards .................................................................... 1
Changes to Phase Error Between Channels Definition ............... 7
Changes to Figure 24 ...................................................................... 13
Changes to CH2OS Register .......................................................... 16
Change to the Period Measurement Section ............................... 18
Change to Temperature Measurement Section ........................... 21
Changes to Figure 69 ...................................................................... 31
Changes to Figure 71 ...................................................................... 33
Changes to the Apparent Energy Section .................................... 36
Changes to Energies Scaling Section ............................................ 37
Changes to Calibration Section ..................................................... 37
8/03—Revision 0: Initial Version
1/09—Rev. A to Rev B
Changes to Features Section ............................................................ 1
Changes to Zero-Crossing Detection Section and Period
Measurement Section .....................................................................19
Changes to Channel 1 RMS Calculation Section, Channel 1
RMS Offset Compensation Section, and Equation 4 .................25
Changes to Figure 56 and Channel 2 RMS Calculation
Section ..............................................................................................26
Changes to Figure 57 ......................................................................27
Changes to Energy Calculation Section .......................................30
Changes to Energy-to-Frequency Conversion Section ..............31
Changes to Apparent Energy Calculation Section......................36
Changes to Line Apparent Energy Accumulation Section ........37
Changes to Table 10 ........................................................................52
Changes to Table 12 ........................................................................56
Changes to Table 13 ........................................................................57
Changes to Ordering Guide ...........................................................59
Rev. C | Page 3 of 60
ADE7753
SPECIFICATIONS
AVDD = DVDD = 5 V ± 5%, AGND = DGND = 0 V, on-chip reference, CLKIN = 3.579545 MHz XTAL, TMIN to TMAX = −40°C to +85°C. See
the plots in the Typical Performance Characteristics section.
Table 1.
Parameter
ENERGY MEASUREMENT ACCURACY
Active Power Measurement Error
Channel 1 Range = 0.5 V Full Scale
Gain = 1
Gain = 2
Gain = 4
Gain = 8
Channel 1 Range = 0.25 V Full Scale
Gain = 1
Gain = 2
Gain = 4
Gain = 8
Channel 1 Range = 0.125 V Full Scale
Gain = 1
Gain = 2
Gain = 4
Gain = 8
Active Power Measurement Bandwidth
Phase Error 1 between Channels 1
AC Power Supply Rejection1
Output Frequency Variation (CF)
DC Power Supply Rejection1
Output Frequency Variation (CF)
IRMS Measurement Error
IRMS Measurement Bandwidth
VRMS Measurement Error
VRMS Measurement Bandwidth
ANALOG INPUTS 2
Maximum Signal Levels
Input Impedance (dc)
Bandwidth
Gain Error1, 2
Channel 1
Range = 0.5 V Full Scale
Range = 0.25 V Full Scale
Range = 0.125 V Full Scale
Channel 2
Offset Error1
Channel 1
Channel 2
WAVEFORM SAMPLING
Channel 1
Signal-to-Noise Plus Distortion
Bandwidth(–3 dB)
Spec
Unit
Test Conditions/Comments
0.1
0.1
0.1
0.1
% typ
% typ
% typ
% typ
CLKIN = 3.579545 MHz
Channel 2 = 300 mV rms/60 Hz, gain = 2
Over a dynamic range 1000 to 1
Over a dynamic range 1000 to 1
Over a dynamic range 1000 to 1
Over a dynamic range 1000 to 1
0.1
0.1
0.1
0.2
% typ
% typ
% typ
% typ
Over a dynamic range 1000 to 1
Over a dynamic range 1000 to 1
Over a dynamic range 1000 to 1
Over a dynamic range 1000 to 1
0.1
0.1
0.2
0.2
14
±0.05
% typ
% typ
% typ
% typ
kHz
max
Over a dynamic range 1000 to 1
Over a dynamic range 1000 to 1
Over a dynamic range 1000 to 1
Over a dynamic range 1000 to 1
0.2
% typ
±0.3
% typ
0.5
14
0.5
140
% typ
kHz
% typ
Hz
±0.5
390
14
V max
k min
kHz
±4
±4
±4
±4
±32
±13
±32
±13
% typ
% typ
% typ
% typ
mV max
mV max
mV max
mV max
62
14
dB typ
kHz
Line Frequency = 45 Hz to 65 Hz, HPF on
AVDD = DVDD = 5 V + 175 mV rms/120 Hz
Channel 1 = 20 mV rms, gain = 16, range = 0.5 V
Channel 2 = 300 mV rms/60 Hz, gain = 1
AVDD = DVDD = 5 V ± 250 mV dc
Channel 1 = 20 mV rms/60 Hz, gain = 16, range = 0.5 V
Channel 2 = 300 mV rms/60 Hz, gain = 1
Over a dynamic range 100 to 1
Over a dynamic range 20 to 1
See the Analog Inputs section
V1P, V1N, V2N, and V2P to AGND
CLKIN/256, CLKIN = 3.579545 MHz
External 2.5 V reference, gain = 1 on Channels 1 and 2
V1 = 0.5 V dc
V1 = 0.25 V dc
V1 = 0.125 V dc
V2 = 0.5 V dc
Gain 1
Gain 16
Gain 1
Gain 16
Sampling CLKIN/128, 3.579545 MHz/128 = 27.9 kSPS
See the Channel 1 Sampling section
150 mV rms/60 Hz, range = 0.5 V, gain = 2
CLKIN = 3.579545 MHz
Rev. C | Page 4 of 60
ADE7753
Parameter
Channel 2
Signal-to-Noise Plus Distortion
Bandwidth (–3 dB)
REFERENCE INPUT
REFIN/OUT Input Voltage Range
Input Capacitance
ON-CHIP REFERENCE
Reference Error
Current Source
Output Impedance
Temperature Coefficient
CLKIN
Input Clock Frequency
LOGIC INPUTS
RESET, DIN, SCLK, CLKIN, and CS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
Input Capacitance, CIN
LOGIC OUTPUTS
SAG and IRQ
Output High Voltage, VOH
Output Low Voltage, VOL
ZX and DOUT
Output High Voltage, VOH
Output Low Voltage, VOL
CF
Output High Voltage, VOH
Output Low Voltage, VOL
POWER SUPPLY
AVDD
DVDD
AIDD
DIDD
1
2
Spec
Unit
Test Conditions/Comments
See the Channel 2 Sampling section
150 mV rms/60 Hz, gain = 2
CLKIN = 3.579545 MHz
60
140
dB typ
Hz
2.6
2.2
10
V max
V min
pF max
±200
10
3.4
30
mV max
μA max
kΩ min
ppm/°C typ
4
1
MHz max
MHz min
2.4
0.8
±3
10
V min
V max
μA max
pF max
4
0.4
V min
V max
Open-drain outputs, 10 kΩ pull-up resistor
ISOURCE = 5 mA
ISINK = 0.8 mA
4
0.4
V min
V max
ISOURCE = 5 mA
ISINK = 0.8 mA
4
1
V min
V max
4.75
5.25
4.75
5.25
3
4
V min
V max
V min
V max
mA max
mA max
ISOURCE = 5 mA
ISINK = 7 mA
For specified performance
5 V – 5%
5 V + 5%
5 V – 5%
5 V + 5%
Typically 2.0 mA
Typically 3.0 mA
2.4 V + 8%
2.4 V – 8%
Nominal 2.4 V at REFIN/OUT pin
All specifications CLKIN of 3.579545 MHz
DVDD = 5 V ± 10%
DVDD = 5 V ± 10%
Typically 10 nA, VIN = 0 V to DVDD
See the Terminology section for explanation of specifications.
See the Analog Inputs section.
200 μA
TO
OUTPUT
PIN
IOl
+2.1V
CL
50pF
1.6mA
IOH
02875-0-002
Figure 2. Load Circuit for Timing Specifications
Rev. C | Page 5 of 60
ADE7753
TIMING CHARACTERISTICS
AVDD = DVDD = 5 V ± 5%, AGND = DGND = 0 V, on-chip reference, CLKIN = 3.579545 MHz XTAL, TMIN to TMAX = −40°C to +85°C.
Sample tested during initial release and after any redesign or process change that could affect this parameter. All input signals are specified with
tr = tf = 5 ns (10% to 90%) and timed from a voltage level of 1.6 V. See Figure 3, Figure 4, and the ADE7753 Serial Interface section.
Table 2.
Parameter
Spec
Unit
Test Conditions/Comments
t1
50
ns (min)
CS falling edge to first SCLK falling edge.
t2
t3
t4
t5
t6
t7
t8
50
50
10
5
4
50
100
ns (min)
ns (min)
ns (min)
ns (min)
μs (min)
ns (min)
ns (min)
SCLK logic high pulse width.
SCLK logic low pulse width.
Valid data setup time before falling edge of SCLK.
Data hold time after SCLK falling edge.
Minimum time between the end of data byte transfers.
Minimum time between byte transfers during a serial write.
CS hold time after SCLK falling edge.
t9 1
4
μs (min)
t10
t11
50
30
ns (min)
ns (min)
t12 2
100
10
100
ns (max)
ns (min)
ns (max)
Minimum time between read command (i.e., a write to communication
register) and data read.
Minimum time between data byte transfers during a multibyte read.
Data access time after SCLK rising edge following a write to the
communications register.
Bus relinquish time after falling edge of SCLK.
10
ns (min)
Write Timing
Read Timing
t13 3
1
2
3
Bus relinquish time after rising edge of CS.
Minimum time between read command and data read for all registers except waveform register, which is t9 = 500 ns min.
Measured with the load circuit in Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V.
Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit in Figure 2. The measured number is then extrapolated back
to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted in the timing characteristics is the true bus relinquish time of
the part and is independent of the bus loading.
t8
CS
t1
t6
t3
t7
t7
SCLK
t4
t2
0
1
DIN
A5
A4
t5
A3
A2
A1
DB7
A0
MOST SIGNIFICANT BYTE
COMMAND BYTE
DB0
DB7
DB0
LEAST SIGNIFICANT BYTE
02875-0-081
Figure 3. Serial Write Timing
CS
t1
t13
t9
SCLK
DIN
0
0
A5
A4
A3
A2
A1
t10
A0
DB7
COMMAND BYTE
t12
t11
t11
DOUT
DB0
MOST SIGNIFICANT BYTE
DB7
DB0
LEAST SIGNIFICANT BYTE
02875-0-083
Figure 4. Serial Read Timing
Rev. C | Page 6 of 60
ADE7753
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
AVDD to AGND
DVDD to DGND
DVDD to AVDD
Analog Input Voltage to AGND,
V1P, V1N, V2P, and V2N
Reference Input Voltage to AGND
Digital Input Voltage to DGND
Digital Output Voltage to DGND
Operating Temperature Range
Industrial
Storage Temperature Range
Junction Temperature
20-Lead SSOP, Power Dissipation
θJA Thermal Impedance
Lead Temperature, Soldering
Vapor Phase (60 sec)
Infrared (15 sec)
Rating
–0.3 V to +7 V
–0.3 V to +7 V
–0.3 V to +0.3 V
–6 V to +6 V
–0.3 V to AVDD + 0.3 V
–0.3 V to DVDD + 0.3 V
–0.3 V to DVDD + 0.3 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
–40°C to +85°C
–65°C to +150°C
150°C
450 mW
112°C/W
215°C
220°C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. C | Page 7 of 60
ADE7753
TERMINOLOGY
Measurement Error
The error associated with the energy measurement made by the
ADE7753 is defined by the following formula:
Percentage Error =
⎛ Energy Register ADE7753 − True Energy ⎞
⎜
⎟ × 100%
⎜
⎟
True Energy
⎝
⎠
Phase Error between Channels
The digital integrator and the high-pass filter (HPF) in Channel 1
have a non-ideal phase response. To offset this phase response
and equalize the phase response between channels, two phasecorrection networks are placed in Channel 1: one for the digital
integrator and the other for the HPF. The phase correction
networks correct the phase response of the corresponding
component and ensure a phase match between Channel 1
(current) and Channel 2 (voltage) to within ±0.1° over a range
of 45 Hz to 65 Hz with the digital integrator off. With the digital
integrator on, the phase is corrected to within ±0.4°
over a range of 45 Hz to 65 Hz.
Power Supply Rejection
This quantifies the ADE7753 measurement error as a percentage
of reading when the power supplies are varied. For the ac PSR
measurement, a reading at nominal supplies (5 V) is taken. A
second reading is obtained with the same input signal levels
when an ac (175 mV rms/120 Hz) signal is introduced onto the
supplies. Any error introduced by this ac signal is expressed as a
percentage of reading—see the Measurement Error definition.
For the dc PSR measurement, a reading at nominal supplies
(5 V) is taken. A second reading is obtained with the same input
signal levels when the supplies are varied ±5%. Any error
introduced is again expressed as a percentage of the reading.
ADC Offset Error
The dc offset associated with the analog inputs to the ADCs. It
means that with the analog inputs connected to AGND, the
ADCs still see a dc analog input signal. The magnitude of the
offset depends on the gain and input range selection—see the
Typical Performance Characteristics section. However, when
HPF1 is switched on, the offset is removed from Channel 1
(current) and the power calculation is not affected by this offset.
The offsets can be removed by performing an offset
calibration—see the Analog Inputs section.
Gain Error
The difference between the measured ADC output code (minus
the offset) and the ideal output code—see the Channel 1 ADC
and Channel 2 ADC sections. It is measured for each of the
input ranges on Channel 1 (0.5 V, 0.25 V, and 0.125 V). The
difference is expressed as a percentage of the ideal code.
Rev. C | Page 8 of 60
ADE7753
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
RESET 1
20 DIN
DVDD 2
19 DOUT
AVDD 3
18 SCLK
V1P 4
ADE7753
17 CS
16 CLKOUT
TOP VIEW
V2N 6 (Not to Scale) 15 CLKIN
V1N 5
14 IRQ
V2P 7
13 SAG
AGND 8
12 ZX
REFIN/OUT 9
11 CF
DGND 10
02875-0-005
Figure 5. Pin Configuration (SSOP Package)
Table 4. Pin Function Descriptions
Pin No.
1
Mnemonic
RESET
2
DVDD
3
AVDD
4, 5
V1P, V1N
6, 7
V2N, V2P
8
AGND
9
REFIN/OUT
10
DGND
11
CF
1
Description
Reset Pin for the ADE7753. A logic low on this pin holds the ADCs and digital circuitry (including the serial
interface) in a reset condition.
Digital Power Supply. This pin provides the supply voltage for the digital circuitry in the ADE7753. The
supply voltage should be maintained at 5 V ± 5% for specified operation. This pin should be decoupled to
DGND with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor.
Analog Power Supply. This pin provides the supply voltage for the analog circuitry in the ADE7753. The
supply should be maintained at 5 V ± 5% for specified operation. Every effort should be made to minimize
power supply ripple and noise at this pin by the use of proper decoupling. The typical performance graphs
show the power supply rejection performance. This pin should be decoupled to AGND with a 10 μF
capacitor in parallel with a ceramic 100 nF capacitor.
Analog Inputs for Channel 1. This channel is intended for use with a di/dt current transducer such as a
Rogowski coil or another current sensor such as a shunt or current transformer (CT). These inputs are fully
differential voltage inputs with maximum differential input signal levels of ±0.5 V, ±0.25 V, and ±0.125 V,
depending on the full-scale selection—see the Analog Inputs section. Channel 1 also has a PGA with gain
selections of 1, 2, 4, 8, or 16. The maximum signal level at these pins with respect to AGND is ±0.5 V. Both
inputs have internal ESD protection circuitry, and, in addition, an overvoltage of ±6 V can be sustained on
these inputs without risk of permanent damage.
Analog Inputs for Channel 2. This channel is intended for use with the voltage transducer. These inputs are
fully differential voltage inputs with a maximum differential signal level of ±0.5 V. Channel 2 also has a PGA
with gain selections of 1, 2, 4, 8, or 16. The maximum signal level at these pins with respect to AGND is
±0.5 V. Both inputs have internal ESD protection circuitry, and an overvoltage of ±6 V can be sustained on
these inputs without risk of permanent damage.
Analog Ground Reference. This pin provides the ground reference for the analog circuitry in the ADE7753,
i.e., ADCs and reference. This pin should be tied to the analog ground plane or the quietest ground
reference in the system. This quiet ground reference should be used for all analog circuitry, for example,
anti-aliasing filters, current and voltage transducers, etc. To keep ground noise around the ADE7753 to a
minimum, the quiet ground plane should connected to the digital ground plane at only one point. It is
acceptable to place the entire device on the analog ground plane.
Access to the On-Chip Voltage Reference. The on-chip reference has a nominal value of 2.4 V ± 8% and a
typical temperature coefficient of 30 ppm/°C. An external reference source can also be connected at this
pin. In either case, this pin should be decoupled to AGND with a 1 μF ceramic capacitor.
Digital Ground Reference. This pin provides the ground reference for the digital circuitry in the ADE7753,
i.e., multiplier, filters, and digital-to-frequency converter. Because the digital return currents in the ADE7753
are small, it is acceptable to connect this pin to the analog ground plane of the system. However, high bus
capacitance on the DOUT pin could result in noisy digital current, which could affect performance.
Calibration Frequency Logic Output. The CF logic output gives active power information. This output is
intended to be used for operational and calibration purposes. The full-scale output frequency can be
adjusted by writing to the CFDEN and CFNUM registers—see the Energy-to-Frequency Conversion section.
Rev. C | Page 9 of 60
ADE7753
Pin No.
12
Mnemonic
ZX
13
SAG
14
IRQ
15
CLKIN
16
CLKOUT
17
CS
18
SCLK
19
DOUT
20
DIN
1
Description
Voltage Waveform (Channel 2) Zero-Crossing Output. This output toggles logic high and logic low at the
zero crossing of the differential signal on Channel 2—see the Zero-Crossing Detection section.
This open-drain logic output goes active low when either no zero crossings are detected or a low voltage
threshold (Channel 2) is crossed for a specified duration—see the Line Voltage Sag Detection section.
Interrupt Request Output. This is an active low open-drain logic output. Maskable interrupts include active
energy register rollover, active energy register at half level, and arrivals of new waveform samples—see the
ADE7753 Interrupts section.
Master Clock for ADCs and Digital Signal Processing. An external clock can be provided at this logic input.
Alternatively, a parallel resonant AT crystal can be connected across CLKIN and CLKOUT to provide a clock
source for the ADE7753. The clock frequency for specified operation is 3.579545 MHz. Ceramic load
capacitors of between 22 pF and 33 pF should be used with the gate oscillator circuit. Refer to the crystal
manufacturer’s data sheet for load capacitance requirements.
A crystal can be connected across this pin and CLKIN as described for Pin 15 to provide a clock source for
the ADE7753. The CLKOUT pin can drive one CMOS load when either an external clock is supplied at CLKIN
or a crystal is being used.
Chip Select. Part of the 4-wire SPI serial interface. This active low logic input allows the ADE7753 to share
the serial bus with several other devices—see the ADE7753 Serial Interface section.
Serial Clock Input for the Synchronous Serial Interface. All serial data transfers are synchronized to this
clock—see the ADE7753 Serial Interface section. The SCLK has a Schmitt-trigger input for use with a clock
source that has a slow edge transition time, for example, opto-isolator output.
Data Output for the Serial Interface. Data is shifted out at this pin on the rising edge of SCLK. This logic
output is normally in a high impedance state unless it is driving data onto the serial data bus—see the
ADE7753 Serial Interface section.
Data Input for the Serial Interface. Data is shifted in at this pin on the falling edge of SCLK—see the
ADE7753 Serial Interface section.
It is recommended to drive the RESET, SCLK, and CS pins with either a push-pull without an external series resistor or with an open-collector with a 10 kΩ pull-up
resistor. Pull-down resistors are not recommended because under some conditions, they may interact with internal circuitry.
Rev. C | Page 10 of 60
ADE7753
TYPICAL PERFORMANCE CHARACTERISTICS
0.5
0.3
GAIN = 1
INTEGRATOR OFF
INTERNAL REFERENCE
0.4
0.3
–40°C, PF = 0.5
+85°C, PF = 1
0.1
+25°C, PF = 1
ERROR (%)
ERROR (%)
0.2
0.1
GAIN = 8
INTEGRATOR OFF
EXTERNAL REFERENCE
0.2
0
–0.1
–0.1
+25°C, PF = 0.5
–0.2
+25°C, PF = 1
0
–40°C, PF = 1
–0.3
–0.2
+85°C, PF = 0.5
–0.4
–0.5
0.1
1
10
FULL-SCALE CURRENT (%)
–0.3
0.1
100
1
10
FULL-SCALE CURRENT (%)
02875-0-006
02875-0-010
Figure 6. Active Energy Error as a Percentage of Reading (Gain = 1) over
Power Factor with Internal Reference and Integrator Off
Figure 9. Active Energy Error as a Percentage of Reading (Gain = 8) over
Temperature with External Reference and Integrator Off
0.6
0.4
GAIN = 8
INTEGRATOR OFF
INTERNAL REFERENCE
0.3
GAIN = 8
INTEGRATOR OFF
EXTERNAL REFERENCE
0.4
+85°C, PF = 1
0.2
–40°C, PF = 1
0.2
ERROR (%)
0.1
ERROR (%)
100
0
+25°C, PF = 1
–0.1
+85°C, PF = 0.5
+25°C, PF = 1
0
–0.2
–40°C, PF = 0.5
–0.2
–0.4
+25°C, PF = 0.5
–0.3
–0.4
0.1
1
10
FULL-SCALE CURRENT (%)
–0.6
0.1
100
1
10
FULL-SCALE CURRENT (%)
02875-0-008
100
02875-0-011
Figure 7. Active Energy as a Percentage of Reading (Gain = 8) over
Temperature with Internal Reference and Integrator Off
Figure 10. Active Energy Error as a Percentage of Reading (Gain = 8) over
Power Factor with External Reference and Integrator Off
0.8
0.5
GAIN = 8
INTEGRATOR OFF
INTERNAL REFERENCE
0.6
GAIN = 1
INTEGRATOR OFF
INTERNAL REFERENCE
0.4
0.3
0.2
0.2
ERROR (%)
ERROR (%)
0.4
+25°C, PF = 1
0
–0.2
0
–40°C, PF = 0.5
–0.1
–0.2
+25°C, PF = 0.5
+25°C, PF = 0
0.1
+85°C, PF = 0.5
+25°C, PF = 0.5
–0.3
–0.4
–0.6
0.1
–40°C, PF = 0.5
+85°C, PF = 0.5
1
10
FULL-SCALE CURRENT (%)
–0.4
–0.5
0.1
100
02875-0-009
1
10
FULL-SCALE CURRENT (%)
100
02875-0-012
Figure 8. Active Energy Error as a Percentage of Reading (Gain = 8) over
Power Factor with Internal Reference and Integrator Off
Figure 11. Reactive Energy Error as a Percentage of Reading (Gain = 1) over
Power Factor with Internal Reference and Integrator Off
Rev. C | Page 11 of 60
ADE7753
0.5
0.35
GAIN = 1
INTEGRATOR OFF
EXTERNAL REFERENCE
0.4
GAIN = 8
INTEGRATOR OFF
EXTERNAL REFERENCE
0.25
0.3
0.15
0.2
+25°C, PF = 0
0.1
0
ERROR (%)
ERROR (%)
+25°C, PF = 0
+25°C, PF = 0.5
–0.1
–0.2
0.05
–0.05
–0.15
+85°C, PF = 0.5
–0.3
–40°C, PF = 0.5
+85°C, PF = 0
–40°C, PF = 0
–0.25
–0.4
–0.5
0.1
1
10
FULL-SCALE CURRENT (%)
–0.35
0.1
100
1
10
FULL-SCALE CURRENT (%)
02875-0-013
100
02875-0-016
Figure 12. Reactive Energy Error as a Percentage of Reading (Gain = 1) over
Power Factor with External Reference and Integrator Off
Figure 15. Reactive Energy Error as a Percentage of Reading (Gain = 8) over
Temperature with External Reference and Integrator Off
0.5
0.20
GAIN = 8
INTEGRATOR OFF
EXTERNAL REFERENCE
0.4
0.15
0.3
–40°C, PF = 0
0.10
ERROR (%)
GAIN = 8
INTEGRATOR OFF
INTERNAL REFERENCE
0.2
ERROR (%)
+25°C, PF = 0
0.05
0
–0.05
+25°C, PF = 0
0
–0.1
+85°C, PF = 0.5
–0.2
+85°C, PF = 0
–0.10
0.1
–40°C, PF = 0.5
–0.3
–0.15
–0.4
–0.20
0.1
1
10
FULL-SCALE CURRENT (%)
–0.5
0.1
100
+25°C, PF = 0.5
1
10
FULL-SCALE CURRENT (%)
02875-0-014
02875-0-017
Figure 13. Reactive Energy Error as a Percentage of Reading (Gain = 8) over
Temperature with Internal Reference and Integrator Off
Figure 16. Reactive Energy Error as a Percentage of Reading (Gain = 8) over
Power Factor with External Reference and Integrator Off
0.3
0.3
GAIN = 8
INTEGRATOR OFF
INTERNAL REFERENCE
0.2
0.1
0.2
5.25V
0.1
–40°C, PF = 0.5
ERROR (%)
ERROR (%)
100
+25°C, PF = 0
0
GAIN = 8
INTEGRATOR OFF
INTERNAL REFERENCE
0
5.0V
–0.1
–0.1
4.75V
+85°C, PF = 0.5
+25°C, PF = 0.5
–0.2
–0.2
–0.3
0.1
1
10
FULL-SCALE CURRENT (%)
–0.3
0.1
100
1
10
FULL-SCALE CURRENT (%)
100
02875-0-018
02875-0-015
Figure 14. Reactive Energy Error as a Percentage of Reading (Gain = 8) over
Power Factor with Internal Reference and Integrator Off
Figure 17. Active Energy Error as a Percentage of Reading (Gain = 8) over
Power Supply with Internal Reference and Integrator Off
Rev. C | Page 12 of 60
ADE7753
0.1
1.0
GAIN = 8
INTEGRATOR OFF
EXTERNAL REFERENCE
0.8
0.6
0.6
–40°C, PF = 1
0.4
PF = 1
0.2
ERROR (%)
ERROR (%)
0.4
0
–0.2
–0.4
PF = 0.5
0.2
0
–0.4
–0.6
–0.8
–0.8
50
25°C, PF = 1
–0.2
–0.6
–0.1
45
GAIN = 8
INTEGRATOR ON
INTERNAL REFERENCE
0.8
55
LINE FREQUENCY (Hz)
60
85°C, PF = 1
–1.0
0.1
65
1
10
FULL-SCALE CURRENT (%)
02875-0-019
02875-0-023
Figure 18. Active Energy Error as a Percentage of Reading (Gain = 8) over
Frequency with External Reference and Integrator Off
Figure 21. Active Energy Error as a Percentage of Reading (Gain = 8) over
Temperature with Internal Reference and Integrator On
0.5
1.0
GAIN = 8
INTEGRATOR OFF
INTERNAL REFERENCE
0.4
–40°C, PF = 0.5
0.6
0.2
0.4
0.1
PF = 1
ERROR (%)
ERROR (%)
GAIN = 8
INTEGRATOR ON
INTERNAL REFERENCE
0.8
0.3
0
–0.1
–0.2
PF = 0.5
0.2
+85°C, PF = 0.5
0
+25°C, PF = 0
–0.2
–0.4
–0.3
–0.6
–0.4
–0.5
0.1
+25°C, PF = 0.5
–0.8
1
10
FULL-SCALE CURRENT (%)
–1.0
0.1
100
1
10
FULL-SCALE CURRENT (%)
02875-0-020
Figure 22. Reactive Energy Error as a Percentage of Reading (Gain = 8) over
Power Factor with Internal Reference and Integrator On
1.0
1.0
0.8
–40°C, PF = 0.5
GAIN = 8
INTEGRATOR ON
INTERNAL REFERENCE
0.6
0.4
0.2
ERROR (%)
ERROR (%)
+25°C, PF = 0.5
0
+25°C, PF = 1
–0.4
–0.6
–40°C, PF = 0
0.2
0
+25°C, PF = 0
–0.2
–0.4
+85°C, PF = 0.5
–0.6
–0.8
–1.0
0.1
GAIN = 8
INTEGRATOR ON
INTERNAL REFERENCE
0.8
0.4
–0.2
100
02875-0-024
Figure 19. IRMS Error as a Percentage of Reading (Gain = 8) with
Internal Reference and Integrator Off
0.6
100
+85°C, PF = 0
–0.8
1
10
FULL-SCALE CURRENT (%)
–1.0
0.1
100
02875-0-022
1
10
FULL-SCALE CURRENT (%)
100
02875-0-025
Figure 20. Active Energy Error as a Percentage of Reading (Gain = 8) over
Power Factor with Internal Reference and Integrator On
Figure 23. Reactive Energy Error as a Percentage of Reading (Gain = 8) over
Temperature with Internal Reference and Integrator On
Rev. C | Page 13 of 60
ADE7753
3.0
0.8
GAIN = 8
INTEGRATOR ON
INTERNAL REFERENCE
2.5
GAIN = 1
EXTERNAL REFERENCE
0.6
2.0
0.4
PF = 0.5
0.2
1.0
ERROR (%)
ERROR (%)
1.5
0.5
PF = 1
0
0
–0.2
–0.5
–0.4
–1.0
–0.6
–1.5
–0.8
–2.0
45
47
49
51
53
55
57
59
FREQUENCY (Hz)
61
63
1
65
10
FULL-SCALE VOLTAGE
100
02875-0-026
02875-0-029
Figure 24. Active Energy Error as a Percentage of Reading (Gain = 8) over
Power Factor with Internal Reference and Integrator On
Figure 27. VRMS Error as a Percentage of Reading (Gain = 1) with
External Reference
0.3
8
0.2
5.25V
GAIN = 8
INTEGRATOR ON
INTERNAL REFERENCE
6
HITS
ERROR (%)
0.1
0
4
5.0V
–0.1
4.75V
2
–0.2
0
–0.3
0.1
1
10
FULL-SCALE CURRENT (%)
–15
100
–12
0
–9
–6
–3
CH1 OFFSET (0p5V_1X) (mV)
Figure 25. Active Energy Error as a Percentage of Reading (Gain = 8) over
Power Supply with Internal Reference and Integrator On
0.5
0.3
GAIN = 8
INTEGRATOR ON
INTERNAL REFERENCE
PF = 1
ERROR (%)
0.2
0.1
0
–0.1
–0.2
PF = 0.5
–0.3
–0.4
–0.5
0.1
1
10
FULL-SCALE CURRENT (%)
6
02875-0-087
02875-0-027
0.4
3
100
02875-0-028
Figure 26. IRMS Error as a Percentage of Reading (Gain = 8) with
Internal Reference and Integrator On
Rev. C | Page 14 of 60
Figure 28. Channel 1 Offset (Gain = 1)
ADE7753
VDD
10μF
I
100nF
di/dt CURRENT
SENSOR
100Ω 1kΩ
33nF
33nF
100Ω
1kΩ
33nF
VDD
33nF
100nF
AVDD DVDD RESET
DIN
V1P
DOUT
V1N
SCLK
U1
ADE7753
10μF
CURRENT
TRANSFORMER
1kΩ
TO SPI BUS
(USED ONLY FOR
CALIBRATION)
V2N
33nF
600kΩ
110V
1kΩ
CLKIN
V2P
33nF
SAG
V1N
SCLK
U1
ADE7753
22pF
10μF
100nF
TO SPI BUS
(USED ONLY FOR
CALIBRATION)
CS
V2N
1kΩ
22pF
33nF
600kΩ
110V
NOT CONNECTED
1kΩ
CLKIN
V2P
Y1
3.58MHz
22pF
22pF
IRQ
33nF
SAG
ZX
REFIN/OUT
10μF
CLKOUT
IRQ
33nF
AVDD DVDD RESET
DIN
V1P
DOUT
1kΩ
33nF
Y1
3.58MHz
100nF
RB
CS
CLKOUT
1kΩ
100nF
10μF
I
NOT CONNECTED
ZX
CF
U3
10μF
AGND DGND
TO
FREQUENCY
COUNTER
CHANNEL 1 GAIN = 8
CHANNEL 2 GAIN = 1
PS2501-1
02875-A-012
100nF
REFIN/OUT
CF
U3
AGND DGND
CT TURN RATIO = 1800:1
CHANNEL 2 GAIN = 1
GAIN 1 (CH1) RB
10Ω
1
1.21Ω
8
Figure 29. Test Circuit for Performance Curves with Integrator On
TO
FREQUENCY
COUNTER
PS2501-1
02875-0-030
Figure 30. Test Circuit for Performance Curves with Integrator Off
Rev. C | Page 15 of 60
ADE7753
THEORY OF OPERATION
ANALOG INPUTS
Table 5. Maximum Input Signal Levels for Channel 1
The ADE7753 has two fully differential voltage input channels.
The maximum differential input voltage for input pairs V1P/V1N
and V2P/V2N is ±0.5 V. In addition, the maximum signal level
on analog inputs for V1P/V1N and V2P/ V2N is ±0.5 V with
respect to AGND.
Max Signal
Channel 1
0.5 V
0.25 V
0.125 V
0.0625 V
0.0313 V
0.0156 V
0.00781 V
Each analog input channel has a programmable gain amplifier
(PGA) with possible gain selections of 1, 2, 4, 8, and 16. The
gain selections are made by writing to the gain register—see
Figure 32. Bits 0 to 2 select the gain for the PGA in Channel 1,
and the gain selection for the PGA in Channel 2 is made via
Bits 5 to 7. Figure 31 shows how a gain selection for Channel 1
is made using the gain register.
7
6
5
GAIN[7:0]
4
3
2
0
0
0
0
0
0
1
0
0
0
ADC Input Range Selection
0.5 V
0.25 V
0.125 V
Gain = 1
−
−
Gain = 2
Gain = 1
−
Gain = 4
Gain = 2
Gain = 1
Gain = 8
Gain = 4
Gain = 2
Gain = 16
Gain = 8
Gain = 4
−
Gain = 16
Gain = 8
−
−
Gain = 16
GAIN REGISTER*
CHANNEL 1 AND CHANNEL 2 PGA CONTROL
7
6
5
4
3
2
1
0
0
0
0
0
0
0
PGA 2 GAIN SELECT
000 = × 1
001 = × 2
010 = × 4
011 = × 8
100 = × 16
GAIN (K)
SELECTION
* REGISTER CONTENTS
SHOW POWER-ON DEFAULTS
V1P
0
0
ADDR:
0x0F
PGA 1 GAIN SELECT
000 = × 1
001 = × 2
010 = × 4
011 = × 8
100 = × 16
CHANNEL 1 FULL-SCALE SELECT
00 = 0.5V
01 = 0.25V
10 = 0.125V
02875-0-032
Figure 32. ADE7753 Analog Gain Register
VIN
K × VIN
V1N
+
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
OFFSET ADJUST
(±50mV)
CH1OS[7:0]
BITS 0 to 5: SIGN MAGNITUDE CODED OFFSET CORRECTION
BIT 6: NOT USED
BIT 7: DIGITAL INTEGRATOR (ON = 1, OFF = 0; DEFAULT OFF)
02875-0-031
Figure 31. PGA in Channel 1
In addition to the PGA, Channel 1 also has a full-scale input
range selection for the ADC. The ADC analog input range
selection is also made using the gain register—see Figure 32. As
mentioned previously, the maximum differential input voltage
is 0.5 V. However, by using Bits 3 and 4 in the gain register, the
maximum ADC input voltage can be set to 0.5 V, 0.25 V, or
0.125 V. This is achieved by adjusting the ADC reference—see
the ADE7753 Reference Circuit section. Table 5 summarizes the
maximum differential input signal level on Channel 1 for the
various ADC range and gain selections.
It is also possible to adjust offset errors on Channel 1 and
Channel 2 by writing to the offset correction registers, CH1OS
and CH2OS, respectively. These registers allow channel offsets
in the range ±20 mV to ±50 mV (depending on the gain setting)
to be removed. Channel 1 and 2 offset registers are sign magnitude coded. A negative number is applied to the Channel 1
offset register, CH1OS, for a negative offset adjustment. Note
that the Channel 2 offset register is inverted. A negative number
is applied to CH2OS for a positive offset adjustment. It is not
necessary to perform an offset correction in an energy measurement application if HPF in Channel 1 is switched on. Figure 33
shows the effect of offsets on the real power calculation. As seen
from Figure 33, an offset on Channel 1 and Channel 2
contributes a dc component after multiplication. Because this dc
component is extracted by LPF2 to generate the active (real)
power information, the offsets contribute an error to the active
power calculation. This problem is easily avoided by enabling
HPF in Channel 1. By removing the offset from at least one
channel, no error component is generated at dc by the
multiplication. Error terms at cos(ωt) are removed by LPF2 and
by integration of the active power signal in the active energy
register (AENERGY[23:0]) —see the Energy Calculation section.
Rev. C | Page 16 of 60
ADE7753
The current and voltage rms offsets can be adjusted with the
IRMSOS and VRMSOS registers—see Channel 1 RMS Offset
Compensation and Channel 2 RMS Offset Compensation
sections.
DC COMPONENT (INCLUDING ERROR TERM)
IS EXTRACTED BY THE LPF FOR REAL
POWER CALCULATION
VOS × IOS
V× I
2
di/dt CURRENT SENSOR AND DIGITAL INTEGRATOR
IOS × V
A di/dt sensor detects changes in magnetic field caused by ac
current. Figure 35 shows the principle of a di/dt current sensor.
VOS × I
ω
0
2ω
FREQUENCY (RAD/S)
02875-0-033
Figure 33. Effect of Channel Offsets on the Real Power Calculation
The contents of the offset correction registers are 6-bit, sign and
magnitude coded. The weight of the LSB depends on the gain
setting, i.e., 1, 2, 4, 8, or 16. Table 6 shows the correctable offset
span for each of the gain settings and the LSB weight (mV) for
the offset correction registers. The maximum value that can be
written to the offset correction registers is ±31d—see Figure 34.
Figure 34 shows the relationship between the offset correction
register contents and the offset (mV) on the analog inputs for a
gain setting of 1. In order to perform an offset adjustment, the
analog inputs should be first connected to AGND, and there
should be no signal on either Channel 1 or Channel 2. A read
from Channel 1 or Channel 2 using the waveform register
indicates the offset in the channel. This offset can be canceled
by writing an equal and opposite offset value to the Channel 1
offset register, or an equal value to the Channel 2 offset register.
The offset correction can be confirmed by performing another
read. Note when adjusting the offset of Channel 1, one should
disable the digital integrator and the HPF.
Table 6. Offset Correction Range—Channels 1 and 2
Correctable Span
±50 mV
±37 mV
±30 mV
±26 mV
±24 mV
LSB Size
1.61 mV/LSB
1.19 mV/LSB
0.97 mV/LSB
0.84 mV/LSB
0.77 mV/LSB
+ EMF (ELECTROMOTIVE FORCE)
– INDUCED BY CHANGES IN
MAGNETIC FLUX DENSITY (di/dt)
02875-0-035
Figure 35. Principle of a di/dt Current Sensor
The flux density of a magnetic field induced by a current is
directly proportional to the magnitude of the current. The
changes in the magnetic flux density passing through a
conductor loop generate an electromotive force (EMF) between
the two ends of the loop. The EMF is a voltage signal, which is
proportional to the di/dt of the current. The voltage output
from the di/dt current sensor is determined by the mutual
inductance between the current-carrying conductor and the
di/dt sensor. The current signal needs to be recovered from the
di/dt signal before it can be used. An integrator is therefore
necessary to restore the signal to its original form. The ADE7753
has a built-in digital integrator to recover the current signal
from the di/dt sensor. The digital integrator on Channel 1 is
switched off by default when the ADE7753 is powered up.
Setting the MSB of CH1OS register turns on the integrator.
Figure 36 to Figure 39 show the magnitude and phase response
of the digital integrator.
10
CH1OS[5:0]
0
0x1F
01,1111b
SIGN + 5 BITS
–10
GAIN (dB)
Gain
1
2
4
8
16
MAGNETIC FIELD CREATED BY CURRENT
(DIRECTLY PROPORTIONAL TO CURRENT)
0x00
0mV
–50mV
+50mV
OFFSET
ADJUST
0x3F
–20
–30
11,1111b SIGN + 5 BITS
–40
02875-0-034
Figure 34. Channel 1 Offset Correction Range (Gain = 1)
–50
102
103
FREQUENCY (Hz)
Figure 36. Combined Gain Response of the
Digital Integrator and Phase Compensator
Rev. C | Page 17 of 60
02875-0-036
ADE7753
cant high frequency noise, therefore a more effective antialiasing filter is needed to avoid noise due to aliasing—see the
Antialias Filter section.
–88.0
PHASE (Degrees)
–88.5
When the digital integrator is switched off, the ADE7753 can be
used directly with a conventional current sensor such as a current
transformer (CT) or with a low resistance current shunt.
–89.0
ZERO-CROSSING DETECTION
–89.5
The ADE7753 has a zero-crossing detection circuit on
Channel 2. This zero crossing is used to produce an external
zero-crossing signal (ZX), and it is also used in the calibration
mode—see the Calibrating an Energy Meter Based on the
ADE7753 section. The zero-crossing signal is also used to
initiate a temperature measurement on the ADE7753—see the
Temperature Measurement section.
–90.0
–90.5
102
103
FREQUENCY (Hz)
FREQ
02875-0-037
Figure 37. Combined Phase Response of the
Digital Integrator and Phase Compensator
Figure 40 shows how the zero-crossing signal is generated from
the output of LPF1.
–1.0
×1, ×2, ×1,
×8, ×16
–1.5
–2.0
V2P
GAIN (dB)
–2.5
–3.0
{GAIN [7:5]}
PGA2
V2
REFERENCE
1
ADC 2
–63% TO +63% FS
TO
MULTIPLIER
V2N
–3.5
ZERO
CROSS
–4.0
–4.5
ZX
LPF1
f–3dB = 140Hz
–5.0
–5.5
–6.0
40
2.32° @ 60Hz
1.0
0.93
45
50
55
60
FREQUENCY (Hz)
ZX
70
65
02875-0-038
Figure 38. Combined Gain Response of the
Digital Integrator and Phase Compensator (40 Hz to 70 Hz)
–89.70
V2
LPF1
02875-0-040
–89.75
Figure 40. Zero-Crossing Detection on Channel 2
PHASE (Degrees)
–89.80
–89.85
–89.90
–89.95
–90.00
–90.05
40
45
50
55
60
FREQUENCY (Hz)
65
70
02875-0-039
Figure 39. Combined Phase Response of the
Digital Integrator and Phase Compensator (40 Hz to 70 Hz)
Note that the integrator has a –20 dB/dec attenuation and an
approximately –90° phase shift. When combined with a di/dt
sensor, the resulting magnitude and phase response should be a
flat gain over the frequency band of interest. The di/dt sensor
has a 20 dB/dec gain associated with it. It also generates signifi-
The ZX signal goes logic high on a positive-going zero crossing
and logic low on a negative-going zero crossing on Channel 2.
The zero-crossing signal ZX is generated from the output of
LPF1. LPF1 has a single pole at 140 Hz (at CLKIN = 3.579545
MHz). As a result, there is a phase lag between the analog input
signal V2 and the output of LPF1. The phase response of this
filter is shown in the Channel 2 Sampling section. The phase lag
response of LPF1 results in a time delay of approximately
1.14 ms (@ 60 Hz) between the zero crossing on the analog
inputs of Channel 2 and the rising or falling edge of ZX.
The zero-crossing detection also drives the ZX flag in the
interrupt status register. The ZX flag is set to Logic 0 on the
rising and falling edge of the voltage waveform. It stays low
until the status register is read with reset. An active low in the
IRQ output also appears if the corresponding bit in the
interrupt enable register is set to Logic 1.
Rev. C | Page 18 of 60
ADE7753
The flag in the interrupt status register as well as the IRQ output
are reset to their default values when the interrupt status register
with reset (RSTSTATUS) is read.
Zero-Crossing Timeout
The zero-crossing detection also has an associated timeout
register, ZXTOUT. This unsigned, 12-bit register is decremented
(1 LSB) every 128/CLKIN seconds. The register is reset to its
user programmed full-scale value every time a zero crossing is
detected on Channel 2. The default power on value in this
register is 0xFFF. If the internal register decrements to 0 before
a zero crossing is detected and the DISSAG bit in the mode
register is Logic 0, the SAG pin goes active low. The absence
of a zero crossing is also indicated on the IRQ pin if the ZXTO
enable bit in the interrupt enable register is set to Logic 1.
Irrespective of the enable bit setting, the ZXTO flag in the
interrupt status register is always set when the internal ZXTOUT
register is decremented to 0—see the ADE7753 Interrupts section.
The ZXOUT register can be written/read by the user and has an
address of 1Dh—see the ADE7753 Serial Interface section. The
resolution of the register is 128/CLKIN seconds per LSB. Thus the
maximum delay for an interrupt is 0.15 second (128/CLKIN × 212).
The resolution of this register is 2.2 μs/LSB when CLKIN =
3.579545 MHz, which represents 0.013% when the line frequency is 60 Hz. When the line frequency is 60 Hz, the value of
the period register is approximately CLKIN/4/32/60 Hz × 16 =
7457d. The length of the register enables the measurement of line
frequencies as low as 13.9 Hz.
The period register is stable at ±1 LSB when the line is
established and the measurement does not change. A settling
time of 1.8 seconds is associated with this filter before the
measurement is stable.
POWER SUPPLY MONITOR
The ADE7753 also contains an on-chip power supply monitor.
The analog supply (AVDD) is continuously monitored by the
ADE7753. If the supply is less than 4 V ± 5%, then the
ADE7753 goes into an inactive state, that is, no energy is
accumulated when the supply voltage is below 4 V. This is
useful to ensure correct device operation at power-up and
during power-down. The power supply monitor has built-in
hysteresis and filtering, which give a high degree of immunity
to false triggering due to noisy supplies.
AVDD
Figure 41 shows the mechanism of the zero-crossing timeout
detection when the line voltage stays at a fixed dc level for more
than CLKIN/128 × ZXTOUT seconds.
5V
4V
12-BIT INTERNAL
REGISTER VALUE
ZXTOUT
0V
TIME
ADE7753
POWER-ON
INACTIVE INACTIVE
STATE
CHANNEL 2
ACTIVE
INACTIVE
SAG
02875-0-042
Figure 42. On-Chip Power Supply Monitor
ZXTO
DETECTION
BIT
02875-0-041
Figure 41. Zero-Crossing Timeout Detection
PERIOD MEASUREMENT
The ADE7753 also provides the period measurement of the
line. The period register is an unsigned 16-bit register and is
updated every period. The MSB of this register is always zero.
As seen in Figure 42, the trigger level is nominally set at 4 V.
The tolerance on this trigger level is about ±5%. The SAG pin
can also be used as a power supply monitor input to the MCU.
The SAG pin goes logic low when the ADE7753 is in its inactive
state. The power supply and decoupling for the part should be
such that the ripple at AVDD does not exceed 5 V ±5%, as
specified for normal operation.
LINE VOLTAGE SAG DETECTION
In addition to the detection of the loss of the line voltage signal
(zero crossing), the ADE7753 can also be programmed to detect
when the absolute value of the line voltage drops below a
certain peak value for a number of line cycles. This condition is
illustrated in Figure 43.
Rev. C | Page 19 of 60
ADE7753
V2
CHANNEL 2
FULL SCALE
VPKLVL[7:0]
SAGLVL [7:0]
PKV RESET LOW
WHEN RSTSTATUS
REGISTER IS READ
SAG RESET HIGH
WHEN CHANNEL 2
EXCEEDS SAGLVL [7:0]
SAGCYC [7:0] = 0x04
3 LINE CYCLES
PKV INTERRUPT
FLAG (BIT 8 OF
STATUS REGISTER)
SAG
02875-0-043
READ RSTSTATUS
REGISTER
Figure 43. ADE7753 Sag Detection
Figure 43 shows the line voltage falling below a threshold that is
set in the sag level register (SAGLVL[7:0]) for three line cycles.
The quantities 0 and 1 are not valid for the SAGCYC register,
and the contents represent one more than the desired number
of full line cycles. For example, when the sag cycle (SAGCYC[7:0])
contains 0x04, the SAG pin goes active low at the end of the
third line cycle for which the line voltage (Channel 2 signal)
falls below the threshold, if the DISSAG bit in the mode register
is Logic 0. As is the case when zero crossings are no longer
detected, the sag event is also recorded by setting the SAG flag
in the interrupt status register. If the SAG enable bit is set to
Logic 1, the IRQ logic output goes active low—see the ADE7753
Interrupts section. The SAG pin goes logic high again when the
absolute value of the signal on Channel 2 exceeds the sag level
set in the sag level register. This is shown in Figure 43 when the
SAG pin goes high again during the fifth line cycle from the
time when the signal on Channel 2 first dropped below the
threshold level.
Sag Level Set
The contents of the sag level register (1 byte) are compared to
the absolute value of the most significant byte output from LPF1
after it is shifted left by one bit, thus, for example, the nominal
maximum code from LPF1 with a full-scale signal on Channel 2
is 0x2518—see the Channel 2 Sampling section. Shifting one bit
left gives 0x4A30. Therefore writing 0x4A to the SAG level
register puts the sag detection level at full scale. Writing 0x00 or
0x01 puts the sag detection level at 0. The SAG level register is
compared to the most significant byte of a waveform sample
after the shift left and detection is made when the contents of
the sag level register are greater.
PEAK DETECTION
The ADE7753 can also be programmed to detect when the
absolute value of the voltage or current channel exceeds a
specified peak value. Figure 44 illustrates the behavior of the
peak detection for the voltage channel. Both Channel 1 and
Channel 2 are monitored at the same time.
02875-0-088
Figure 44. ADE7753 Peak Level Detection
Figure 44 shows a line voltage exceeding a threshold that is set
in the voltage peak register (VPKLVL[7:0]). The voltage peak
event is recorded by setting the PKV flag in the interrupt status
register. If the PKV enable bit is set to Logic 1 in the interrupt
mask register, the IRQ logic output goes active low. Similarly,
the current peak event is recorded by setting the PKI flag in the
interrupt status register—see the ADE7753 Interrupts section.
Peak Level Set
The contents of the VPKLVL and IPKLVL registers are
respectively compared to the absolute value of Channel 1 and
Channel 2 after they are multiplied by 2. Thus, for example, the
nominal maximum code from the Channel 1 ADC with a fullscale signal is 0x2851EC—see the Channel 1 Sampling section.
Multiplying by 2 gives 0x50A3D8. Therefore, writing 0x50 to
the IPKLVL register, for example, puts the Channel 1 peak
detection level at full scale and sets the current peak detection
to its least sensitive value. Writing 0x00 puts the Channel 1
detection level at 0. The detection is done by comparing the
contents of the IPKLVL register to the incoming Channel 1
sample. The IRQ pin indicates that the peak level is exceeded if
the PKI or PKV bits are set in the interrupt enable register
(IRQEN[15:0]) at Address 0x0A.
Peak Level Record
The ADE7753 records the maximum absolute value reached by
Channel 1 and Channel 2 in two different registers—IPEAK
and VPEAK, respectively. VPEAK and IPEAK are 24-bit
unsigned registers. These registers are updated each time the
absolute value of the waveform sample from the corresponding
channel is above the value stored in the VPEAK or IPEAK
register. The contents of the VPEAK register correspond to 2×
the maximum absolute value observed on the Channel 2 input.
The contents of IPEAK represent the maximum absolute value
observed on the Channel 1 input. Reading the RSTVPEAK and
RSTIPEAK registers clears their respective contents after the read
operation.
Rev. C | Page 20 of 60
ADE7753
ADE7753 INTERRUPTS
Using the ADE7753 Interrupts with an MCU
ADE7753 interrupts are managed through the interrupt status
register (STATUS[15:0]) and the interrupt enable register
(IRQEN[15:0]). When an interrupt event occurs in the ADE7753,
the corresponding flag in the status register is set to Logic 1—
see the Interrupt Status Register section. If the enable bit for this
interrupt in the interrupt enable register is Logic 1, then the
IRQ logic output goes active low. The flag bits in the status
register are set irrespective of the state of the enable bits.
Figure 46 shows a timing diagram with a suggested implementation of ADE7753 interrupt management using an MCU. At
time t1, the IRQ line goes active low indicating that one or more
interrupt events have occurred in the ADE7753. The IRQ logic
output should be tied to a negative edge-triggered external
interrupt on the MCU. On detection of the negative edge, the
MCU should be configured to start executing its interrupt
service routine (ISR). On entering the ISR, all interrupts should
be disabled by using the global interrupt enable bit. At this
point, the MCU external interrupt flag can be cleared to capture
interrupt events that occur during the current ISR. When the
MCU interrupt flag is cleared, a read from the status register
with reset is carried out. This causes the IRQ line to be reset
logic high (t2)—see the Interrupt Timing section. The status
register contents are used to determine the source of the
interrupt(s) and therefore the appropriate action to be taken. If
a subsequent interrupt event occurs during the ISR, that event is
recorded by the MCU external interrupt flag being set again
(t3). On returning from the ISR, the global interrupt mask is
cleared (same instruction cycle), and the external interrupt flag
causes the MCU to jump to its ISR once a gain. This ensures
that the MCU does not miss any external interrupts.
To determine the source of the interrupt, the system master
(MCU) should perform a read from the status register with
reset (RSTSTATUS[15:0]). This is achieved by carrying out a
read from Address 0x0C. The IRQ output goes logic high on
completion of the interrupt status register read command—see
the Interrupt Timing section. When carrying out a read with
reset, the ADE7753 is designed to ensure that no interrupt
events are missed. If an interrupt event occurs just as the status
register is being read, the event is not lost and the IRQ logic
output is guaranteed to go high for the duration of the interrupt
status register data transfer before going logic low again to
indicate the pending interrupt. See the next section for a more
detailed description.
t1
t2
MCU
INTERRUPT
FLAG SET
t3
IRQ
MCU
PROGRAM
SEQUENCE
JUMP
TO
ISR
GLOBAL
INTERRUPT
MASK SET
CLEAR MCU
INTERRUPT
FLAG
READ
STATUS WITH
RESET (0x05)
ISR RETURN
GLOBAL INTERRUPT
MASK RESET
ISR ACTION
(BASED ON STATUS CONTENTS)
JUMP
TO
ISR
02875-0-044
Figure 45. ADE7753 Interrupt Management
CS
t1
t9
SCLK
DIN
0
0
0
0
0
1
0
1
t11
t11
DB7
DOUT
DB0 DB7
DB0
READ STATUS REGISTER COMMAND
STATUS REGISTER CONTENTS
IRQ
02875-0-045
Figure 46. ADE7753 Interrupt Timing
Rev. C | Page 21 of 60
ADE7753
Interrupt Timing
The ADE7753 Serial Interface section should be reviewed first
before reviewing the interrupt timing. As previously described,
when the IRQ output goes low, the MCU ISR must read the
interrupt status register to determine the source of the interrupt.
When reading the status register contents, the IRQ output is set
high on the last falling edge of SCLK of the first byte transfer
(read interrupt status register command). The IRQ output is
held high until the last bit of the next 15-bit transfer is shifted
out (interrupt status register contents)—see Figure 45. If an
interrupt is pending at this time, the IRQ output goes low again.
If no interrupt is pending, the IRQ output stays high.
TEMPERATURE MEASUREMENT
The ADE7753 also includes an on-chip temperature sensor. A
temperature measurement can be made by setting Bit 5 in the
mode register. When Bit 5 is set logic high in the mode register,
the ADE7753 initiates a temperature measurement on the next
zero crossing. When the zero crossing on Channel 2 is detected,
the voltage output from the temperature sensing circuit is
connected to ADC1 (Channel 1) for digitizing. The resulting
code is processed and placed in the temperature register
(TEMP[7:0]) approximately 26 μs later (96/CLKIN seconds). If
enabled in the interrupt enable register (Bit 5), the IRQ output
goes active low when the temperature conversion is finished.
The contents of the temperature register are signed (twos
complement) with a resolution of approximately 1.5 LSB/°C.
The temperature register produces a code of 0x00 when the
ambient temperature is approximately −25°C. The temperature
measurement is uncalibrated in the ADE7753 and has an offset
tolerance as high as ±25°C.
ADE7753 ANALOG-TO-DIGITAL CONVERSION
The analog-to-digital conversion in the ADE7753 is carried out
using two second-order Σ-Δ ADCs. For simplicity, the block
diagram in Figure 47 shows a first-order Σ-Δ ADC. The converter
is made up of the Σ-Δ modulator and the digital low-pass filter.
INTEGRATOR
+
R
C
+
–
The Σ-Δ converter uses two techniques to achieve high resolution
from what is essentially a 1-bit conversion technique. The first
is oversampling. Oversampling means that the signal is sampled
at a rate (frequency), which is many times higher than the
bandwidth of interest. For example, the sampling rate in the
ADE7753 is CLKIN/4 (894 kHz) and the band of interest is
40 Hz to 2 kHz. Oversampling has the effect of spreading the
quantization noise (noise due to sampling) over a wider
bandwidth. With the noise spread more thinly over a wider
bandwidth, the quantization noise in the band of interest is
lowered—see Figure 48. However, oversampling alone is not
efficient enough to improve the signal-to-noise ratio (SNR) in
the band of interest. For example, an oversampling ratio of 4 is
required just to increase the SNR by only 6 dB (1 bit). To keep
the oversampling ratio at a reasonable level, it is possible to
shape the quantization noise so that the majority of the noise
lies at the higher frequencies. In the Σ-Δ modulator, the noise is
shaped by the integrator, which has a high-pass-type response
for the quantization noise. The result is that most of the noise is
at the higher frequencies where it can be removed by the digital
low-pass filter. This noise shaping is shown in Figure 48.
DIGITAL
FILTER
SIGNAL
MCLK/4
ANALOG
LOW-PASS FILTER
A Σ-Δ modulator converts the input signal into a continuous
serial stream of 1s and 0s at a rate determined by the sampling
clock. In the ADE7753, the sampling clock is equal to CLKIN/4.
The 1-bit DAC in the feedback loop is driven by the serial data
stream. The DAC output is subtracted from the input signal. If
the loop gain is high enough, the average value of the DAC output (and therefore the bit stream) can approach that of the input
signal level. For any given input value in a single sampling interval,
the data from the 1-bit ADC is virtually meaningless. Only when
a large number of samples are averaged is a meaningful result
obtained. This averaging is carried out in the second part of the
ADC, the digital low-pass filter. By averaging a large number of
bits from the modulator, the low-pass filter can produce 24-bit
data-words that are proportional to the input signal level.
LATCHED
COMPARATOR
DIGITAL
LOW-PASS
FILTER
ANTILALIAS
FILTER (RC)
SAMPLING
FREQUENCY
SHAPED
NOISE
NOISE
24
–
0
VREF
.....10100101.....
447
FREQUENCY (kHz)
894
HIGH RESOLUTION
OUTPUT FROM DIGITAL
LPF
SIGNAL
1-BIT DAC
2
02875-0-046
Figure 47. First-Order Σ-∆ ADC
NOISE
0
2
447
FREQUENCY (kHz)
894
Figure 48. Noise Reduction Due to Oversampling and
Noise Shaping in the Analog Modulator
Rev. C | Page 22 of 60
02875-0-047
ADE7753
Antialias Filter
ADE7753 Reference Circuit
Figure 47 also shows an analog low-pass filter (RC) on the input
to the modulator. This filter is present to prevent aliasing.
Aliasing is an artifact of all sampled systems. Aliasing means
that frequency components in the input signal to the ADC,
which are higher than half the sampling rate of the ADC,
appear in the sampled signal at a frequency below half the
sampling rate. Figure 49 illustrates the effect. Frequency
components (arrows shown in black) above half the sampling
frequency (also know as the Nyquist frequency, i.e., 447 kHz)
are imaged or folded back down below 447 kHz. This happens
with all ADCs regardless of the architecture. In the example
shown, only frequencies near the sampling frequency, i.e.,
894 kHz, move into the band of interest for metering, i.e., 40 Hz
to 2 kHz. This allows the use of a very simple LPF (low-pass
filter) to attenuate high frequency (near 900 kHz) noise, and
prevents distortion in the band of interest. For conventional
current sensors, a simple RC filter (single-pole LPF) with a
corner frequency of 10 kHz produces an attenuation of
approximately 40 dB at 894 kHz—see Figure 49. The 20 dB per
decade attenuation is usually sufficient to eliminate the effects
of aliasing for conventional current sensors. However, for a
di/dt sensor such as a Rogowski coil, the sensor has a 20 dB per
decade gain. This neutralizes the –20 dB per decade attenuation
produced by one simple LPF. Therefore, when using a di/dt
sensor, care should be taken to offset the 20 dB per decade gain.
One simple approach is to cascade two RC filters to produce the
–40 dB per decade attenuation needed.
Figure 50 shows a simplified version of the reference output
circuitry. The nominal reference voltage at the REFIN/OUT pin is
2.42 V. This is the reference voltage used for the ADCs in the
ADE7753. However, Channel 1 has three input range selections
that are selected by dividing down the reference value used for
the ADC in Channel 1. The reference value used for Channel 1
is divided down to ½ and ¼ of the nominal value by using an
internal resistor divider, as shown in Figure 50.
ALIASING EFFECTS
SAMPLING
FREQUENCY
IMAGE
FREQUENCIES
0
2
447
894
FREQUENCY (kHz)
02875-0-048
Figure 49. ADC and Signal Processing in Channel 1 Outline Dimensions
ADC Transfer Function
The following expression relates the output of the LPF in the
Σ-Δ ADC to the analog input signal level. Both ADCs in the
ADE7753 are designed to produce the same output code for the
same input signal level.
Code ( ADC) = 3.0492 ×
V IN
× 262,144
VOUT
(1)
Therefore with a full-scale signal on the input of 0.5 V and an
internal reference of 2.42 V, the ADC output code is nominally
165,151 or 2851Fh. The maximum code from the ADC is
±262,144; this is equivalent to an input signal level of ±0.794 V.
However, for specified performance, it is recommended that the
full-scale input signal level of 0.5 V not be exceeded.
MAXIMUM
LOAD = 10μA
PTAT
OUTPUT
IMPEDANCE
6kΩ
REFIN/OUT
2.42V
60μA
1.7kΩ
2.5V
12.5kΩ
12.5kΩ
12.5kΩ
12.5kΩ
REFERENCE INPUT
TO ADC CHANNEL 1
(RANGE SELECT)
2.42V, 1.21V, 0.6V
02875-0-049
Figure 50. ADE7753 Reference Circuit Output
The REFIN/OUT pin can be overdriven by an external source, for
example, an external 2.5 V reference. Note that the nominal
reference value supplied to the ADCs is now 2.5 V, not 2.42 V,
which has the effect of increasing the nominal analog input
signal range by 2.5/2.42 × 100% = 3% or from 0.5 V to 0.5165 V.
The voltage of the ADE7753 reference drifts slightly with
temperature—see the ADE7753 Specifications for the temperature
coefficient specification (in ppm/°C). The value of the temperature
drift varies from part to part. Since the reference is used for the
ADCs in both Channels 1 and 2, any x% drift in the reference
results in 2×% deviation of the meter accuracy. The reference
drift resulting from temperature changes is usually very small
and it is typically much smaller than the drift of other components
on a meter. However, if guaranteed temperature performance
is needed, one needs to use an external voltage reference.
Alternatively, the meter can be calibrated at multiple temperatures.
Real-time compensation can be achieved easily by using the
on-chip temperature sensor.
CHANNEL 1 ADC
Figure 51 shows the ADC and signal processing chain for
Channel 1. In waveform sampling mode, the ADC outputs a
signed twos complement 24-bit data-word at a maximum of
27.9 kSPS (CLKIN/128). With the specified full-scale analog
input signal of 0.5 V (or 0.25 V or 0.125 V—see the Analog
Inputs section) the ADC produces an output code that is
approximately between 0x2851EC (+2,642,412d) and
0xD7AE14 (–2,642,412d)—see Figure 51.
Rev. C | Page 23 of 60
ADE7753
2.42V, 1.21V, 0.6V
⋅ 1, ⋅ 2, ⋅ 4,
REFERENCE
⋅ 8, ⋅ 16
{GAIN[2:0]}
V1P
{GAIN[4:3]}
HPF
DIGITAL
INTEGRATOR*
ADC 1
PGA1
V1
CURRENT RMS (IRMS)
CALCULATION
WAVEFORM SAMPLE
REGISTER
ACTIVE AND REACTIVE
POWER CALCULATION
dt
V1N
CHANNEL 1
(CURRENT WAVEFORM)
DATA RANGE AFTER
INTEGRATOR (50Hz)
50Hz
0.5V, 0.25V,
0.125V, 62.5mV,
31.3mV, 15.6mV,
0x1EF73C
V1
0x2851EC
0V
CHANNEL 1
(CURRENT WAVEFORM)
DATA RANGE
0x00000
0x000000
0xEI08C4
0x2851EC
0xD7AE14
ANALOG
INPUT
RANGE
ADC OUTPUT
WORD RANGE
0x000000
CHANNEL 1
(CURRENT WAVEFORM)
DATA RANGE AFTER
INTEGRATOR (60Hz)
60Hz
0xD7AE14
0x19CE08
0x000000
*WHEN DIGITAL INTEGRATOR IS ENABLED, FULL-SCALE OUTPUT DATA IS ATTENUATED
0xE631F8
DEPENDING ON THE SIGNAL FREQUENCY BECAUSE THE INTEGRATOR HAS A –20dB/DECADE
FREQUENCY RESPONSE. WHEN DISABLED, THE OUTPUT WILL NOT BE FURTHER ATTENUATED.
02875-0-052
Figure 51. ADC and Signal Processing in Channel 1
Channel 1 Sampling
Channel 1 RMS Calculation
The waveform samples can also be routed to the waveform
register (MODE[14:13] = 1,0) to be read by the system master
(MCU). In waveform sampling mode, the WSMP bit (Bit 3) in
the interrupt enable register must also be set to Logic 1. The
active, apparent power, and energy calculation remain
uninterrupted during waveform sampling.
Root mean square (rms) value of a continuous signal V(t) is
defined as
When in waveform sampling mode, one of four output sample
rates can be chosen by using Bits 11 and 12 of the mode register
(WAVSEL1,0). The output sample rate can be 27.9 kSPS, 14 kSPS,
7 kSPS, or 3.5 kSPS—see the Mode Register (0x09) section. The
interrupt request output, IRQ, signals a new sample availability
by going active low. The timing is shown in Figure 52. The 24-bit
waveform samples are transferred from the ADE7753 one byte
(eight bits) at a time, with the most significant byte shifted out
first. The 24-bit data-word is right justified—see the ADE7753
Serial Interface section. The interrupt request output IRQ stays
low until the interrupt routine reads the reset status register—
see the ADE7753 Interrupts section.
For time sampling signals, rms calculation involves squaring the
signal, taking the average and obtaining the square root:
IRQ
SCLK
DIN
DOUT
T
VRMS = Vrms =
(2)
0
VRMS = Vrms =
1
×
N
N
∑V
2
(i )
(3)
i =1
The ADE7753 simultaneously calculates the rms values for
Channel 1 and Channel 2 in different registers. Figure 53 shows
the detail of the signal processing chain for the rms calculation
on Channel 1. The Channel 1 rms value is processed from the
samples used in the Channel 1 waveform sampling mode. The
Channel 1 rms value is stored in an unsigned 24-bit register
(IRMS). One LSB of the Channel 1 rms register is equivalent to
one LSB of a Channel 1 waveform sample. The update rate of
the Channel 1 rms measurement is CLKIN/4.
READ FROM WAVEFORM
0 0 0 01 HEX
SIGN
CHANNEL 1 DATA
(24 BITS)
∫
1
× V 2 (t ) dt
T
02875-0-050
Figure 52. Waveform Sampling Channel 1
Rev. C | Page 24 of 60
ADE7753
CURRENT SIGNAL (i(t))
0x2851EC
IRMSOS[11:0]
IRMS(t)
0x00
0xD7AE14
HPF1
CHANNEL 1
217 216 215 0x1C82B3
0x00
sgn 225 226 227
LPF3
+
24
24
IRMS
02875-0-0051
Figure 53. Channel 1 RMS Signal Processing
CHANNEL 2 ADC
Channel 2 Sampling
In Channel 2 waveform sampling mode (MODE[14:13] = 1,1
and WSMP = 1), the ADC output code scaling for Channel 2 is
not the same as Channel 1. The Channel 2 waveform sample is a
16-bit word and sign extended to 24 bits. For normal operation,
the differential voltage signal between V2P and V2N should not
exceed 0.5 V. With maximum voltage input (±0.5 V at PGA gain
of 1), the output from the ADC swings between 0x2852 and
0xD7AE (±10,322d). However, before being passed to the waveform register, the ADC output is passed through a single-pole,
low-pass filter with a cutoff frequency of 140 Hz. The plots in
Figure 54 show the magnitude and phase response of this filter.
0
Table 7.
100%
895 ms
1340 ms
One LSB of the Channel 1 rms offset is equivalent to 32,768 LSB
of the square of the Channel 1 rms register. Assuming that the
maximum value from the Channel 1 rms calculation is
1,868,467d with full-scale ac inputs, then 1 LSB of the Channel 1
rms offset represents 0.46% of measurement error at –60 dB
down of full scale.
IRMS0 2 + IRMSOS × 32768
–4
50Hz, –19.7°
The ADE7753 incorporates a Channel 1 rms offset compensation register (IRMSOS). This is a 12-bit signed register that can
be used to remove offset in the Channel 1 rms calculation. An
offset could exist in the rms calculation due to input noises that
are integrated in the dc component of V2(t). The offset calibration
allows the content of the IRMS register to match the theoretical
value even when the Channel 1 input is low.
–6
–30
60Hz, –23.2°
–40
–8
–50
–10
–60
–12
–70
–14
–80
–16
–90
101
102
FREQUENCY (Hz)
–18
103
02875-0-053
Figure 54. Magnitude and Phase Response of LPF1
The LPF1 has the effect of attenuating the signal. For example,
if the line frequency is 60 Hz, then the signal at the output of
LPF1 is attenuated by about 8%.
H( f ) =
1
⎛ 60 Hz ⎞
⎟⎟
1 + ⎜⎜
⎝ 140 Hz ⎠
(4)
where IRMS0 is the rms measurement without offset correction.
To measure the offset of the rms measurement, two data points
are needed from non-zero input values, for example, the base
current, Ib, and Imax/100. The offset can be calculated from these
measurements.
0
–2
–20
Channel 1 RMS Offset Compensation
IRMS =
50Hz, –0.52dB
–10
95%
219 ms
78.5 ms
PHASE (Degrees)
Integrator Off
Integrator On
60Hz, –0.73dB
GAIN (dB)
With the specified full-scale analog input signal of 0.5 V, the
ADC produces an output code that is approximately
±2,642,412d—see the Channel 1 ADC section. The equivalent
rms value of a full-scale ac signal are 1,868,467d (0x1C82B3).
The current rms measurement provided in the ADE7753 is
accurate to within 0.5% for signal input between full scale and
full scale/100. Table 7 shows the settling time for the IRMS
measurement, which is the time it takes for the rms register to
reflect the value at the input to the current channel. The
conversion from the register value to amps must be done
externally in the microprocessor using an amps/LSB constant. To
minimize noise, synchronize the reading of the rms register
with the zero crossing of the voltage input and take the average
of a number of readings.
2
= 0.919 = −0.73 dB
(5)
Note LPF1 does not affect the active power calculation. The
signal processing chain in Channel 2 is illustrated in Figure 55.
Rev. C | Page 25 of 60
ADE7753
2.42V
×1, ×2, ×4,
REFERENCE
×8, ×16
{GAIN [7:5]}
V2P
PGA2
V2
ACTIVE AND REACTIVE
ENERGY CALCULATION
ADC 2
LPF1
V2N
ANALOG
V1
INPUT RANGE
0.5V, 0.25, 0.125,
62.5mV, 31.25mV
0V
0x2852
0x2581
VRMS CALCULATION
AND WAVEFORM
SAMPLING
(PEAK/SAG/ZX)
LPF OUTPUT
WORD RANGE
0x0000
0xDAE8
0xD7AE
02875-0-054
Figure 55. ADC and Signal Processing in Channel 2
VOLTAGE SIGNAL (V(t))
0x2518
VRMOS[11:0]
0x0
sgn 29 28
22 21 20
0xDAE8
LPF1
CHANNEL 2
VRMS[23:0]
0x17D338
LPF3
+
|x|
+
0x00
02875-0-0055
Figure 56. Channel 2 RMS Signal Processing
Channel 2 has only one analog input range (0.5 V differential).
Like Channel 1, Channel 2 has a PGA with gain selections of 1,
2, 4, 8, and 16. For energy measurement, the output of the ADC
is passed directly to the multiplier and is not filtered. An HPF is
not required to remove any dc offset since it is only required to
remove the offset from one channel to eliminate errors due to
offsets in the power calculation. When in waveform sampling
mode, one of four output sample rates can be chosen by using
Bits 11 and 12 of the mode register. The available output sample
rates are 27.9 kSPS, 14 kSPS, 7 kSPS, or 3.5 kSPS—see the Mode
Register (0x09) section. The interrupt request output IRQ
signals that a sample is available by going active low. The timing
is the same as that for Channel 1, as shown in Figure 52.
Channel 2 RMS Calculation
Figure 56 shows the details of the signal processing chain for the
rms estimation on Channel 2. This Channel 2 rms estimation is
done in the ADE7753 using the mean absolute value calculation, as
shown in Figure 56. The Channel 2 rms value is processed from
the samples used in the Channel 2 waveform sampling mode.
The rms value is slightly attenuated because of LPF1. Channel 2
rms value is stored in the unsigned 24-bit VRMS register. The
update rate of the Channel 2 rms measurement is CLKIN/4.
With the specified full-scale ac analog input signal of 0.5 V, the
output from the LPF1 swings between 0x2518 and 0xDAE8 at
60 Hz—see the Channel 2 ADC section. The equivalent rms
value of this full-scale ac signal is approximately 1,561,400
(0x17D338) in the VRMS register. The voltage rms measurement provided in the ADE7753 is accurate to within ±0.5% for
signal input between full scale and full scale/20. Table 8 shows
the settling time for the VRMS measurement, which is the time
it takes for the rms register to reflect the value at the input to
the voltage channel. The conversion from the register value to
volts must be done externally in the microprocessor using a
volts/LSB constant. Since the low-pass filtering used for
calculating the rms value is imperfect, there is some ripple noise
from 2ω term present in the rms measurement. To minimize
the noise effect in the reading, synchronize the rms reading
with the zero crossings of the voltage input.
Table 8.
95%
220 ms
100%
670 ms
Channel 2 RMS Offset Compensation
The ADE7753 incorporates a Channel 2 rms offset compensation
register (VRMSOS). This is a 12-bit signed register that can be
used to remove offset in the Channel 2 rms calculation. An
offset could exist in the rms calculation due to input noises and
dc offset in the input samples. The offset calibration allows the
contents of the VRMS register to be maintained at 0 when no
voltage is applied. One LSB of the Channel 2 rms offset is
equivalent to one LSB of the rms register. Assuming that the
maximum value from the Channel 2 rms calculation is
1,561,400d with full-scale ac inputs, then one LSB of the
Channel 2 rms offset represents 0.064% of measurement
error at –60 dB down of full scale.
VRMS = VRMS0 + VRMSOS
(6)
where VRMS0 is the rms measurement without offset correction.
The voltage rms offset compensation should be done by testing
the rms results at two non-zero input levels. One measurement
can be done close to full scale and the other at approximately
full scale/10. The voltage offset compensation can be derived
Rev. C | Page 26 of 60
ADE7753
from these measurements. If the voltage rms offset register does
not have enough range, the CH2OS register can also be used.
V1P
HPF
24
PGA1
V1
ADC 1
V1N
PHASE COMPENSATION
LPF2
24
V2P
1
PGA2
V2
DELAY BLOCK
2.24µs/LSB
ADC 2
V2N
5
Rev. C | Page 27 of 60
CHANNEL 2 DELAY
REDUCED BY 4.48µs
(0.1°LEAD AT 60Hz)
0Bh IN PHCAL [5.0]
V2
V1
PHCAL [5:0]
--100µs TO +34µs
0.1°
V1
60Hz
60Hz
02875-0-056
Figure 57. Phase Calibration
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
The phase calibration register (PHCAL[5:0]) is a twos complement signed single-byte register that has values ranging from
0x21 (–31d) to 0x1F (31d).
–0.1
102
103
FREQUENCY (Hz)
104
02875-0-057
Figure 58. Combined Phase Response of the HPF and
Phase Compensation (10 Hz to 1 kHz)
0.20
0.18
0.16
0.14
PHASE (Degrees)
The register is centered at 0x0D, so that writing 0x0D to the
register gives 0 delay. By changing the PHCAL register, the time
delay in the Channel 2 signal path can change from –102.12 μs
to +39.96 μs (CLKIN = 3.579545 MHz). One LSB is equivalent
to 2.22 μs (CLKIN/8) time delay or advance. A line frequency of
60 Hz gives a phase resolution of 0.048° at the fundamental (i.e.,
360° × 2.22 μs × 60 Hz). Figure 57 illustrates how the phase
compensation is used to remove a 0.1° phase lead in Channel 1
due to the external transducer. To cancel the lead (0.1°) in
Channel 1, a phase lead must also be introduced into Channel 2.
The resolution of the phase adjustment allows the introduction
of a phase lead in increment of 0.048°. The phase lead is achieved
by introducing a time advance into Channel 2. A time advance
of 4.48 μs is made by writing −2 (0x0B) to the time delay block,
thus reducing the amount of time delay by 4.48 μs, or equivalently, a phase lead of approximately 0.1° at line frequency of 60 Hz.
0x0B represents –2 because the register is centered with 0 at 0x0D.
0
0 0 1 0 1 1
V2
PHASE (Degrees)
When the HPF is disabled, the phase error between Channel 1
and Channel 2 is 0 from dc to 3.5 kHz. When HPF is enabled,
Channel 1 has the phase response illustrated in Figure 58 and
Figure 59. Also shown in Figure 60 is the magnitude response of
the filter. As can be seen from the plots, the phase response is
almost 0 from 45 Hz to 1 kHz. This is all that is required in
typical energy measurement applications. However, despite
being internally phase compensated, the ADE7753 must work
with transducers, which could have inherent phase errors. For
example, a phase error of 0.1° to 0.3° is not uncommon for a
current transformer (CT). These phase errors can vary from
part to part, and they must be corrected in order to perform
accurate power calculations. The errors associated with phase
mismatch are particularly noticeable at low power factors. The
ADE7753 provides a means of digitally calibrating these small
phase errors. The ADE7753 allows a small time delay or time
advance to be introduced into the signal processing chain to
compensate for small phase errors. Because the compensation is
in time, this technique should be used only for small phase
errors in the range of 0.1° to 0.5°. Correcting large phase errors
using a time shift technique can introduce significant phase
errors at higher harmonics.
0.12
0.10
0.08
0.06
0.04
0.02
0
40
45
50
55
60
FREQUENCY (Hz)
65
70
02875-0-058
Figure 59. Combined Phase Response of the HPF and
Phase Compensation (40 Hz to 70 Hz)
ADE7753
0.4
the current and voltage signals. The dc component of the
instantaneous power signal is then extracted by LPF2 (low-pass
filter) to obtain the active power information. This process is
illustrated in Figure 61.
0.3
ERROR (%)
0.2
INSTANTANEOUS
POWER SIGNAL
0.1
p(t) = v×i-v×i×cos(2ωt)
0x19999A
0.0
ACTIVE REAL POWER
SIGNAL = v × i
–0.1
–0.2
VI
0xCCCCD
–0.3
–0.4
54
56
58
60
62
FREQUENCY (Hz)
64
66
0x00000
02875-0-059
CURRENT
i(t) = 2×i×sin(ωt)
Figure 60. Combined Gain Response of the HPF and Phase Compensation
ACTIVE POWER CALCULATION
Power is defined as the rate of energy flow from source to load.
It is defined as the product of the voltage and current waveforms. The resulting waveform is called the instantaneous
power signal and is equal to the rate of energy flow at every
instant of time. The unit of power is the watt or joules/sec.
Equation 9 gives an expression for the instantaneous power
signal in an ac system.
v(t) =
2 × V sin(ωt )
(7)
i(t) =
2 × I sin(ωt )
(8)
VOLTAGE
v(t) = 2×v×sin(ωt)
02875-0-060
Figure 61. Active Power Calculation
Since LPF2 does not have an ideal “brick wall” frequency
response—see Figure 62, the active power signal has some
ripple due to the instantaneous power signal. This ripple is
sinusoidal and has a frequency equal to twice the line frequency.
Because the ripple is sinusoidal in nature, it is removed when
the active power signal is integrated to calculate energy—see the
Energy Calculation section.
0
where:
V is the rms voltage.
I is the rms current.
–8
(9)
The average power over an integral number of line cycles (n) is
given by the expression in Equation 10.
P=
1
nT
nT
∫0
dB
p (t ) = v (t ) × i (t )
p(t ) = VI − VI cos(2ωt )
–4
–12
–16
p(t )dt = VI
(10)
–20
where:
T is the line cycle period.
P is referred to as the active or real power.
–24
1
Note that the active power is equal to the dc component of the
instantaneous power signal p(t) in Equation 8, i.e., VI. This is
the relationship used to calculate active power in the ADE7753.
The instantaneous power signal p(t) is generated by multiplying
Rev. C | Page 28 of 60
3
10
FREQUENCY (Hz)
30
Figure 62. Frequency Response of LPF2
100
02875-0-061
ADE7753
APOS[15:0]
CURRENT
CHANNEL
WDIV[7:0]
AENERGY [23:0]
LPF2
+
23
+
VOLTAGE
CHANNEL
0
UPPER 24 BITS ARE
ACCESSIBLE THROUGH
AENERGY[23:0] REGISTER
%
WGAIN[11:0]
48
0
ACTIVE POWER
SIGNAL
4
CLKIN
WAVEFORM
REGISTER
VALUES
OUTPUT LPF2
T
OUTPUTS FROM THE LPF2 ARE
ACCUMULATED (INTEGRATED) IN
THE INTERNAL ACTIVE ENERGY REGISTER
TIME (nT)
02875-0-063
Figure 63. ADE7753 Active Energy Calculation
⎛
⎧ WGAIN ⎫ ⎞
Output WGAIN = ⎜⎜ Active Power × ⎨1 +
⎬ ⎟⎟
212 ⎭ ⎠
⎩
⎝
ACTIVE POWER OUTPUT
Figure 63 shows the signal processing chain for the active power
calculation in the ADE7753. As explained, the active power is
calculated by low-pass filtering the instantaneous power signal.
Note that when reading the waveform samples from the output
of LPF2, the gain of the active energy can be adjusted by using
the multiplier and watt gain register (WGAIN[11:0]). The gain
is adjusted by writing a twos complement 12-bit word to the
watt gain register. Equation 11 shows how the gain adjustment
is related to the contents of the watt gain register:
0x133333
POSITIVE
POWER
0xCCCCD
0x66666
0x00000
0xF9999A
NEGATIVE
POWER
0xF33333
0xECCCCD
0x000
0x7FF
0x800
{WGAIN[11:0]}
ACTIVE POWER
CALIBRATION RANGE
(11)
02875-0-062
Figure 64. Active Power Calculation Output Range
For example, when 0x7FF is written to the watt gain register, the
power output is scaled up by 50%. 0x7FF = 2047d, 2047/212 =
0.5. Similarly, 0x800 = –2048d (signed twos complement) and
power output is scaled by –50%. Each LSB scales the power output
by 0.0244%. Figure 64 shows the maximum code (in hex) output
range for the active power signal (LPF2). Note that the output
range changes depending on the contents of the watt gain register.
The minimum output range is given when the watt gain register
contents are equal to 0x800, and the maximum range is given by
writing 0x7FF to the watt gain register. This can be used to
calibrate the active power (or energy) calculation in the ADE7753.
ENERGY CALCULATION
As stated earlier, power is defined as the rate of energy flow.
This relationship can be expressed mathematically in Equation 12.
P=
dE
dt
(12)
where:
P is power.
E is energy.
Conversely, energy is given as the integral of power.
∫
E = Pdt
Rev. C | Page 29 of 60
(13)
ADE7753
APOS [15:0]
HPF
sgn 26 25
I
CURRENT SIGNAL – i(t)
LPF2
24
+
FOR WAVEF0RM
SAMPLING
24
2-6 2-7 2-8
0x19999
+
32
FOR WAVEFORM
ACCUMULATIOIN
MULTIPLIER
1
V
VOLTAGE SIGNAL– v(t)
INSTANTANEOUS
POWER SIGNAL – p(t)
0xCCCCD
WGAIN[11:0]
0x19999A
0x000000
02875-0-064
Figure 65. Active Power Signal Processing
The ADE7753 achieves the integration of the active power signal by
continuously accumulating the active power signal in an internal
nonreadable 49-bit energy register. The active energy register
(AENERGY[23:0]) represents the upper 24 bits of this internal
register. This discrete time accumulation or summation is
equivalent to integration in continuous time. Equation 14
expresses the relationship.
⎧∞
⎫
E = ∫ p(t )dt = Lim⎨∑ p(nT ) × T ⎬
t →0 ⎩n =1
⎭
Figure 66 shows this energy accumulation for full-scale signals
(sinusoidal) on the analog inputs. The three curves displayed
illustrate the minimum period of time it takes the energy register
to roll over when the active power gain register contents are
0x7FF, 0x000, and 0x800. The watt gain register is used to carry
out power calibration in the ADE7753. As shown, the fastest
integration time occurs when the watt gain register is set to
maximum full scale, i.e., 0x7FF.
(14)
AENERGY [23:0]
0x7F,FFFF
where:
n is the discrete time sample number.
T is the sample period.
WGAIN = 0x7FF
WGAIN = 0x000
WGAIN = 0x800
0x3F,FFFF
The discrete time sample period (T) for the accumulation
register in the ADE7753 is 1.1μs (4/CLKIN). As well as
calculating the energy, this integration removes any sinusoidal
components that might be in the active power signal. Figure 65
shows this discrete time integration or accumulation. The active
power signal in the waveform register is continuously added to
the internal active energy register. This addition is a signed
addition; therefore negative energy is subtracted from the active
energy contents. The exception to this is when POAM is
selected in the MODE[15:0] register. In this case, only positive
energy contributes to the active energy accumulation—see the
Positive-Only Accumulation Mode section.
The output of the multiplier is divided by WDIV. If the value in
the WDIV register is equal to 0, then the internal active energy
register is divided by 1. WDIV is an 8-bit unsigned register.
After dividing by WDIV, the active energy is accumulated in a
49-bit internal energy accumulation register. The upper 24 bits
of this register are accessible through a read to the active energy
register (AENERGY[23:0]). A read to the RAENERGY register
returns the content of the AENERGY register and the upper 24
bits of the internal register are cleared. As shown in Figure 65, the
active power signal is accumulated in an internal 49-bit signed
register. The active power signal can be read from the waveform
register by setting MODE[14:13] = 0,0 and setting the WSMP
bit (Bit 3) in the interrupt enable register to 1. Like the Channel 1
and Channel 2 waveform sampling modes, the waveform date is
available at sample rates of 27.9 kSPS, 14 kSPS, 7 kSPS, or
3.5 kSPS—see Figure 52.
0x00,0000
4 6.2
8
12.5
TIME (minutes)
0x40,0000
0x80,0000
02875-0-065
Figure 66. Energy Register Rollover Time for Full-Scale Power
(Minimum and Maximum Power Gain)
Note that the energy register contents rolls over to full-scale
negative (0x800000) and continues to increase in value when
the power or energy flow is positive—see Figure 66. Conversely,
if the power is negative, the energy register underflows to fullscale positive (0x7FFFFF) and continues to decrease in value.
By using the interrupt enable register, the ADE7753 can be
configured to issue an interrupt (IRQ) when the active energy
register is greater than half-full (positive or negative) or when
an overflow or underflow occurs.
Integration Time under Steady Load
As mentioned in the last section, the discrete time sample
period (T) for the accumulation register is 1.1 μs (4/CLKIN).
With full-scale sinusoidal signals on the analog inputs and the
WGAIN register set to 0x000, the average word value from each
LPF2 is 0xCCCCD—see Figure 61. The maximum positive
value that can be stored in the internal 49-bit register is 248 or
Rev. C | Page 30 of 60
ADE7753
0xFFFF,FFFF,FFFF before it overflows. The integration time
under these conditions with WDIV = 0 is calculated as follows:
Time =
0 xFFFF, FFFF, FFFF
× 1.12 μs = 375.8 s = 6.26 min(15)
0 xCCCCD
When WDIV is set to a value different from 0, the integration
time varies, as shown in Equation 16.
Time = TimeWDIV =0 × WDIV
(16)
POWER OFFSET CALIBRATION
The ADE7753 also incorporates an active power offset register
(APOS[15:0]). This is a signed twos complement 16-bit register
that can be used to remove offsets in the active power calculation—
see Figure 65. An offset could exist in the power calculation due
to crosstalk between channels on the PCB or in the IC itself.
The offset calibration allows the contents of the active power
register to be maintained at 0 when no power is being consumed.
The 256 LSBs (APOS = 0x0100) written to the active power
offset register are equivalent to 1 LSB in the waveform sample
register. Assuming the average value, output from LPF2 is
0xCCCCD (838,861d) when inputs on Channels 1 and 2 are
both at full scale. At −60 dB down on Channel 1 (1/1000 of the
Channel 1 full-scale input), the average word value output from
LPF2 is 838.861 (838,861/1,000). One LSB in the LPF2 output
has a measurement error of 1/838.861 × 100% = 0.119% of the
average value. The active power offset register has a resolution
equal to 1/256 LSB of the waveform register, therefore the power
offset correction resolution is 0.00047%/LSB (0.119%/256) at –60 dB.
ENERGY-TO-FREQUENCY CONVERSION
ADE7753 also provides energy-to-frequency conversion for
calibration purposes. After initial calibration at manufacturing,
the manufacturer or end customer often verify the energy meter
calibration. One convenient way to verify the meter calibration
is for the manufacturer to provide an output frequency, which is
proportional to the energy or active power under steady load
conditions. This output frequency can provide a simple, singlewire, optically isolated interface to external calibration
equipment. Figure 67 illustrates the energy-to-frequency
conversion in the ADE7753.
are generated at the DFC output. Under steady load conditions,
the output frequency is proportional to the active power.
The maximum output frequency, with ac input signals at full scale
and CFNUM = 0x00 and CFDEN = 0x00, is approximately 23 kHz.
The ADE7753 incorporates two registers, CFNUM[11:0] and
CFDEN[11:0], to set the CF frequency. These are unsigned
12-bit registers, which can be used to adjust the CF frequency to
a wide range of values. These frequency-scaling registers are
12-bit registers, which can scale the output frequency by 1/212 to
1 with a step of 1/212.
If the value 0 is written to any of these registers, the value 1
would be applied to the register. The ratio (CFNUM + 1)/
(CFDEN + 1) should be smaller than 1 to ensure proper
operation. If the ratio of the registers (CFNUM + 1)/(CFDEN + 1)
is greater than 1, the register values would be adjusted to a ratio
(CFNUM + 1)/(CFDEN + 1) of 1. For example, if the output
frequency is 1.562 kHz while the contents of CFDEN are 0
(0x000), then the output frequency can be set to 6.1 Hz by
writing 0xFF to the CFDEN register.
When CFNUM and CFDEN are both set to one, the CF pulse
width is fixed at 16 CLKIN/4 clock cycles, approximately 18 μs
with a CLKIN of 3.579545 MHz. If the CF pulse output is
longer than 180 ms for an active energy frequency of less than
5.56 Hz, the pulse width is fixed at 90 ms. Otherwise, the pulse
width is 50% of the duty cycle.
The output frequency has a slight ripple at a frequency equal to
twice the line frequency. This is due to imperfect filtering of the
instantaneous power signal to generate the active power signal—
see the Active Power Calculation section. Equation 9 from the
Active Power Calculation section gives an expression for the
instantaneous power signal. This is filtered by LPF2, which has
a magnitude response given by Equation 17.
The active power signal (output of LPF2) can be rewritten as
⎡
⎤
⎢
⎥
⎢
⎥
VI
× cos(4πfLt)
p(t) = VI − ⎢
2 ⎥
⎢
⎛ 2f L ⎞ ⎥
⎢ 1 + ⎜ 8.9 ⎟ ⎥
⎝
⎠ ⎦
⎣
0
%
DFC
48
CF
0
(17)
f2
1+
8.9 2
CFNUM[11:0]
11
1
H( f ) =
(18)
where fL is the line frequency, for example, 60 Hz.
AENERGY[48:0]
11
From Equation 13,
0
CFDEN[11:0]
02875-0-066
Figure 67. ADE7753 Energy-to-Frequency Conversion
A digital-to-frequency converter (DFC) is used to generate the
CF pulsed output. The DFC generates a pulse each time 1 LSB
in the active energy register is accumulated. An output pulse is
generated when (CFDEN + 1)/(CFNUM + 1) number of pulses
Rev. C | Page 31 of 60
⎤
⎡
⎥
⎢
⎥
⎢
VI
E(t) = VIt − ⎢
× sin(4πfLt)
2 ⎥
⎢
⎛ 2f L ⎞ ⎥
⎢ 4 π f L 1 + ⎜ 8.9 ⎟ ⎥
⎝
⎠ ⎦
⎣
(19)
ADE7753
a lower output frequency at CF for calibration can significantly
reduce the ripple. Also, averaging the output frequency by using
a longer gate time for the counter achieves the same results.
From Equation 19 it can be seen that there is a small ripple in
the energy calculation due to a sin(2 ωt) component. This is
shown graphically in Figure 68. The active energy calculation is
shown by the dashed straight line and is equal to V × I × t. The
sinusoidal ripple in the active energy calculation is also shown.
E(t)
Since the average value of a sinusoid is 0, this ripple does not
contribute to the energy calculation over time. However, the
ripple can be observed in the frequency output, especially at
higher output frequencies. The ripple gets larger as a percentage
of the frequency at larger loads and higher output frequencies.
The reason is simply that at higher output frequencies the
integration or averaging time in the energy-to-frequency
conversion process is shorter. As a consequence, some of the
sinusoidal ripple is observable in the frequency output. Choosing
Vlt
–
VI
4×π×fL(1+2×fL/8. 9Hz )
t
sin(4×π×fL×t)
02875-0-067
Figure 68. Output Frequency Ripple
WGAIN[11:0]
OUTPUT
FROM
LPF2
+
+
APOS[15:0]
0
WDIV[7:0]
23
LPF1
FROM
CHANNEL 2
ADC
48
%
ZERO CROSS
DETECTION
CALIBRATION
CONTROL
0
LAENERGY [23:0]
LINECYC [15:0]
Figure 69. Energy Calculation Line Cycle Energy Accumulation Mode
Rev. C | Page 32 of 60
ACCUMULATE ACTIVE
ENERGY IN INTERNAL
REGISTER AND UPDATE
THE LAENERGY REGISTER
AT THE END OF LINECYC
LINE CYCLES
02875-0-068
ADE7753
LINE CYCLE ENERGY ACCUMULATION MODE
In line cycle energy accumulation mode, the energy accumulation of the ADE7753 can be synchronized to the Channel 2 zero
crossing so that active energy can be accumulated over an
integral number of half line cycles. The advantage of summing
the active energy over an integer number of line cycles is that
the sinusoidal component in the active energy is reduced to 0.
This eliminates any ripple in the energy calculation. Energy is
calculated more accurately and in a shorter time because the
integration period can be shortened. By using the line cycle
energy accumulation mode, the energy calibration can be
greatly simplified, and the time required to calibrate the meter
can be significantly reduced. The ADE7753 is placed in line
cycle energy accumulation mode by setting Bit 7 (CYCMODE)
in the mode register. In line cycle energy accumulation mode,
the ADE7753 accumulates the active power signal in the
LAENERGY register (Address 0x04) for an integral number of
line cycles, as shown in Figure 69. The number of half line
cycles is specified in the LINECYC register (Address 0x1C). The
ADE7753 can accumulate active power for up to 65,535 half
line cycles. Because the active power is integrated on an integral
number of line cycles, at the end of a line cycle energy accumulation cycle the CYCEND flag in the interrupt status register is
set (Bit 2). If the CYCEND enable bit in the interrupt enable
register is enabled, the IRQ output also goes active low. Thus the
IRQ line can also be used to signal the completion of the line
cycle energy accumulation. Another calibration cycle can start
as long as the CYCMODE bit in the mode register is set.
Note that in this mode, the 16-bit LINECYC register can hold a
maximum value of 65,535. In other words, the line energy
accumulation mode can be used to accumulate active energy for
a maximum duration over 65,535 half line cycles. At 60 Hz line
frequency, it translates to a total duration of 65,535/120 Hz =
546 seconds.
POSITIVE-ONLY ACCUMULATION MODE
In positive-only accumulation mode, the energy accumulation
is done only for positive power, ignoring any occurrence of
negative power above or below the no-load threshold, as shown
in Figure 70. The CF pulse also reflects this accumulation
method when in this mode. The ADE7753 is placed in positiveonly accumulation mode by setting the MSB of the mode
register (MODE[15]). The default setting for this mode is off.
Transitions in the direction of power flow, going from negative
to positive or positive to negative, set the IRQ pin to active low
if the interrupt enable register is enabled. The interrupt status
registers, PPOS and PNEG, show which transition has
occurred—see the ADE7753 register descriptions in Table 12.
ACTIVE ENERGY
NO-LOAD
THRESHOLD
From Equations 13 and 18,
⎫
⎧
⎪
⎪
⎪nT
⎪
VI
cos (2πft)dt
E(t) = ∫ VIdt − ⎨
2 ⎬∫
0
⎪
⎛ f ⎞ ⎪0
⎟ ⎪
⎪ 1+ ⎜
⎝ 8.9 ⎠ ⎭
⎩
ACTIVE POWER
nT
IRQ
where:
n is an integer.
T is the line cycle period.
PPOS
+0
02875-0-069
NO-LOAD THRESHOLD
(21)
0
E(t) = VInT
PPOS PNEG PPOS PNEG
Figure 70. Energy Accumulation in Positive-Only Accumulation Mode
nT
∫ VIdt
PNEG
INTERRUPT STATUS REGISTERS
Since the sinusoidal component is integrated over an integer
number of line cycles, its value is always 0. Therefore,
E=
NO-LOAD
THRESHOLD
(20)
(22)
The ADE7753 includes a no-load threshold feature on the
active energy that eliminates any creep effects in the meter. The
ADE7753 accomplishes this by not accumulating energy if the
multiplier output is below the no-load threshold. This threshold
is 0.001% of the full-scale output frequency of the multiplier.
Compare this value to the IEC1036 specification, which states
that the meter must start up with a load equal to or less than
0.4% Ib. This standard translates to .0167% of the full-scale
output frequency of the multiplier.
REACTIVE POWER CALCULATION
Reactive power is defined as the product of the voltage and
current waveforms when one of these signals is phase-shifted by
Rev. C | Page 33 of 60
ADE7753
90°. The resulting waveform is called the instantaneous reactive
power signal. Equation 25 gives an expression for the instantaneous reactive power signal in an ac system when the phase of
the current channel is shifted by +90°.
v(t) =
2V sin(ωt + θ)
i(t) =
2 I sin(ωt )
The average reactive power over an integral number of lines (n)
is given in Equation 26.
1
RP =
nT
(23)
π
i ′(t ) = 2 I sin⎛⎜ ωt + ⎞⎟
2⎠
⎝
∫ Rp(t ) dt = VI sin(θ )
(26)
0
where:
T is the line cycle period.
RP is referred to as the reactive power.
(24)
Note that the reactive power is equal to the dc component of the
instantaneous reactive power signal Rp(t) in Equation 25. This
is the relationship used to calculate reactive power in the
ADE7753. The instantaneous reactive power signal Rp(t) is
generated by multiplying Channel 1 and Channel 2. In this case,
the phase of Channel 1 is shifted by +90°. The dc component of
the instantaneous reactive power signal is then extracted by a
low-pass filter in order to obtain the reactive power information. Figure 71 shows the signal processing in the reactive
power calculation in the ADE7753.
where:
θ is the phase difference between the voltage and current
channel.
V is the rms voltage.
I is the rms current.
Rp(t) = v(t) × i’(t)
nT
(25)
Rp(t) = VI sin (θ) + VI sin(2ωt + θ)
90 DEGREE
PHASE SHIFT
INSTANTANEOUS REACTIVE
POWER SIGNAL (Rp(t))
I
π
2
+
+
49
0
MULTIPLIER
LPF2
V
23
FROM
CHANNEL 2
ADC
ZERO-CROSSING
DETECTION
CALIBRATION
CONTROL
0
LVARENERGY [23:0]
ACCUMULATE REACTIVE
ENERGY IN INTERNAL
REGISTER AND UPDATE
THE LVARENERGY REGISTER
AT THE END OF LINECYC HALF
LINE CYCLES
LPF1
LINECYC [15:0]
Figure 71. Reactive Power Signal Processing
Rev. C | Page 34 of 60
02875-0-070
ADE7753
The features of the line reactive energy accumulation are the
same as the line active energy accumulation. The number of
half line cycles is specified in the LINECYC register. LINECYC
is an unsigned 16-bit register. The ADE7753 can accumulate
reactive power for up to 65535 combined half cycles. At the end
of an energy calibration cycle, the CYCEND flag in the interrupt
status register is set. If the CYCEND mask bit in the interrupt
mask register is enabled, the IRQ output also goes active low.
Thus the IRQ line can also be used to signal the end of a calibration. The ADE7753 accumulates the reactive power signal in
the LVARENERGY register for an integer number of half cycles,
as shown in Figure 71.
SIGN OF REACTIVE POWER CALCULATION
Note that the average reactive power is a signed calculation. The
phase shift filter has –90° phase shift when the integrator is
enabled, and +90° phase shift when the integrator is disabled.
Table 9 summarizes the relationship between the phase difference between the voltage and the current and the sign of the
resulting VAR calculation.
Table 9. Sign of Reactive Power Calculation
Angle
Between 0° to 90°
Between –90° to 0°
Between 0° to 90°
Between –90° to 0°
Integrator
Off
Off
On
On
Sign
Positive
Negative
Positive
Negative
APPARENT POWER CALCULATION
The apparent power is defined as the maximum power that can
be delivered to a load. Vrms and Irms are the effective voltage and
current delivered to the load; the apparent power (AP) is defined
as Vrms × Irms. The angle θ between the active power and the
apparent power generally represents the phase shift due to nonresistive loads. For single-phase applications, θ represents the
angle between the voltage and the current signals—see Figure 72.
APPARENT POWER
SIGNAL (P)
Irms
CURRENT RMS SIGNAL – i(t)
MULTIPLIER
0xAD055
0x1C82B3
0x00
Vrms
VAGAIN
02875-0-072
VOLTAGE RMS SIGNAL– v(t)
0x17D338
0x00
Figure 73. Apparent Power Signal Processing
The gain of the apparent energy can be adjusted by using the
multiplier and VAGAIN register (VAGAIN[11:0]). The gain is
adjusted by writing a twos complement, 12-bit word to the
VAGAIN register. Equation 29 shows how the gain adjustment
is related to the contents of the VAGAIN register.
⎛
⎧ VAGAIN ⎫ ⎞
OutputVAGAIN = ⎜⎜ Apparent Power × ⎨1 +
⎬ ⎟⎟ (29)
212 ⎭ ⎠
⎩
⎝
For example, when 0x7FF is written to the VAGAIN register,
the power output is scaled up by 50%. 0x7FF = 2047d, 2047/212
= 0.5. Similarly, 0x800 = –2047d (signed twos complement) and
power output is scaled by –50%. Each LSB represents 0.0244%
of the power output. The apparent power is calculated with the
current and voltage rms values obtained in the rms blocks of the
ADE7753. Figure 74 shows the maximum code (hexadecimal)
output range of the apparent power signal. Note that the output
range changes depending on the contents of the apparent power
gain registers. The minimum output range is given when the
apparent power gain register content is equal to 0x800 and the
maximum range is given by writing 0x7FF to the apparent
power gain register. This can be used to calibrate the apparent
power (or energy) calculation in the ADE7753.
APPARENT POWER 100% FS
APPARENT POWER 150% FS
APPARENT POWER 50% FS
0x103880
APPARENT
POWER
0xAD055
0x5682B
REACTIVE
POWER
0x00000
0x000
0x7FF
0x800
{VAGAIN[11:0]}
APPARENT POWER
CALIBRATION RANGE
VOLTAGE AND CURRENT
CHANNEL INPUTS: 0.5V/GAIN
θ
ACTIVE
POWER
02875-0-073
Figure 74. Apparent Power Calculation Output Range
02875-0-071
Figure 72. Power Triangle
Apparent Power Offset Calibration
The apparent power is defined as Vrms × Irms. This expression is
independent from the phase angle between the current and the
voltage.
Figure 73 illustrates the signal processing in each phase for the
calculation of the apparent power in the ADE7753.
Each rms measurement includes an offset compensation
register to calibrate and eliminate the dc component in the rms
value—see Channel 1 RMS Calculation and Channel 2 RMS
Calculation sections. The Channel 1 and Channel 2 rms values
are then multiplied together in the apparent power signal
processing. Since no additional offsets are created in the
multiplication of the rms values, there is no specific offset
Rev. C | Page 35 of 60
ADE7753
VAENERGY [23:0]
compensation in the apparent power signal processing. The
offset compensation of the apparent power measurement is
done by calibrating each individual rms measurement.
23
APPARENT ENERGY CALCULATION
0
48
0
The apparent energy is given as the integral of the apparent
power.
∫
Apparent Energy = Apparent Power (t ) dt
VADIV
(30)
The ADE7753 achieves the integration of the apparent power
signal by continuously accumulating the apparent power signal
in an internal 49-bit register. The apparent energy register
(VAENERGY[23:0]) represents the upper 24 bits of this internal
register. This discrete time accumulation or summation is
equivalent to integration in continuous time. Equation 31
expresses the relationship
48
+
APPARENT POWER
%
0
+
ACTIVE POWER
SIGNAL = P
APPARENT POWER ARE
ACCUMULATED (INTEGRATED) IN
THE APPARENT ENERGY REGISTER
T
⎧⎪ ∞
⎫⎪
Apparent Energy = Lim ⎨
Apparent Power ( nT ) × T ⎬ (31)
T →0 ⎪
⎪⎭
⎩ n =0
∑
TIME (nT)
02875-0-074
Figure 75. ADE7753 Apparent Energy Calculation
where:
VAENERGY[23:0]
n is the discrete time sample number.
T is the sample period.
0xFF,FFFF
VAGAIN = 0x7FF
VAGAIN = 0x000
VAGAIN = 0x800
The discrete time sample period (T) for the accumulation
register in the ADE7753 is 1.1 μs (4/CLKIN).
0x80,0000
Figure 75 shows this discrete time integration or accumulation.
The apparent power signal is continuously added to the internal
register. This addition is a signed addition even if the apparent
energy remains theoretically always positive.
The 49 bits of the internal register are divided by VADIV. If the
value in the VADIV register is 0, then the internal active energy
register is divided by 1. VADIV is an 8-bit unsigned register.
The upper 24 bits are then written in the 24-bit apparent energy
register (VAENERGY[23:0]). RVAENERGY register (24 bits
long) is provided to read the apparent energy. This register is
reset to 0 after a read operation.
Figure 76 shows this apparent energy accumulation for full-scale
signals (sinusoidal) on the analog inputs. The three curves
displayed illustrate the minimum time it takes the energy register
to roll over when the VAGAIN registers content is equal to 0x7FF,
0x000, and 0x800. The VAGAIN register is used to carry out an
apparent power calibration in the ADE7753. As shown, the fastest
integration time occurs when the VAGAIN register is set to
maximum full scale, i.e., 0x7FF.
0x40,0000
0x20,0000
0x00,0000
6.26
12.52
18.78
25.04
TIME (minutes)
02875-0-075
Figure 76. Energy Register Rollover Time for Full-Scale Power
(Maximum and Minimum Power Gain)
Note that the apparent energy register is unsigned—see Figure 76.
By using the interrupt enable register, the ADE7753 can be configured to issue an interrupt (IRQ) when the apparent energy
register is more than half full or when an overflow occurs. The
half full interrupt for the unsigned apparent energy register is
based on 24 bits as opposed to 23 bits for the signed active energy
register.
Integration Times under Steady Load
As mentioned in the last section, the discrete time sample
period (T) for the accumulation register is 1.1 μs (4/CLKIN).
With full-scale sinusoidal signals on the analog inputs and the
VAGAIN register set to 0x000, the average word value from
apparent power stage is 0xAD055—see the Apparent Power
Calculation section. The maximum value that can be stored in
the apparent energy register before it overflows is 224 or
0xFF,FFFF. The average word value is added to the internal
register, which can store 248 or 0xFFFF,FFFF,FFFF before it
Rev. C | Page 36 of 60
ADE7753
overflows. Therefore, the integration time under these conditions
with VADIV = 0 is calculated as follows:
LINE APPARENT ENERGY ACCUMULATION
0 xFFFF, FFFF, FFFF
Time =
× 1.2 μs = 888 s = 12.52 min(32)
0 xD 055
When VADIV is set to a value different from 0, the integration
time varies, as shown in Equation 33.
Time = TimeWDIV = 0 × VADIV
(33)
The ADE7753 is designed with a special apparent energy
accumulation mode, which simplifies the calibration process.
By using the on-chip zero-crossing detection, the ADE7753
accumulates the apparent power signal in the LVAENERGY
register for an integral number of half cycles, as shown in
Figure 77. The line apparent energy accumulation mode is
always active.
The number of half line cycles is specified in the LINECYC
register, which is an unsigned 16-bit register. The ADE7753 can
accumulate apparent power for up to 65535 combined half
cycles. Because the apparent power is integrated on the same
integral number of line cycles as the line active energy register,
these two values can be compared easily. The active energy and
the apparent energy are calculated more accurately because of
this precise timing control and provide all the information
needed for reactive power and power factor calculation. At the
end of an energy calibration cycle, the CYCEND flag in the
interrupt status register is set. If the CYCEND mask bit in the
interrupt mask register is enabled, the IRQ output also goes
active low. Thus the IRQ line can also be used to signal the end
of a calibration.
The line apparent energy accumulation uses the same signal
path as the apparent energy accumulation. The LSB size of these
two registers is equivalent.
APPARENT
POWER
+
+
48
LVAENERGY REGISTER IS
UPDATED EVERY LINECYC
ZERO CROSSINGS WITH THE
TOTAL APPARENT ENERGY
DURING THAT DURATION
VADIV[7:0]
LPF1
FROM
CHANNEL 2
ADC
ZERO-CROSSING
DETECTION
0
%
CALIBRATION
CONTROL
23
0
LVAENERGY [23:0]
LINECYC [15:0]
Figure 77. ADE7753 Apparent Energy Calibration
Rev. C | Page 37 of 60
02875-0-076
ADE7753
ENERGIES SCALING
The ADE7753 provides measurements of active, reactive, and
apparent energies. These measurements do not have the same
scaling and thus cannot be compared directly to each other.
Table 10. Energies Scaling
PF = 1
Integrator On at 50 Hz
Active
Wh
Reactive
0
Apparent
Wh × 0.848
Integrator Off at 50 Hz
Active
Wh
Reactive
0
Apparent
Wh × 0.848
Integrator On at 60 Hz
Active
Wh
Reactive
0
Apparent
Wh × 0.827
Integrator Off at 60 Hz
Active
Wh
Reactive
0
Apparent
Wh × 0.827
When using a reference meter, the ADE7753 calibration output
frequency, CF, is adjusted to match the frequency output of the
reference meter. A pulse output is only provided for the active
energy measurement in the ADE7753. If it is desired to use a
reference meter for calibrating the VA and VAR, then additional
code would have to be written in a microprocessor to produce a
pulsed output for these quantities. Otherwise, VA and VAR
calibration require an accurate source.
PF = 0.707
PF = 0
Wh × 0.707
Wh × 0.508
Wh × 0.848
0
Wh × 0.719
Wh × 0.848
Wh × 0.707
Wh × 0.245
Wh × 0.848
0
Wh × 0.347
Wh × 0.848
Wh × 0.707
Wh × 0.610
Wh × 0.827
0
Wh × 0.863
Wh × 0.827
Wh × 0.707
Wh × 0.204
Wh × 0.827
0
Wh × 0.289
Wh × 0.827
Current and voltage rms offset calibration removes any apparent
energy offset. A gain calibration is also provided for apparent
energy. Figure 79 shows an optimized calibration flow for active
energy, rms, and apparent energy.
CALIBRATING AN ENERGY METER BASED ON THE
ADE7753
Active and apparent energy gain calibrations can take place
concurrently, with a read of the accumulated apparent energy
register following that of the accumulated active energy register.
The ADE7753 provides gain and offset compensation for active
and apparent energy calibration. Its phase compensation corrects
phase error in active, apparent and reactive energy. If a shunt is
used, offset and phase calibration may not be required. A
reference meter or an accurate source can be used to calibrate
the ADE7753.
WATT/VA GAIN CALIBRATION
RMS CALIBRATION
The ADE7753 provides a line cycle accumulation mode for
calibration using an accurate source. In this method, the active
energy accumulation rate is adjusted to produce a desired CF
frequency. The benefit of using this mode is that the effect of
the ripple noise in the active energy is eliminated. Up to 65535
half line cycles can be accumulated, thus providing a stable
energy value to average. The accumulation time is calculated
from the line cycle period, measured by the ADE7753 in the
PERIOD register, and the number of half line cycles in the
accumulation, fixed by the LINECYC register.
Figure 78 shows the calibration flow for the active energy
portion of the ADE7753.
WATT GAIN CALIBRATION
WATT OFFSET CALIBRATION
PHASE CALIBRATION
02875-A-005
Figure 78. Active Energy Calibration
The ADE7753 does not provide means to calibrate reactive
energy gain and offset. The reactive energy portion of the
ADE7753 can be calibrated externally, through a MCU.
WATT OFFSET CALIBRATION
PHASE CALIBRATION
02875-A-002
Figure 79. Apparent and Active Energy Calibration
Rev. C | Page 38 of 60
ADE7753
AENERGYexpected = AENERGYnominal × ⎛⎜1 +
Watt Gain
The first step of calibrating the gain is to define the line voltage,
base current and the maximum current for the meter. A meter
constant needs to be determined for CF, such as 3200 imp/kWh
or 3.2 imp/Wh. Note that the line voltage and the maximum
current scale to half of their respective analog input ranges in
this example.
The expected CF in Hz is
CFexpected (Hz) =
MeterConstant (imp/Wh) × Load(W)
3600 s/h
× cos(ϕ)
(34)
where ϕ is the angle between I and V, and cos (ϕ) is the power
factor.
The ratio of active energy LSBs per CF pulse is adjusted using
the CFNUM, CFDEN, and WDIV registers.
CFexpected =
(CFNUM + 1)
LAENERGY
× WDIV ×
(CFDEN + 1)
AccumulationTime(s)
(35)
The relationship between watt-hours accumulated and the
quantity read from AENERGY can be determined from the
amount of active energy accumulated over time with a given
load:
Wh
LSB =
Load(W) × Accumulation Time(s)
LAENERGY × 3600 s/ h
(36)
⎝
CFexpected (Hz) = CFnominal ×
LINECYC IB × Line Period(s)
2
(37)
8
CLKIN
(38)
The AENERGY Wh/LSB ratio can also be expressed in terms of
the meter constant:
(CFNUM + 1)
× WDIV
(CFDEN + 1)
Wh
LSB = MeterConstant (imp/Wh)
(39)
In a meter design, WDIV, CFNUM, and CFDEN should be kept
constant across all meters to ensure that the Wh/LSB constant is
maintained. Leaving WDIV at its default value of 0 ensures
maximum resolution. The WDIV register is not included in the
CF signal chain so it does not affect the frequency pulse output.
The WGAIN register is used to finely calibrate each meter. Calibrating the WGAIN register changes both CF and AENERGY for
a given load condition.
(CFNUM + 1) ⎛ WGAIN ⎞
× ⎜1 +
⎟ (41)
(CFDEN + 1) ⎝
212 ⎠
The steps of designing and calibrating the active energy portion
of a meter with either a reference meter or an accurate source
are outlined in the following examples. The specifications for
this example are
Meter Constant:
= 3.2
Base Current:
Maximum Current:
Line Voltage:
Line Frequency:
MeterConstant(imp/Wh)
Ib = 10 A
IMAX = 60 A
Vnominal = 220 V
fl = 50 Hz
The first step in calibration with either a reference meter or an
accurate source is to calculate the CF denominator, CFDEN.
This is done by comparing the expected CF pulse output to the
nominal CF output with the default CFDEN = 0x3F and
CFNUM = 0x3F and when the base current is applied.
The expected CF output for this meter with the base current
applied is 1.9556 Hz using Equation 34.
CFIB(expected)(Hz) =
3.200 imp/Wh× 10 A× 220 V
3600 s/h
× cos(ϕ) = 1.9556 Hz
Alternatively, CFexpected can be measured from a reference meter
pulse output if available.
The line period can be determined from the PERIOD register:
Line Period(s) = PERIOD ×
(40)
When calibrating with a reference meter, WGAIN is adjusted
until CF matches the reference meter pulse output. If an accurate
source is used to calibrate, WGAIN is modified until the active
energy accumulation rate yields the expected CF pulse rate.
where Accumulation Time can be determined from the value in
the line period and the number of half line cycles fixed in the
LINECYC register.
Accumulation time(s) =
WGAIN ⎞
⎟
212 ⎠
CFexpected(Hz) = CFref
(42)
The maximum CF frequency measured without any frequency
division and with ac inputs at full scale is 23 kHz. For this
example, the nominal CF with the test current, Ib, applied is
958 Hz. In this example the line voltage and maximum current
scale half of their respective analog input ranges. The line
voltage and maximum current should not be fixed at the
maximum analog inputs to account for occurrences such as
spikes on the line.
CFnominal(Hz) = 23 kHz × 1 2 × 1 2 ×
I
I MAX
(43)
CFIB(nominal)(Hz) = 23 kHz × 1 2 × 1 2 × 10 60 = 958 Hz
The nominal CF on a sample set of meters should be measured
using the default CFDEN, CFNUM, and WDIV to ensure that
the best CFDEN is chosen for the design.
With the CFNUM register set to 0, CFDEN is calculated to be
489 for the example meter:
Rev. C | Page 39 of 60
ADE7753
⎛ CFIB(nominal )
CFDEN = INT ⎜
⎜ CFIB(expected )
⎝
⎞
⎟ −1
⎟
⎠
For this example:
(44)
958 ⎞
CFDEN = INT ⎛⎜
⎟ − 1 = (490 − 1) = 489
⎝ 1.9556 ⎠
This value for CFDEN should be loaded into each meter before
calibration. The WGAIN and WDIV registers can then be used
to finely calibrate the CF output. The following sections explain
how to calibrate a meter based on ADE7753 when using a
reference meter or an accurate source.
Calibrating Watt Gain Using a Reference Meter Example
The CFDEN and CFNUM values for the design should be
written to their respective registers before beginning the
calibration steps shown in Figure 80. When using a reference
meter, the %ERROR in CF is measured by comparing the CF
output of the ADE7753 meter with the pulse output of the
reference meter with the same test conditions applied to both
meters. Equation 45 defines the percent error with respect to
the pulse outputs of both meters (using the base current, Ib):
%ERRORCF(IB) =
CFIB − CFref ( IB )
CFref ( IB )
× 100
(45)
Meter Constant:
MeterConstant(imp/Wh)
= 3.2
CF Numerator:
CFNUM = 0
CF Denominator:
CFDEN = 489
% Error measured at Base Current:
%ERRORCF(IB) = -3.07%
One LSB change in WGAIN changes the active energy registers
and CF by 0.0244%. WGAIN is a signed twos complement
register and can correct for up to a 50% error. Assuming a
−3.07% error, WGAIN is 126:
⎛ % ERRORCF (IB )
WGAIN = INT ⎜⎜ −
0.0244%
⎝
⎞
⎟⎟
⎠
(46)
−3.07% ⎞
WGAIN = INT ⎛⎜ −
⎟ = 126
⎝ 0.0244% ⎠
When CF is calibrated, the AENERGY register has the same
Wh/LSB constant from meter to meter if the meter constant,
WDIV, and the CFNUM/CFDEN ratio remain the same. The
Wh/LSB ratio for this meter is 6.378 × 10−4 using Equation 39
with WDIV at the default value.
(CFNUM + 1)
× WDIV
(CFDEN + 1)
Wh
=
LSB MeterConstant (imp/Wh)
CALCULATE CFDEN VALUE FOR DESIGN
WRITE CFDEN VALUE TO CFDEN REGISTER
ADDR. 0x15 = CFDEN
1
1
+ 1)
(
490
−4
Wh
LSB = 3.200 imp/Wh = 490 × 3.2 = 6.378 × 10
SET ITEST = Ib, VTEST = VNOM, PF = 1
Calibrating Watt Gain Using an Accurate Source Example
MEASURE THE % ERROR BETWEEN
THE CF OUTPUT AND THE
REFERENCE METER OUTPUT
CALCULATE WGAIN. SEE EQUATION 46.
WRITE WGAIN VALUE TO THE WGAIN
REGISTER: ADDR. 0x12
02875-A-006
Figure 80. Calibrating Watt Gain Using a Reference Meter
The CFDEN value calculated using Equation 44 should be
written to the CFDEN register before beginning calibration and
zero should be written to the CFNUM register. First, the line
accumulation mode and the line accumulation interrupt should
be enabled. Next, the number of half line cycles for the energy
accumulation is written to the LINECYC register. This sets the
accumulation time. Reset the interrupt status register and wait
for the line cycle accumulation interrupt. The first line cycle
accumulation results may not have used the accumulation time
set by the LINECYC register and should be discarded. After
resetting the interrupt status register, the following line cycle
readings will be valid. When LINECYC half line cycles have
elapsed, the IRQ pin goes active low and the nominal LAENERGY
with the test current applied can be read. This LAENERGY
value is compared to the expected LAENERGY value to determine the WGAIN value. If apparent energy gain calibration is
performed at the same time, LVAENERGY can be read directly
after LAENERGY. Both registers should be read before the next
interrupt is issued on the IRQ pin. Refer to the Apparent Energy
Calculation section for more details. Figure 81 details the steps
that calibrate the watt gain using an accurate source.
Rev. C | Page 40 of 60
ADE7753
The nominal LAENERGY reading, LAENERGYIB(nominal), is the
LAENERGY reading with the test current applied. The
expected LAENERGY reading is calculated from the following
equation:
CALCULATE CFDEN VALUE FOR DESIGN
WRITE CFDEN VALUE TO CFDEN REGISTER
ADDR. 0x15 = CFDEN
LAENERGYIB(expected) =
⎛
⎞
⎜ CFIB(expected ) × Accumulation Time(s) ⎟
⎟
INT ⎜
CFNUM + 1
⎜
⎟
×
WDIV
⎜
⎟
CFDEN + 1
⎝
⎠
SET ITEST = Ib, VTEST = VNOM, PF = 1
SET HALF LINECYCLES FOR ACCUMULATION
IN LINECYC REGISTER ADDR. 0x1C
SET MODE FOR LINE CYCLE
ACCUMULATION ADDR. 0x09 = 0x0080
where CFIB(expected)(Hz) is calculated from Equation 34, accumulation time is calculated from Equation 37, and the line period is
determined from the PERIOD register according to Equation 38.
ENABLE LINE CYCLE ACCUMULATION
INTERRUPT ADDR. 0x0A = 0x04
For this example:
Meter Constant:
MeterConstant(imp/Wh)
= 3.2
Test Current:
Ib = 10 A
Line Voltage:
Vnominal = 220 V
Line Frequency:
fl = 50 Hz
Half Line Cycles:
LINECYCIB = 2000
CF Numerator:
CFNUM = 0
CF Denominator:
CFDEN = 489
Energy Reading at Base Current:
LAENERGYIB (nominal) = 17174
Period Register Reading:
PERIOD = 8959
Clock Frequency:
CLKIN = 3.579545 MHz
RESET THE INTERRUPT STATUS
READ REGISTER ADDR. 0x0C
INTERRUPT?
NO
YES
RESET THE INTERRUPT STATUS
READ REGISTER ADDR. 0x0C
INTERRUPT?
(48)
NO
CFexpected is calculated to be 1.9556 Hz according to Equation 34.
LAENERGYexpected is calculated to be 19186 using Equation 48.
YES
CFIB(expected)(Hz) =
3.200 imp/Wh× 220 V× 10 A
READ LINE ACCUMULATION ENERGY
ADDR. 0x04
3600 s/h
× (cos(ϕ) = 1.9556 Hz
CALCULATE WGAIN. SEE EQUATION 47.
LAENERGYIB(expected) =
⎛
⎞
⎜ CFIB(expected ) × LINECYC IB / 2 × PERIOD × 8 / CLKIN ⎟
⎟
INT ⎜
CFNUM + 1
⎜
⎟
× WDIV
⎜
⎟
CFDEN + 1
⎝
⎠
WRITE WGAIN VALUE TO THE WGAIN
REGISTER: ADDR. 0x12
02875-A-007
Figure 81. Calibrating Watt Gain Using an Accurate Source
Equation 47 describes the relationship between the expected
LAENERGY value and the LAENERGY measured in the test
condition:
⎛ ⎛ LAENERGYIB(expected )
⎞
⎞
WGAIN = INT ⎜ ⎜
− 1⎟ × 212 ⎟
⎟
⎜ ⎜ LAENERGYIB(nominal)
⎟
⎠
⎝⎝
⎠
LAENERGYIB(expected) =
⎛
⎞
⎜ 1.9556 × 2000 / 2 × 8959 × 8 /(3.579545 × 10 6 ) ⎟
⎟1 =
INT ⎜
1
⎜
⎟
⎜
⎟
489 + 1
⎝
⎠
(47)
INT (19186.4) = 19186
WGAIN is calculated to be 480 using Equation 47.
⎛ 19186 ⎞ 12 ⎞
WGAIN = INT ⎜ ⎛⎜
− 1⎟ × 2 ⎟ = 480
⎝ ⎝ 17174 ⎠
⎠
Note that WGAIN is a signed twos complement register.
With WDIV and CFNUM set to 0, LAENERGY can be
expressed as
Rev. C | Page 41 of 60
ADE7753
LAENERGYIB(expected) =
INT (CFIB (expected ) × LINECYC IB / 2 × PERIOD × 8 / CLKIN × (CFDEN + 1))
The calculated Wh/LSB ratio for the active energy register,
using Equation 39 is 6.378 × 10−4:
1
(
489
+ 1)
−4
Wh
LSB = 3.200 imp/Wh = 6.378 × 10
Minimum Current:
Load at Minimum Current:
CF Error at Minimum Current:
CF Numerator:
CF Denominator:
Clock Frequency:
Using Equation 49, APOS is calculated to be −522 for this
example.
Watt Offset
CF Absolute Error = CFIMIN(nominal) − CFIMIN(expected)
Offset calibration allows outstanding performance over a wide
dynamic range, for example, 1000:1. To do this calibration two
measurements are needed at unity power factor, one at Ib and
the other at the lowest current to be corrected. Either
calibration frequency or line cycle accumulation measurements
can be used to determine the energy offset. Gain calibration
should be performed prior to offset calibration.
Offset calibration is performed by determining the active
energy error rate. Once the active energy error rate has been
determined, the value to write to the APOS register to correct
the offset is calculated.
APOS = −
AENERGY Error Rate × 2 35
The AENERGY registers update at a rate of CLKIN/4. The twos
complement APOS register provides a fine adjustment to the
active power calculation. It represents a fixed amount of power
offset to be adjusted every CLKIN/4. The 8 LSBs of the APOS
register are fractional such that one LSB of APOS represents
1/256 of the least significant bit of the internal active energy
register. Therefore, one LSB of the APOS register represents 2−33
of the AENERGY[23:0] active energy register.
The steps involved in determining the active energy error rate
for both line accumulation and reference meter calibration
options are shown in the following sections.
Calibrating Watt Offset Using a Reference Meter Example
Figure 82 shows the steps involved in calibrating watt offset
with a reference meter.
SET ITEST = IMIN, VTEST = VNOM, PF = 1
(50)
CF Absolute Error =
(%ERRORCF(IMIN)) × WIMIN ×
MeterConstant (imp/Wh)
3600
(51)
CF Absolute Error =
⎛ 1.3% ⎞ × 9.6 × 3.200 = 0.000110933 Hz
⎜
⎟
3600
⎝ 100 ⎠
Then,
AENERGY Error Rate (LSB/s) =
CFDEN + 1
CF Absolute Error ×
CFNUM + 1
(49)
CLKIN
IMIN = 40 mA
WIMIN = 9.6 W
%ERRORCF(IMIN) = 1.3%
CFNUM = 0
CFDEN = 489
CLKIN = 3.579545 MHz
(52)
AENERGY Error Rate (LSB/s) =
490
0.000110933 ×
= 0.05436
1
Using Equation 49, APOS is −522.
APOS = −
0.05436 × 2 35
= −522
3.579545 × 10 6
APOS can be represented as follows with CFNUM and WDIV
set at 0:
APOS =
−
MEASURE THE % ERROR BETWEEN THE
CF OUTPUT AND THE REFERENCE METER
OUTPUT, AND THE LOAD IN WATTS
CALCULATE APOS. SEE EQUATION 49.
WRITE APOS VALUE TO THE APOS
REGISTER: ADDR. 0x11
02875-A-008
Figure 82. Calibrating Watt Offset Using a Reference Meter
For this example:
Meter Constant:
MeterConstant(imp/Wh) = 3.2
Rev. C | Page 42 of 60
(%ERRORCF ( IMIN ) ) × WIMIN ×
MeterConstant (imp/Wh)
× (CFDEN + 1) × 235
3600
CLKIN
ADE7753
Calibrating Watt Offset with an Accurate Source Example
LAENERGYIMIN(nominal) = 1395
Figure 83 is the flowchart for watt offset calibration with an
accurate source.
The LAENERGYexpected at IMIN is 1370 using Equation 53.
LAENERGYIMIN(expected) =
SET ITEST = IMIN, VTEST = VNOM, PF = 1
⎛I
LINECYCI MIN
INT ⎜⎜ MIN × LAENERGY IB(expected ) ×
LINECYC IB
⎝ IB
SET HALF LINE CYCLES FOR ACCUMULATION
IN LINECYC REGISTER ADDR. 0x1C
LAENERGYIMIN(expected) =
0.04
35700 ⎞
× 19186 ×
INT ⎛⎜
⎟ = INT (1369.80) = 1370
2000 ⎠
⎝ 10
SET MODE FOR LINE CYCLE
ACCUMULATION ADDR. 0x09 = 0x0080
ENABLE LINE CYCLE ACCUMULATION
INTERRUPT ADDR. 0x0A = 0x04
where:
LAENERGYIB(expected) is the expected LAENERGY reading at Ib
from the watt gain calibration.
LINECYCIMIN is the number of half line cycles that energy is
accumulated over when measuring at IMIN.
RESET THE INTERRUPT STATUS
READ REGISTER ADDR. 0x0C
INTERRUPT?
NO
More line cycles could be required at the minimum current to
minimize the effect of quantization error on the offset calibration.
For example, if a test current of 40 mA results in an active energy
accumulation of 113 after 2000 half line cycles, one LSB variation
in this reading represents an 0.8% error. This measurement
does not provide enough resolution to calibrate out a <1% offset
error. However, if the active energy is accumulated over 37,500
half line cycles, one LSB variation results in 0.05% error, reducing
the quantization error.
YES
RESET THE INTERRUPT STATUS
READ REGISTER ADDR. 0x0C
INTERRUPT?
⎞
⎟ (53)
⎟
⎠
NO
YES
APOS is −672 using Equations 55 and 49.
READ LINE ACCUMULATION ENERGY
ADDR. 0x04
LAENERGY Absolute Error =
LAENERGYIMIN(nominal) − LAENERGYIMIN(expected)
CALCULATE APOS. SEE EQUATION 49.
LAENERGY Absolute Error = 1395 − 1370 = 25
WRITE APOS VALUE TO THE APOS
REGISTER: ADDR. 0x11
AENERGY Error Rate (LSB/s) =
LAENERGY Absolute Error
CLKIN
×
LINECYC / 2
8 × PERIOD
02875-A-009
Figure 83. Calibrating Watt Offset with an Accurate Source
For this example:
MeterConstant(imp/Wh)
Meter Constant:
= 3.2
Vnominal = 220 V
Line Voltage:
Line Frequency:
fl = 50 Hz
CFNUM = 0
CF Numerator:
CF Denominator:
CFDEN = 489
Ib = 10 A
Base Current:
Half Line Cycles Used at Base Current:
LINECYC(IB) = 2000
Period Register Reading:
PERIOD = 8959
CLKIN = 3.579545 MHz
Clock Frequency:
Expected LAENERGY Register Value at Base Current
(from the Watt Gain section):LAENERGYIB(expected) = 19186
Minimum Current:
IMIN = 40 mA
Number of Half Line Cycles used at Minimum Current:
LINECYC(IMIN) =
35700
Active energy Reading at Minimum Current:
Rev. C | Page 43 of 60
AENERGY Error Rate (LSB/s) =
25
3.579545 × 10 6
×
= 0.069948771
35700 / 2
8 × 8959
APOS = −
APOS = −
AENERGY Error Rate × 2 35
CLKIN
0.069948771 × 2 35
= −672
3.579545 × 10 6
(54)
(55)
ADE7753
Phase Calibration
SET ITEST = Ib, VTEST = VNOM, PF = 0.5
The PHCAL register is provided to remove small phase errors.
The ADE7753 compensates for phase error by inserting a small
time delay or advance on the voltage channel input. Phase leads
up to 1.84° and phase lags up to 0.72° at 50 Hz can be corrected.
The error is determined by measuring the active energy at IB
and two power factors, PF = 1 and PF =0.5 inductive.
MEASURE THE % ERROR BETWEEN
THE CF OUTPUT AND THE
REFERENCE METER OUTPUT
CALCULATE PHCAL. SEE EQUATION 59.
WRITE PHCAL VALUE TO THE PHCAL
REGISTER: ADDR. 0x10
Some CTs may introduce large phase errors that are beyond the
range of the phase calibration register. In this case, coarse phase
compensation has to be done externally with an analog filter.
The phase error can be obtained from either CF or LAENERGY
measurements:
Error =
LAENERGY IB, PF =.5 − LAENERGY IB(expected ) 2
LAENERGY IB(expected ) 2
(56)
If watt gain and offset calibration have been performed, there
should be 0% error in CF at unity power factor and then:
Error = %ERRORCF(IB,PF = .5) /100
02875-A-010
Figure 84. Calibrating Phase Using a Reference Meter
For this example:
CF % Error at PF = .5 Inductive:
0.215%
PERIOD Register Reading:
Error = 0.215% / 100 = 0.00215
⎛ 0.00215 ⎞
Phase Error (°) = −Arcsin ⎜⎜
⎟ = −0.07°
3 ⎟⎠
⎝
The phase error is
8959 ⎞
PHCAL = INT ⎛⎜ − 0.07° ×
⎟ +0x0D = −2 + 13 = 11
360° ⎠
⎝
(58)
The relationship between phase error and the PHCAL phase
correction register is
PHCAL can be expressed as follows:
PHCAL =
⎛
⎛ Error ⎞ PERIOD ⎞
⎟ + 0x0D
INT ⎜⎜ − Arcsin⎜⎜
⎟⎟ ×
2π ⎟⎠
⎝ 3 ⎠
⎝
PHCAL=
PERIOD ⎞
INT ⎛⎜ Phase Error (°) ×
⎟ + 0x0D
360° ⎠
⎝
(59)
Setting the PHCAL register to 11 provides a phase correction
of 0.08° to correct the phase lead:
Arcsin(x) ≈ x
Phase Correction (°) = − (PHCAL − 0x0D) ×
The delay introduced in the voltage channel by PHCAL is
(60)
The delay associated with the PHCAL register is a time delay if
(PHCAL − 0x0D) is positive but represents a time advance if
this quantity is negative. There is no time delay if PHCAL =
0x0D.
The phase correction is in the opposite direction of the phase
error.
Phase Correction (°) = −(PHCAL − 0x0D) ×
(62)
Note that PHCAL is a signed twos complement register.
The expression for PHCAL can be simplified using the
assumption that at small x:
Delay = (PHCAL − 0x0D) × 8/CLKIN
PERIOD = 8959
Then PHCAL is 11 using Equations 57 through 59:
(57)
⎛ Error ⎞
Phase Error (°) = −Arcsin ⎜⎜
⎟⎟
⎝ 3 ⎠
%ERRORCF(IB,PF = .5) =
360°
(61)
PERIOD
Calibrating Phase Using a Reference Meter Example
A power factor of 0.5 inductive can be assumed if the pulse
output rate of the reference meter is half of its PF = 1 rate. Then
the %ERROR between CF and the pulse output of the reference
meter can be used to perform the preceding calculations.
Rev. C | Page 44 of 60
Phase Correction (°) = − (11 − 0x0D) ×
360°
PERIOD
360°
= 0.08°
8960
ADE7753
Calibrating Phase with an Accurate Source Example
LAENERGYIB, PF
With an accurate source, line cycle accumulation is a good
method of calibrating phase error. The value of LAENERGY
must be obtained at two power factors, PF = 1 and PF = 0.5
inductive.
= .5 = 9613
The error using Equation 56 is
9613 − 19186
Error =
SET ITEST = Ib, VTEST = VNOM, PF = 0.5
19186
2 = 0.0021
2
⎛ 0.0021 ⎞
Phase Error (°) = −Arcsin ⎜⎜
⎟ = −0.07°
3 ⎟⎠
⎝
SET HALF LINE CYCLES FOR ACCUMULATION
IN LINECYC REGISTER ADDR. 0x1C
Using Equation 59, PHCAL is calculated to be 11.
SET MODE FOR LINE CYCLE
ACCUMULATION ADDR. 0x09 = 0x0080
8959 ⎞
PHCAL = INT ⎛⎜ − 0.07° ×
⎟ + 0x0D = −2 + 13 = 11
360° ⎠
⎝
ENABLE LINE CYCLE ACCUMULATION
INTERRUPT ADDR. 0x0A = 0x04
Note that PHCAL is a signed twos complement register.
The phase lead is corrected by 0.08° when the PHCAL register
is set to 11:
RESET THE INTERRUPT STATUS
READ REGISTER ADDR. 0x0C
Phase Correction (°) = − (PHCAL − 0x0D) ×
INTERRUPT?
NO
Phase Correction (°) = − (11 − 0x0D) ×
360°
PERIOD
360°
= 0.08°
8960
VRMS and IRMS Calibration
YES
VRMS and IRMS are calculated by squaring the input in a
digital multiplier.
RESET THE INTERRUPT STATUS
READ REGISTER ADDR. 0x0C
v 2 (t ) = 2 V sin(ωt ) × 2 V sin(ωt ) = V 2 − V 2 × cos(2ωt ) (63)
INTERRUPT?
NO
The square of the rms value is extracted from v2(t) by a low-pass
filter. The square root of the output of this low-pass filter gives
the rms value. An offset correction is provided to cancel noise
and offset contributions from the input.
YES
READ LINE ACCUMULATION ENERGY
ADDR. 0x04
There is ripple noise from the 2ω term because the low-pass
filter does not completely attenuate the signal. This noise can be
minimized by synchronizing the rms register readings with the
zero crossing of the voltage signal. The IRQ output can be
configured to indicate the zero crossing of the voltage signal.
CALCULATE PHCAL. SEE EQUATION 59.
WRITE PHCAL VALUE TO THE PHCAL
REGISTER: ADDR. 0x10
02875-A-011
This flowchart demonstrates how VRMS and IRMS readings
are synchronized to the zero crossings of the voltage input.
Figure 85. Calibrating Phase with an Accurate Source
For this example:
Meter Constant:
MeterConstant(imp/Wh)
= 3.2
Line Voltage:
Vnominal = 220 V
Line Frequency:
fl = 50 Hz
CF Numerator:
CFNUM = 0
CF Denominator:
CFDEN = 489
Base Current:
Ib = 10 A
Half Line Cycles Used at Base Current:
LINECYCIB = 2000
PERIOD Register:
PERIOD = 8959
Expected Line Accumulation at Unity Power Factor (from Watt
Gain Section:
LAENERGYIB(expected) =
19186
Active Energy Reading at PF = .5 inductive:
SET INTERRUPT ENABLE FOR ZERO
CROSSING ADDR. 0x0A = 0x0010
RESET THE INTERRUPT STATUS
READ REGISTER ADDR. 0x0C
INTERRUPT?
NO
YES
READ VRMS OR IRMS
ADDR. 0x17; 0x16
RESET THE INTERRUPT STATUS
READ REGISTER ADDR. 0x0C
02875-A-003
Figure 86. Synchronizing VRMS and IRMS Readings with Zero Crossings
Rev. C | Page 45 of 60
ADE7753
Apparent Energy
Voltage rms compensation is done after the LPF3 filter (see
Figure 56).
VRMS = VRMS0 + VRMSOS
(64)
Apparent energy gain calibration is provided for both meter-tometer gain adjustment and for setting the VAh/LSB constant.
where:
VAENERGY =
VRMS0 is the rms measurement without offset correction.
VRMS is linear from full-scale to full-scale/20.
VAENERGYinitial ×
To calibrate the offset, two VRMS measurements are required,
for example, at Vnominal and Vnominal/10. Vnominal is set at half of the
full-scale analog input range so the smallest linear VRMS
reading is at Vnominal/10.
VRMSOS =
V1 × VRMS 2 − V 2 × VRMS1
V 2 − V1
(65)
where VRMS1 and VRMS2 are rms register values without offset
correction for input V1 and V2, respectively.
If the range of the 12-bit, twos complement VRMSOS register is
not enough, the voltage channel offset register, CH2OS, can be
used to correct the VRMS offset.
Current rms compensation is performed before the square root:
IRMS2 = IRMS02 + 32768 × IRMSOS
(66)
(67)
where IRMS1 and IRMS2 are rms register values without offset
correction for input I1 and I2, respectively.
VAGAIN ⎞
⎟
2 12
⎠
(68)
Apparent energy gain calibration should be performed before
rms offset correction to make most efficient use of the current
test points. Apparent energy gain and watt gain compensation
require testing at Ib while rms and watt offset correction require
a lower test current. Apparent energy gain calibration can be
done at the same time as the watt-hour gain calibration using
line cycle accumulation. In this case, LAENERGY and
LVAENERGY, the line cycle accumulation apparent energy
register, are both read following the line cycle accumulation
interrupt. Figure 87 shows a flowchart for calibrating active and
apparent energy simultaneously.
⎛ ⎛ LVAENERGYIB(expected )
⎞
⎞
− 1⎟ × 212 ⎟ (69)
VAGAIN = INT ⎜ ⎜
⎟
⎜ ⎜ LVAENERGYIB(nominal )
⎟
⎠
⎝⎝
⎠
LVAENERGYIB(expected) =
To calibrate this offset, two IRMS measurements are required,
for example, at Ib and IMAX/50. IMAX is set at half of the full-scale
analog input range so the smallest linear IRMS reading is at
IMAX/50.
I 2 × IRMS 2 2 − I 2 2 × IRMS1 2
1
× 1
32768
I 2 2 − I12
× ⎛⎜1 +
⎝
VADIV is similar to the CFDEN for the watt hour calibration. It
should be the same across all meters and determines the VAh/LSB
constant. VAGAIN is used to calibrate individual meters.
where IRMS0 is the rms measurement without offset correction.
The current rms calculation is linear from full-scale to fullscale/100.
IRMSOS =
1
VADIV
⎛
⎞
⎜
⎟
Vnominal × I B
× Accumulation time(s) ⎟ (70)
INT ⎜
⎜ VAh
⎟
constant × 3600 s/h
⎜
⎟
⎝ LSB
⎠
The accumulation time is determined from Equation 37 and the
line period can be determined from the PERIOD register according to Equation 38. The VAh represented by the VAENERGY
register is
VAh = VAENERGY × VAh/LSB constant
(71)
The VAh/LSB constant can be verified using this equation:
VAh
Rev. C | Page 46 of 60
LSB constant =
VA ×
Accumulation time(s)
LVAENERGY
3600 (72)
ADE7753
CALCULATE CFDEN VALUE FOR DESIGN
WRITE CFDEN VALUE TO CFDEN REGISTER
ADDR. 0x15 = CFDEN
SET ITEST = Ib, VTEST = VNOM, PF = 1
SET HALF LINE CYCLES FOR ACCUMULATION
IN LINECYC REGISTER ADDR. 0x1C
SET MODE FOR LINE CYCLE
ACCUMULATION ADDR. 0x09 = 0x0080
ENABLE LINE CYCLE ACCUMULATION
INTERRUPT ADDR. 0x0A = 0x04
RESET THE INTERRUPT STATUS
READ REGISTER ADDR. = 0x0C
INTERRUPT?
NO
YES
RESET THE INTERRUPT STATUS
READ REGISTER ADDR. = 0x0C
INTERRUPT?
NO
YES
READ LINE ACCUMULATION ENERGY
ACTIVE ENERGY: ADDR. 0x04
APPARAENT ENERGY: ADDR. 0x07
CALCULATE WGAIN. SEE EQUATION 47.
WRITE WGAIN VALUE TO ADDR. 0x12
CALCULATE VAGAIN. SEE EQUATION 69.
WRITE VGAIN VALUE TO ADDR. 0x1A
02875-A-004
Figure 87. Active/Apparent Gain Calibration
Reactive Energy
Reactive energy is only available in line accumulation mode in
the ADE7753. The accumulated reactive energy over LINECYC
number of half line cycles is stored in the LVARENERGY register.
by comparing the nominal reactive energy accumulation rate to
the expected value. The attenuation correction factor is multiplied by the contents of the LVARENERGY register, with the
ADE7753 in line accumulation mode.
In the ADE7753, a low-pass filter at 2 Hz on the current
channel is implemented for the reactive power calculation. This
provides the 90 degree phase shift needed to calculate the reactive
power. This filter introduces 1/f attenuation in the reactive
energy accumulated. Compensation for this attenuation can be
done externally in a microcontroller. The microcontroller can
use the LVARENERGY register in order to produce a pulse
output similar to the CF pulse for reactive energy.
To create a VAR pulse, an impulse/VARh constant must be
determined. The 1/f attenuation correction factor is determined
Rev. C | Page 47 of 60
ADE7753
The impulse/LSB ratio used to convert the value in the
LVARENERGY register into a pulse output can be expressed in
terms of impulses/VARh and VARh/LSB.
imp/LSB = imp / VARh × VARh / LSB =
VARCFIB (expected )
VARCFnominal
VARCFIB(expected) =
VARConstant (imp / VARh) × Vnominal × I b
3600 s/h
VARCFIB(nominal) =
× sin(ϕ)
LVARENERGYIB × PERIOD 50 Hz
Accumulation time(s) × PERIOD
(73)
(74)
(75)
where the accumulation time is calculated from Equation 37.
The line period can be determined from the PERIOD register
according to Equation 38. Then VAR can be determined from
the LVARENERGY register value:
VARh =
LVARENERGYIB × VARh / LSB × PERIOD 50 Hz
PERIOD
VAR =
LVARENERGYIB × VARh / LSB × 3600 s/h PERIOD50 Hz
Accumulation time(s) × PERIOD
(76)
(77)
The PERIOD50 Hz/PERIOD factor in the preceding VAR equations
is the correction factor for the 1/f frequency attenuation of the
low-pass filter. The PERIOD50 Hz term refers to the line period at
calibration and could represent a frequency other than 50 Hz.
CLKIN FREQUENCY
In this data sheet, the characteristics of the ADE7753 are shown
when CLKIN frequency is equal to 3.579545 MHz. However, the
ADE7753 is designed to have the same accuracy at any CLKIN
frequency within the specified range. If the CLKIN frequency is
not 3.579545 MHz, various timing and filter characteristics need
to be redefined with the new CLKIN frequency. For example,
the cutoff frequencies of all digital filters such as LPF1, LPF2, or
HPF1, shift in proportion to the change in CLKIN frequency
according to the following equation:
New Frequency = Original Frequency ×
CLKIN Frequency
3.579545 MHz
Table 11. Frequency Dependencies of the ADE7753
Parameters
Parameter
Nyquist Frequency for CH 1 and CH 2 ADCs
PHCAL Resolution (Seconds per LSB)
Active Energy Register Update Rate (Hz)
Waveform Sampling Rate (per Second)
WAVSEL 1,0 =
00
01
10
11
Maximum ZXTOUT Period
CLKIN Dependency
CLKIN/8
4/CLKIN
CLKIN/4
CLKIN/128
CLKIN/256
CLKIN/512
CLKIN/1024
524,288/CLKIN
SUSPENDING ADE7753 FUNCTIONALITY
The analog and the digital circuit can be suspended separately.
The analog portion of the ADE7753 can be suspended by setting
the ASUSPEND bit (Bit 4) of the mode register to logic high—
see the Mode Register (0x9) section. In suspend mode, all waveform samples from the ADCs are set to 0. The digital circuitry
can be halted by stopping the CLKIN input and maintaining a
logic high or low on the CLKIN pin. The ADE7753 can be
reactivated by restoring the CLKIN input and setting the
ASUSPEND bit to logic low.
CHECKSUM REGISTER
The ADE7753 has a checksum register (CHECKSUM[5:0]) to
ensure the data bits received in the last serial read operation are
not corrupted. The 6-bit checksum register is reset before the
first bit (MSB of the register to be read) is put on the DOUT
pin. During a serial read operation, when each data bit becomes
available on the rising edge of SCLK, the bit is added to the
checksum register. In the end of the serial read operation, the
content of the checksum register is equal to the sum of all ones
in the register previously read. Using the checksum register, the
user can determine if an error has occurred during the last read
operation. Note that a read to the checksum register also
generates a checksum of the checksum register itself.
(78)
CONTENT OF REGISTER (n-bytes)
DOUT
+
The change of CLKIN frequency does not affect the timing
characteristics of the serial interface because the data transfer is
synchronized with serial clock signal (SCLK). But one needs to
observe the read/write timing of the serial data transfer—see
the ADE7753 timing characteristics in Table 2. Table 11 lists
various timing changes that are affected by CLKIN frequency.
Rev. C | Page 48 of 60
CHECKSUM REGISTER ADDR: 0x3E
+
02875-0-077
Figure 88. Checksum Register for Serial Interface Read
ADE7753
ADE7753 SERIAL INTERFACE
All ADE7753 functionality is accessible via several on-chip
registers—see Figure 89. The contents of these registers can be
updated or read using the on-chip serial interface. After poweron or toggling the RESET pin low or a falling edge on CS, the
ADE7753 is placed in communications mode. In communications mode, the ADE7753 expects a write to its communications
register. The data written to the communications register
determines whether the next data transfer operation is a read
or a write and also which register is accessed. Therefore all data
transfer operations with the ADE7753, whether a read or a write,
must begin with a write to the communications register.
DIN
DOUT
CS
SCLK
COMMUNICATIONS REGISTER WRITE
DIN
IN
OUT
REGISTER 2
IN
OUT
REGISTER 3
IN
OUT
REGISTER n–1
IN
OUT
REGISTER n
IN
OUT
ADDRESS
DOUT
MULTIBYTE
READ DATA
02875-0-079
Figure 90. Reading Data from the ADE7753 via the Serial Interface
CS
SCLK
COMMUNICATIONS REGISTER WRITE
DIN
1 0
ADDRESS
MULTIBYTE
READ DATA
02875-0-080
COMMUNICATIONS
REGISTER
REGISTER 1
0 0
Figure 91. Writing Data to the ADE7753 via the Serial Interface
REGISTER
ADDRESS
DECODE
02875-0-078
Figure 89. Addressing ADE7753 Registers via the Communications Register
The communications register is an 8-bit wide register. The MSB
determines whether the next data transfer operation is a read or
a write. The six LSBs contain the address of the register to be
accessed—see the Communications Register section for a more
detailed description.
Figure 90 and Figure 91 show the data transfer sequences for a
read and write operation, respectively. On completion of a data
transfer (read or write), the ADE7753 once again enters
communications mode. A data transfer is complete when the
LSB of the ADE7753 register being addressed (for a write or a
read) is transferred to or from the ADE7753.
The serial interface of the ADE7753 is made up of four signals:
SCLK, DIN, DOUT, and CS. The serial clock for a data transfer
is applied at the SCLK logic input. This logic input has a
Schmitt-trigger input structure that allows slow rising (and
falling) clock edges to be used. All data transfer operations are
synchronized to the serial clock. Data is shifted into the
ADE7753 at the DIN logic input on the falling edge of SCLK.
Data is shifted out of the ADE7753 at the DOUT logic output
on a rising edge of SCLK. The CS logic input is the chip-select
input. This input is used when multiple devices share the serial
bus. A falling edge on CS also resets the serial interface and
places the ADE7753 into communications mode. The CS input
should be driven low for the entire data transfer operation.
Bringing CS high during a data transfer operation aborts the
transfer and places the serial bus in a high impedance state. The
CS logic input can be tied low if the ADE7753 is the only device
on the serial bus. However, with CS tied low, all initiated data
transfer operations must be fully completed, i.e., the LSB of each
register must be transferred because there is no other way of
bringing the ADE7753 back into communications mode
without resetting the entire device by using RESET.
Rev. C | Page 49 of 60
ADE7753
ADE7753 Serial Write Operation
The serial write sequence takes place as follows. With the
ADE7753 in communications mode (i.e., the CS input logic
low), a write to the communications register first takes place.
The MSB of this byte transfer is a 1, indicating that the data
transfer operation is a write. The LSBs of this byte contain the
address of the register to be written to. The ADE7753 starts
shifting in the register data on the next falling edge of SCLK. All
remaining bits of register data are shifted in on the falling edge
of subsequent SCLK pulses—see Figure 92. As explained earlier,
the data write is initiated by a write to the communications
register followed by the data. During a data write operation to
the ADE7753, data is transferred to all on-chip registers one
byte at a time. After a byte is transferred into the serial port,
there is a finite time before it is transferred to one of the
ADE7753 on-chip registers. Although another byte transfer to
the serial port can start while the previous byte is being
transferred to an on-chip register, this second byte transfer
should not finish until at least 4 μs after the end of the previous
byte transfer. This functionality is expressed in the timing
specification t6—see Figure 92. If a write operation is aborted
during a byte transfer (CS brought high), then that byte cannot
be written to the destination register.
Destination registers can be up to 3 bytes wide—see the
ADE7753 Register Description tables. Therefore the first byte
shifted into the serial port at DIN is transferred to the MSB
(most significant byte) of the destination register. If, for
example, the addressed register is 12 bits wide, a 2-byte data
transfer must take place. The data is always assumed to be right
justified, therefore in this case, the four MSBs of the first byte
would be ignored and the four LSBs of the first byte written to
the ADE7753 would be the four MSBs of the 12-bit word.
Figure 93 illustrates this example.
t8
CS
t1
t6
t3
t7
t7
SCLK
t4
t2
1
DIN
0
A5
A4
t5
A3
A2
A1
DB7
A0
DB0
MOST SIGNIFICANT BYTE
COMMAND BYTE
DB0
DB7
LEAST SIGNIFICANT BYTE
02875-0-081
Figure 92. Serial Interface Write Timing
SCLK
DIN
X
X
X
X
DB11 DB10
DB9
DB8
DB7
MOST SIGNIFICANT BYTE
DB6
DB5
DB4
DB3
DB2
DB1
DB0
LEAST SIGNIFICANT BYTE
02875-0-082
Figure 93. 12-Bit Serial Write Operation
Rev. C | Page 50 of 60
ADE7753
ADE7753 Serial Read Operation
During a data read operation from the ADE7753, data is shifted
out at the DOUT logic output on the rising edge of SCLK. As is
the case with the data write operation, a data read must be
preceded with a write to the communications register.
high impedance state on the falling edge of the last SCLK pulse.
The read operation can be aborted by bringing the CS logic
input high before the data transfer is complete. The DOUT
output enters a high impedance state on the rising edge of CS.
With the ADE7753 in communications mode (i.e., CS logic
low), an 8-bit write to the communications register first takes
place. The MSB of this byte transfer is a 0, indicating that the
next data transfer operation is a read. The LSBs of this byte
contain the address of the register that is to be read. The
ADE7753 starts shifting out of the register data on the next
rising edge of SCLK—see Figure 94. At this point, the DOUT
logic output leaves its high impedance state and starts driving
the data bus. All remaining bits of register data are shifted out
on subsequent SCLK rising edges. The serial interface also
enters communications mode again as soon as the read has
been completed. At this point, the DOUT logic output enters a
When an ADE7753 register is addressed for a read operation,
the entire contents of that register are transferred to the serial
port. This allows the ADE7753 to modify its on-chip registers
without the risk of corrupting data during a multibyte transfer.
Note that when a read operation follows a write operation, the
read command (i.e., write to communications register) should
not happen for at least 4 μs after the end of the write operation.
If the read command is sent within 4 μs of the write operation,
the last byte of the write operation could be lost. This timing
constraint is given as timing specification t9.
CS
t1
t13
t9
SCLK
DIN
0
0
A5
A4
A3
A2
A1
t10
A0
DOUT
DB7
COMMAND BYTE
t12
t11
t11
DB0
MOST SIGNIFICANT BYTE
DB7
DB0
LEAST SIGNIFICANT BYTE
02875-0-083
Figure 94. Serial Interface Read Timing
Rev. C | Page 51 of 60
ADE7753
ADE7753 REGISTERS
Table 12. Summary of Registers by Address
Type 1
Address
Name
R/W
No. Bits
Default
0x01
WAVEFORM
R
24
0x0
S
0x02
AENERGY
R
24
0x0
S
0x03
RAENERGY
R
24
0x0
S
0x04
LAENERGY
R
24
0x0
S
0x05
VAENERGY
R
24
0x0
U
0x06
RVAENERGY
R
24
0x0
U
0x07
LVAENERGY
R
24
0x0
U
0x08
LVARENERGY
R
24
0x0
S
0x09
MODE
R/W
16
0x000C
U
0x0A
IRQEN
R/W
16
0x40
U
0x0B
STATUS
R
16
0x0
U
0x0C
RSTSTATUS
R
16
0x0
U
0x0D
CH1OS
R/W
8
0x00
S*
0x0E
CH2OS
R/W
8
0x0
S*
0x0F
GAIN
R/W
8
0x0
U
0x10
PHCAL
R/W
6
0x0D
S
0x11
APOS
R/W
16
0x0
S
Description
Waveform Register. This read-only register contains the sampled waveform
data from either Channel 1, Channel 2, or the active power signal. The data
source and the length of the waveform registers are selected by data
Bits 14 and 13 in the mode register—see the Channel 1 Sampling and
Channel 2 Sampling sections.
Active Energy Register. Active power is accumulated (integrated) over time
in this 24-bit, read-only register—see the Energy Calculation section.
Same as the active energy register except that the register is reset to 0
following a read operation.
Line Accumulation Active Energy Register. The instantaneous active power
is accumulated in this read-only register over the LINECYC number of half
line cycles.
Apparent Energy Register. Apparent power is accumulated over time in this
read-only register.
Same as the VAENERGY register except that the register is reset to 0
following a read operation.
Line Accumulation Apparent Energy Register. The instantaneous real power
is accumulated in this read-only register over the LINECYC number of half
line cycles.
Line Accumulation Reactive Energy Register. The instantaneous reactive
power is accumulated in this read-only register over the LINECYC number
of half line cycles.
Mode Register. This is a 16-bit register through which most of the ADE7753
functionality is accessed. Signal sample rates, filter enabling, and
calibration modes are selected by writing to this register. The contents can
be read at any time—see the Mode Register (0x9) section.
Interrupt Enable Register. ADE7753 interrupts can be deactivated at any time
by setting the corresponding bit in this 16- bit enable register to Logic 0.
The status register continues to register an interrupt event even if disabled.
However, the IRQ output is not activated—see the ADE7753 Interrupts
section.
Interrupt Status Register. This is an 16-bit read-only register. The status
register contains information regarding the source of ADE7753
interrupts—the see ADE7753 Interrupts section.
Same as the interrupt status register except that the register contents are
reset to 0 (all flags cleared) after a read operation.
Channel 1 Offset Adjust. Bit 6 is not used. Writing to Bits 0 to 5 allows
offsets on Channel 1 to be removed—see the Analog Inputs and CH1OS
Register (0x0D) sections. Writing a Logic 1 to the MSB of this register
enables the digital integrator on Channel 1, a Logic 0 disables the
integrator. The default value of this bit is 0.
Channel 2 Offset Adjust. Bits 6 and 7 are not used. Writing to Bits 0 to 5 of
this register allows any offsets on Channel 2 to be removed—see the
Analog Inputs section. Note that the CH2OS register is inverted. To apply a
positive offset, a negative number is written to this register.
PGA Gain Adjust. This 8-bit register is used to adjust the gain selection for
the PGA in Channels 1 and 2—see the Analog Inputs section.
Phase Calibration Register. The phase relationship between Channel 1 and
2 can be adjusted by writing to this 6-bit register. The valid content of this
twos compliment register is between 0x1D to 0x21. At a line frequency of
60 Hz, this is a range from –2.06° to +0.7°—see the Phase Compensation
section.
Active Power Offset Correction. This 16-bit register allows small offsets in
the active power calculation to be removed—see the Active Power
Calculation section.
Rev. C | Page 52 of 60
ADE7753
Type 1
Address
Name
R/W
No. Bits
Default
0x12
WGAIN
R/W
12
0x0
S
0x13
WDIV
R/W
8
0x0
U
0x14
CFNUM
R/W
12
0x3F
U
0x15
CFDEN
R/W
12
0x3F
U
0x16
0x17
0x18
0x19
0x1A
IRMS
VRMS
IRMSOS
VRMSOS
VAGAIN
R
R
R/W
R/W
R/W
24
24
12
12
12
0x0
0x0
0x0
0x0
0x0
U
U
S
S
S
0x1B
VADIV
R/W
8
0x0
U
0x1C
LINECYC
R/W
16
0xFFFF
U
0x1D
ZXTOUT
R/W
12
0xFFF
U
0x1E
SAGCYC
R/W
8
0xFF
U
0x1F
SAGLVL
R/W
8
0x0
U
0x20
IPKLVL
R/W
8
0xFF
U
0x21
VPKLVL
R/W
8
0xFF
U
0x22
IPEAK
R
24
0x0
U
0x23
RSTIPEAK
R
24
0x0
U
0x24
VPEAK
R
24
0x0
U
0x25
RSTVPEAK
R
24
0x0
U
0x26
TEMP
R
8
0x0
S
Description
Power Gain Adjust. This is a 12-bit register. The active power calculation can
be calibrated by writing to this register. The calibration range is ±50% of
the nominal full-scale active power. The resolution of the gain adjust is
0.0244%/LSB —see the Calibrating an Energy Meter Based on the ADE7753
section.
Active Energy Divider Register. The internal active energy register is divided
by the value of this register before being stored in the AENERGY register.
CF Frequency Divider Numerator Register. The output frequency on the CF
pin is adjusted by writing to this 12-bit read/write register—see the Energyto-Frequency Conversion section.
CF Frequency Divider Denominator Register. The output frequency on the
CF pin is adjusted by writing to this 12-bit read/write register—see the
Energy-to-Frequency Conversion section.
Channel 1 RMS Value (Current Channel).
Channel 2 RMS Value (Voltage Channel).
Channel 1 RMS Offset Correction Register.
Channel 2 RMS Offset Correction Register.
Apparent Gain Register. Apparent power calculation can be calibrated by
writing to this register. The calibration range is 50% of the nominal fullscale real power. The resolution of the gain adjust is 0.02444%/LSB.
Apparent Energy Divider Register. The internal apparent energy register is
divided by the value of this register before being stored in the VAENERGY
register.
Line Cycle Energy Accumulation Mode Line-Cycle Register. This 16-bit
register is used during line cycle energy accumulation mode to set the
number of half line cycles for energy accumulation—see the Line Cycle
Energy Accumulation Mode section.
Zero-Crossing Timeout. If no zero crossings are detected on Channel 2
within a time period specified by this 12-bit register, the interrupt request
line (IRQ) is activated—see the Zero-Crossing Detection section.
Sag Line Cycle Register. This 8-bit register specifies the number of
consecutive line cycles the signal on Channel 2 must be below SAGLVL
before the SAG output is activated—see the Line Voltage Sag Detection
section.
Sag Voltage Level. An 8-bit write to this register determines at what peak
signal level on Channel 2 the SAG pin becomes active. The signal must
remain low for the number of cycles specified in the SAGCYC register
before the SAG pin is activated—see the Line Voltage Sag Detection
section.
Channel 1 Peak Level Threshold (Current Channel). This register sets the
level of the current peak detection. If the Channel 1 input exceeds this
level, the PKI flag in the status register is set.
Channel 2 Peak Level Threshold (Voltage Channel). This register sets the
level of the voltage peak detection. If the Channel 2 input exceeds this
level, the PKV flag in the status register is set.
Channel 1 Peak Register. The maximum input value of the current channel
since the last read of the register is stored in this register.
Same as Channel 1 Peak Register except that the register contents are reset
to 0 after read.
Channel 2 Peak Register. The maximum input value of the voltage channel
since the last read of the register is stored in this register.
Same as Channel 2 Peak Register except that the register contents are reset
to 0 after a read.
Temperature Register. This is an 8-bit register which contains the result of
the latest temperature conversion—see the Temperature Measurement
section.
Rev. C | Page 53 of 60
ADE7753
Type 1
Address
Name
R/W
No. Bits
Default
0x27
PERIOD
R
16
0x0
U
0x28–
0x3C
0x3D
0x3E
Period of the Channel 2 (Voltage Channel) Input Estimated by ZeroCrossing Processing. The MSB of this register is always zero.
Reserved.
TMODE
CHKSUM
R/W
R
8
6
–
0x0
U
U
0x3F
DIEREV
R
8
–
U
Test Mode Register.
Checksum Register. This 6-bit read-only register is equal to the sum of all
the ones in the previous read—see the ADE7753 Serial Read Operation
section.
Die Revision Register. This 8-bit read-only register contains the revision
number of the silicon.
1
Description
Type decoder: U = unsigned, S = signed by twos complement method, and S* = signed by sign magnitude method.
Rev. C | Page 54 of 60
ADE7753
ADE7753 REGISTER DESCRIPTIONS
All ADE7753 functionality is accessed via the on-chip registers. Each register is accessed by first writing to the communications register
and then transferring the register data. A full description of the serial interface protocol is given in the ADE7753 Serial Interface section.
COMMUNICATIONS REGISTER
The communications register is an 8-bit, write-only register which controls the serial data transfer between the ADE7753 and the host
processor. All data transfer operations must begin with a write to the communications register. The data written to the communications
register determines whether the next operation is a read or a write and which register is being accessed. Table 13 outlines the bit
designations for the communications register.
DB7
W/R
DB6
0
DB5
A5
DB4
A4
DB3
A3
DB2
A2
DB1
A1
DB0
A0
Table 13. Communications Register
Bit Location
0 to 5
Bit Mnemonic
A0 to A5
6
7
RESERVED
W/R
Description
The six LSBs of the communications register specify the register for the data transfer operation.
Table 12 lists the address of each ADE7753 on-chip register.
This bit is unused and should be set to 0.
When this bit is a Logic 1, the data transfer operation immediately following the write to the
communications register is interpreted as a write to the ADE7753.
When this bit is a Logic 0, the data transfer operation immediately following the write to the
communications register is interpreted as a read operation.
MODE REGISTER (0x09)
The ADE7753 functionality is configured by writing to the mode register. Table 14 describes the functionality of each bit in the register.
Table 14. Mode Register
Bit Location
0
1
2
3
4
Bit Mnemonic
DISHPF
DISLPF2
DISCF
DISSAG
ASUSPEND
Default
Value
0
0
1
1
0
5
TEMPSEL
0
6
SWRST
0
7
8
9
10
CYCMODE
DISCH1
DISCH2
SWAP
0
0
0
0
12, 11
DTRT1, 0
00
Description
HPF (high-pass filter) in Channel 1 is disabled when this bit is set.
LPF (low-pass filter) after the multiplier (LPF2) is disabled when this bit is set.
Frequency output CF is disabled when this bit is set.
Line voltage sag detection is disabled when this bit is set.
By setting this bit to Logic 1, both ADE7753 A/D converters can be turned off.
In normal operation, this bit should be left at Logic 0. All digital functionality can be
stopped by suspending the clock signal at CLKIN pin.
Temperature conversion starts when this bit is set to 1. This bit is automatically reset to 0
when the temperature conversion is finished.
Software Chip Reset. A data transfer should not take place to the ADE7753 for at least
18 μs after a software reset.
Setting this bit to Logic 1 places the chip into line cycle energy accumulation mode.
ADC 1 (Channel 1) inputs are internally shorted together.
ADC 2 (Channel 2) inputs are internally shorted together.
By setting this bit to Logic 1 the analog inputs V2P and V2N are connected to ADC 1 and
the analog inputs V1P and V1N are connected to ADC 2.
These bits are used to select the waveform register update rate.
DTRT 1
DTRT0
Update Rate
0
0
27.9 kSPS (CLKIN/128)
0
1
14 kSPS (CLKIN/256)
1
0
7 kSPS (CLKIN/512)
1
1
3.5 kSPS (CLKIN/1024)
Rev. C | Page 55 of 60
ADE7753
Bit Location
14, 13
Bit Mnemonic
WAVSEL1, 0
Default
Value
00
Description
These bits are used to select the source of the sampled data for the waveform register.
WAVSEL1, 0
0
0
15
POAM
0
Length
0
1
Source
24 bits active power signal (output of LPF2)
Reserved
1
0
24 bits Channel 1
1
1
24 bits Channel 2
Writing Logic 1 to this bit allows only positive active power to be accumulated in the ADE7753.
15 14 13 12 11 10
0
0
0
0
0
0
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
1
1
0
0
ADDR: 0x09
DISHPF
(DISABLE HPF1 IN CHANNEL 1)
POAM
(POSITIVE ONLY ACCUMULATION)
WAVSEL
(WAVEFORM SELECTION FOR SAMPLE MODE)
00 = LPF2
01 = RESERVED
10 = CH1
11 = CH2
DISLPF2
(DISABLE LPF2 AFTER MULTIPLIER)
DISCF
(DISABLE FREQUENCY OUTPUT CF)
DISSAG
(DISABLE SAG OUTPUT)
DTRT
(WAVEFORM SAMPLES OUTPUT DATA RATE)
00 = 27.9kSPS (CLKIN/128)
01 = 14.4kSPS (CLKIN/256)
10 = 7.2kSPS (CLKIN/512)
11 = 3.6kSPS (CLKIN/1024)
ASUSPEND
(SUSPEND CH1 AND CH2 ADCs)
TEMPSEL
(START TEMPERATURE SENSING)
SWAP
(SWAP CH1 AND CH2 ADCs)
SWRST
(SOFTWARE CHIP RESET)
DISCH2
(SHORT THE ANALOG INPUTS ON CHANNEL 2)
CYCMODE
(LINE CYCLE ENERGY ACCUMULATION MODE)
DISCH1
(SHORT THE ANALOG INPUTS ON CHANNEL 1)
NOTE: REGISTER CONTENTS SHOW POWER-ON DEFAULTS
Figure 95. Mode Register
Rev. C | Page 56 of 60
02875-0-084
ADE7753
INTERRUPT STATUS REGISTER (0x0B), RESET INTERRUPT STATUS REGISTER (0x0C),
INTERRUPT ENABLE REGISTER (0x0A)
The status register is used by the MCU to determine the source of an interrupt request (IRQ). When an interrupt event occurs in the
ADE7753, the corresponding flag in the interrupt status register is set to logic high. If the enable bit for this flag is Logic 1 in the interrupt
enable register, the IRQ logic output goes active low. When the MCU services the interrupt, it must first carry out a read from the
interrupt status register to determine the source of the interrupt.
Table 15. Interrupt Status Register, Reset Interrupt Status Register, and Interrupt Enable Register
Bit Location
0
1
2
Interrupt Flag
AEHF
SAG
CYCEND
3
4
WSMP
ZX
5
6
TEMP
RESET
7
8
9
A
B
C
AEOF
PKV
PKI
VAEHF
VAEOF
ZXTO
D
E
F
PPOS
PNEG
RESERVED
Description
Indicates that an interrupt occurred because the active energy register, AENERGY, is more than half full.
Indicates that an interrupt was caused by a SAG on the line voltage.
Indicates the end of energy accumulation over an integer number of half line cycles as defined by
the content of the LINECYC register—see the Line Cycle Energy Accumulation Mode section.
Indicates that new data is present in the waveform register.
This status bit is set to Logic 0 on the rising and falling edge of the the voltage waveform.
See the Zero-Crossing Detection section.
Indicates that a temperature conversion result is available in the temperature register.
Indicates the end of a reset (for both software or hardware reset). The corresponding enable bit has no
function in the interrupt enable register, i.e., this status bit is set at the end of a reset, but it cannot
be enabled to cause an interrupt.
Indicates that the active energy register has overflowed.
Indicates that waveform sample from Channel 2 has exceeded the VPKLVL value.
Indicates that waveform sample from Channel 1 has exceeded the IPKLVL value.
Indicates that an interrupt occurred because the active energy register, VAENERGY, is more than half full.
Indicates that the apparent energy register has overflowed.
Indicates that an interrupt was caused by a missing zero crossing on the line voltage for the specified
number of line cycles—see the Zero-Crossing Timeout section.
Indicates that the power has gone from negative to positive.
Indicates that the power has gone from positive to negative.
Reserved.
15 14 13 12 11 10
0
0
0
0
0
0
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
ADDR: 0x0A, 0x0B, 0x0C
AEHF
(ACTIVE ENERGY HALF-FULL)
RESERVED
PNEG
(POWER POSITIVE TO NEGATIVE)
SAG
(SAG ONLINE VOLTAGE)
PPOS
(POWER NEGATIVE TO POSITIVE)
CYCEND
(END OF LINECYC HALF LINE CYCLES)
WSMP
(WAVEFORM SAMPLES DATA READY)
ZXTO
(ZERO-CROSSING TIMEOUT)
ZX
(ZERO CROSSING)
VAEOF
(VAENERGY OVERFLOW)
TEMPL
(TEMPERATURE DATA READY)
VAEHF
(VAENERGY IS HALF-FULL)
PK1
(CHANNEL 1 SAMPLE ABOVE IPKLVL)
RESET
(END OF SOFTWARE/HARDWARE RESET)
PKV
(CHANNEL 2 SAMPLE ABOVE VPKLVL)
AEOF
(ACTIVE ENERGY REGISTER OVERFLOW)
02875-A-013
Figure 96. Interrupt Status/Interrupt Enable Register
Rev. C | Page 57 of 60
ADE7753
CH1OS REGISTER (0x0D)
The CH1OS register is an 8-bit, read/write enabled register. The MSB of this register is used to switch on/off the digital integrator in
Channel 1, and Bits 0 to 5 indicates the amount of the offset correction in Channel 1. Table 16 summarizes the function of this register.
Table 16. CH1OS Register
Bit Location
0 to 5
Bit Mnemonic
OFFSET
6
7
Not Used
INTEGRATOR
Description
The six LSBs of the CH1OS register control the amount of dc offset correction in Channel 1 ADC. The
6-bit offset correction is sign and magnitude coded. Bits 0 to 4 indicate the magnitude of the offset
correction. Bit 5 shows the sign of the offset correction. A 0 in Bit 5 means the offset correction is
positive and a 1 indicates the offset correction is negative.
This bit is unused.
This bit is used to activate the digital integrator on Channel 1. The digital integrator is switched on by
setting this bit. This bit is set to be 0 on default.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
ADDR: 0x0D
DIGITAL INTEGRATOR SELECTION
1 = ENABLE
0 = DISABLE
SIGN AND MAGNITUDE CODED
OFFSET CORRECTION BITS
NOT USED
02875-0-086
Figure 97. Channel 1 Offset Register
Rev. C | Page 58 of 60
ADE7753
OUTLINE DIMENSIONS
7.50
7.20
6.90
11
20
5.60
5.30
5.00
1
8.20
7.80
7.40
10
0.65 BSC
0.38
0.22
SEATING
PLANE
8°
4°
0°
0.95
0.75
0.55
COMPLIANT TO JEDEC STANDARDS MO-150-AE
060106-A
0.05 MIN
COPLANARITY
0.10
0.25
0.09
1.85
1.75
1.65
2.00 MAX
Figure 98. 20-Lead Shrink Small Outline Package [SSOP]
(RS-20)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
ADE7753ARS
ADE7753ARSRL
ADE7753ARSZ
ADE7753ARSZRL
EVAL-ADE7753ZEB
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
20-Lead Shrink Small Outline Package [SSOP]
20-Lead Shrink Small Outline Package [SSOP]
20-Lead Shrink Small Outline Package [SSOP]
20-Lead Shrink Small Outline Package [SSOP]
Evaluation Board
Z = RoHS Compliant Part.
Rev. C | Page 59 of 60
Package Option
RS-20
RS-20
RS-20
RS-20
ADE7753
NOTES
©2003–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D02875-0-1/10(C)
Rev. C | Page 60 of 60