LINER LT4356CS-3TR Surge stopper with fault latchoff Datasheet

LT4356-3
Surge Stopper with
Fault Latchoff
FEATURES
DESCRIPTION
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The LT®4356-3 surge stopper protects loads from high
voltage transients. It regulates the output during an
overvoltage event, such as load dump in automobiles,
by controlling the gate of an external N-channel MOSFET.
The output is limited to a safe value thereby allowing the
loads to continue functioning. The LT4356-3 also monitors
the voltage drop between the VCC and SNS pins to protect
against overcurrent faults. An internal amplifier limits
the current sense voltage to 50mV. In either fault condition, a timer is started inversely proportional to MOSFET
stress. If the timer expires, the FLT pin pulls low to warn
of an impending power down. If the condition persists,
the MOSFET is turned off, until the SHDN pin pulls low
momentarily.
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Stops High Voltage Surges
Adjustable Output Clamp Voltage
Overcurrent Protection
Wide Operation Range: 4V to 80V
Reverse Input Protection to –60V
Low 7μA Shutdown Current
Adjustable Latchoff Fault Timer
Controls N-channel MOSFET
Shutdown Pin Withstands –60V to 100V
Fault Output Indication
Spare Amplifier for Level Detection Comparator or
Linear Regulator Controller
Available in (4mm × 3mm) 12-Pin DFN,
10-Pin MSOP or 16-Pin SO Packages
APPLICATIONS
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Automotive/Avionic Surge Protection
Hot Swap/Live Insertion
High Side Switch for Battery Powered Systems
Intrinsic Safety Applications
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
The spare amplifier may be used as a voltage detection
comparator or as a linear regulator controller driving an
external PNP pass transistor.
Back-to-back FETs can be used in lieu of a Schottky diode
for reverse input protection, reducing voltage drop and
power loss. A shutdown pin reduces the quiescent current
to less than 7μA during shutdown.
TYPICAL APPLICATION
4A, 12V Overvoltage Output Regulator
10mΩ
VIN
12V
IRLR2908
VOUT
80V INPUT SURGE
10Ω
383k
Overvoltage Protector Regulates Output at
27V During Transient
VCC
SNS
GATE
CTMR = 6.8μF
ILOAD = 500mA
102k
VIN
20V/DIV
OUT
FB
SHDN
IN+
4.99k
LT4356DE-3
100k
SHDN GND
EN
UNDERVOLTAGE
AOUT
GND
TMR
VCC
DC-DC
CONVERTER
FLT
FAULT
12V
27V ADJUSTABLE CLAMP
VOUT
20V/DIV
12V
100ms/DIV
LT4356-3TA01b
43563 TA01
0.1μF
43563f
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LT4356-3
ABSOLUTE MAXIMUM RATINGS (Notes 1 and 2)
VCC, SHDN ................................................ –60V to 100V
SNS............................. VCC – 30V or –60V to VCC + 0.3V
OUT, AOUT, FLT, EN...................................... –0.3V to 80V
GATE (Note 3) .................................–0.3V to VOUT + 10V
FB, TMR, IN+ ................................................ –0.3V to 6V
AOUT, EN, FLT, IN+...................................................–3mA
Operating Temperature Range
LT4356C-3 ............................................... 0°C to 70°C
LT4356I-3 ............................................ –40°C to 85°C
Storage Temperature Range
DE12 .................................................. –65°C to 125°C
MS, SO .............................................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)
MS, SO ............................................................. 300°C
PIN CONFIGURATION
TOP VIEW
TOP VIEW
TMR
1
12 IN+
FB
2
11 AOUT
OUT
3
10 GND
GATE
4
9
EN
SNS
5
8
FLT
VCC
6
7
SHDN
13
TOP VIEW
FB
OUT
GATE
SNS
VCC
1
2
3
4
5
10
9
8
7
6
TMR
GND
EN
FLT
SHDN
MS PACKAGE
10-LEAD PLASTIC MSOP
TJMAX = 125°C, θJA = 120°C/W
DE PACKAGE
12-LEAD (4mm s 3mm) PLASTIC DFN
TJMAX = 125°C, θJA = 43°C/W
EXPOSED PAD (PIN 13) PCB GND CONNECTION OPTIONAL
TMR 1
16 IN+
FB 2
15 NC
NC 3
14 AOUT
OUT 4
GATE 5
13 NC
12 GND
NC 6
11 EN
SNS 7
10 FLT
VCC 8
9
SHDN
S PACKAGE
16-LEAD PLASTIC SO
TJMAX = 150°C, θJA = 100°C/W
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT4356CDE-3#PBF
LT4356CDE-3#TRPBF
43563
12-Lead (4mm × 3mm) Plastic DFN
0°C to 70°C
LT4356IDE-3#PBF
LT4356IDE-3#TRPBF
43563
12-Lead (4mm × 3mm) Plastic DFN
–40°C to 85°C
LT4356CMS-3#PBF
LT4356CMS-3#TRPBF
LTFFK
10-Lead Plastic MSOP
0°C to 70°C
LT4356IMS-3#PBF
LT4356IMS-3#TRPBF
LTFFK
10-Lead Plastic MSOP
–40°C to 85°C
LT4356CS-3#PBF
LT4356CS-3#TRPBF
LT4356S-3
16-Lead Plastic SO
0°C to 70°C
LT4356IS-3#PBF
LT4356IS-3#TRPBF
LT4356S-3
16-Lead Plastic SO
–40°C to 85°C
LEAD BASED FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT4356CDE-3
LT4356CDE-3#TR
43563
12-Lead (4mm × 3mm) Plastic DFN
0°C to 70°C
LT4356IDE-3
LT4356IDE-3#TR
43563
12-Lead (4mm × 3mm) Plastic DFN
–40°C to 85°C
LT4356CMS-3
LT4356CMS-3#TR
LTFFK
10-Lead Plastic MSOP
0°C to 70°C
LT4356IMS-3
LT4356IMS-3#TR
LTFFK
10-Lead Plastic MSOP
–40°C to 85°C
LT4356CS-3
LT4356CS-3#TR
LT4356S-3
16-Lead Plastic SO
0°C to 70°C
LT4356IS-3
LT4356CS-3#TR
LT4356S-3
16-Lead Plastic SO
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
43563f
2
LT4356-3
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 12V unless otherwise noted.
SYMBOL
PARAMETER
VCC
ICC
Operating Voltage Range
VCC Supply Current
IR
Reverse Input Current
ΔVGATE
GATE Pin Output High Voltage
IGATE(UP)
GATE Pin Pull-Up Current
IGATE(DN)
GATE Pin Pull-Down Current
VFB
IFB
FB Pin Servo Voltage
FB Pin Input Current
Overcurrent Fault Threshold
ΔVSNS
ISNS
ILEAK
ITMR
SNS Pin Input Current
FLT, EN Pins Leakage Current
AOUT Pin Leakage Current
TMR Pin Pull-up Current
TMR Pin Pull-down Current
VTMR
ΔVTMR
VIN+
IIN+
VOL
IOUT
TMR Pin Thresholds
Early Warning Period
IN+ Pin Threshold
IN+ Pin Input Current
FLT, EN, AOUT Pins Output Low
OUT Pin Input Current
CONDITIONS
MIN
l
TYP
4
MAX
UNITS
80
1.5
25
30
1
2
8
16
–36
–50
1.275
1
55
56
V
mA
μA
μA
mA
mA
V
V
μA
μA
mA
mA
mA
V
μA
mV
mV
μA
μA
μA
μA
μA
μA
μA
μA
μA
VSHDN = Float
VSHDN = 0V, IN+ = 1.3V
l
VSNS = VCC = –30V, SHDN Open
VSNS = VCC = VSHDN = –30V
VCC = 4V; (VGATE – VOUT)
80V ≥ VCC ≥ 8V; (VGATE – VOUT)
VGATE = 12V; VCC = 12V
VGATE = 48V; VCC = 48V
Overvoltage, VFB = 1.4V, VGATE = 12V
Overcurrent, VCC – VSNS = 120mV, VGATE = 12V
Shutdown Mode, VSHDN = 0V, VGATE = 12V
VGATE = 12V; VOUT = 12V
VFB = 1.25V
l
l
ΔVSNS = (VCC – VSNS), VCC = 12V
ΔVSNS = (VCC – VSNS), VCC = 48V
VSNS = VCC = 12V to 48V
FLT, EN = 80V
AOUT = 80V
VTMR = 1V, VFB = 1.5V, (VCC – VOUT) = 0.5V
VTMR = 1V, VFB = 1.5V, (VCC – VOUT) = 75V
VTMR = 1.3V, VFB = 1.5V
VTMR = 1V, ΔVSNS = 60mV, (VCC – VOUT) = 0.5V
VTMR = 1V, ΔVSNS = 60mV, (VCC – VOUT) = 80V
l
l
45
46
–23
–30
150
10
5
1.25
0.3
50
51
l
5
10
VTMR = 1V, VFB = 1V, ΔVSNS = 0V
FLT From High to Low, VCC = 5V to 80V
From FLT going Low to GATE going Low, VCC = 5V to 80V
l
–1.5
–44
–3.5
–2.5
–195
1.5
–2.5
–50
–5.5
–4.5
–260
2.2
22
2.5
4.5
–4
–56
–8.5
–6.5
–315
2.7
l
1.22
80
1.25
100
1.28
120
V
mV
l
1.22
1.25
0.3
2
300
200
6
1.28
1
8
800
300
14
V
μA
V
mV
μA
mA
VIN+ = 1.25V
ISINK = 2mA
ISINK = 0.1mA
VOUT = VCC = 12V
VOUT = VCC = 12V, VSHDN = 0V
1
7
7
0.3
0.8
l
l
l
l
l
l
l
l
l
4.5
10
–4
–4.5
75
5
1.5
1.225
l
l
l
l
l
l
l
l
l
l
l
l
l
43563f
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LT4356-3
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 12V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
ΔVOUT
VSHDN
OUT Pin High Threshold
ΔVOUT = VCC – VOUT; EN From Low to High
VCC = 12V to 48V
l
VCC = 12V to 48V
VSHDN = 0V
l
GATE From High to Low, ΔVSNS = 0 → 120mV
GATE From High to Low, VFB = 0 → 1.5V
SHDN Pin Threshold
VSHDN(FLT) SHDN Pin Float Voltage
SHDN Pin Current
ISHDN
Overcurrent Turn Off Delay Time
tOFF(OC)
Overvoltage Turn Off Delay Time
tOFF(OV)
MIN
TYP
MAX
UNITS
0.25
0.5
0.7
V
0.6
0.4
0.6
–1
1.4
l
1.2
–4
2
1.7
2.1
2
–8
4
V
V
V
μA
μs
l
0.25
1
μs
l
l
Note 3: An internal clamp limits the GATE pin to a minimum of 10V above
the OUT pin. Driving this pin to voltages beyond the clamp may damage
the device.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to GND unless otherwise
specified.
TYPICAL PERFORMANCE CHARACTERISTICS
Specifications are at VCC = 12V, TA = 25°C unless otherwise noted.
ICC vs VCC
ICC (Shutdown) vs VCC
1000
800
ICC (Shutdown) vs Temperature
60
35
50
30
25
400
ICC (μA)
600
ICC (μA)
ICC (μA)
40
30
20
200
0
10
20
30
40 50
VCC (V)
60
70
80
43563 G02
15
10
10
0
20
5
0
0
10
20
30
40 50
VCC (V)
60
70
80
43563 G01
0
–50
–25
25
75
0
50
TEMPERATURE (°C)
100
125
43563 G03
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LT4356-3
TYPICAL PERFORMANCE CHARACTERISTICS
Specifications are at VCC = 12V, TA = 25°C unless otherwise noted.
SHDN Current vs Temperature
6
GATE Pull-Up Current vs
Temperature
GATE Pull-Up Current vs VCC
VSHDN = 0V
5
40
35
35
30
30
3
25
25
IGATE (μA)
IGATE (μA)
ISHDN (μA)
4
20
15
2
–25
25
75
0
50
TEMPERATURE (°C)
100
0
125
0
10
43563 G04
GATE Pull-Down Current vs
Temperature
220
12
OVERVOLTAGE CONDITION
VFB = 1.5V
30
40 50
VCC (V)
60
70
0
–50
80
160
140
120
0
50
25
75
TEMPERATURE (°C)
100
125
14
OVERCURRENT CONDITION
ΔVSNS = 120mV
43563 G07
VOUT = 12V
12
10
8
6
4
0
–50
125
ΔVGATE vs IGATE
8
6
4
2
–25
100
43563 G06
ΔVGATE (V)
180
0
50
25
75
TEMPERATURE (°C)
–25
43563 G05
10
IGATE(DOWN) (mA)
IGATE(DOWN) (mA)
20
GATE Pull-Down Current vs
Temperature
200
100
–50
15
5
5
0
–50
20
10
10
1
VGATE = VOUT = 12V
2
–25
25
75
0
50
TEMPERATURE (°C)
100
125
43563 G08
0
0
2
4
6
10
8
IGATE (μA)
12
14
16
43563 G09
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5
LT4356-3
TYPICAL PERFORMANCE CHARACTERISTICS
Specifications are at VCC = 12V, TA = 25°C unless otherwise noted.
ΔVGATE vs Temperature
14
OVERVOLTAGE CONDITION
VOUT = 5V
40 VTMR = 1V
TA = 130°C
14
VCC = 8V
12
8
6
VCC = 4V
4
TA = –45°C
10
32
TA = 25°C
ITMR (μA)
ΔVGATE (V)
10
ΔVGATE (V)
48
16
IGATE = –1μA
12
8
6
24
16
4
2
0
–50
–25
0
50
25
75
TEMPERATURE (°C)
100
2 I
GATE = –1μA
VOUT = VCC
0
0
10 20
125
8
0
30
43563 G10
40 50
VCC (V)
60
70
3.0
160
120
6
4
40
2
10
20
30 40 50
VCC – VOUT (V)
60
70
80
43563 G13
70
80
43563 G12
VTMR = 1V
1.5
1.0
0.5
0
0
60
2.0
8
80
30 40 50
VCC – VOUT (V)
2.5
ITMR (μA)
ITMR (μA)
200
20
TMR Pull-Down Current vs
Temperature
OVERVOLTAGE, EARLY
WARNING PERIOD
12 VFB = 1.5V
VTMR = 1.3V
10
OVERCURRENT CONDITION
VOUT = 0V
240 VTMR = 1V
10
43563 G11
14
280
0
0
80
Warning Period
TMR Current vs VCC
Overcurrent TMR Current vs
(VCC – VOUT)
ITMR (μA)
Overvoltage TMR Current vs
(VCC – VOUT)
ΔVGATE vs VCC
0
10
20
30
40 50
VCC (V)
60
70
80
43563 G14
0
–50
–25
0
25
50
75
TEMPERATURE (°C)
100
125
43563 G15
43563f
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LT4356-3
TYPICAL PERFORMANCE CHARACTERISTICS
Specifications are at VCC = 12V, TA = 25°C unless otherwise noted.
Overvoltage Turn-Off Time vs
Temperature
Output Low Voltage vs Current
4.0
500
3.5
AOUT
400
3.0
FLT
2.0
tOFF (ns)
VOL (V)
2.5
OVERVOLTAGE CONDITION
VFB = 1.5V
EN
1.5
1.0
300
200
100
0.5
0
0
0.5
2.0
1.0
1.5
CURRENT (mA)
2.5
0
–50
3.0
–25
0
25
50
75
TEMPERATURE (°C)
43563 G16
125
43563 G17
Reverse Current vs Reverse
Voltage
Overcurrent Turn-Off Time vs
Temperature
4.0
100
–20
OVERCURRENT CONDITION
ΔVSNS = 120mV
VCC = SNS
3.5
–15
ICC (mA)
tOFF (μs)
3.0
2.5
–10
2.0
–5
1.5
1.0
–50
–25
0
25
50
75
TEMPERATURE (°C)
100
125
43563 G18
0
0
–20
–40
–60
–80
VCC (V)
43563 G19
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LT4356-3
PIN FUNCTIONS
AOUT : Amplifier Output. Open collector output of the auxiliary amplifier. It is capable of sinking up to 2mA from 80V.
The negative input of the amplifier is internally connected
to a 1.25V reference.
OUT: Output Voltage Sense Input. This pin senses the
voltage at the source of the N-channel MOSFET and sets
the fault timer current. When the OUT pin voltage reaches
0.7V away from VCC, the EN pin goes high impedance.
EN: Open-Collector Enable Output. The EN pin goes high
impedance when the voltage at the OUT pin is above (VCC
– 0.7V), indicating the external MOSFET is fully on. The
state of the pin is latched until the OUT pin voltage resets
at below 0.5V and goes back up above 2V. The internal
NPN is capable of sinking up to 3mA of current from 80V
to drive an LED or opto-coupler.
SHDN: Shutdown Control Input. The LT4356-3 can be
shut down to a low current mode by pulling the SHDN
pin below the shutdown threshold of 0.6V. Pull this pin
above 1.7V or disconnect it and allow the internal current
source to turn the part back on. After GATE pin pulls low
due to fault time out, the part can be restarted by pulling the SHDN pin low for at least 100μs and pulled high
with a slew rate faster than 10V/ms. The leakage current
to ground at the pin should be limited to no more than
1μA if no pull up device is used to turn the part on. The
SHDN pin can be pulled up to 100V or below GND by 60V
without damage.
Exposed Pad: Exposed pad may be left open or connected
to device ground (GND).
FB: Voltage Regulator Feedback Input. Connect this pin
to the center tap of the output resistive divider connected
between the OUT pin and ground. During an overvoltage
condition, the GATE pin is servoed to maintain a 1.25V
threshold at the FB pin. This pin is clamped internally to
7V. Tie to GND to disable the OV clamp.
FLT: Open-Collector Fault Output. This pin pulls low
after the voltage at the TMR pin has reached the fault
threshold of 1.25V. It indicates the pass transistor is
about to turn off because either the supply voltage has
stayed at an elevated level for an extended period of
time (voltage fault) or the device is in an overcurrent
condition (current fault). The internal NPN is capable of
sinking up to 3mA of current from 80V to drive an LED or
opto-coupler.
GATE: N-Channel MOSFET Gate Drive Output. The GATE pin
is pulled up by an internal charge pump current source and
clamped to 14V above the OUT pin. Both voltage and current amplifiers control the GATE pin to regulate the output
voltage and limit the current through the MOSFET.
GND: Device Ground.
IN+: Positive Input of the Auxiliary Amplifier. This amplifier
can be used as a level detection comparator with external
hysteresis or linear regulator controlling an external PNP
transistor. This pin is clamped internally to 7V. Connect
to ground if unused.
SNS: Current Sense Input. Connect this pin to the output of
the current sense resistor. The current limit circuit controls
the GATE pin to limit the sense voltage between VCC and
SNS pins to 50mV. At the same time the sense amplifier
also starts a current source to charge up the TMR pin.
This pin can be pulled below GND by up to 60V, though
the voltage difference with the VCC pin must be limited to
less than 30V. Connect to VCC if unused.
TMR: Fault Timer Input. Connect a capacitor between this
pin and ground to set the times for early warning and fault
periods. The current charging up this pin during fault
conditions depends on the voltage difference between the
VCC and OUT pins. When VTMR reaches 1.25V, the FLT pin
pulls low to indicate the detection of a fault condition. If
the condition persists, the pass transistor turns off when
VTMR reaches the threshold of 1.35V. The GATE pin remains
low even after the fault condition has disappeared and the
voltage at the TMR pin has reached 0.5V.
VCC: Positive Supply Voltage Input. The positive supply
input ranges from 4V to 80V for normal operation. It
can also be pulled below ground potential by up to 60V
during a reverse battery condition, without damaging the
part. The supply current is reduced to 7μA with all the
functional blocks off.
43563f
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LT4356-3
BLOCK DIAGRAM
VCC
GATE
+
–
14V
CHARGE
PUMP
+
OUT
FB
+
50mV
SNS
–
VA
IA
1.25V
–
SHDN
FLT
AOUT
OC
1.25V
AUXILLARY
AMPLIFIER
SHDN
OUT
OV
EN
CONTROL
LOGIC
GATEOFF
FLT
–
+
IN+
1.35V
–
VCC
+
0.5V
+
ITMR
–
+
2μA
1.25V
TMR
–
GND
43563 BD
43563f
9
LT4356-3
OPERATION
Some power systems must cope with high voltage surges
of short duration such as those in automobiles. Load
circuitry must be protected from these transients, yet
high availability systems must continue operating during
these events.
The potential at the TMR pin starts decreasing as soon
as the overvoltage condition disappears, but the GATE
pin remains low even when the voltage at the TMR pin
reaches 0.5V. Pulling the SHDN pin low momentarily will
turn the GATE pin back on.
The LT4356-3 is an overvoltage protection regulator that
drives an external N-channel MOSFET as the pass transistor. It operates from a wide supply voltage range of 4V to
80V. It can also be pulled below ground potential by up
to 60V without damage. The low power supply requirement of 4V allows it to operate even during cold cranking
conditions in automotive applications. The internal charge
pump turns on the N-channel MOSFET to supply current
to the loads with very little power loss. Two MOSFETs can
be connected back to back to replace an inline Schottky
diode for reverse input protection. This improves the efficiency and increases the available supply voltage level
to the load circuitry during cold crank.
The fault timer allows the loads to continue functioning
during short transient events while protecting the MOSFET
from being damaged by a long period of supply overvoltage,
such as a load dump in automobiles. The timer period varies with the voltage across the MOSFET. A higher voltage
corresponds to a shorter fault timer period, ensuring the
MOSFET operates within its safe operating area (SOA).
Normally, the pass transistor is fully on, powering the
loads with very little voltage drop. When the supply voltage surges too high, the voltage amplifier (VA) controls
the gate of the MOSFET and regulates the voltage at the
source pin to a level that is set by the external resistor
divider from the OUT pin to ground and the internal 1.25V
reference. A current source starts charging up the capacitor connected at the TMR pin to ground. If the voltage at
the TMR pin, VTMR, reaches 1.25V, the FLT pin pulls low
to indicate impending turn-off due to the overvoltage
condition. The pass transistor stays on until the TMR
pin reaches 1.35V, at which point the GATE pin pulls low
turning off the MOSFET.
The LT4356-3 senses an overcurrent condition by monitoring the voltage across an optional sense resistor placed
between the VCC and SNS pins. An active current limit
circuit (IA) controls the GATE pin to limit the sense voltage to 50mV. A current is also generated to start charging
up the TMR pin. This current is about 5 times the current
generated during an overvoltage event. The FLT pin pulls
low when the voltage at the TMR pin reaches 1.25V and
the MOSFET is turned off when it reaches 1.35V.
A spare amplifier (SA) is provided with the negative input
connected to an internal 1.25V reference. The output pull
down device is capable of sinking up to 2mA of current
allowing it to drive an LED or opto coupler. This amplifier
can be configured as a linear regulator controller driving
an external PNP transistor or a comparator function to
monitor voltages.
The SHDN pin turns off the pass transistor and reduces
the supply current to less than 7μA.
43563f
10
LT4356-3
APPLICATIONS INFORMATION
The LT4356-3 can limit the voltage and current to the load
circuitry during supply transients or overcurrent events.
The total fault timer period should be set to ride through
short overvoltage transients while not causing damage
to the pass transistor. The selection of this N-channel
MOSFET pass transistor is critical for this application.
It must stay on and provide a low impedance path from
the input supply to the load during normal operation and
then dissipate power during overvoltage or overcurrent
conditions.
The following sections describe the overcurrent and the
overvoltage faults, and the selection of the timer capacitor
value based on the required warning time. The selection
of the N-channel MOSFET pass transistor is discussed
next. Auxiliary amplifier, reverse input, and the shutdown
functions are covered after the MOSFET selection. External
component selection is discussed in detail in the Design
Example section.
Overvoltage Fault
The LT4356-3 limits the voltage at the OUT pin during an
overvoltage situation. An internal voltage amplifier regulates the GATE pin voltage to maintain a 1.25V threshold at
the FB pin. During this period of time, the power MOSFET
is still on and continues to supply current to the load. This
allows uninterrupted operation during short overvoltage
transient events.
When the voltage regulation loop is engaged for longer
than the time-out period, set by the timer capacitor connected from the TMR pin to ground, an overvoltage fault
is detected. The GATE pin is pulled down to the OUT pin
by a 150mA current. This prevents the power MOSFET
from being damaged during a long period of overvoltage,
such as during load dump in automobiles. Pulling the
SHDN pin low for at least 100μs and pulled high with a
slew rate faster than 10V/ms will allow the GATE pin to
pull back up.
Overcurrent Fault
The LT4356-3 features an adjustable current limit that
protects against short circuits or excessive load current.
During an overcurrent event, the GATE pin is regulated to
limit the current sense voltage across the VCC and SNS
pins to 50mV.
An overcurrent fault occurs when the current limit circuitry
has been engaged for longer than the time-out delay set
by the timer capacitor. The GATE pin is then immediately
pulled low by a 10mA current to GND turning off the
MOSFET. The GATE pin stays low until the SHDN pin is
pulled low for at least 100μs and pulled high with a slew
rate faster than 10V/ms.
Fault Timer
The LT4356-3 includes an adjustable fault timer pin. Connecting a capacitor from the TMR pin to ground sets the
delay timer period before the MOSFET is turned off. The
same capacitor also sets the cool down period before the
MOSFET is allowed to turn back on after the fault condition
has disappeared.
Once a fault condition, either overvoltage or overcurrent,
is detected, a current source charges up the TMR pin. The
current level varies depending on the voltage drop across
the drain and source terminals of the power MOSFET(VDS),
which is typically from the VCC pin to the OUT pin. This
scheme takes better advantage of the available Safe Operating Area (SOA) of the MOSFET than would a fixed timer
current. The timer function operates down to VCC = 5V
across the whole temperature range.
43563f
11
LT4356-3
APPLICATIONS INFORMATION
Fault Timer Current
The timer current starts at around 2μA with 0.5V or less
of VDS, increasing linearly to 50μA with 75V of VDS during an overvoltage fault (Figure 1). During an overcurrent
fault, it starts at 4μA with 0.5V or less of VDS but increases
to 260μA with 80V across the MOSFET (Figure 2). This
arrangement allows the pass transistor to turn off faster
during an overcurrent event, since more power is dissipated
during this condition. Refer to the Typical Performance
Characteristics section for the timer current at different
VDS in both overvoltage and overcurrent events.
When the voltage at the TMR pin, VTMR, reaches the 1.25V
threshold, the FLT pin pulls low to indicate the detection
of a fault condition and provide warning to the load of
the impending power loss. In the case of an overvoltage
fault, the timer current then switches to a fixed 5μA. The
interval between FLT asserting low and the MOSFET turning off is given by:
t WARNING =
CTMR • 100mV
5μA
VTMR(V)
ITMR = 5μA
ITMR = 5μA
1.35
1.25
VDS = 75V
(ITMR = 50μA)
VDS = 10V
(ITMR = 8μA)
0.50
TIME
tFLT
= 15ms/μF
tWARNING
= 20ms/μF
tFLT = 93.75ms/μF
tWARNING
= 20ms/μF
TOTAL FAULT TIMER = tFLT + tWARNING
43563 F01
Figure 1. Overvoltage Fault Timer Current
VTMR(V)
1.35
1.25
VDS = 80V
(ITMR = 260μA)
0.50
tFLT
= 2.88ms/μF
VDS = 10V
(ITMR = 35μA)
TIME
tWARNING
= 0.38ms/μF
tFLT = 21.43ms/μF
TOTAL FAULT TIMER = tFLT + tWARNING
tWARNING
= 2.86ms/μF
43563 F02
Figure 2. Overcurrent Fault Timer Current
43563f
12
LT4356-3
APPLICATIONS INFORMATION
This fixed early warning period allows the systems to perform necessary backup or house keeping functions before
the power supply is cut off. After VTMR crosses the 1.35V
threshold, the pass transistor turns off immediately. Note
that during an overcurrent event, the timer current is not
reduced to 5μA after VTMR has reached 1.25V threshold,
since it would lengthen the overall fault timer period and
cause more stress on the power MOSFET.
As soon as the fault condition has disappeared, a 2μA
current discharges the timer capacitor back to 0.5V. Once
the TMR pin returns to 0.5V, the fault condition may be
reset by pulling SHDN low for at least 100μs and pulled
high with a slew rate faster than 10V/ms. The FLT output
goes high when the fault condition is reset.
MOSFET Selection
The LT4356-3 drives an N-channel MOSFET to conduct the
load current. The important features of the MOSFET are
on-resistance RDS(ON), the maximum drain-source voltage
V(BR)DSS, the threshold voltage, and the SOA.
The maximum allowable drain-source voltage must be
higher than the supply voltage. If the output is shorted
to ground or during an overvoltage event, the full supply
voltage will appear across the MOSFET.
The gate drive for the MOSFET is guaranteed to be more
than 10V and less than 16V for those applications with VCC
higher than 8V. This allows the use of standard threshold
voltage N-channel MOSFETs. For systems with VCC less
than 8V, a logic level MOSFET is required since the gate
drive can be as low as 4.5V.
The SOA of the MOSFET must encompass all fault conditions. In normal operation the pass transistor is fully on,
dissipating very little power. But during either overvoltage
or overcurrent faults, the GATE pin is servoed to regulate either the output voltage or the current through the
MOSFET. Large current and high voltage drop across the
MOSFET can coexist in these cases. The SOA curves of
the MOSFET must be considered carefully along with the
selection of the fault timer capacitor.
Transient Stress in the MOSFET
During an overvoltage event, the LT4356-3 drives a series
pass MOSFET to regulate the output voltage at an acceptable
level. The load circuitry may continue operating throughout
this interval, but only at the expense of dissipation in the
MOSFET pass device. MOSFET dissipation or stress is a
function of the input voltage waveform, regulation voltage
and load current. The MOSFET must be sized to survive
this stress.
Most transient event specifications use the model shown
in Figure 3. The idealized waveform comprises a linear
ramp of rise time tr, reaching a peak voltage of VPK and
exponentially decaying back to VIN with a time constant
of t. A common automotive transient specification has
constants of tr = 10μs, VPK = 80V and τ = 1ms. A surge
condition known as “load dump” has constants of tr = 5ms,
VPK = 60V and τ = 200ms.
VPK
T
VIN
tr
43563 F03
Figure 3. Prototypical Transient Waveform
43563f
13
LT4356-3
APPLICATIONS INFORMATION
MOSFET stress is the result of power dissipated within
the device. For long duration surges of 100ms or more,
stress is increasingly dominated by heat transfer; this is
a matter of device packaging and mounting, and heatsink
thermal mass. This is analyzed by simulation, using the
MOSFET thermal model.
For short duration transients of less than 100ms, MOSFET
survival is increasingly a matter of safe operating area
(SOA), an intrinsic property of the MOSFET. SOA quantifies the time required at any given condition of VDS and
ID to raise the junction temperature of the MOSFET to its
rated maximum. MOSFET SOA is expressed in units of
watt-squared-seconds (P2t). This figure is essentially constant for intervals of less than 100ms for any given device
type, and rises to infinity under DC operating conditions.
Destruction mechanisms other than bulk die temperature
distort the lines of an accurately drawn SOA graph so that
P2t is not the same for all combinations of ID and VDS.
In particular P2t tends to degrade as VDS approaches the
maximum rating, rendering some devices useless for
absorbing energy above a certain voltage.
VPK
T
VREG
VIN
tr
43563 F04
Figure 4. Safe Operating Area Required to Survive Prototypical
Transient Waveform
Typically VREG ≈ VIN and τ >> tr simplyfying the above to
P2 t =
1
2
ILOAD 2 ( VPK – VREG ) τ
2
(W 2 S )
For the transient conditions of VPK = 80V, VIN = 12V, VREG
= 16V, tr = 10μs and τ = 1ms, and a load current of 3A, P2t
is 18.4W2s—easily handled by a MOSFET in a D-pak package. The P2t of other transient waveshapes is evaluated by
integrating the square of MOSFET power versus time.
Calculating Short-Circuit Stress
Calculating Transient Stress
To select a MOSFET suitable for any given application, the
SOA stress must be calculated for each input transient
which shall not interrupt operation. It is then a simple matter
to chose a device which has adequate SOA to survive the
maximum calculated stress. P2t for a prototypical transient
waveform is calculated as follows (Figure 4).
Let
a = VREG – VIN
b = VPK – VIN
(VIN = Nominal Input Voltage)
Then
⎤
⎡ 1 ( b – a )3
⎥
⎢ tr
+
2 ⎢3
2
b
⎥
P t = ILOAD
⎥
⎢1 ⎛ 2 b
⎞
2
2
⎢ τ ⎜ 2a ln + 3a + b − 4ab⎟ ⎥
⎠⎦
a
⎣2 ⎝
SOA stress must also be calculated for short-circuit conditions. Short-circuit P2t is given by:
P2t = (VIN • ΔVSNS/RSNS)2 • tTMR
(W2s)
where, ΔVSNS is the SENSE pin threshold, and tTMR is the
overcurrent timer interval.
For VIN = 14.7V, VSNS = 50mV, RSNS = 12mΩ and CTMR
= 100nF, P2t is 6.6W2s—less than the transient SOA
calculated in the previous example. Nevertheless, to
account for circuit tolerances this figure should be doubled
to 13.2W2s.
Limiting Inrush Current and GATE Pin Compensation
The LT4356-3 limits the inrush current to any load capacitance by controlling the GATE pin voltage slew rate. An
external capacitor can be connected from GATE to ground
to slow down the inrush current further at the expense of
slower turn-off time. The gate capacitor is set at:
C1 =
IGATE(UP)
IINRUSH
•CL
43563f
14
LT4356-3
APPLICATIONS INFORMATION
The LT4356-3 does not need extra compensation components at the GATE pin for stability during an overvoltage or
overcurrent event. However, with fast, high voltage transient
steps at the input, a gate capacitor, C1, to ground is needed
to prevent turn-on of the N-channel MOSFET.
The extra gate capacitance slows down the turn off time
during fault conditions and may allow excessive current
during an output short event. An extra resistor, R1, in series
with the gate capacitor can improve the turn off time. A
diode, D1, should be placed across R1 with the cathode
connected to C1 as shown in Figure 5.
Q1
D1
IN4148W
R3
R1
C1
GATE
LT4356-3
43563 F05
Figure 5
Auxiliary Amplifier
An uncommitted amplifier is included in the LT4356-3 to
provide flexibility in the system design. With the negative
input connected internally to the 1.25V reference, the amplifier can be connected as a level detect comparator with
external hysteresis. The open collector output pin, AOUT,
is capable of driving an opto or LED. It can also interface
with the system via a pull-up resistor to a supply voltage
up to 80V.
The amplifier can also be configured as a low dropout
linear regulator controller. With an external PNP transistor,
such as 2N2905A, it can supply up to 100mA of current
with only a few hundred mV of dropout voltage. Current
limit can be easily included by adding two diodes and one
resistor (Figure 6).
2N2905A OR
BCP53
*4.7Ω
INPUT
R6
100k
OUTPUT
* OPTIONAL FOR
CURRENT LIMIT
D1*
BAV99
11
AOUT
LT4356DE-3
43563 F06
Figure 6. Auxiliary LDO Output with Optional Current Limit
Reverse Input Protection
A blocking diode is commonly employed when reverse
input potential is possible, such as in automotive applications. This diode causes extra power loss, generates heat,
and reduces the available supply voltage range. During
cold crank, the extra voltage drop across the diode is
particularly undesirable.
The LT4356-3 is designed to withstand reverse voltage
without damage to itself or the load. The VCC, SNS, and
SHDN pins can withstand up to 60V of DC voltage below
the GND potential. Back-to-back MOSFETs must be used
to eliminate the current path through their body diodes
(Figure 7). Figure 8 shows the approach with a P-Channel
MOSFET in place of Q2.
RSNS
10mΩ
VIN
12V
Q2
IRLR2908
D2*
SMAJ58CA
Q3
2N3904
D1
1N4148
6
Q1
IRLR2908
R4 R5
10Ω 1M
VOUT
12V, 3A
CLAMPED
AT 16V
R3
10Ω
R1
59k
R7
10k
5
SNS
4
GATE
VCC
3
OUT
FB
2
R2
4.99k
LT4356DE-3
7
11
12
SHDN
FLT
AOUT
IN+
GND
10
*DIODES INC.
EN
TMR
1
8
9
43563 F07
CTMR
0.1μF
Figure 7. Overvoltage Regulator with N-channel MOSFET
Reverse Input Protection
43563f
15
LT4356-3
APPLICATIONS INFORMATION
RSNS
10mΩ
VIN
12V
Q2
Si4435
Q1
IRLR2908
VOUT
12V, 3A
CLAMPED AT 16V
D1
1N5245
15V
D2*
SMAJ58CA
R3
10Ω
R6
10k
5
SNS
6
4
GATE
6
R2
4.99k
7
11
12
SHDN
FLT
IN
+
GND
EN
TMR
10
*DIODES INC.
1
R3
10Ω
5
4
3
SNS GATE OUT
R4
383k
7
12
VCC
FB
IN+
8
UNDERVOLTAGE
LT4356DE-3
AOUT
GND
10
9
Figure 8. Overvoltage Regulator with P-Channel MOSFET
Reverse Input Protection
Shutdown
The LT4356-3 can be shut down to a low current mode
when the voltage at the SHDN pin goes below the shutdown
threshold of 0.6V. The quiescent current drops to 7μA.
The SHDN pin can be pulled up to VCC or below GND by
up to 60V without damaging the pin. Leaving the pin open
allows an internal current source to pull it up and turn
on the part while clamping the pin to 2.5V. The leakage
current at the pin should be limited to no more than 1μA
if no pull up device is used to help turn it on.
Supply Transient Protection
The LT4356-3 is 100% tested and guaranteed to be safe
from damage with supply voltages up to 80V. Nevertheless, voltage transients above 100V may cause permanent
damage. During a short-circuit condition, the large change
in current flowing through power supply traces and associated wiring can cause inductive voltage transients which
could exceed 100V. To minimize the voltage transients, the
power trace parasitic inductance should be minimized by
using wide traces. A small surge suppressor, D2, in Figure
9, at the input will clamp the voltage spikes.
TMR
1
FLT
9
8
VCC
DC-DC
CONVERTER
SHDN GND
FAULT
43563 F09
CTMR
47nF
43563 F08
CTMR
0.1μF
2
R2
4.99k
EN
11
R1
59k
SHDN
R5
100k
LT4356DE-3
AOUT
CL*
22μF
D2
SMAJ58A
3
OUT
2
Q1
IRLR2908
VIN
R1
59k
FB
VCC
RSNS
10mΩ
*SANYO 25CE22GA
Figure 9. Overvoltage Regulator with Low-Battery Detection
A total bulk capacitance of at least 22μF low ESR is required
close to the source pin of MOSFET Q1. In addition, the
bulk capacitance should be at least 10 times larger than
the total ceramic bypassing capacitor on the input of the
DC/DC converter.
Layout Considerations
To achieve accurate current sensing, Kelvin connection
to the current sense resistor (RSNS in Figure 9) is recommended. The minimum trace width for 1oz copper foil is
0.02" per amp to ensure the trace stays at a reasonable
temperature. 0.03" per amp or wider is recommended.
Note that 1oz copper exhibits a sheet resistance of about
530μΩ/square. Small resistances can cause large errors in
high current applications. Noise immunity will be improved
significantly by locating resistive dividers close to the pins
with short VCC and GND traces.
Design Example
As a design example, take an application with the following specifications: VCC = 8V to 14V DC with transient up
to 80V, VOUT ≤ 16V, current limit (ILIM) at 5A, low battery
detection at 6V, and 1ms of overvoltage early warning
(Figure 9).
43563f
16
LT4356-3
APPLICATIONS INFORMATION
First, calculate the resistive divider value to limit VOUT to
16V during an overvoltage event:
VREG =
1.25V • (R1 + R2)
= 16V
R2
Set the current through R1 and R2 during the overvoltage
condition to 250μA.
Finally, calculate R4 and R5 for the 6V low battery threshold
detection:
6V =
Choose 100kΩ for R5.
R4 =
1.25V
R2 =
= 5kΩ
250μA
1.25V • (R4 + R5)
R5
(6V – 1.25V ) • R5
1.25V
= 380kΩ
Select 383kΩ for R4.
Choose 4.99kΩ for R2.
R1 =
(16V – 1.25V ) • R2
1.25V
= 58.88kΩ
The closest standard value for R1 is 59kΩ.
Next calculate the sense resistor, RSNS, value:
RSNS =
50mV 50mV
=
= 10mΩ
ILIM
5A
CTMR is then chosen for 1ms of early warning time:
CTMR =
1ms • 5μA
= 50nF
100mV
The pass transistor, Q1, should be chosen to withstand
the output short condition with VCC = 14V.
The total overcurrent fault time is:
tOC =
47nF • 0.85V
= 0.878ms
45.5μA
The power dissipation on Q1 equals to:
P=
14V • 50mV
= 70W
10mΩ
These conditions are well within the Safe Operating Area
of IRLR2908.
The closest standard value for CTMR is 47nF.
43563f
17
LT4356-3
TYPICAL APPLICATIONS
Wide Input Range 5V to 28V Hot Swap with Undervoltage Lockout
RSNS
0.02Ω
Q1
SUD50N03-10
VIN
VOUT
100μF
R6
118k
R3
10Ω
C1
47nF
SNS
VCC
GATE
OUT
SHDN
FB
AOUT
IN+
LT4356DE-3
R7
49.9k
FLT
GND
EN
TMR
43563 TA10
CTMR
1μF
24V Overvoltage Regulator Withstands 150V at VIN
VIN
24V
Q1
IRF640
R9
1k
1W
VOUT
CLAMPED AT 32V
R3
10Ω
5
SNS
6
4
GATE
VCC
FB
D2*
SMAT70A
2
R2
4.99k
7
SHDN
8
FLT
9
LT4356DE-3
EN
GND
10
*DIODES INC.
R1
118k
3
OUT
TMR
1
43563 TA05
CTMR
0.1μF
43563f
18
LT4356-3
TYPICAL APPLICATIONS
Overvoltage Regulator with Low Battery Detection and Output Keep Alive During Shutdown
1k
0.5W
RSNS
10mΩ
VIN
12V
D2*
SMAJ58A
Q1
IRLR2908
R3
10Ω
R4
402k
6
12
R5
105k
7
5
SNS
4
GATE
VOUT
12V, 4A
CLAMPED AT 16V
Q2
VN2222
3
OUT
VCC
FB
LT4356DE-3
AOUT
SHDN
FLT
GND
EN
TMR
10
2
R2
VDD
24.9k
R6
47k
IN+
*DIODES INC.
R1
294k
D1
1N4746A
18V
1W
1
11
LBO
8
9
43563 TA03
CTMR
0.1μF
2.5A, 48V Hot Swap with Overvoltage Output Regulation at 72V and UV Shutdown at 35V
RSNS
15mΩ
VIN
48V
Q1
FDB3632
D2*
SMAT70A
R4
140k
R3
10Ω
VOUT
48V
2.5A
R6
100k
CL
300μF
C1
6.8nF
D1
1N4714
BV = 33V
7
6
VCC
5
4
SNS GATE
3
OUT
12
IN+
SHDN
R5
4.02k
R8
47k
LT4356DE-3
8
9
*DIODES INC.
FB
2
R1
226k
R2
4.02k
FLT
EN
R7
1M
GND
10
TMR
1
AOUT
11
PWRGD
43563 TA06
CTMR
0.1μF
43563f
19
LT4356-3
TYPICAL APPLICATIONS
2.5A, 28V Hot Swap with Overvoltage Output Regulation at 36V and UV Shutdown at 15V
RSNS
15mΩ
VIN
28V
Q1
FDB3632
D2*
SMAT70A
R4
113k
R3
10Ω
VOUT
28V
2.5A
R6
27k
CL
300μF
C1
6.8nF
D1
1N4700
BV = 13V
7
6
VCC
5
4
SNS GATE
3
OUT
R7
1M
12
IN+
SHDN
R5
4.02k
R8
47k
LT4356DE-3
8
9
FB
R1
110k
2
R2
4.02k
FLT
EN
*DIODES INC.
GND
AOUT
TMR
10
11
PWRGD
43563 TA07
1
CTMR
0.1μF
Overvoltage Regulator with Reverse Input Protection Up to –80V
RSNS
10mΩ
Q2
IRLR2908
VIN
12V
D2*
R4 SMAJ58CA
10Ω
Q3
2N3904
R5
1M
6
D1
1N4148
Q1
IRLR2908
5
SNS
VCC
R7
10k
VOUT
12V, 3A
CLAMPED
AT 16V
R3
10Ω
4
GATE
3
OUT
FB
2
R1
59k
R2
4.99k
LT4356DE-3
7
11
12
*DIODES INC.
SHDN
FLT
AOUT
IN+
GND
10
EN
TMR
1
8
9
43563 TA09
CTMR
0.1μF
43563f
20
LT4356-3
DE/UE Package
12-Lead Plastic DFN (4mm × 3mm)
(Reference LTC DWG # 05-08-1695 Rev D)
0.70 p0.05
3.60 p0.05
2.20 p0.05
3.30 p0.05
1.70 p 0.05
PACKAGE OUTLINE
0.25 p 0.05
0.50 BSC
2.50 REF
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
4.00 p0.10
(2 SIDES)
7
R = 0.115
TYP
0.40 p 0.10
12
R = 0.05
TYP
PIN 1
TOP MARK
(NOTE 6)
0.200 REF
3.00 p0.10
(2 SIDES)
3.30 p0.10
1.70 p 0.10
PIN 1 NOTCH
R = 0.20 OR
0.35 s 45o
CHAMFER
0.75 p0.05
6
0.25 p 0.05
1
(UE12/DE12) DFN 0806 REV D
0.50 BSC
2.50 REF
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE A VARIATION OF VERSION
(WGED) IN JEDEC PACKAGE OUTLINE M0-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
43563f
21
LT4356-3
MS Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661)
0.889 ± 0.127
(.035 ± .005)
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
0.50
0.305 ± 0.038
(.0197)
(.0120 ± .0015)
BSC
TYP
RECOMMENDED SOLDER PAD LAYOUT
0.254
(.010)
10 9 8 7 6
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
4.90 ± 0.152
(.193 ± .006)
DETAIL “A”
0.497 ± 0.076
(.0196 ± .003)
REF
0° – 6° TYP
GAUGE PLANE
1 2 3 4 5
0.53 ± 0.152
(.021 ± .006)
DETAIL “A”
0.86
(.034)
REF
1.10
(.043)
MAX
0.18
(.007)
SEATING
PLANE
0.17 – 0.27
(.007 – .011)
TYP
0.50
(.0197)
BSC
0.1016 ± 0.0508
(.004 ± .002)
MSOP (MS) 0307 REV E
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
43563f
22
LT4356-3
PACKAGE DESCRIPTION
S Package
16-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
.386 – .394
(9.804 – 10.008)
NOTE 3
.045 p.005
.050 BSC
16
N
15
14
13
12
11
10
9
N
.245
MIN
.160 p.005
.150 – .157
(3.810 – 3.988)
NOTE 3
.228 – .244
(5.791 – 6.197)
1
.030 p.005
TYP
2
3
N/2
N/2
RECOMMENDED SOLDER PAD LAYOUT
1
.010 – .020
s 45o
(0.254 – 0.508)
2
3
4
5
6
.053 – .069
(1.346 – 1.752)
.008 – .010
(0.203 – 0.254)
NOTE:
1. DIMENSIONS IN
.014 – .019
(0.355 – 0.483)
TYP
8
.004 – .010
(0.101 – 0.254)
0o – 8o TYP
.016 – .050
(0.406 – 1.270)
7
.050
(1.270)
BSC
S16 0502
INCHES
(MILLIMETERS)
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
43563f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LT4356-3
TYPICAL APPLICATION
Overvoltage Regulator with Linear Regulator Up to 100mA
Q2
2N2905A
2.5V, 100mA
RSNS
10mΩ
VIN
12V
Q1
IRLR2908
D2*
SMAJ58A
6
VOUT
12V, 3A
CLAMPED AT 16V
R3
10Ω
4
GATE
5
SNS
R6
100k
C5
10μF
R1
59k
3
OUT
VCC
FB
2
R2
4.99k
11
7
LT4356DE-3
+ 12
AOUT
IN
SHDN
FLT
*DIODES INC.
GND
10
EN
TMR
1
8
R4
249k
C3
47nF
R5
249k
9
43563 TA04
CTMR
0.1μF
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Hot Swap, No RSENSE and ThinSOT are trademarks of Linear Technology Corporation.
43563f
24
Linear Technology Corporation
LT 0309 • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2009