HD74AC166/HD74ACT166 8-bit Shift Register Description The HD74AC166/HD74ACT166 is an 8-bit, serial or parallel-in, serial-out shift register using edge triggered D-type flip-flops. Serial and parallel entry are synchronous, with state changes initiated by the rising edge of the clock. An asynchronous Master Reset overrides other inputs and clears all flip-flops. The circuit can be clocked from two sources or one CP input can be used to trigger the other. Features • Outputs Source/Sink 24 mA • HD74ACT166 has TTL-Compatible Inputs Pin Arrangement DS 1 16 VCC P0 2 15 PE P1 3 14 P7 P2 4 13 Q7 P3 5 12 P6 CP2 6 11 P5 CP1 7 10 P4 9 MR GND 8 (Top view) HD74AC166/HD74ACT166 Logic Symbol 15 2 3 4 5 10 11 12 14 PE P0 P1 P2 P3 P4 P5 P6 P7 7 6 1 DS 1 2 CP MR Q7 9 13 VCC=Pin16 GND=Pin8 Pin Names CP1, CP2 DS PE P 0 to P7 MR Q7 Clock Pulse Inputs (Active Rising Edge) Serial Data Input Parallel Enable Input (Active Low) Parallel Data Inputs Asynchronous Master Reset Input (Active Low) Last Stage Output Functional Description Operation is synchronous (except for Master Reset) and state changes are initiated by the rising edge of either clock input if the other clock input is Low. When one of the clock inputs is used as an active High clock inhibt, it should attain the High state while the other clock is still in the High state following the previous operation. When the Parallel Enable (PE) input is Low, data is loaded into the register from the Parallel Data (P0 to P7) inputs on the next rising edge of the clock. When PE is High, information is shifted from the Serial Data (DS) input to Q0 and all data in the register is shifted one bit position (i.e., Q0 → Q1, Q1 → Q2, etc.) on the rising edge of the clock. 2 HD74AC166/HD74ACT166 Truth Table Inputs Parallel Internal Outputs Output MR PE CP 2 CP 1 DS P0 to P7 Q0 Q6 Q7 L X X X X X L L L H X L L X X QA0 QB0 QH0 H L L X a ··· h a b h H H L H X H QAn QGn H H L L X L QAn QGn H X H X X QA0 QB0 QH0 H : L : X : High Voltage Level Low Voltage Level Immaterial : Low-to-High Clock Transition Logic Diagram P0 DS R CP S CD Q P1 P2 P3 P4 P5 P6 MR P7 PE CP 1 2 R CP S CD Q Q7 3 HD74AC166/HD74ACT166 DC Characteristics (unless otherwise specified) Item Symbol Max Unit Condition Maximum quiescent supply current I CC 80 µA VIN = VCC or ground, VCC = 5.5 V, Ta = Worst case Maximum quiescent supply current I CC 8.0 µA VIN = VCC or ground, VCC = 5.5 V, Ta = 25°C Maximum additional ICC/input (HD74ACT166) I CCT 1.5 mA VIN = VCC – 2.1 V, VCC = 5.5 V, Ta = Worst case AC Characteristics: HD74AC166 Ta = +25°C CL = 50 pF Ta = –40°C to +85°C CL = 50 pF Item Symbol VCC (V)*1 Min Typ Max Min Max Unit Maximum clock f max 3.3 75 — — 65 — MHz 5.0 100 — — 80 — 3.3 1.0 11.0 14.5 1.0 15.5 5.0 1.0 9.5 11.5 1.0 12.5 3.3 1.0 10.5 14.0 1.0 15.0 5.0 1.0 9.0 11.0 1.0 12.0 3.3 1.0 9.5 12.0 1.0 13.0 5.0 1.0 6.5 9.0 1.0 10.0 frequency Propagation delay t PLH CP 1 or CP2 to Q 7 Propagation delay t PHL CP 1 or CP2 to Q 7 Propagation delay MR to Q 7 Note: 4 t PHL 1. Voltage Range 3.3 is 3.3 V ± 0.3 V Voltage Range 5.0 is 5.0 V ± 0.5 V ns HD74AC166/HD74ACT166 AC Operating Requirements: HD74AC166 Ta = –40°C to +85°C CL = 50 pF Ta = +25°C CL = 50 pF Item Symbol VCC (V)*1 Typ Guaranteed Minimum Unit Setup time t su 3.3 3.0 5.5 6.0 ns 5.0 2.0 4.0 4.5 3.3 –1.5 3.0 3.0 5.0 –0.5 3.0 3.0 3.3 2.0 5.5 7.0 5.0 2.0 4.5 5.0 3.3 –2.5 0.0 0.0 5.0 –1.5 0.0 0.0 PE or Pn or DS to CPn Hold time th CP n to PE or Pn or DS Pulse width tw CP n or MR Recovery time t rec MR to CPn Note: 1. Voltage Range 3.3 is 3.3 V ± 0.3 V Voltage Range 5.0 is 5.0 V ± 0.5 V AC Characteristics: HD74ACT166 Ta = +25°C CL = 50 pF Ta = –40°C to +85°C CL = 50 pF Item Symbol VCC (V)*1 Min Typ Max Min Max Unit Maximum clock frequency f max 5.0 100 — — 80 — MHz Propagation delay CP n to Q 7 t PLH 5.0 1.0 10.0 12.5 1.0 13.5 ns Propagation delay CP n to Q 7 t PHL 5.0 1.0 9.5 12.0 1.0 13.0 Propagation delay MR to Q 7 t PHL 5.0 1.0 8.5 11.0 1.0 12.0 Note: 1. Voltage Range 5.0 is 5.0 V ± 0.5 V 5 HD74AC166/HD74ACT166 AC Operating Requirements: HD74ACT166 Ta = –40°C to +85°C CL = 50 pF Ta = +25°C CL = 50 pF Item Symbol VCC (V)*1 Typ Guaranteed Minimum Unit Setup time PE or Pn or DS to CPn t su 5.0 2.5 7.0 8.0 ns Hold time CP n to PE or Pn or DS th 5.0 0.0 1.5 1.5 Pulse width CPn or MR tw 5.0 4.5 7.0 8.0 Recovery time MR to CPn t rec 5.0 –2.5 0.5 0.5 Note: 1. Voltage Range 5.0 is 5.0 V ± 0.5 V Capacitance Item Symbol Typ Unit Condition Input capacitance CIN 4.5 pF VCC = 5.5 V Power dissipation capacitance CPD 35.0 pF VCC = 5.0 V 6 Unit: mm 19.20 20.00 Max 1 7.40 Max 9 6.30 16 8 1.3 0.48 ± 0.10 2.54 Min 5.06 Max 2.54 ± 0.25 0.51 Min 1.11 Max 7.62 + 0.13 0.25 – 0.05 0° – 15° Hitachi Code JEDEC EIAJ Weight (reference value) DP-16 Conforms Conforms 1.07 g Unit: mm 10.06 10.5 Max 9 1 8 1.27 *0.42 ± 0.08 0.40 ± 0.06 0.10 ± 0.10 0.80 Max *0.22 ± 0.05 0.20 ± 0.04 2.20 Max 5.5 16 0.20 7.80 +– 0.30 1.15 0° – 8° 0.70 ± 0.20 0.15 0.12 M *Dimension including the plating thickness Base material dimension Hitachi Code JEDEC EIAJ Weight (reference value) FP-16DA — Conforms 0.24 g Unit: mm 9.9 10.3 Max 9 1 8 0.635 Max *0.42 ± 0.08 0.40 ± 0.06 0.15 *0.22 ± 0.03 0.20 ± 0.03 1.27 0.11 0.14 +– 0.04 1.75 Max 3.95 16 0.10 6.10 +– 0.30 1.08 0° – 8° 0.67 0.60 +– 0.20 0.25 M *Dimension including the plating thickness Base material dimension Hitachi Code JEDEC EIAJ Weight (reference value) FP-16DN Conforms Conforms 0.15 g Unit: mm 4.40 5.00 5.30 Max 16 9 1 8 0.65 0.13 M 1.10 Max 0.65 Max 0.10 *Dimension including the plating thickness Base material dimension 6.40 ± 0.20 0.07 +0.03 –0.04 0.20 ± 0.06 1.0 *0.17 ± 0.05 0.15 ± 0.04 0.08 *0.22 +– 0.07 0° – 8° 0.50 ± 0.10 Hitachi Code JEDEC EIAJ Weight (reference value) TTP-16DA — — 0.05 g Cautions 1. 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