Elantec EL4585C Horizontal genlock, 8 fsc Datasheet

EL4585C
EL4585C
Horizontal Genlock, 8 FSC
Features
General Description
# 36 MHz, general purpose PLL
# 8 FSC timing. (Use the EL4584
for 4 FSC)
# Compatible with EL4583C Sync
Separator
# VCXO, Xtal, or LC tank
oscillator
# k 2nS jitter (VCXO)
# User-controlled PLL capture and
lock
# Compatible with NTSC and PAL
TV formats
# 8 pre-programmed popular TV
scan rate clock divisors
# Single 5V, low current operation
The EL4585C is a PLL (Phase Lock Loop) sub system, designed
for video applications, but also suitable for general purpose use
up to 36 MHz. In a video application this device generates a
TTL/CMOS compatible Pixel Clock (Clk Out) which is a multiple of the TV Horizontal scan rate, and phase locked to it.
Applications
# Pixel Clock regeneration
# Video compression engine
(MPEG) clock generator
# Video Capture or digitization
# PIP (Picture In Picture) timing
generator
# Text or Graphics overlay timing
Ordering Information
Part No.
Temp. Range
Package
EL4585CN b 40§ C to a 85§ C 16-Pin DIP
EL4585CS b 40§ C to a 85§ C 16-Lead SO
Outline Ý
MDP0031
MDP0027
For 3Fsc and 4Fsc clock frequency operation,
see EL4584 datasheet.
The reference signal is a horizontal sync signal, TTL/CMOS
format, which can be easily derived from an analog composite
video signal with the EL4583 Sync Separator. An input signal
to ‘‘coast’’ is provided for applications where periodic disturbances are present in the reference video timing such as VTR
head switching. The Lock detector output indicates correct lock.
The divider ratio is four ratios for NTSC and four similar ratios
for the PAL video timing standards, by external selection of
three control pins. These four ratios have been selected for common video applications including 8 FSC, 6 FSC, 27 MHz (CCIR
601 format) and square picture elements used in some workstation graphics. To generate 4 FSC, 3 FSC, 13.5 MHz (CCIR 601
format) etc., use the EL4584, which does not have the additional divide by 2 stage of the EL4585.
For applications where these frequencies are inappropriate or
for general purpose PLL applications the internal divider can be
by passed and an external divider chain used.
FREQUENCIES and DIVISORS
Function
6Fsc
CCIR 601
Square
8Fsc
Divisor*
PAL Fosc (MHz)
1702
26.602
1728
27.0
1888
29.5
2270
35.468
Divisor*
NTSC Fosc (MHz)
1364
21.476
1716
27.0
1560
24.546
1820
28.636
CCIR 601 divisors yield 1440 pixels in the active portion of each line for NTSC and PAL.
Square pixels format gives 640 pixels for NTSC and 768 pixels for PAL.
6Fsc frequencies do not yield integer divisors.
*Divisor does not include d 2 block.
Demo Board
A demo PCB is available for this
product. Request ‘‘EL4584/5 Demo
Board’’.
Connection Diagram
EL4585 SO, P-DIP Packages
© 1995 Elantec, Inc.
March 1996 Rev C
4585 – 17
Note: All information contained in this data sheet has been carefully checked and is believed to be accurate as of the date of publication; however, this data sheet cannot be a ‘‘controlled document’’. Current revisions, if any, to these
Ý4585C
specifications are maintained at the factory and are available upon your request. We recommend checking the revision level before finalization of your design documentation.
EL4585C
Horizontal Genlock, 8 FSC
Absolute Maximum Ratings (TA e 25§ C)
125§ C
400mW
36MHz
Operating Junction Temp
Power Dissipation
Oscillator Frequency
7V
VCC Supply
b 65§ C to a 150§ C
Storage Temperature
Lead Temperature
260§ C
b 0.5V to VCC a 0.5V
Pin Voltages
b 40§ C to a 85§ C
Operating Ambient Temperature Range
Important Note:
All parameters having Min/Max specifications are guaranteed. The Test Level column indicates the specific device testing actually
performed during production and Quality inspection. Elantec performs most electrical tests using modern high-speed automatic test
equipment, specifically the LTX77 Series system. Unless otherwise noted, all tests are pulsed tests, therefore TJ e TC e TA.
Test Level
I
II
III
IV
V
Test Procedure
100% production tested and QA sample tested per QA test plan QCX0002.
100% production tested at TA e 25§ C and QA sample tested at TA e 25§ C ,
TMAX and TMIN per QA test plan QCX0002.
QA sample tested per QA test plan QCX0002.
Parameter is guaranteed (but not tested) by Design and Characterization Data.
Parameter is typical value at TA e 25§ C for information purposes only.
Parameter
IDD
Conditions
Temp
Min
25§ C
VDD e 5V (Note 1)
2
VIL Input Low Voltage
25§ C
VIH Input High Voltage
25§ C
3.5
IIL Input Low Current
All inputs except COAST, Vin e 1.5V
25§ C
b 100
IIH Input High Current
All inputs except COAST, Vin e 3.5V
25§ C
IIL Input Low Current
COAST pin, Vin e 1.5V
25§ C
b 100
COAST pin, Vin e 3.5V
25§ C
VOL Output Low Voltage
Lock Det, IOL e 1.6mA
25§ C
VOH Output High Voltage
Lock Det, IOH eb1.6mA
25§ C
VOL Output Low Voltage
CLK, IOL e 3.2mA
25§ C
VOH Output High Voltage
CLK, IOH eb3.2mA
25§ C
VOL Output Low Voltage
OSC Out, IOL e 200mA
25§ C
VOH Output High Voltage
OSC Out, IOH eb200mA
25§ C
2.4
IOL Output Low Current
Filter Out, VOUT e 2.5V
25§ C
200
IOH Output High Current
Filter Out, VOUT e 2.5V
25§ C
IOL/IOH Current Ratio
Filter Out, VOUT e 2.5V
25§ C
ILEAK Filter Out
Coast Mode, VDDlVOUTl0V
25§ C
2
Test
Level
Units
4
I
mA
1.5
I
V
I
V
Max
I
nA
I
nA
I
mA
100
I
mA
0.4
I
V
I
V
0.4
I
V
I
V
I
V
100
IIH Input High Current
Note 1: All inputs to 0V, COAST floating.
Typ
b 60
60
2.4
2.4
0.4
300
I
V
I
mA
mA
b 300
b 200
I
1.05
1.0
0.95
I
b 100
g1
100
I
nA
TD is 3.5in
DC Electrical Characteristics (VDD e 5V, TA e 25§ C unless otherwise noted)
TD is 3.5in
EL4585C
Horizontal Genlock, 8 FSC
AC Electrical Characteristics (VDD e 5V, TA e 25§ C unless otherwise noted)
Parameter
Conditions
Temp
Test circuit 1
25§ C
H-sync S/N Ratio
VDD e 5V (Note 2)
25§ C
Jitter
VCXO Oscillator
25§ C
Jitter
LC Oscillator (Typ)
25§ C
VCO Gain
@
20 MHz
Min
Typ
Max
15.5
Test
Level
Units
V
dB
V
dB
1
V
ns
10
V
ns
35
Note 2: Noisy video signal input to EL4583C, H-sync input to EL4585C. Test for positive signal lock.
Pin Description
Pin Name
Function
Digital inputs to select d N value for internal counter. See table below for values.
16, 1, 2
Prog A,B,C
3
Osc/VCO Out
Output of internal inverter/oscillator. Connect to external crystal or LC tank VCO circuit.
4
VDD (A)
Analog positive supply for oscillator, PLL circuits.
5
Osc/VCO In
Input from external VCO.
6
VSS (A)
Analog ground for oscillator, PLL circuits.
7
Charge Pump
Out
Connect to loop filter. If the H-sync phase is leading or H-sync frequency l CLK d 2N, current is
pumped into the filter capacitor to increase VCO frequency. If H-sync phase is lagging or frequency
k CLK d 2N, current is pumped out of the filter capacitor to decrease VCO frequency. During coast
mode or when locked, charge pump goes to a high impedance state.
8
Div Select
Divide select input. When high, the internal divider is enabled and EXT DIV becomes a test pin,
outputting CLK d 2N. When low, the internal divider is disabled and EXT DIV is an input from an
external d N.
9
Coast
Tri-state logic input. Low(k(/3*VCC) e normal mode, Hi Z(or (/3 to )/3*VCC) e fast lock mode,
High(l)/3*VCC) e coast mode.
10
H-sync In
Horizontal sync pulse (CMOS level) input.
11
VDD (D)
Positive supply for digital, I/O circuits.
12
Lock Det
Lock Detect output. Low level when PLL is locked. Pulses high when out of lock.
13
Ext Div
External Divide input when DIV SEL is low, internal d 2N output when DIV SEL is high.
14
VSS (D)
Ground for digital, I/O circuits.
15
CLK Out
Buffered output of the VCO.
Table 5. VCO Divisors
Prog A
Pin 16
Prog B
Pin 1
Prog C
Pin 2
Div Value
N
0
0
0
1702
0
0
1
1728
0
1
0
1888
0
1
1
2270
1
0
0
1364
1
0
1
1716
1
1
0
1560
1
1
1
1820
3
TD is 3.5in
Pin No.
EL4585C
Horizontal Genlock, 8 FSC
Timing Diagrams
PLL Locked Condition (Phase Error e 0)
4585 – 2
Out of Lock Condition
Ti
c 360§
TH
TH e H-sync period
Ti e phase error period
iE e
4585 – 3
Typical Performance Curves
Test Circuit 1
4585 – 5
4
EL4585C
Horizontal Genlock, 8 FSC
Typical Performance Curves Ð Contd.
Idd vs Fosc
OSC Gain
@
20 MHz vs Temp
4585 – 6
4585 – 4
Typical Varactor
OSC Gain vs Fosc
Charge Pump Duty Cycle Vs iE
4585 – 9
4585 – 7
4585 – 8
EL4585 Block Diagram
4585 – 1
5
EL4585C
Horizontal Genlock, 8 FSC
5 volts, and it can source or sink a maximum of
about 300mA, so all frequency control must be
accomplished with variable capacitance from the
varactor within this range. Crystal oscillators are
more stable than LC oscillators, which translates
into lower jitter, but LC oscillators can be pulled
from their mid-point values further, resulting in
a greater capture and locking range. If the incoming horizontal sync signal is known to be very
stable, then a crystal oscillator circuit can be
used. If the H-sync signal experiences frequency
variations of greater than about 300ppm, an LC
oscillator should be considered, as crystal oscillators are very difficult to pull this far. When Hsync input frequency is greater than CLK frequency d 2N, charge pump output (pin 7) sources
current into the filter capacitor, increasing the
voltage across the varactor, thus tending to increase VCO frequency. Conversely, charge pump
output pulls current from the filter capacitor
when H-sync frequency is less than CLK d 2N,
forcing the VCO frequency lower.
Description Of Operation
The horizontal sync signal (CMOS level, falling
leading edge) is input to H-SYNC input (pin 10).
This signal is delayed about 110nS, the falling
edge of which becomes the reference to which the
clock output will be locked. (See timing diagrams.) The clock is generated by the signal on
pin 5, OSC in. There are 2 general types of VCO
that can be used with the EL4585C, LC and crystal controlled. Additionally, each type can be either built up using discrete components, including a varactor as the frequency controlling element, or complete, self contained modules can be
purchased with everything inside a metal can.
These modules are very forgiving of PCB layout,
but cost more than discrete solutions. The VCO
or VCXO is used to regulate the clock. An LC
tank resonator has greater ‘‘pull’’ than a crystal
controlled circuit, but will also be more likely to
drift over time, and thus will generate more jitter. The ‘‘pullability’’ of the circuit refers to the
ability to pull the frequency of oscillation away
from its center frequency by modulating the voltage on the control pin of the VCO module or varactor, and is a function of the slope and range of
the capacitance-voltage curve of the varactor or
VCO module used. The VCO signal is sent to the
CLK out pin, divided by two, then sent to the
divide by N counter. The divisor N is determined
by the state of pins 1, 2, and 16 and is described
in table 5 above. The divided signal is sent, along
with the delayed H-sync input, to the phase/frequency detector, which compares the two signals
for phase and frequency differences. Any phase
difference is converted to a current at the charge
pump output, (pin 7). A VCO with a positive frequency deviation with control voltage must be
used. Varactors have negative capacitance slope
with voltage, resulting in positive frequency deviation with increasing control voltage for the oscillators in figures 10 and 11 below.
Loop Filter
The loop filter controls how fast the VCO will
respond to a change in phase comparator output
stimulus. Its components should be chosen so
that fast lock can be achieved, yet with a minimum of VCO ‘‘hunting’’, preferably in one to two
oscillations of charge pump output, assuming the
VCO frequency starts within capture range. If
the filter is under-damped, the VCO will over and
under-shoot the desired operating point many
times before a stable lock takes place. It is possible to under-damp the filter so much that the
loop itself oscillates, and VCO lock is never
achieved. If the filter is over-damped, the VCO
response time will be excessive and many cycles
will be required for a lock condition. Over-damping is also characterized by an easily unlocked
system because the filter can’t respond fast
enough to perturbations in VCO frequency. A severely over damped system will seem to endlessly
oscillate, like a very large mass at the end of a
long pendulum. Due to parasitic effects of PCB
traces and component variables, it will take some
trial and error experimentation to determine the
best values to use for any given situation. Use the
component tables as a starting point, but be
aware that deviations from these values are not
out of the ordinary.
VCO
The VCO should be tuned so that its frequency of
oscillation is very close to the required clock output frequency when the voltage on the varactor
is 2.5 volts. VCXO and VCO modules are already
tuned to the desired frequency, so this step is not
necessary if using one of these units. The output
range of the charge pump output (pin 7) is 0 to
6
EL4585C
Horizontal Genlock, 8 FSC
be regular during this time. Once the near lock
condition is attained, charge pump output should
be very close to its lock-on value, and placing the
device into normal mode should result in a normal lock very quickly. Fast lock mode is intended
to be used where H-sync becomes irregular, until
a stable signal is again obtained.
Description Of Operation Ð Contd.
External Divide
DIV SEL (pin 8) controls the use of the internal
divider. When high, the internal divider is enabled and EXT DIV (pin 13) outputs the CLK
out divided by 2N. This is the signal to which the
horizontal sync input will lock. When divide select is low, the internal divider output is disabled,
and external divide becomes an input from an external divider, so that a divisor other than one of
the 8 pre-programmed internal divisors can be
used.
Coast Mode
Coast mode is enabled by pulling COAST (pin 9)
high (above )/3*Vcc). In coast mode the internal
phase detector is disabled and filter out remains
in high impedance mode to keep filter out voltage and VCO frequency as constant a possible.
VCO frequency will drift as charge leaks from the
filter capacitor, and the voltage changes the VCO
operating point. Coast mode is intended to be
used when noise or signal degradation result in
loss of horizontal sync for many cycles. The
phase detector will not attempt to adjust to the
resultant loss of signal so that when horizontal
sync returns, sync lock can be re-established
quickly. However, if much VCO drift has occurred, it may take as long to re-lock as when
restarting.
Normal Mode
Normal mode is enabled by pulling COAST (pin
9) low (below (/3*Vcc). If H-SYNC and CLK d 2N
have any phase or frequency difference, an error
signal is generated and sent to the charge pump.
The charge pump will either force current into or
out of the filter capacitor in an attempt to modulate the VCO frequency. Modulation will continue until the phase and frequency of CLK d 2N
exactly match the H-sync input. When the phase
and frequency match (with some offset in phase
that is a function of the VCO characteristics), the
error signal goes to zero, lock detect no longer
pulses high, and the charge pump enters a high
impedance state. The clock is now locked to the
H-sync input. As long as phase and frequency
differences remain small, the PLL can adjust the
VCO to remain locked and lock detect remains
low.
Lock Detect
Lock detect (pin 12) will go low when lock is established. Any DC current path from charge
pump out will skew EXT DIV relative to HSYNC in, tending to offset or add to the 110nS
internal delay, depending on which way the extra
current is flowing. This offset is called static
phase error, and is always present in any PLL
system. If, when the part stabilizes in a locked
mode, lock detect is not low, adding or subtracting from the loop filter series resistor R2 will
change this static phase error to allow LDET to
go low while in lock. The goal is to put the rising
edge of EXT DIV in sync with the falling edge of
H-SYNC a 110nS. (See timing diagrams.) Increasing R2 decreases phase error, while decreasing R2 increases phase error. (Phase error is positive when EXT DIV lags H-SYNC.) The resistance needed will depend on VCO design or VCXO
module selection.
Fast Lock Mode
Fast Lock mode is enabled by either allowing
coast to float, or pulling it to mid supply (between (/3 and )/3*Vcc). In this mode, lock is
achieved much faster than in normal mode, but
the clock divisor is modified on the fly to achieve
this. If the phase detector detects an error of
enough magnitude, the clock is either inhibited
or reset to attempt a ‘‘fast lock’’ of the signals.
Forcing the clock to be synchronized to the
H-sync input this way allows a lock in approximately 2 H-cycles, but the clock spacing will not
7
EL4585C
Horizontal Genlock, 8 FSC
Typical LC VCO
Applications Information
Choosing External Components
1. To choose LC VCO components, first pick the
desired operating frequency. For our example
we will use 28.636MHz, with an H-sync frequency of 15.734kHz.
2. Choose a reasonable inductor value (1-5mH
works well). We choose 3.3mH.
3. Calculate CT needed to produce FOSC.
FOSC e
4585 – 10
1
2q 0LCT
LC VCO Component Values (Approximate)
Frequency
(MHz)
1
1
e
e 9.4pF
4q2F2L 4q2(28.636e6)2(3.3e b 6)
4. From the varactor data sheet find CV @ 2.5V,
the desired lock voltage. CV e 23pF for our
SMV1204-12 for example.
5. C2 should be about 10CV, so we choose
C2 e 220pF for our example.
6. Calculate C1. Since
CT e
C1C2CV
CT e
,
a
(C1C2)
(C1CV) a (C2CV)
C1
(pF)
C2
(pF)
26.602
3.3
22
220
27.0
3.3
21
220
29.5
2.7
22
220
35.468
2.2
16
220
21.476
4.7
26
220
24.546
3.9
22
220
28.636
3.3
17
220
Note: Use shielded inductors for optimum performance.
Typical Xtal VCO
then
C1 e
L1
(mH)
C2CTCV
.
(C2Cv) b (C2CT) b (CTCV)
For our example, C1 e 17pF. (A trim cap may be
used for fine tuning.) Examples for each frequency using the internal divider follow.
4585 – 11
8
EL4585C
Horizontal Genlock, 8 FSC
Typical Application
Horizontal genlock provides clock for an analog to digital converter, digitizing analog video.
4585 – 18
Xtal VCO Component Values (Approximate)
Frequency
(MHz)
R1
(kX)
C1
(pF)
C2
(mF)
26.602
300
15
.001
27.0
300
15
.001
29.5
300
15
.001
35.468
300
15
.001
21.476
300
15
.001
24.546
300
15
.001
28.636
300
15
.001
Colpitts Oscillator
4585 – 12
C1 is to adjust the center frequency, C2 DC isolates the control from the oscillator, and V1 is the
primary control device. C2 should be much larger
than CV so that V1 has maximum modulation
capability. The frequency of oscillation is given
by:
The above oscillators are arranged as Colpitts oscillators, and the structure is redrawn here to emphasize the split capacitance used in a Colpitts
oscillator. It should be noted that this oscillator
configuration is just one of literally hundreds
possible, and the configuration shown here does
not necessarily represent the best solution for all
applications. Crystal manufacturers are very informative sources on the design and use of oscillators in a wide variety of applications, and the
reader is encouraged to become familiar with
them.
Fe
1
2q0LCT
CT e
9
C1C2CV
(C1C2) a (C1CV) a (C2CV)
EL4585C
Horizontal Genlock, 8 FSC
transfer function Cv e F(VC), where VC is the reverse bias control voltage, and CV is varactor capacitance. Since F(VC) is nonlinear, it is probably
best to build the VCO and measure KVCO about
2.5V. The results of one such measurement are
shown below. The slope of the curve is determined by linear regression techniques and equals
KVCO. For our example, KVCO e 9.06 Mrad/s/V.
Choosing Loop Filter
Components
The PLL, VCO, and loop filter can be described
as:
FOSC vs VC, LC VCO
4585 – 13
Where:
Kd e phase detector gain in A/rad
F(s) e loop filter impedance in V/A
KVCO e VCO gain in rad/s/V
N e Total internal or external divisor (see 3 below)
It can be shown that for the loop filter shown
below:
C3 e
4585 – 14
5. Now we can solve for C3, C4, and R3.
KdKVCO
C3
2Ng0n
, C4 e , R3 e
N0n2
10
KdKVCO
Where 0n e loop filter bandwidth, and g e loop
filter damping factor.
1. Kd e 300mA/2qrad e 4.77e-5A/rad for the
EL4585C.
2. The loop bandwidth should be about H-sync
frequency/20, and the damping ratio should be
1 for optimum performance. For our example,
0n e 15.734kHz/20 e 787 Hz & 5000 rad/S.
3. N e 910x2 e 1820 from table 1.
C3 e
KdKVCO
(4.77e b 5)(9.06e6)
e
e 0.01mF
2
N0n
(1820)(5000)2
C4 e
C3
e 0.001mF
10
R3 e
2Ng0n
(2)(1820)(1)(5000)
e
e 42.1kX
(4.77e b 5)(9.06e6)
KdKVCO
We choose R3 e 43kX for convenience.
6. Notice R2 has little effect on the loop filter design. R2 should be large, around 100k, and can
be adjusted to compensate for any static phase
error Ti at lock, but if made too large, will
slow loop response. If R2 is made smaller, Ti
(see timing diagrams) increases, and if R2 in-
FVCO
28.636M
e
e 1820 e 910x2
FHsync
15.73426k
4. KVCO represents how much the VCO frequency changes for each volt applied at the control
pin. It is assumed (but probably isn’t) linear
about the lock point (2.5V). Its value depends
on the VCO configuration and the varactor
Ne
10
EL4585C
Horizontal Genlock, 8 FSC
creases, Ti decreases. For LDET to be low at
lock, l Ti l k 50nS. C4 is used mainly to attenuate
high frequency noise from the charge pump. The
effect these components have on time to lock is
illustrated below.
Xtal Loop Filter Components (Approximate)
Frequency
(MHz)
Lock Time
Let T e R3C3. As T increases, damping increases,
but so does lock time. Decreasing T decreases
damping and speeds up loop response, but increases overshoot and thus increases the number
of hunting oscillations before lock. Critical damping (g e 1) occurs at minimum lock time. Because
decreased damping also decreases loop stability,
it is sometimes desirable to design slightly overdamped (g l 1), trading lock time for increased
stability.
4585 – 16
R3
(kX)
C3
(mF)
C4
(mF)
26.602
100
39
0.01
0.001
27.0
100
39
0.01
0.001
29.5
100
43
0.01
0.001
35.468
100
51
0.01
0.001
21.476
100
30
0.01
0.001
24.546
100
36
0.01
0.001
28.636
100
43
0.01
0.001
C3
(pF)
C4
(pF)
26.602
100
4.3
68
6.8
27.0
100
4.3
68
6.8
29.5
100
4.3
68
6.8
35.468
100
4.3
68
6.8
21.476
100
4.3
68
6.8
24.546
100
4.3
68
6.8
28.636
100
4.3
68
6.8
It is highly recommended that power and ground
planes be used in layout. The oscillator and filter
sections constitute a feedback loop and thus care
must be taken to avoid any feedback signal influencing the oscillator except at the control input.
The entire oscillator/filter section should be surrounded by copper ground to prevent unwanted
influences from nearby signals. Use separate
paths for analog and digital supplies, keeping the
analog (oscillator section) as short and free from
spurious signals as possible. Careful attention
must be paid to correct bypassing. Keep lead
lengths short and place bypass caps as close to
the supply pins as possible. If laying out a PCB
to use discrete components for the VCO section,
care must be taken to avoid parasitic capacitance
at the OSC pins 3 and 5, and FILTER out (pin
7). Remove ground and power plane copper
above and below these traces to avoid making a
capacitive connection to them. It is also recommended to enclose the oscillator section within a
shielded cage to reduce external influences on the
VCO, as they tend to be very sensitive to ‘‘hand
waving’’ influences, the LC variety being more
sensitive than crystal controlled oscillators. In
general, the higher the operating frequency, the
more important these considerations are. Self
contained VCXO or VCO modules are already
mounted in a shielding cage and therefore do not
require as much consideration in layout. Many
crystal manufacturers publish informative literature regarding use and layout of oscillators which
should be helpful.
LC Loop Filter Components (Approximate)
R2
(kX)
R3
(MX)
PCB Layout Considerations
Typical Loop Filter
Frequency
(MHz)
R2
(kX)
11
EL4585C
4585–19
Horizontal Genlock, 8 FSC
EL4585/4 Demo Board
12
EL4585C
Horizontal Genlock, 8 FSC
EL4585/4 Demo Board Ð Contd.
The VCO and loop filter section of the EL4583/4/5 Demo Board can be implemented in the following
configurations:
(1) VCXO
4585 – 20
(2) XTAL
4585 – 21
(3) LC Tank
4585 – 22
13
14
BLANK
15
BLANK
EL4585C
EL4585C
Horizontal Genlock, 8 FSC
Component Sources
# SaRonix
151 Laura Lane
Palo Alto, CA 94043
(415) 856-6900
Inductors
# Dale Electronics
E. Highway 50
PO Box 180
Yankton, SD 57078-0180
(605) 665-9301
# Standard Crystal
9940 Baldwin Place
El Monte, CA 91731
(818) 443-2121
Crystals, VCXO, VCO Modules
# Connor-Winfield
2111 Comprehensive Drive
Aurora, IL 60606
(708) 851-4722
Varactors
# Alpha Industries
20 Sylvan Road
Woburn, MA 01801
(617) 935-5150
# Piezo Systems
100 K Street
PO Box 619
Carlisle, PA 17013
(717) 249-2151
# Motorola Semiconductor Products
2100 E. Elliot
Tempe, AZ 85284
(602) 244-6900
# Reeves-Hoffman
400 West North Street
Carlisle, PA 17013
(717) 243-5929
Note: These sources are provided for information
purposes only. No endorsement of these companies is implied by this listing.
General Disclaimer
Specifications contained in this data sheet are in effect as of the publication date shown. Elantec, Inc. reserves the right to make changes
in the circuitry or specifications contained herein at any time without notice. Elantec, Inc. assumes no responsibility for the use of any
circuits described herein and makes no representations that they are free from patent infringement.
March 1996 Rev C
WARNING Ð Life Support Policy
Elantec, Inc. products are not authorized for and should not be
used within Life Support Systems without the specific written
consent of Elantec, Inc. Life Support systems are equipment intended to support or sustain life and whose failure to perform
when properly used in accordance with instructions provided can
be reasonably expected to result in significant personal injury or
death. Users contemplating application of Elantec, Inc. products
in Life Support Systems are requested to contact Elantec, Inc.
factory headquarters to establish suitable terms & conditions for
these applications. Elantec, Inc.’s warranty is limited to replacement of defective components and does not cover injury to persons or property or other consequential damages.
Elantec, Inc.
1996 Tarob Court
Milpitas, CA 95035
Telephone: (408) 945-1323
(800) 333-6314
Fax: (408) 945-9305
European Office: 44-71-482-4596
16
Printed in U.S.A.