IRF IRF7103IPBF Hexfet power mosfet Datasheet

PD -96085
IRF7103IPbF
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Adavanced Process Technology
Ultra Low On-Resistance
Dual N-Channel MOSFET
Surface Mount
Available in Tape & Reel
Dynamic dv/dt Rating
Fast Switching
Lead-Free
HEXFET® Power MOSFET
S1
G1
S2
G2
1
8
D1
2
7
D1
3
6
D2
4
5
D2
VDSS = 50V
RDS(on) = 0.130Ω
ID = 3.0A
Top View
Description
The SO-8 has been modified through a customized
leadframe for enhanced thermal characteristics and
dual-die capability making it ideal in a variety of power
applications. With these improvements, multiple
devices can be used in an application with dramatically
reduced board space. The package is designed for
vapor phase, infra red, or wave soldering techniques.
Power dissipation of greater than 0.8W is possible in
a typical PCB mount application.
SO-8
Absolute Maximum Ratings
Parameter
ID @ TA = 25°C
ID @ TA = 70°C
IDM
PD @TC = 25°C
VGS
dv/dt
TJ, TSTG
Max.
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Peak Diode Recovery dv/dt
Junction and Storage Temperature Range
Units
3.0
2.3
10
2.0
0.016
± 20
4.5
-55 to + 150
A
W
W/°C
V
V/nS
°C
Thermal Resistance Ratings
Parameter
RθJA
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Maximum Junction-to-Ambient
Min.
Typ.
Max.

62.5
Units
°C/W
1
07/07/06
IRF7103IPbF
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
∆V(BR)DSS/∆TJ
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Qg
Q gs
Qgd
td(on)
tr
td(off)
tf
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Min.
50

1.0

Typ.

0.049
0.11
0.16

3.8

12
1.2
3.5
9.0
8.0
45
25
RDS(ON)
Static Drain-to-Source On-Resistance
VGS(th)
g fs
Gate Threshold Voltage
Forward Transconductance
IDSS
Drain-to-Source Leakage Current
LD
Internal Drain Inductance

4.0

LS
Internal Source Inductance

6.0

Ciss
Coss
Crss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance

290
140
37

V(BR)DSS
IGSS
Max. Units
Conditions

V
VGS = 0V, ID = 250µA
V/°C Reference to 25°C, ID = 1mA
0.13
VGS = 10V, ID = 3.0A
Ω
0.20
VGS = 4.5V, ID = 1.5A
3.0
V
VDS = VGS, ID = 250µA

S
VDS = 15V, ID = 3.0A
2.0
VDS = 40V, VGS = 0V
µA
25
VDS = 40V, VGS = 0V, T J = 55 °C
100
VGS = 20V
nA
-100
VGS = - 20V
30
ID = 2.0A

nC VDS = 25V

VGS = 10V
20
VDD = 25V
20
ID = 1.0A
ns
70
RG = 6.0Ω
50
RD = 25Ω
D
nH
pF
Between lead,6mm(0.25in.)
from package and center
of die contact
VGS = 0V
VDS = 25V
= 1.0MHz
G
S
Source-Drain Ratings and Characteristics
IS
I SM
V SD
t rr
Q rr
ton
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Forward Turn-On Time
Min. Typ. Max. Units
Conditions
D
MOSFET symbol
2.0
showing the
A
G
integral reverse
12
p-n junction diode.
S
1.2
V
TJ = 25°C, IS = 1.5A, V GS = 0V
70 100
ns
TJ = 25°C, IF = 1.5A
110 170
nC di/dt = 100A/µs
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Repetitive rating; pulse width limited by
max. junction temperature.
ISD ≤ 1.8A, di/dt ≤ 90A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 150°C
2
Pulse width ≤ 300µs; duty cycle ≤ 2%.
Surface mounted on FR-4 board, t ≤ 10sec.
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IRF7103IPbF
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3
C,
IRF7103IPbF
4
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IRF7103IPbF
V DS
VGS
RD
D.U.T.
RG
+
- VDD
10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
Fig 10a. Switching Time Test Circuit
VDS
90%
10%
VGS
td(on)
tr
t d(off)
tf
Fig 10b. Switching Time Waveforms
Thermal Response (Z thJA )
100
D = 0.50
0.20
10
0.10
0.05
0.02
1
PDM
0.01
t1
SINGLE PULSE
(THERMAL RESPONSE)
0.1
0.0001
t2
Notes:
1. Duty factor D = t 1 / t 2
2. Peak T J = P DM x Z thJA + TA
0.001
0.01
0.1
1
10
100
t1, Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient
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5
IRF7103IPbF
Current Regulator
Same Type as D.U.T.
QG
10V
50KΩ
.2µF
12V
.3µF
QGS
+
V
- DS
QGD
D.U.T.
VG
VGS
3mA
Charge
IG
ID
Current Sampling Resistors
Fig 12a. Basic Gate Charge Waveform
6
Fig 12b. Gate Charge Test Circuit
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IRF7103IPbF
Peak Diode Recovery dv/dt Test Circuit
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
D.U.T

-
-

RG
•
•
•
•
dv/dt controlled by R G
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
Driver Gate Drive
P.W.
Period
D=
+
-
VDD
P.W.
Period
VGS=10V
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor Curent
Ripple ≤ 5%
ISD
* VGS = 5V for Logic Level Devices
Fig 13. For N-Channel HEXFETS
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7
IRF7103IPbF
SO-8 Package Outline
Dimensions are shown in milimeters (inches)
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SO-8 Part Marking Information
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IRF7103IPbF
SO-8 Tape and Reel
Dimensions are shown in milimeters (inches)
TERMINAL NUMBER 1
12.3 ( .484 )
11.7 ( .461 )
8.1 ( .318 )
7.9 ( .312 )
FEED DIRECTION
NOTES:
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS(INCHES).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
330.00
(12.992)
MAX.
14.40 ( .566 )
12.40 ( .488 )
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. OUTLINE CONFORMS TO EIA-481 & EIA-541.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualifications Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 07/2006
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