AMD AM29F002BB-90PF 2 megabit (256 k x 8-bit) cmos 5.0 volt-only boot sector flash memory Datasheet

Am29F002B/Am29F002NB
Data Sheet
The following document contains information on Spansion memory products.
Continuity of Specifications
There is no change to this data sheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal data sheet improvement and are noted in the
document revision summary.
For More Information
Please contact your local sales office for additional information about Spansion memory solutions.
Publication Number 21527
Revision D
Amendment 5
Issue Date November 1, 2006
THIS PAGE LEFT INTENTIONALLY BLANK.
DATA SHEET
Am29F002B/Am29F002NB
2 Megabit (256 K x 8-Bit)
CMOS 5.0 Volt-only Boot Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
■ Single power supply operation
— 5.0 Volt-only operation for read, erase, and
program operations
— Minimizes system level requirements
■ Manufactured on 0.32 µm process technology
— Compatible with 0.5 µm Am29F002 device
■ High performance
— Access times as fast as 55 ns
■ Low power consumption (typical values at
5 MHz)
— 1 µA standby mode current
— 20 mA read current
— 30 mA program/erase current
■ Flexible sector architecture
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and
three 64 Kbyte sectors
— Supports full chip erase
— Sector Protection features:
A hardware method of locking a sector to
prevent any program or erase operations within
that sector
Sectors can be locked via programming equipment
Temporary Sector Unprotect feature allows code
changes in previously locked sectors
■ Top or bottom boot block configurations available
■ Embedded Algorithms
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically
writes and verifies data at specified addresses
■ Minimum 1,000,000 write cycle guarantee per
sector
■ 20-year data retention at 125°C
— Reliable operation for the life of the system
■ Package option
— 32-pin PDIP
— 32-pin TSOP
— 32-pin PLCC
■ Compatibility with JEDEC standards
— Pinout and software compatible with
single-power supply Flash
— Superior inadvertent write protection
■ Data# Polling and toggle bits
— Provides a software method of detecting
program or erase operation completion
■ Erase Suspend/Erase Resume
— Suspends an erase operation to read data from,
or program data to, a sector that is not being
erased, then resumes the erase operation
■ Hardware reset pin (RESET#)
— Hardware method to reset the device to reading
array data (not available on Am29F002NB)
This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication# 21527 Rev: D Amendment: 5
Issue Date: November 1, 2006
D A T A
S H E E T
GENERAL DESCRIPTION
The Am29F002B Family consists of 2 Mbit, 5.0
volt-only Flash memory devices organized as 262,144
bytes. The Am29F002B offers the RESET# function,
the Am29F002NB does not. The data appears on
DQ7–DQ0. The device is offered in 32-pin PLCC,
32-pin TSOP, and 32-pin PDIP packages. This device
is designed to be programmed in-system with the standard system 5.0 volt VCC supply. No VPP is required for
write or erase operations. The device can also be programmed in standard EPROM programmers.
This device is manufactured using AMD’s 0.32 µm
process technology, and offers all the features and benefits of the Am29F002, which was manufactured using
0.5 µm process technology.
The standard device offers access times of 55, 70, and
90 ns, allowing high speed microprocessors to operate
without wait states. To eliminate bus contention the
device has separate chip enable (CE#), write enable
(WE#) and output enable (OE#) controls.
The device requires only a single 5.0 volt power
supply for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Commands are written to the command register using
standard microprocessor write timings. Register contents serve as input to an internal state-machine that
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data needed
for the programming and erase operations. Reading
data out of the device is similar to reading from other
Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that automatically times the program pulse widths and verifies
proper cell margin.
Device erasure occurs by executing the erase
command sequence. This initiates the Embedded
2
Erase algorithm—an internal algorithm that automatically preprograms the array (if it is not already
programmed) before executing the erase operation.
During erase, the device automatically times the erase
pulse widths and verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by reading the DQ7 (Data#
Polling) and DQ6 (toggle) status bits. After a program
or erase cycle has been completed, the device is ready
to read array data or accept another command.
The sector erase architecture allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low VCC
detector that automatically inhibits write operations during
power transitions. The hardware sector protection
feature disables both program and erase operations in
any combination of the sectors of memory. This can be
achieved via programming equipment.
The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.
The hardware RESET# pin terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.
(This feature is not available on the Am29F002NB.)
The system can place the device into the standby mode.
Power consumption is greatly reduced in this mode.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effectiveness.
The device electrically erases all bits within a sector
simultaneously via Fowler-Nordheim tunneling. The
data is programmed using hot electron injection.
Am29F002B/Am29F002NB
21527D5 November 1, 2006
D A T A
S H E E T
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 5
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 7
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 8
Table 1. Am29F002B/Am29F002NB Device Bus Operations . . . . . .8
Requirements for Reading Array Data . . . . . . . . . . . . . . . . . .
Writing Commands/Command Sequences . . . . . . . . . . . . . . .
Program and Erase Operation Status . . . . . . . . . . . . . . . . . . .
Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RESET#: Hardware Reset Pin . . . . . . . . . . . . . . . . . . . . . . . .
Output Disable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
8
8
9
9
9
Table 2. Am29F002B/Am29F002NB Top Boot Block Sector
Address Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Table 3. Am29F002B/Am29F002NB Bottom Boot Block Sector
Address Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Autoselect Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 4. Am29F002B/Am29F002NB Autoselect Codes (High
Voltage Method) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Sector Protection/Unprotection . . . . . . . . . . . . . . . . . . . . . . . 10
Temporary Sector Unprotect . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 1. Temporary Sector Unprotect Operation . . . . . . . . . . . . . .11
Hardware Data Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Low VCC Write Inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Write Pulse “Glitch” Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Logical Inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Power-Up Write Inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 12
Reading Array Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Autoselect Command Sequence . . . . . . . . . . . . . . . . . . . . . . 12
Byte Program Command Sequence . . . . . . . . . . . . . . . . . . . 12
Figure 2. Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Chip Erase Command Sequence . . . . . . . . . . . . . . . . . . . . . 13
Sector Erase Command Sequence . . . . . . . . . . . . . . . . . . . . 13
Figure 3. Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Erase Suspend/Erase Resume Commands . . . . . . . . . . . . . 15
Command Definitions ............................................................. 16
Table 5. Am29F002B/Am29F002NB Command Definitions . . . . . .16
Write Operation Status . . . . . . . . . . . . . . . . . . . . . 17
DQ7: Data# Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 4. Data# Polling Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . .17
Reading Toggle Bits DQ6/DQ2 . . . . . . . . . . . . . . . . . . . . . . . 18
DQ5: Exceeded Timing Limits . . . . . . . . . . . . . . . . . . . . . . . . 18
DQ3: Sector Erase Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 5. Toggle Bit Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 6. Write Operation Status . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 21
Figure 6. Maximum Negative Overshoot Waveform . . . . . . . . . . . 21
Figure 7. Maximum Positive Overshoot Waveform . . . . . . . . . . . . 21
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 21
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 22
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 8. Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 7. Test Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Key to Switching Waveforms . . . . . . . . . . . . . . . 24
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 9. Read Operations Timings . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 10. RESET# Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 11. Program Operation Timings . . . . . . . . . . . . . . . . . . . . . 28
Figure 12. Chip/Sector Erase Operation Timings . . . . . . . . . . . . . 29
Figure 13. Data# Polling Timings (During Embedded Algorithms) . 30
Figure 14. Toggle Bit Timings (During Embedded Algorithms) . . . 30
Figure 15. DQ2 vs. DQ6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 16. Temporary Sector Unprotect Timing Diagram
(Am29F002B only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 17. Alternate CE# Controlled Write Operation Timings . . . 33
Erase and Programming Performance . . . . . . . 34
Latchup Characteristics . . . . . . . . . . . . . . . . . . . 34
TSOP Pin Capacitance . . . . . . . . . . . . . . . . . . . . 34
PLCC and PDIP Pin Capacitance . . . . . . . . . . . . 35
Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 36
PD 032—32-Pin Plastic DIP . . . . . . . . . . . . . . . . . . . . . . . . . 36
PL 032—32-Pin Plastic Leaded Chip Carrier . . . . . . . . . . . . 37
TS 032—32-Pin Standard Thin Small Package . . . . . . . . . . 38
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 39
Revision A (July 1998) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Revision B (January 1999) . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Revision C (November 12, 1999) . . . . . . . . . . . . . . . . . . . . . 39
Revision D (November 28, 2000) . . . . . . . . . . . . . . . . . . . . . 39
Revision D +1 (November 5, 2004) . . . . . . . . . . . . . . . . . . . . 39
Revision D +2 (August 3, 2005) . . . . . . . . . . . . . . . . . . . . . . . 39
Revision D3 (December 13, 2005) . . . . . . . . . . . . . . . . . . . . 39
Revision D4 (May 17, 2006) . . . . . . . . . . . . . . . . . . . . . . . . . 39
Revision D5 (November 1, 2006) . . . . . . . . . . . . . . . . . . . . . 39
DQ6: Toggle Bit I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
DQ2: Toggle Bit II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
November 1, 2006 21527D5
Am29F002B/Am29F002NB
3
D A T A
S H E E T
PRODUCT SELECTOR GUIDE
Family Part Number
Am29F002B/Am29F002NB
VCC = 5.0 V ± 5%
Speed Option
-55
VCC = 5.0 V ± 10%
-70
-90
Max access time, ns (tACC)
55
70
90
Max CE# access time, ns (tCE)
55
70
90
Max OE# access time, ns (tOE)
30
30
35
Note: See “AC Characteristics” for full specifications.
BLOCK DIAGRAM
DQ0–DQ7
VCC
Sector Switches
VSS
Erase Voltage
Generator
RESET#
Input/Output
Buffers
n/a Am29F002NB
WE#
State
Control
Command
Register
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
CE#
OE#
VCC Detector
A0–A17
4
Timer
Address Latch
STB
STB
Data
Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
Am29F002B/Am29F002NB
21527D5 November 1, 2006
D A T A
S H E E T
CONNECTION DIAGRAMS
A16
2
31
WE#
A15
3
30
A17
A12
4
29
A14
A7
5
28
A13
4 3 2
VCC
VCC
RESET#
32
A16
1
A12
A15
RESET#
WE#
A17
NC on Am29F002NB
NC on Am29F002NB
1 32 31 30
A7
5
29
A14
A6
6
28
A13
A5
A4
7
8
27
26
A8
A9
25
A11
A6
6
27
A8
A5
7
26
A9
A4
8 PDIP
25
A11
A3
9
A3
9
24
OE#
A2
10
24
OE#
A2
10
23
A10
A1
11
23
A10
A1
11
22
CE#
A0
12
22
A0
12
21
DQ7
DQ0
13
CE#
DQ7
DQ0
13
20
DQ6
DQ1
14
19
DQ5
DQ2
15
18
DQ4
VSS
16
17
DQ3
NC on Am29F002NB
A11
A9
A8
A13
A14
A17
WE#
VCC
RESET#
A16
A15
A12
A7
A6
A5
A4
November 1, 2006 21527D5
PLCC
21
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Standard TSOP
Am29F002B/Am29F002NB
DQ5
DQ6
DQ4
DQ3
VSS
DQ1
DQ2
14 15 16 17 18 19 20
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3
5
D A T A
PIN CONFIGURATION
A0–A17
S H E E T
LOGIC SYMBOL
= 18 addresses
18
DQ0–DQ7 = 8 data inputs/outputs
A0–A17
CE#
= Chip enable
OE#
= Output enable
WE#
= Write enable
CE#
RESET#
= Hardware reset pin, active low
(not available on Am29F002NB)
OE#
VCC
= +5.0 V single power supply
(see Product Selector Guide for
device speed ratings and voltage
supply tolerances)
DQ0–DQ7
VSS
= Device ground
NC
= Pin not connected internally
6
8
Am29F002B/Am29F002NB
WE#
RESET#
N/C on Am29F002NB
21527D5 November 1, 2006
D A T A
S H E E T
ORDERING INFORMATION
Standard Product
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below.
Am29F002B/
Am29F002NB
T
-55
P
C
TEMPERATURE RANGE
C
= Commercial (0°C to +70°C)
I
= Industrial (–40°C to +85°C)
E
= Extended (–55°C to +125°C)
D
= Commercial (0°C to +70°C) for Pb-free Package
F
= Industrial (–40°C to +85°C) for Pb-free Package
K
= Extended (–55°C to +125°C) for Pb-free Package
PACKAGE TYPE
P
= 32-Pin Plastic DIP (PD 032)
J
= 32-Pin Rectangular Plastic Leaded Chip Carrier (PL 032)
E
= 32-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 032)
SPEED OPTION
See Product Selector Guide and Valid Combinations
BOOT CODE SECTOR ARCHITECTURE
T
=
Top sector
B
=
Bottom sector
DEVICE NUMBER/DESCRIPTION
Am29F002B/Am29F002NB
2 Megabit (256 K x 8-Bit) CMOS Flash Memory
5.0 Volt-only Program and Erase
Valid Combinations
AM29F002BT-55
AM29F002BB-55
AM29F002NBT-55
AM29F002NBB-55
PC,
JC, JI,
EC, EI, ED, EF,
PD, JD, JF
AM29F002BT-70
AM29F002BB-70
AM29F002NBT-70
AM29F002NBB-70
PC, PI,
JC, JI,
EC, EI, ED, EF
PD, PF, JD, JF
AM29F002BT-90
AM29F002BB-90
AM29F002NBT-90
AM29F002NBB-90
PC, PI, PE,
JC, JI, JE,
EC, EI, EE
ED, EF, EK
PD, PF, PK
JD, JF, JK
November 1, 2006 21527D5
Valid Combinations
VCC Voltage
5.0 V ± 5%
Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
5.0 V ± 10%
Am29F002B/Am29F002NB
7
D A T A
S H E E T
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register
itself does not occupy any addressable memory location. The register is composed of latches that store the
commands, along with the address and data information needed to execute the command. The contents of
Table 1.
Operation
Read
Write
CMOS Standby
the register serve as inputs to the internal state
machine. The state machine outputs dictate the function of the device. The appropriate device bus
operations table lists the inputs and control levels
required, and the resulting output. The following subsections describe each of these operations in further
detail.
Am29F002B/Am29F002NB Device Bus Operations
CE#
OE#
WE#
RESET#
(n/a Am29F002NB)
A0–A17
DQ0–DQ7
L
L
H
H
AIN
DOUT
L
H
L
H
AIN
DIN
VCC ± 0.5 V
X
X
H
X
High-Z
TTL Standby
H
X
X
H
X
High-Z
Output Disable
L
H
H
H
X
High-Z
Reset (n/a on Am29F002NB)
X
X
X
L
X
High-Z
Temporary Sector Unprotect
(See Note)
X
X
X
VID
X
X
Legend:
L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, DIN = Data In, DOUT = Data Out, AIN = Address In
Note: See the sections on Sector Group Protection and Temporary Sector Unprotect for more information. This function requires
the RESET# pin and is therefore not available on the Am29F002NB device.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output
control and gates array data to the output pins. WE#
should remain at VIH.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No
command is necessary in this mode to obtain array
data. Standard microprocessor read cycles that assert
valid addresses on the device address inputs produce
valid data on the device data outputs. The device
remains enabled for read access until the command
register contents are altered.
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifications and to the Read Operations Timings diagram for
the timing waveforms. ICC1 in the DC Characteristics
table represents the active current specification for
reading array data.
sectors of memory), the system must drive WE# and
CE# to VIL, and OE# to VIH.
An erase operation can erase one sector, multiple sectors, or the entire device. The Sector Address Tables
indicate the address space that each sector occupies.
A “sector address” consists of the address bits required
to uniquely select a sector. See the Command Definitions section for details on erasing a sector or the entire
chip, or suspending/resuming the erase operation.
After the system writes the autoselect command
sequence, the device enters the autoselect mode. The
system can then read autoselect codes from the
internal register (which is separate from the memory
array) on DQ7–DQ0. Standard read cycle timings apply
in this mode. Refer to the “Autoselect Mode” and
Autoselect Command Sequence sections for more
information.
ICC2 in the DC Characteristics table represents the
active current specification for the write mode. The “AC
Characteristics” section contains timing specification
tables and timing diagrams for write operations.
Program and Erase Operation Status
Writing Commands/Command Sequences
To write a command or command sequence (which
includes programming data to the device and erasing
8
During an erase or program operation, the system may
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and ICC
read specifications apply. Refer to “Write Operation
Am29F002B/Am29F002NB
21527D5 November 1, 2006
D A T A
Status” for more information, and to each AC Characteristics section for timing diagrams.
Standby Mode
When the system is not reading or writing to the device,
it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the
outputs are placed in the high impedance state, independent of the OE# input.
The device enters the CMOS standby mode when CE#
and RESET# pins (CE# only on the Am29F002NB) are
both held at VCC ± 0.5 V. (Note that this is a more
restricted voltage range than VIH.) The device enters
the TTL standby mode when CE# and RESET# pins
(CE# only on the Am29F002NB) are both held at VIH.
The device requires standard access time (tCE) for read
access when the device is in either of these standby
modes, before it is ready to read data.
The device also enters the standby mode when the
RESET# pin is driven low. Refer to the next section,
“RESET#: Hardware Reset Pin”.
If the device is deselected during erasure or programming, the device draws active current until the
operation is completed.
In the DC Characteristics tables, ICC3 represents the
standby current specification.
S H E E T
RESET#: Hardware Reset Pin
Note: The RESET# pin is not available on the
Am29F002NB.
The RESET# pin provides a hardware method of resetting the device to reading array data. When the system
drives the RESET# pin low for at least a period of tRP,
the device immediately terminates any operation in
progress, tristates all data output pins, and ignores all
read/write attempts for the duration of the RESET#
pulse. The device also resets the internal state
machine to reading array data. The operation that was
interrupted should be reinitiated once the device is
ready to accept another command sequence, to
ensure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at VIL, the device enters
the TTL standby mode; if RESET# is held at VSS ±
0.5 V, the device enters the CMOS standby mode.
The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firmware from the Flash memory.
Refer to the AC Characteristics tables for RESET#
parameters and timing diagram.
Output Disable Mode
When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in the high impedance state.
Table 2.
Am29F002B/Am29F002NB Top Boot Block Sector Address Table
Sector
A17
A16
A15
A14
A13
Sector Size
(Kbytes)
Address Range
(in hexadecimal)
SA0
0
0
X
X
X
64
00000h–0FFFFh
SA1
0
1
X
X
X
64
10000h–1FFFFh
SA2
1
0
X
X
X
64
20000h–2FFFFh
SA3
1
1
0
X
X
32
30000h–37FFFh
SA4
1
1
1
0
0
8
38000h–39FFFh
SA5
1
1
1
0
1
8
3A000h–3BFFFh
SA6
1
1
1
1
X
16
3C000h–3FFFFh
November 1, 2006 21527D5
Am29F002B/Am29F002NB
9
D A T A
Table 3.
S H E E T
Am29F002B/Am29F002NB Bottom Boot Block Sector Address Table
Sector
A17
A16
A15
A14
A13
Sector Size
(Kbytes)
Address Range
(in hexadecimal)
SA0
0
0
0
0
X
16
00000h–03FFFh
SA1
0
0
0
1
0
8
04000h–05FFFh
SA2
0
0
0
1
1
8
06000h–07FFFh
SA3
0
0
1
X
X
32
08000h–0FFFFh
SA4
0
1
X
X
X
64
10000h–1FFFFh
SA5
1
0
X
X
X
64
20000h–2FFFFh
SA6
1
1
X
X
X
64
30000h–3FFFFh
Autoselect Mode
The autoselect mode provides manufacturer and
device identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended for programming equipment
to automatically match a device to be programmed with
its corresponding programming algorithm. However,
the autoselect codes can also be accessed in-system
through the command register.
When using programming equipment, the autoselect
mode requires VID on address pin A9. Address pins A6,
A1, and A0 must be as shown in Autoselect Codes
(High Voltage Method) table. In addition, when verifying
sector protection, the sector address must appear on
Table 4.
the appropriate highest order address bits. Refer to the
corresponding Sector Address Tables. The Command
Definitions table shows the remaining address bits that
are don’t care. When all necessary bits have been set
as required, the programming equipment may then
read the corresponding identifier code on DQ7–DQ0.
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in the Command Definitions table. This method does not require VID. See
“Command Definitions” for details on using the autoselect mode.
Am29F002B/Am29F002NB Autoselect Codes (High Voltage Method)
CE#
OE#
WE#
A17
to
A13
Manufacturer ID: AMD
L
L
H
X
X
VID
X
L
X
L
L
01h
Device ID:
Am29F002B/Am29F002NB
(Top Boot Block)
L
L
H
X
X
L
X
L
H
B0h
L
H
VID
X
L
Device ID:
Am29F002B/Am29F002NB
(Bottom Boot Block)
L
L
H
X
X
L
X
L
H
34h
L
H
VID
X
L
Description
A12
to
A10
A9
A8
to
A7
A6
A5
to
A2
A1
A0
DQ7
to
DQ0
01h
(protected)
Sector Protection Verification
L
L
H
SA
X
VID
X
L
X
H
L
00h
(unprotected)
L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
Sector Protection/Unprotection
The hardware sector protection feature disables both
program and erase operations in any sector. The hardware sector unprotection feature re-enables both
10
program and erase operations in previously protected
sectors.
Am29F002B/Am29F002NB
21527D5 November 1, 2006
D A T A
Sector protection/unprotection must be implemented
using programming equipment. The procedure
requires a high voltage (VID) on address pin A9 and the
control pins. Details on this method are provided in the
supplements, publication numbers 20819
(Am29F002B) and 21183 (Am29F002NB). Contact an
AMD representative to obtain a copy of the appropriate
document.
The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device
through AMD’s ExpressFlash™ Service. Contact an
AMD representative for details.
It is possible to determine whether a sector is protected
or unprotected. See “Autoselect Mode” for details.
Temporary Sector Unprotect
Note: This feature requires the RESET# pin and is
therefore not available on the Am29F002NB.
This feature allows temporary unprotection of previously protected sectors to change data in-system. The
Sector Unprotect mode is activated by setting the
RESET# pin to VID. During this mode, formerly protected sectors can be programmed or erased by
selecting the sector addresses. Once VID is removed
from the RESET# pin, all the previously protected
sectors are protected again. Figure 1 shows the algorithm, and the Temporary Sector Unprotect diagram
shows the timing waveforms, for this feature.
S H E E T
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to the Command Definitions table). In addition, the following hardware data
protection measures prevent accidental erasure or programming, which might otherwise be caused by
spurious system level signals during VCC power-up and
power-down transitions, or from system noise.
Low VCC Write Inhibit
When V CC is less than V LKO, the device does not
accept any write cycles. This protects data during VCC
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until VCC
is greater than VLKO. The system must provide the
proper signals to the control pins to prevent unintentional writes when VCC is greater than VLKO.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up, the
device does not accept commands on the rising edge
of WE#. The internal state machine is automatically
reset to reading array data on power-up.
START
RESET# = VID
(Note 1)
Perform Erase or
Program Operations
RESET# = VIH
Temporary Sector
Unprotect
Completed (Note 2)
Notes:
1. All protected sectors unprotected.
2. All previously protected sectors are protected once
again.
Figure 1.
Temporary Sector Unprotect Operation
November 1, 2006 21527D5
Am29F002B/Am29F002NB
11
D A T A
S H E E T
COMMAND DEFINITIONS
Writing specific address and data commands or
sequences into the command register initiates device
operations. The Command Definitions table defines the
valid register command sequences. Writing incorrect
address and data values or writing them in the
improper sequence resets the device to reading array
data.
All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the
“AC Characteristics” section.
Reading Array Data
Erase Suspend mode). Once programming begins,
however, the device ignores reset commands until the
operation is complete.
The reset command may be written between the
sequence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command must
be written to return to reading array data (also applies
to autoselect during Erase Suspend).
If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to
reading array data (also applies dur ing Erase
Suspend).
Autoselect Command Sequence
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after completing an Embedded Program or
Embedded Erase algorithm.
After the device accepts an Erase Suspend command,
the device enters the Erase Suspend mode. The
system can read array data using the standard read
timings, except that if it reads at an address within
erase-suspended sectors, the device outputs status
data. After completing a programming operation in the
Erase Suspend mode, the system may once again
read array data with the same exception. See “Erase
Suspend/Erase Resume Commands” for more information on this mode.
The system must issue the reset command to reenable the device for reading array data if DQ5 goes
high, or while in the autoselect mode. See the “Reset
Command” section, next.
See also “Requirements for Reading Array Data” in the
“Device Bus Operations” section for more information.
The Read Operations table provides the read parameters, and Read Operation Timings diagram shows the
timing diagram.
Reset Command
The autoselect command sequence allows the host
system to access the manufacturer and devices codes,
and determine whether or not a sector is protected.
The Command Definitions table shows the address
and data requirements. This method is an alternative to
that shown in the Autoselect Codes (High Voltage
Method) table, which is intended for PROM programmers and requires VID on address bit A9.
The autoselect command sequence is initiated by
writing two unlock cycles, followed by the autoselect
command. The device then enters the autoselect
mode, and the system may read at any address any
number of times, without initiating another command
sequence.
A read cycle at address XX00h or retrieves the manufacturer code. A read cycle at address XX01h returns
the device code. A read cycle containing a sector
address (SA) and the address 02h in returns 01h if that
sector is protected, or 00h if it is unprotected. Refer to
the Sector Address tables for valid sector addresses.
The system must write the reset command to exit the
autoselect mode and return to reading array data.
Byte Program Command Sequence
The reset command may be written between the
sequence cycles in an erase command sequence
before erasing begins. This resets the device to reading
array data. Once erasure begins, however, the device
ignores reset commands until the operation is
complete.
Programming is a four-bus-cycle operation. The
program command sequence is initiated by writing two
unlock write cycles, followed by the program set-up
command. The program address and data are written
next, which in turn initiate the Embedded Program
algorithm. The system is not required to provide further
controls or timings. The device automatically provides
internally generated program pulses and verify the programmed cell margin. The Command Definitions take
shows the address and data requirements for the byte
program command sequence.
The reset command may be written between the
sequence cycles in a program command sequence
before programming begins. This resets the device to
reading array data (also applies to programming in
When the Embedded Program algorithm is complete,
the device then returns to reading array data and
addresses are no longer latched. The system can
determine the status of the program operation by using
Writing the reset command to the device resets the
device to reading array data. Address bits are don’t
care for this command.
12
Am29F002B/Am29F002NB
21527D5 November 1, 2006
D A T A
DQ7 or DQ6. See “Write Operation Status” for information on these status bits.
Any commands written to the device during the
Embedded Program Algorithm are ignored. On the
Am29F002B only, note that a hardware reset during
the sector erase operation immediately terminates the
operation. The Sector Erase command sequence
should be reinitiated once the device has returned to
reading array data, to ensure data integrity.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from a “0” back to a “1”. Attempting to do so may halt
the operation and set DQ5 to “1”, or cause the Data#
Polling algorithm to indicate the operation was successful. However, a succeeding read will show that the
data is still “0”. Only erase operations can convert a “0”
to a “1”.
Write Program
Command Sequence
Sector Erase Command Sequence
No
Yes
No
Last Address?
Yes
Programming
Completed
Note: See the appropriate Command Definitions table for
program command sequence.
Figure 2.
Program Operation
Chip Erase Command Sequence
Chip erase is a six-bus-cycle operation. The chip erase
command sequence is initiated by writing two unlock
November 1, 2006 21527D5
Any commands wr itten to the chip dur ing the
Embedded Erase algorithm are ignored. On the
Am29F002B only, note that a hardware reset during
the sector erase operation immediately terminates the
operation. The Sector Erase command sequence
should be reinitiated once the device has returned to
reading array data, to ensure data integrity.
Figure 3 illustrates the algorithm for the erase operation. See the Erase/Program Operations tables in “AC
Characteristics” for parameters, and to the Chip/Sector
Erase Operation Timings for timing waveforms.
Data Poll
from System
Verify Data?
Increment Address
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any controls or timings during these operations. The Command
Definitions table shows the address and data requirements for the chip erase command sequence.
The system can determine the status of the erase operation by using DQ7, DQ6, or DQ2. See “Write
Operation Status” for information on these status bits.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are
no longer latched.
START
Embedded
Program
algorithm
in progress
S H E E T
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two
additional unlock write cycles are then followed by the
address of the sector to be erased, and the sector
erase command. The Command Definitions table
shows the address and data requirements for the
sector erase command sequence.
The device does not require the system to preprogram
the memory prior to erase. The Embedded Erase algorithm automatically programs and verifies the sector for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or
timings during these operations.
After the command sequence is written, a sector erase
time-out of 50 µs begins. During the time-out period,
additional sector addresses and sector erase commands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of
sectors may be from one sector to all sectors. The time
between these additional cycles must be less than 50
µs, otherwise the last address and command might not
be accepted, and erasure may begin. It is recommended that processor interrupts be disabled during
this time to ensure all commands are accepted. The
Am29F002B/Am29F002NB
13
D A T A
interrupts can be re-enabled after the last Sector Erase
command is written. If the time between additional
sector erase commands can be assumed to be less
than 50 µs, the system need not monitor DQ3. Any
command other than Sector Erase or Erase
Suspend during the time-out period resets the
device to reading array data. The system must
rewrite the command sequence and any additional
sector addresses and commands.
S H E E T
the Sector Erase Operations Timing diagram for timing
waveforms.
START
Write Erase
Command Sequence
The system can monitor DQ3 to determine if the sector
erase timer has timed out. (See the “DQ3: Sector Erase
Timer” section.) The time-out begins from the rising
edge of the final WE# pulse in the command sequence.
Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other commands
are ignored. On the Am29F002B only, note that a hardware reset dur ing the sector erase operation
immediately terminates the operation. The Sector
Erase command sequence should be reinitiated once
the device has returned to reading array data, to
ensure data integrity.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are
no longer latched. The system can determine the
status of the erase operation by using DQ7, DQ6, or
DQ2. Refer to “Write Operation Status” for information
on these status bits.
Figure 3 illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations tables in
the “AC Characteristics” section for parameters, and to
Data Poll
from System
No
Data = FFh?
Yes
Erasure Completed
Notes:
1. See the appropriate Command Definitions table for erase
command sequence.
2. See “DQ3: Sector Erase Timer” for more information.
Figure 3.
14
Embedded
Erase
algorithm
in progress
Am29F002B/Am29F002NB
Erase Operation
21527D5 November 1, 2006
D A T A
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to
interrupt a sector erase operation and then read data
from, or program data to, any sector not selected for
erasure. This command is valid only during the sector
erase operation, including the 50 µs time-out period
during the sector erase command sequence. The
Erase Suspend command is ignored if written during
the chip erase operation or Embedded Program algorithm. Writing the Erase Suspend command during the
Sector Erase time-out immediately terminates the
time-out period and suspends the erase operation.
Addresses are “don’t-cares” when writing the Erase
Suspend command.
When the Erase Suspend command is written during a
sector erase operation, the device requires a maximum
of 20 µs to suspend the erase operation. However,
when the Erase Suspend command is written during
the sector erase time-out, the device immediately terminates the time-out period and suspends the erase
operation.
After the erase operation has been suspended, the
system can read array data from or program data to
any sector not selected for erasure. (The device “erase
suspends” all sectors selected for erasure.) Normal
read and write timings and command definitions apply.
Reading at any address within erase-suspended
sectors produces status data on DQ7–DQ0. The
November 1, 2006 21527D5
S H E E T
system can use DQ7, or DQ6 and DQ2 together, to
determine if a sector is actively erasing or is erase-suspended. See “Write Operation Status” for information
on these status bits.
After an erase-suspended program operation is complete, the system can once again read array data within
non-suspended sectors. The system can determine
the status of the program operation using the DQ7 or
DQ6 status bits, just as in the standard program operation. See “Wr ite Operation Status” for more
information.
The system may also write the autoselect command
sequence when the device is in the Erase Suspend
mode. The device allows reading autoselect codes
even at addresses within erasing sectors, since the
codes are not stored in the memory array. When the
device exits the autoselect mode, the device reverts to
the Erase Suspend mode, and is ready for another
valid operation. See “Autoselect Command Sequence”
for more information.
The system must write the Erase Resume command
(address bits are “don’t care”) to exit the erase suspend
mode and continue the sector erase operation. Further
writes of the Resume command are ignored. Another
Erase Suspend command can be written after the
device has resumed erasing.
Am29F002B/Am29F002NB
15
D A T A
S H E E T
Command Definitions
Command
Sequence
(Note 1)
Cycles
Table 5.
Am29F002B/Am29F002NB Command Definitions
Bus Cycles (Notes 2–4)
First
Second
Addr
Data
RD
Third
Addr
Data
Addr
Fourth
Data Addr
Data
Read (Note 5)
1
RA
Reset (Note 6)
1
XXX
F0
4
555
AA
2AA
55
555
90
X00
01
4
555
AA
2AA
55
555
90
X01
B0
4
555
AA
2AA
55
555
90
X01
34
4
555
AA
2AA
55
555
90
(SA)
X02
00
PD
Manufacturer ID
Device ID,
Top Boot Block
AutoDevice ID,
select
(Note 7) Bottom Boot Block
Sector Protect Verify
(Note 8)
Fifth
Sixth
Addr Data
Addr
Data
01
Program
4
555
AA
2AA
55
555
A0
PA
Chip Erase
6
555
AA
2AA
55
555
80
555
AA
2AA
55
555
10
Sector Erase
6
555
AA
2AA
55
555
80
555
AA
2AA
55
SA
30
Erase Suspend (Note 9)
1
XXX
B0
Erase Resume (Note 10)
1
XXX
30
Legend:
PD = Data to be programmed at location PA. Data latches on the
rising edge of WE# or CE# pulse, whichever happens first.
X = Don’t care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
SA = Address of the sector to be verified (in autoselect mode) or
erased. Address bits A17–A13 uniquely select any sector.
PA = Address of the memory location to be programmed.
Addresses latch on the falling edge of the WE# or CE# pulse,
whichever happens later.
Notes:
1. See Table 1 for description of bus operations.
7. The fourth cycle of the autoselect command sequence is a
read cycle.
2. All values are in hexadecimal.
3. Except when reading array or autoselect data, all bus cycles
are write operations.
4. Address bits A17–A11 are don’t cares for unlock and
command cycles, except when PA or SA is required.
5. No unlock or command cycles required when reading array
data.
6. The Reset command is required to return to reading array
data when device is in the autoselect mode, or if DQ5 goes
high (while the device is providing status data).
16
8. The data is 00h for an unprotected sector and 01h for a
protected sector. See “Autoselect Command Sequence” for
more information.
9. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend
mode. The Erase Suspend command is valid only during a
sector erase operation.
10. The Erase Resume command is valid only during the Erase
Suspend mode.
Am29F002B/Am29F002NB
21527D5 November 1, 2006
D A T A
S H E E T
WRITE OPERATION STATUS
The device provides several bits to determine the
status of a write operation: DQ2, DQ3, DQ5, DQ6, and
DQ7. Table 6 and the following subsections describe
the functions of these bits. DQ7 and DQ6 each offer a
method for determining whether a program or erase
operation is complete or in progress. These three bits
are discussed first.
Table 6 shows the outputs for Data# Polling on DQ7.
Figure 4 shows the Data# Polling algorithm.
START
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host
system whether an Embedded Algorithm is in progress
or completed, or whether the device is in Erase Suspend. Data# Polling is valid after the rising edge of the
final WE# pulse in the program or erase command
sequence.
During the Embedded Program algorithm, the device
outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to
programming during Erase Suspend. When the
Embedded Program algorithm is complete, the device
outputs the datum programmed to DQ7. The system
must provide the program address to read valid status
information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for
approximately 2 µs, then the device returns to reading
array data.
Read DQ7–DQ0
Addr = VA
DQ7 = Data?
No
No
DQ5 = 1?
Yes
During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7. When the Embedded Erase
algorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
This is analogous to the complement/true datum output
described for the Embedded Program algorithm: the
erase function changes all the bits in a sector to “1”;
prior to this, the device outputs the “complement,” or
“0.” The system must provide an address within any of
the sectors selected for erasure to read valid status
information on DQ7.
Read DQ7–DQ0
Addr = VA
After an erase command sequence is written, if all
sectors selected for erasing are protected, Data#
Polling on DQ7 is active for approximately 100 µs, then
the device returns to reading array data. If not all
selected sectors are protected, the Embedded Erase
algorithm erases the unprotected sectors, and ignores
the selected sectors that are protected.
FAIL
When the system detects DQ7 has changed from the
complement to true data, it can read valid data at DQ7–
DQ0 on the following read cycles. This is because DQ7
may change asynchronously with DQ0–DQ6 while
Output Enable (OE#) is asserted low. The Data#
Polling Timings (During Embedded Algorithms) figure
in the “AC Characteristics” section illustrates this.
November 1, 2006 21527D5
Yes
DQ7 = Data?
Yes
No
PASS
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5.
Figure 4.
Am29F002B/Am29F002NB
Data# Polling Algorithm
17
D A T A
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or complete,
or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is
valid after the rising edge of the final WE# pulse in the
command sequence (prior to the program or erase
operation), and during the sector erase time-out.
During an Embedded Program or Erase algorithm
operation, successive read cycles to any address
cause DQ6 to toggle. (The system may use either OE#
or CE# to control the read cycles.) When the operation
is complete, DQ6 stops toggling.
After an erase command sequence is written, if all
sectors selected for erasing are protected, DQ6 toggles
for approximately 100 μs, then returns to reading array
data. If not all selected sectors are protected, the
Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are
protected.
The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erasesuspended. When the device is actively erasing (that is,
the Embedded Erase algorithm is in progress), DQ6
toggles. When the device enters the Erase Suspend
mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing
or erase-suspended. Alternatively, the system can use
DQ7 (see the subsection on DQ7: Data# Polling).
If a program address falls within a protected sector,
DQ6 toggles for approximately 2 µs after the program
command sequence is written, then returns to reading
array data.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded
Program algorithm is complete.
The Write Operation Status table shows the outputs for
Toggle Bit I on DQ6. Refer to Figure 5 for the toggle bit
algorithm, and to the Toggle Bit Timings figure in the
“AC Characteristics” section for the timing diagram.
The DQ2 vs. DQ6 figure shows the differences
between DQ2 and DQ6 in graphical form. See also the
subsection on DQ2: Toggle Bit II.
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for erasure. (The system may use either OE# or CE# to
18
S H E E T
control the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but
cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and
mode information. Refer to Table 6 to compare outputs
for DQ2 and DQ6.
Figure 5 shows the toggle bit algorithm in flowchart
form, and the section “DQ2: Toggle Bit II” explains the
algorithm. See also the DQ6: Toggle Bit I subsection.
Refer to the Toggle Bit Timings figure for the toggle bit
timing diagram. The DQ2 vs. DQ6 figure shows the differences between DQ2 and DQ6 in graphical form.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 5 for the following discussion. Whenever the system initially begins reading toggle bit
status, it must read DQ7–DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typically, a
system would note and store the value of the toggle bit
after the first read. After the second read, the system
would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can
read array data on DQ7–DQ0 on the following read
cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the
system also should note whether the value of DQ5 is
high (see the section on DQ5). If it is, the system
should then determine again whether the toggle bit is
toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer
toggling, the device has successfully completed the
program or erase operation. If it is still toggling, the
device did not complete the operation successfully, and
the system must write the reset command to return to
reading array data.
The remaining scenario is that the system initially
determines that the toggle bit is toggling and DQ5 has
not gone high. The system may continue to monitor the
toggle bit and DQ5 through successive read cycles,
determining the status as described in the previous
paragraph. Alternatively, it may choose to perform
other system tasks. In this case, the system must start
at the beginning of the algorithm when it returns to
determine the status of the operation (top of Figure 5).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under
these conditions DQ5 produces a “1.” This is a failure
condition that indicates the program or erase cycle was
not successfully completed.
Am29F002B/Am29F002NB
21527D5 November 1, 2006
D A T A
S H E E T
The DQ5 failure condition may appear if the system
tries to program a “1” to a location that is previously programmed to “0.” Only an erase operation can change
a “0” back to a “1.” Under this condition, the device
halts the operation, and when the operation has
exceeded the timing limits, DQ5 produces a “1.”
START
Under both these conditions, the system must issue the
reset command to return the device to reading array
data.
Read DQ7–DQ0
DQ3: Sector Erase Timer
Read DQ7–DQ0
(Note 1)
Toggle Bit
= Toggle?
No
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not an
erase operation has begun. (The sector erase timer
does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire timeout also applies after each additional sector erase command. When the time-out is complete, DQ3 switches
from “0” to “1.” The system may ignore DQ3 if the
system can guarantee that the time between additional
sector erase commands will always be less than 50 μs.
See also the “Sector Erase Command Sequence”
section.
Yes
No
DQ5 = 1?
Yes
After the sector erase command sequence is written,
the system should read the status on DQ7 (Data#
Polling) or DQ6 (Toggle Bit I) to ensure the device has
accepted the command sequence, and then read DQ3.
If DQ3 is “1”, the internally controlled erase cycle has
begun; all further commands (other than Erase Suspend) are ignored until the erase operation is complete.
If DQ3 is “0”, the device will accept additional sector
erase commands. To ensure the command has been
accepted, the system software should check the status
of DQ3 prior to and following each subsequent sector
erase command. If DQ3 is high on the second status
check, the last command might not have been
accepted. Table 6 shows the outputs for DQ3.
Read DQ7–DQ0
Twice
Toggle Bit
= Toggle?
(Notes
1, 2)
No
Yes
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Notes:
1. Read toggle bit twice to determine whether or not it is
toggling. See text.
2. Recheck toggle bit because it may stop toggling as DQ5
changes to “1”. See text.
Figure 5.
November 1, 2006 21527D5
Am29F002B/Am29F002NB
Toggle Bit Algorithm
19
D A T A
S H E E T
Table 6. Write Operation Status
DQ7
(Note 1)
DQ6
DQ5
(Note 2)
DQ3
DQ2
(Note 1)
DQ7#
Toggle
0
N/A
No toggle
Embedded Erase Algorithm
0
Toggle
0
1
Toggle
Reading within Erase
Suspended Sector
1
No toggle
0
N/A
Toggle
Reading within Non-Erase
Suspended Sector
Data
Data
Data
Data
Data
Erase-Suspend-Program
DQ7#
Toggle
0
N/A
N/A
Operation
Standard
Mode
Erase
Suspend
Mode
Embedded Program Algorithm
Notes:
1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
2. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
See “DQ5: Exceeded Timing Limits” for more information.
20
Am29F002B/Am29F002NB
21527D5 November 1, 2006
D A T A
S H E E T
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C
Ambient Temperature
with Power Applied. . . . . . . . . . . . . . –55°C to +125°C
20 ns
20 ns
+0.8 V
–0.5 V
Voltage with Respect to Ground
VCC (Note 1) . . . . . . . . . . . . . . . . –2.0 V to +7.0 V
–2.0 V
A9, OE#, and
RESET# (Note 2). . . . . . . . . . . .–2.0 V to +12.5 V
20 ns
All other pins (Note 1) . . . . . . . . . –0.5 V to +7.0 V
Figure 6. Maximum Negative
Overshoot Waveform
Output Short Circuit Current (Note 3) . . . . . . 200 mA
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V. During
voltage transitions, input or I/O pins may overshoot VSS to
–2.0 V for periods of up to 20 ns. See Figure 6. Maximum
DC voltage on input or I/O pins is VCC +0.5 V. During
voltage transitions, input or I/O pins may overshoot to VCC
+2.0 V for periods up to 20 ns. See Figure 7.
2. Minimum DC input voltage on pins A9, OE#, and RESET#
is –0.5 V. During voltage transitions, A9, OE#, and
RESET# may overshoot VSS to –2.0 V for periods of up to
20 ns. See Figure 6. Maximum DC input voltage on pin A9
is +12.5 V which may overshoot to +13.5 V for periods up
to 20 ns. (RESET# is not available on Am29F002NB)
20 ns
VCC
+2.0 V
VCC
+0.5 V
2.0 V
3. No more than one output may be shorted to ground at a
time. Duration of the short circuit should not be greater
than one second.
20 ns
20 ns
Figure 7. Maximum Positive
Overshoot Waveform
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is
a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the
operational sections of this data sheet is not implied.
Exposure of the device to absolute maximum rating
conditions for extended periods may affect device reliability.
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (TA) . . . . . . . . . . . 0°C to +70°C
Industrial (I) Devices
Ambient Temperature (TA) . . . . . . . . . –40°C to +85°C
Extended (E) Devices
Ambient Temperature (TA) . . . . . . . . –55°C to +125°C
VCC Supply Voltages
VCC for ± 5% devices . . . . . . . . . . .+4.75 V to +5.25 V
VCC for ± 10% devices . . . . . . . . . . . .+4.5 V to +5.5 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
November 1, 2006 21527D5
Am29F002B/Am29F002NB
21
D A T A
S H E E T
DC CHARACTERISTICS
TTL/NMOS Compatible
Parameter
Description
Test Conditions
Min
Typ
Max
Unit
±1.0
µA
50
µA
±1.0
µA
ILI
Input Load Current
VIN = VSS to VCC, VCC = VCC max
ILIT
A9, OE#, RESET# Input Load Current
(Notes 1, 5)
VCC = VCC max;
A9, OE#, RESET# = 12.5 V
ILO
Output Leakage Current
VOUT = VSS to VCC, VCC = VCC max
ICC1
VCC Active Read Current (Notes 2, 3)
CE# = VIL, OE# = VIH
20
30
mA
ICC2
VCC Active Write Current (Notes 2, 4, 5) CE# = VIL, OE# = VIH
30
40
mA
ICC3
VCC Standby Current (Note 2)
CE#, OE# = VIH
0.4
1
mA
ICC4
VCC Reset Current (Notes 1, 2)
RESET# = VIL
0.4
1
mA
VIL
Input Low Voltage
–0.5
0.8
V
VIH
Input High Voltage
2.0
VCC
+ 0.5
V
VID
Voltage for Autoselect and Temporary
Sector Unprotect
VCC = 5.0 V
11.5
12.5
V
VOL
Output Low Voltage
IOL = 12 mA, VCC = VCC min
0.45
V
VOH
Output High Voltage
IOH = –2.5 mA, VCC = VCC min
VLKO
Low VCC Lock-Out Voltage
2.4
3.2
V
4.2
V
Notes:
1. RESET# is not available on Am29F002NB.
2. Maximum ICC specifications are tested with VCC = VCCmax.
3. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH.
4. ICC active while Embedded Erase or Embedded Program is in progress.
5. Not 100% tested.
22
Am29F002B/Am29F002NB
21527D5 November 1, 2006
D A T A
S H E E T
DC CHARACTERISTICS
CMOS Compatible
Parameter
Description
Test Conditions
Min
Typ
Max
Unit
±1.0
µA
50
µA
±1.0
µA
ILI
Input Load Current
VIN = VSS to VCC,
VCC = VCC max
ILIT
A9, OE#, RESET#
Input Load Current (Notes 1, 5)
VCC = VCC max;
A9, OE#, RESET# = 12.5 V
ILO
Output Leakage Current
VOUT = VSS to VCC,
VCC = VCC max
ICC1
VCC Active Read Current
(Notes 2, 3)
CE# = VIL, OE# = VIH
20
30
mA
ICC2
VCC Active Write Current
(Notes 2, 4, 5)
CE# = VIL, OE# = VIH
30
40
mA
ICC3
VCC Standby Current
(Notes 2, 6)
CE# = VCC ± 0.5 V
1
5
µA
ICC4
VCC Reset Current
(Notes 1, 2, 6)
RESET# = VIL
1
5
µA
VIL
Input Low Voltage
–0.5
0.8
V
VIH
Input High Voltage
0.7 x VCC
VCC + 0.3
V
VID
Voltage for Autoselect and
Temporary Sector Unprotect
VCC = 5.0 V
11.5
12.5
V
VOL
Output Low Voltage
IOL = 12 mA, VCC = VCC min
0.45
V
VOH1
Output High Voltage
VOH2
VLKO
IOH = –2.5 mA, VCC = VCC min
0.85 VCC
IOH = –100 µA, VCC = VCC min
VCC–0.4
Low VCC Lock-Out Voltage
3.2
V
4.2
V
Notes:
1. RESET# is not available on Am29F002NB.
2. Maximum ICC specifications are tested with VCC = VCCmax.
3. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH.
4. ICC active while Embedded Erase or Embedded Program is in progress.
5. Not 100% tested.
6. ICC3 and ICC4 = 20 µA max at extended temperature (>+85° C).
November 1, 2006 21527D5
Am29F002B/Am29F002NB
23
D A T A
S H E E T
TEST CONDITIONS
Table 7.
Test Specifications
5.0 V
Test Condition
2.7 kΩ
Device
Under
Test
CL
All
others
-55
Output Load
Unit
1 TTL gate
Output Load Capacitance, CL
(including jig capacitance)
30
100
pF
Input Rise and Fall Times
5
20
ns
0.0–3.0
0.45–2.4
V
Input timing measurement
reference levels
1.5
0.8, 2.0
V
Output timing measurement
reference levels
1.5
0.8, 2.0
V
6.2 kΩ
Input Pulse Levels
Note: Diodes are IN3064 or equivalent
Figure 8.
Test Setup
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
24
Don’t Care, Any Change Permitted
Changing, State Unknown
Does Not Apply
Center Line is High Impedance State (High Z)
Am29F002B/Am29F002NB
21527D5 November 1, 2006
D A T A
S H E E T
AC CHARACTERISTICS
Read Operations
Parameter
Speed Options
JEDEC
Std
Description
tAVAV
tRC
Read Cycle Time (Note 1)
tAVQV
tACC
Address to Output Delay
tELQV
tCE
Chip Enable to Output Delay
tGLQV
tOE
tEHQZ
tGHQZ
tAXQX
Test Setup
-55
-70
-90
Unit
Min
55
70
90
ns
CE# = VIL
OE# = VIL
Max
55
70
90
ns
OE# = VIL
Max
55
70
90
ns
Output Enable to Output Delay
Max
30
30
35
ns
tDF
Chip Enable to Output High Z (Note 1)
Max
15
20
20
ns
tDF
Output Enable to Output High Z
(Note 1)
Max
15
20
20
ns
Read
Min
0
ns
Toggle and
Data# Polling
Min
10
ns
Min
0
ns
tOEH
Output Enable
Hold Time
(Note 1)
tOH
Output Hold Time From Addresses, CE# or
OE#, Whichever Occurs First (Note 1)
Notes:
1. Not 100% tested.
2. See Table 7 and Figure 8 for test specifications.
tRC
Addresses Stable
Addresses
tACC
CE#
tDF
tOE
OE#
tOEH
WE#
tCE
tOH
HIGH Z
Outputs
HIGH Z
Output Valid
RESET#
n/a Am29F002NB
Figure 9. Read Operations Timings
November 1, 2006 21527D5
Am29F002B/Am29F002NB
25
D A T A
S H E E T
AC CHARACTERISTICS
Hardware Reset (RESET#)
Parameter
JEDEC
Std
Description
Test Setup
All Speed Options
Unit
tREADY
RESET# Pin Low (During Embedded
Algorithms) to Read or Write (See Note)
Max
20
µs
tREADY
RESET# Pin Low (NOT During Embedded
Algorithms) to Read or Write (See Note)
Max
500
ns
tRP
RESET# Pulse Width
Min
500
ns
tRH
RESET# High Time Before Read (See Note)
Min
50
ns
Note: Not 100% tested. RESET# is not available on Am29F002NB.
CE#, OE#
tRH
RESET#
n/a Am29F002NB
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
RESET#
n/a Am29F002NB
tRP
Figure 10.
26
RESET# Timings
Am29F002B/Am29F002NB
21527D5 November 1, 2006
D A T A
S H E E T
AC CHARACTERISTICS
Erase/Program Operations
Parameter
Speed Options
JEDEC
Std
Description
-55
-70
-90
Unit
tAVAV
tWC
Write Cycle Time (Note 1)
Min
55
70
90
ns
tAVWL
tAS
Address Setup Time
Min
tWLAX
tAH
Address Hold Time
Min
45
45
45
ns
tDVWH
tDS
Data Setup Time
Min
25
30
45
ns
tWHDX
tDH
Data Hold Time
Min
0
ns
tOES
Output Enable Setup Time
Min
0
ns
Read Recovery Time Before Write
(OE# High to WE# Low)
Min
0
ns
0
ns
tGHWL
tGHWL
tELWL
tCS
CE# Setup Time
Min
0
ns
tWHEH
tCH
CE# Hold Time
Min
0
ns
tWLWH
tWP
Write Pulse Width
Min
tWHWL
tWPH
Write Pulse Width High
Min
20
ns
tWHWH1
tWHWH1
Programming Operation (Note 2)
Typ
7
µs
tWHWH2
tWHWH2
Sector Erase Operation (Note 2)
Typ
1
sec
VCC Setup Time (Note 1)
Min
50
µs
tVCS
30
35
45
ns
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
November 1, 2006 21527D5
Am29F002B/Am29F002NB
27
D A T A
S H E E T
AC CHARACTERISTICS
Program Command Sequence (last two cycles)
tAS
tWC
Addresses
Read Status Data (last two cycles)
555h
PA
PA
PA
tAH
CE#
tCH
OE#
tWHWH1
tWP
WE#
tWPH
tCS
tDS
tDH
PD
A0h
Data
Status
DOUT
VCC
tVCS
Notes:
1. PA = program address, PD = program data, DOUT is the true data at the program address.
Figure 11.
28
Program Operation Timings
Am29F002B/Am29F002NB
21527D5 November 1, 2006
D A T A
S H E E T
AC CHARACTERISTICS
Erase Command Sequence (last two cycles)
tAS
tWC
2AAh
Addresses
Read Status Data
VA
SA
VA
555h for chip erase
tAH
CE#
tCH
OE#
tWP
WE#
tWPH
tCS
tWHWH2
tDS
tDH
Data
55h
30h
In
Progress
Complete
10 for Chip Erase
tVCS
VCC
Notes:
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (”see “Write Operation Status”).
Figure 12.
November 1, 2006 21527D5
Chip/Sector Erase Operation Timings
Am29F002B/Am29F002NB
29
D A T A
S H E E T
AC CHARACTERISTICS
tRC
Addresses
VA
VA
VA
tACC
tCE
CE#
tCH
tOE
OE#
tOEH
tDF
WE#
tOH
High Z
DQ7
Complement
Complement
DQ0–DQ6
Status Data
Status Data
Valid Data
True
High Z
Valid Data
True
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
Figure 13. Data# Polling Timings (During Embedded Algorithms)
tRC
Addresses
VA
VA
VA
VA
tACC
tCE
CE#
tCH
tOE
OE#
tOEH
tDF
WE#
tOH
DQ6/DQ2
High Z
Valid Status
Valid Status
(first read)
(second read)
Valid Status
Valid Data
(stops toggling)
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read
cycle, and array data read cycle.
Figure 14.
30
Toggle Bit Timings (During Embedded Algorithms)
Am29F002B/Am29F002NB
21527D5 November 1, 2006
D A T A
S H E E T
AC CHARACTERISTICS
Enter
Embedded
Erasing
Erase
Suspend
Erase
WE#
Enter Erase
Suspend Program
Erase
Resume
Erase
Suspend
Program
Erase Suspend
Read
Erase Suspend
Read
Erase
Complete
Erase
DQ6
DQ2
Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an
erase-suspended sector.
Figure 15. DQ2 vs. DQ6
Temporary Sector Unprotect (Am29F002B only)
Parameter
JEDEC
Std.
Description
tVIDR
VID Rise and Fall Time (See Note)
tRSP
RESET# Setup Time for Temporary Sector
Unprotect
All Speed Options
Unit
Min
500
ns
Min
4
µs
Note: Not 100% tested.
12 V
RESET#
0 or 5 V
0 or 5 V
tVIDR
tVIDR
Program or Erase Command Sequence
CE#
WE#
tRSP
RY/BY#
Figure 16. Temporary Sector Unprotect Timing Diagram (Am29F002B only)
November 1, 2006 21527D5
Am29F002B/Am29F002NB
31
D A T A
S H E E T
AC CHARACTERISTICS
Alternate CE# Controlled Erase/Program Operations
Parameter
Speed Options
JEDEC
Std.
Description
-55
-70
-90
Unit
tAVAV
tWC
Write Cycle Time (Note 1)
Min
55
70
90
ns
tAVEL
tAS
Address Setup Time
Min
tELAX
tAH
Address Hold Time
Min
45
45
45
ns
tDVEH
tDS
Data Setup Time
Min
25
30
45
ns
tEHDX
tDH
Data Hold Time
Min
0
ns
tOES
Output Enable Setup Time
Min
0
ns
tGHEL
tGHEL
Read Recovery Time Before Write
(OE# High to WE# Low)
Min
0
ns
tWLEL
tWS
WE# Setup Time
Min
0
ns
tEHWH
tWH
WE# Hold Time
Min
0
ns
tELEH
tCP
CE# Pulse Width
Min
tEHEL
tCPH
CE# Pulse Width High
Min
20
ns
tWHWH1
tWHWH1
Programming Operation (Note 2)
Typ
7
µs
tWHWH2
tWHWH2
Sector Erase Operation (Note 2)
Typ
1
sec
0
30
35
ns
45
ns
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
32
Am29F002B/Am29F002NB
21527D5 November 1, 2006
D A T A
S H E E T
AC CHARACTERISTICS
555 for program
2AA for erase
PA for program
SA for sector erase
555 for chip erase
Data# Polling
Addresses
PA
tWC
tAS
tAH
tWH
WE#
tGHEL
OE#
tCP
CE#
tWS
tWHWH1 or 2
tCPH
tDS
tDH
DQ7#
Data
tRH
A0 for program
55 for erase
DOUT
PD for program
30 for sector erase
10 for chip erase
RESET#
Notes:
1. PA = Program Address, PD = Program Data, DQ7# = complement of data written to device, DOUT = data written to device.
2. Figure indicates the last two bus cycles of the command sequence.
Figure 17.
November 1, 2006 21527D5
Alternate CE# Controlled Write Operation Timings
Am29F002B/Am29F002NB
33
D A T A
S H E E T
ERASE AND PROGRAMMING PERFORMANCE
Parameter
Typ (Note 1)
Max (Note 2)
Unit
Sector Erase Time
1
8
s
Chip Erase Time
7
Byte Programming Time
7
300
µs
1.8
5.4
s
Chip Programming Time (Note 3)
s
Comments
Excludes 00h programming
prior to erasure (Note 4)
Excludes system level
overhead (Note 5)
Notes:
1. Typical program and erase times assume the following conditions: 25×C, 5.0 V VCC, 1,000,000 cycles. Additionally,
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 4.5 V (4.75 V for ±5% devices), 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the four-bus-cycle sequence for the program command. See Table 5
for further information on command definitions.
6. The device has a minimum guaranteed erase and program cycle endurance of 1,000,000 cycles.
LATCHUP CHARACTERISTICS
Description
Min
Max
Input voltage with respect to VSS on all pins except I/O pins
(including A9, OE#, and RESET#)
–1.0 V
12.5 V
Input voltage with respect to VSS on all I/O pins
–1.0 V
VCC + 1.0 V
–100 mA
+100 mA
VCC Current
Note: Includes all pins except VCC. Test conditions: VCC = 5.0 V, one pin at a time. RESET# not available on Am29F002NB.
TSOP PIN CAPACITANCE
Parameter
Symbol
Parameter Description
Test Setup
Typ
Max
Unit
CIN
Input Capacitance
VIN = 0
6
7.5
pF
COUT
Output Capacitance
VOUT = 0
8.5
12
pF
CIN2
Control Pin Capacitance
VIN = 0
7.5
9
pF
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
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Am29F002B/Am29F002NB
21527D5 November 1, 2006
D A T A
S H E E T
PLCC AND PDIP PIN CAPACITANCE
Parameter
Symbol
Parameter Description
Test Conditions
Typ
Max
Unit
Input Capacitance
VIN = 0
4
6
pF
COUT
Output Capacitance
VOUT = 0
8
12
pF
CIN2
Control Pin Capacitance
VPP = 0
8
12
pF
CIN
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
DATA RETENTION
Parameter
Test Conditions
Min
Unit
150°C
10
Years
125°C
20
Years
Minimum Pattern Data Retention Time
November 1, 2006 21527D5
Am29F002B/Am29F002NB
35
D A T A
S H E E T
PHYSICAL DIMENSIONS
PD 032—32-Pin Plastic DIP
Dwg rev AD; 10/99
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Am29F002B/Am29F002NB
21527D5 November 1, 2006
D A T A
S H E E T
PHYSICAL DIMENSIONS (continued)
PL 032—32-Pin Plastic Leaded Chip Carrier
Dwg rev AH; 10/99
November 1, 2006 21527D5
Am29F002B/Am29F002NB
37
D A T A
S H E E T
PHYSICAL DIMENSIONS (continued)
TS 032—32-Pin Standard Thin Small Package
Dwg rev AA; 10/99
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Am29F002B/Am29F002NB
21527D5 November 1, 2006
D A T A
S H E E T
REVISION SUMMARY
Revision A (July 1998)
Physical Dimensions
Initial release.
Replaced figures with more detailed illustrations.
Revision B (January 1999)
Revision D (November 28, 2000)
Distinctive Characteristics
Global
Added:
Added table of contents.
■ 20-year data retention at 125°C
Ordering Information
— Reliable operation for the life of the system
Deleted burn-in option.
AC Characterisitics—Read Operations Table
Table 5, Command Definitions
tEHQZ, tGHQZ: Changed the 55 speed option to 15 ns
from 20 ns
In Note 4, changed the lower address bit of don’t care
range to A11.
AC Characteristics—Erase/Program Operations
tWLAX: Changed the 90 speed option to 45 ns from 50 ns.
tDVWH: Changed the 55 speed option to 25 ns from 30 ns.
tWLWH: changed the 55 speed option to 30 ns from 35 ns.
AC Characteristics—Alternate CE# Controlled
Erase/Program Operations
Revision D +1 (November 5, 2004)
Ordering Information and Valid Combinations
Added Pb-Free options
Revision D +2 (August 3, 2005)
Ordering Information and Valid Combinations
tDVEH: Changed the 55 speed option to 25 ns from 30 ns.
Added Pb-Free options
tELEH: Changed the 55 speed option to 30 ns from 35 ns.
Revision D3 (December 13, 2005)
tELAX: Changed the 90 speed option to 45 ns from 50 ns.
Global
DC Characteristics—TTL/NMOS Compatible
Deleted 120 ns speed option.
ICC1, ICC2, ICC3, ICC4: Added Note 2 “Maximum ICC
specifications are tested with VCC = VCCmax”.
Revision D4 (May 17, 2006)
Added “Not recommended for new designs” note.
DC Characteristics—CMOS Compatible
ICC1, ICC2, ICC3, ICC4: Added Note 2 “Maximum ICC
specifications are tested with VCC = VCCmax”.
Revision D5 (November 1, 2006)
Deleted “Not recommended for new designs” note.
Revision C (November 12, 1999)
AC Characteristics—Figure 11. Program
Operations Timing and Figure 12. Chip/Sector
Erase Operations
Deleted tGHWL and changed OE# waveform to start at
high.
November 1, 2006 21527D5
Am29F002B/Am29F002NB
39
D A T A
S H E E T
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the
public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for
any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to
you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating
conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign
Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products.
Trademarks
Copyright © 2006 Spansion Inc. All rights reserved. Spansion, the Spansion logo, MirrorBit, ORNAND, HD-SIM, and combinations thereof, are
trademarks of Spansion Inc. Other company and product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
Copyright © 1998–2005 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are
for identification purposes only and may be trademarks of their respective companies
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