ON NLAS4053DT Analog multiplexer/demultiplexer Datasheet

NLAS4053
Analog Multiplexer/
Demultiplexer
Triple 2:1 Analog Switch−Multiplexer
Improved Process, Sub−Micron Silicon
Gate CMOS
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MARKING
DIAGRAMS
The NLAS4053 is an improved version of the MC14053 and
MC74HC4053 fabricated in sub−micron Silicon Gate CMOS
technology for lower RDS(on) resistance and improved linearity with
low current. This device may be operated either with a single supply or
dual supply up to ±3.0 V to pass a 6 VPP signal without coupling
capacitors.
When operating in single supply mode, it is only necessary to tie
VEE, pin 7 to ground. For dual supply operation, VEE is tied to a
negative voltage, not to exceed maximum ratings. Pin for pin
compatible with all industry standard versions of ‘4053.’
SOIC−16
D SUFFIX
CASE 751B
Features
TSSOP−16
DT SUFFIX
CASE 948F
• Improved RDS(on) Specifications
• Pin for Pin Replacement for MAX4053 and MAX4053A
•
16
NLAS4053G
AWLYWW
1
16
NLAS
4053
ALYWG
G
1
− One Half the Resistance Operating at 5.0 Volts
Single or Dual Supply Operation
− Single 3−5 Volt Operation, or Dual ±3.0 Volt Operation
− With VCC of 3.0 to 3.3 V, Device Can Interface with 1.8 V Logic,
− No Translators Needed
− Address and Inhibit Pins are Over−Voltage Tolerant and May Be
− Driven Up +6.0 V Regardless of VCC
− Greatly Improved Noise Margin Over MAX4053 and MAX4053A
Improved Linearity Over Standard HC4053 Devices
•
• Popular SOIC and the Space Saving TSSOP Packages
• Pb−Free Packages are Available*
A
= Assembly Location
L, WL
= Wafer Lot
Y
= Year
W, WW = Work Week
G
= Pb−Free Package
G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2005
November, 2005 − Rev. 2
1
Publication Order Number:
NLAS4053/D
NLAS4053
NOB
VCC
16
1
NOB
COMB COMC
15
14
2
3
NCB
NOA
NOC
NCC
13
12
4
5
AddC AddB
11
10
6
COMA NCA Inhibit
AddA
NCB
COMB
9
NOA
COMC
7
8
VEE
GND
COMA
NOC
NCA
NCC
Enable
C
Figure 1. Pin Connection
(Top View)
B
A
Figure 2. Logic Diagram
TRUTH TABLE
Address
Inhibit
C
B
A
ON SWITCHES*
1
X
don’t care
X
don’t care
X
don’t care
All switches open
0
0
0
0
COMA−NCA,
COMB−NCB,
COMC−NCC
0
0
0
1
COMA−NOA,
COMB−NCB,
COMC−NCC
0
0
1
0
COMA−NCA,
COMB−NOB,
COMC−NCC
0
0
1
1
COMA−NOA,
COMB−NOB,
COMC−NCC
0
1
0
0
COMA−NCA,
COMB−NCB,
COMC−NOC
0
1
0
1
COMA−NOA,
COMB−NCB,
COMC−NOC
0
1
1
0
COMA−NCA,
COMB−NOB,
COMC−NOC
0
1
1
1
COMA−NOA,
COMB−NOB,
COMC−NOC
*NO, NC, and COM pins are identical and interchangeable. Either may be
considered an input or output; signals pass equally well in either direction.
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2
NLAS4053
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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MAXIMUM RATINGS
Symbol
Value
Unit
VEE
Negative DC Supply Voltage
(Referenced to GND)
−7.0 to 0.5
V
VCC
Positive DC Supply Voltage (Note 1)
(Referenced to GND)
(Referenced to VEE)
−0.5 to 7.0
−0.5 to 7.0
V
VIS
Analog Input Voltage
VEE −0.5 to VCC 0.5
V
VIN
Digital Input Voltage
−0.5 to 7.0
V
50
mA
−65 to 150
_C
260
_C
150
_C
I
TSTG
Parameter
(Referenced to GND)
DC Current, Into or Out of Any Pin
Storage Temperature Range
TL
Lead Temperature, 1 mm from Case for 10 Seconds
TJ
Junction Temperature under Bias
JA
Thermal Resistance
SOIC
TSSOP
143
164
°C/W
PD
Power Dissipation in Still Air,
SOIC
TSSOP
500
450
mW
MSL
Moisture Sensitivity
FR
Flammability Rating
VESD
ILATCHUP
Level 1
Oxygen Index: 30% − 35%
Human Body Model (Note 2)
Machine Model (Note 3)
Charged Device Model (Note 4)
2000
200
1000
V
Above VCC and Below GND at 125°C (Note 5)
300
mA
ESD Withstand Voltage
Latchup Performance
UL 94 V−0 @ 0.125 in
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. The absolute value of VCC |VEE| ≤ 7.0.
2. Tested to EIA/JESD22−A114−A.
3. Tested to EIA/JESD22−A115−A.
4. Tested to JESD22−C101−A.
5. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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Symbol
Parameter
Min
Max
Unit
VEE
Negative DC Supply Voltage
(Referenced to GND)
−5.5
GND
V
VCC
Positive DC Supply Voltage
(Referenced to GND)
(Referenced to VEE)
2.5
2.5
5.5
6.6
V
VEE
VCC
V
0
5.5
V
−55
125
_C
0
0
100
20
ns/V
VIS
Analog Input Voltage
VIN
Digital Input Voltage
TA
Operating Temperature Range, All Package Types
tr, tf
Input Rise/Fall Time
(Channel Select or Enable Inputs)
(Note 6) (Referenced to GND)
VCC = 3.0 V 0.3 V
VCC = 5.0 V 0.5 V
6. Unused digital inputs may not be left open. All digital inputs must be tied to a high−logic voltage level or a low−logic input voltage level.
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3
NLAS4053
ORDERING INFORMATION
Package
Shipping†
NLAS4053D
SOIC−16
48 Units / Rail
NLAS4053DG
SOIC−16
(Pb−Free)
48 Units / Rail
NLAS4053DR2
SOIC−16
2500 Tape & Reel
NLAS4053DR2G
SOIC−16
(Pb−Free)
2500 Tape & Reel
NLAS4053DT
TSSOP−16*
96 Units / Rail
NLAS4053DTG
TSSOP−16*
96 Units / Rail
NLAS4053DTR2
TSSOP−16*
2500 Tape & Reel
NLAS4053DTR2G
TSSOP−16*
2500 Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
DC CHARACTERISTICS − Digital Section (Voltages Referenced to GND)
VCC
V
Guaranteed Limit
Symbol
Parameter
−55 to 25°C
v85°C
v125°C
Unit
VIH
Minimum High−Level Input
Voltage, Address and Inhibit Inputs
2.0
3.0
4.5
5.5
1.5
2.1
3.15
3.85
1.5
2.1
3.15
3.85
1.5
2.1
3.15
3.85
V
VIL
Maximum Low−Level Input
Voltage, Address and Inhibit Inputs
2.0
3.0
4.5
5.5
0.5
0.9
1.35
1.65
0.5
0.9
1.35
1.65
0.5
0.9
1.35
1.65
V
IIN
Maximum Input Leakage Current,
Address or Inhibit Inputs
VIN = 6.0 or GND
0 V to 6.0 V
0.1
1.0
1.0
A
ICC
Maximum Quiescent Supply
Current (per Package)
Channel Select, Enable and
VIS = VCC or GND
6.0
4.0
40
80
A
Condition
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ÎÎ
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ÎÎ
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ÎÎ
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DC ELECTRICAL CHARACTERISTICS − Analog Section
Symbol
RON
Parameter
Test Conditions
Guaranteed Limit
VCC
V
VEE
V
−55 to 25°C
v85_C
v125_C
Unit
3.0
4.5
3.0
0
0
−3.0
86
37
26
108
46
33
120
55
37
3.0
4.5
3.0
0
0
−3.0
15
13
10
20
18
15
20
18
15
Maximum “ON” Resistance
VIN = VIL or VIH
VIS = VEE to VCC
|IS| = 10 mA
(Figures 4 thru 9)
Maximum Difference in “ON”
Resistance Between Any Two
Channels in the Same Package
VIN = VIL or VIH,
Rflat(ON)
COM−NO
On−Resistance Flatness
Vcom 1, 2, 3.5 V
Vcom −2, 0, 2 V
|IS| = 10 mA
4.5
3.0
0
−3.0
4
2
4
2
5
3
INC(OFF)
INO(OFF)
Maximum Off−Channel Leakage
Current
Switch Off
VIN = VIL or VIH
VIO = VCC −1.0 V or VEE +1.0 V
(Figure 17)
6.0
3.0
0
−3.0
0.1
0.1
5.0
5.0
100
100
nA
ICOM(ON)
Maximum On−Channel Leakage
Current, Channel− to−Channel
Switch On
VIO = VCC −1.0 V or VEE +1.0 V
(Figure 17)
6.0
3.0
0
−3.0
0.1
0.1
5.0
5.0
100
100
nA
RON
|IS| = 10 mA,
VIS = 2.0 V
VIS = 3.5 V
VIS = 2.0 V
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NLAS4053
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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ÎÎÎÎÎÎÎÎÎ
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ÎÎÎ
ÎÎ
ÎÎ
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ÎÎÎ
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AC CHARACTERISTICS (Input tr = tf = 3 ns)
Guaranteed Limit
Symbol
tBBM
Parameter
Minimum Break−Before−Make
Time
Test Conditions
VIN = VIL or VIH
VIS = VCC
RL = 300 CL = 35 pF
(Figure 19)
−55 to 25_C
VCC
V
VEE
V
Min
Typ*
v85_C
v125_C
Unit
3.0
4.5
3.0
0.0
0.0
−3.0
1.0
1.0
1.0
6.5
5.0
3.5
−
−
−
−
−
−
ns
*Typical Characteristics are at 25_C.
AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 3 ns)
Guaranteed Limit
v85°C
−55 to 25°C
v125°C
VCC
V
VEE
V
Transition Time
(Address Selection Time)
(Figure 18)
2.5
3.0
4.5
3.0
0
0
0
−3.0
40
28
23
23
tON
Turn−on Time
(Figures 14, 15, 20, and 21)
Enable to NO or NC
2.5
3.0
4.5
3.0
0
0
0
−3.0
tOFF
Turn−off Time
(Figures 14, 15, 20, and 21)
Enable to NO or NC
2.5
3.0
4.5
3.0
0
0
0
−3.0
CIN
Maximum Input Capacitance,Select Inputs
8
CNO or
CNC
Analog I/O
10
CCOM
Common I/O
10
C(ON)
Feedthrough
1.0
Symbol
tTRANS
Parameter
Min
Typ
Max
Min
Max
Min
Max
Unit
45
30
25
25
50
35
30
28
ns
40
28
23
23
45
30
25
25
50
35
30
28
ns
40
28
23
23
45
30
25
25
50
35
30
28
ns
Typical @ 25°C, VCC = 5.0 V
pF
ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0 V)
Symbol
Parameter
Condition
Typ
VCC
V
VEE
V
25°C
Unit
BW
Maximum On−Channel
Bandwidth or Minimum
Frequency Response
VIS = ½ (VCC − VEE)
Source Amplitude = 0 dBm
(Figures 10 and 22)
3.0
4.5
6.0
3.0
0.0
0.0
0.0
−3.0
145
165
180
180
MHz
VISO
Off−Channel Feedthrough
Isolation
f = 100 kHz; VIS = ½ (VCC − VEE)
Source = 0 dBm
(Figures 12 and 22)
3.0
4.5
6.0
3.0
0.0
0.0
0.0
−3.0
−93
−93
−93
−93
dB
VONL
Maximum Feedthrough
On Loss
VIS = ½ (VCC − VEE)
Source = 0 dBm
(Figures 10 and 22)
3.0
4.5
6.0
3.0
0.0
0.0
0.0
−3.0
−2
−2
−2
−2
dB
Charge Injection
VIN = VCC to VEE, fIS = 1 kHz, tr = tf = 3 ns
RIS = 0 , CL= 1000 pF, Q = CL * VOUT
(Figures 16 and 23)
5.0
3.0
0.0
−3.0
9.0
12
pC
Total Harmonic Distortion
THD + Noise
fIS = 1 MHz, RL = 10 K, CL = 50 pF,
VIS = 5.0 VPP sine wave
VIS = 6.0 VPP sine wave
(Figure 13)
6.0
3.0
0.0
−3.0
0.10
0.05
Q
THD
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5
%
NLAS4053
100
100
10
2.0 V
80
RON ()
ICC (nA)
1
0.1
0.01
40
VCC = 3.0 V
0.001
3.0 V
3.3 V
4.5 V
5.5 V
20
0.0001
VCC = 5.0 V
0.00001
−40
−20
0
20
60
80
100
0
−4.0
120
−2.0
0
2.0
4.0
6.0
Temperature (°C)
VIS (VDC)
Figure 3. ICC versus Temp, VCC = 3 V and 5 V
Figure 4. RON versus VCC, Temp = 255C
50
100
125°C
90
125°C
85°C
40
80
25°C
70
60
RON ()
RON ()
60
50
85°C
40
25°C
30
20
−55°C
30
10
20
−55°C
10
0
0
0.5
1.0
1.5
0
2.0
1.0
1.5
2.0
2.5
VCom (V)
Figure 5. Typical On Resistance
VCC = 2.0 V, VEE = 0 V
Figure 6. Typical On Resistance
VCC = 3.0 V, VEE = 0 V
25
3.0
25
125°C
125°C
85°C
85°C
20
20
15
RON ()
RON ()
0.5
VCom (V)
10
25°C
15
25°C
10
−55°C
−55°C
5
5
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
VCom (V)
VCom (V)
Figure 7. Typical On Resistance
VCC = 4.5 V, VEE = 0 V
Figure 8. Typical On Resistance
VCC = 5.5 V, VEE = 0 V
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6
5
5.5
NLAS4053
25
125°C
85°C
RON ()
20
15
10
−55°C
25°C
5
0
−4
−2
0
VCom (V)
2
4
50
90
40
72
30
54
PHASE SHIFT (Deg)
BANDWIDTH (dB)
Figure 9. Typical On Resistance
VCC = 3.3 V, VEE = −3.3 V
20
10
0
−10
BANDWIDTH (ON−RESPONSE)
−20
36
18
0
−36
−30
−54
−40
−72
−50
PHASE SHIFT
−18
−90
0.1
1.0
10
0.1
100
1.0
10
100
FREQUENCY (mHz)
FREQUENCY (mHz)
Figure 10. Bandwidth
Figure 11. Phase Shift
0
0
−20
DISTORTION (%)
OFF ISOLATION 10 dB/DIV
−10
−30
−40
−50
−60
−70
3.0
5.5
4.5
0.1
3.3
−80
−90
0.01
−100
0.1
1.0
10
10
100
FREQUENCY (mHz)
100
1000
10000
10000
FREQUENCY (mHz)
Figure 13. Total Harmonic Distortion
Figure 12. Off Isolation
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NLAS4053
30
30
VCC = 4.5 V
25
20
20
TIME (ns)
TIME (ns)
TA = 25_C
25
15
tON (ns)
10
tOFF (ns)
5
0
2.5
3
3.5
4
4.5
15
10
tON
5
tOFF
0
−55
5
−40
25
85
125
VCC (VOLTS)
Temperature (°C)
Figure 14. tON and tOFF versus VCC
Figure 15. tON and tOFF versus Temp
3.0
100
2.5
10
VCC = 5 V
LEAKAGE (nA)
Q (pC)
2.0
1.5
1.0
0.5
1
ICOM(ON)
0.1
ICOM(OFF)
VCC = 3 V
0.01
0
VCC = 5.0 V
INO(OFF)
−0.5
0.001
0
1
2
3
4
5
−55
−20
25
70
85
125
VCOM (V)
TEMPERATURE (°C)
Figure 16. Charge Injection versus COM Voltage
Figure 17. Switch Leakage versus Temperature
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NLAS4053
VCC
0.1 F
VCC
Output
VOUT
VEE
300
50%
Input
50%
0V
35 pF
VCC
90%
Output
Address Select Pin
10%
VEE
ttrans
ttrans
Figure 18. Channel Selection Propagation Delay
VCC
DUT
VCC
Input
Output
GND
VOUT
0.1 F
300
tBMM
35 pF
90%
90% of VOH
Output
Address Select Pin
GND
Figure 19. tBBM (Time Break−Before−Make)
VCC
DUT
VCC
0.1 F
Input
50%
0V
Output
VOUT
Open
300
50%
VOH
35 pF
90%
90%
Output
Input
GND
Enable
tON
Figure 20. tON/tOFF
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tOFF
NLAS4053
VCC
VCC
Input
DUT
Output
50%
0V
300 VOUT
Open
50%
VCC
35 pF
Output
Input
10%
VOL
Enable
tOFF
10%
tON
Figure 21. tON/tOFF
50 Reference
DUT
Transmitted
Input
Output
50 Generator
50 Channel switch control/s test socket is normalized. Off isolation is measured across an off channel. On loss is
the bandwidth of an On switch. VISO, Bandwidth and VONL are independent of the input signal direction.
VVOUT
for VIN at 100 kHz
IN
VOUT
for VIN at 100 kHz to 50 MHz
VONL = On Channel Loss = 20 Log VIN
VISO = Off Channel Isolation = 20 Log
Bandwidth (BW) = the frequency 3 dB below VONL
Figure 22. Off Channel Isolation/On Channel Loss (BW)/Crosstalk
(On Channel to Off Channel)/VONL
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NLAS4053
DUT
VCC
VIN
Output
Open
GND
CL
Output
Off
Off
On
VIN
Figure 23. Charge Injection: (Q)
TYPICAL OPERATION
+5.0 V
16
VEE
GND
+3.0 V
VCC
16
VEE
7
8
GND
VCC
7
8
−3.0 V
Figure 24. 5.0 Volts Single Supply
VCC = 5.0 V, VEE = 0
Figure 25. Dual Supply
VCC = 3.0 V, VEE = −3.0 V
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VOUT
NLAS4053
PACKAGE DIMENSIONS
SOIC−16
D SUFFIX
CASE 751B−05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
−A−
16
9
−B−
1
P
8 PL
0.25 (0.010)
8
B
M
S
G
R
K
F
X 45 _
C
−T−
SEATING
PLANE
J
M
D
16 PL
0.25 (0.010)
M
T B
S
A
S
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DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.229
0.244
0.010
0.019
NLAS4053
PACKAGE DIMENSIONS
TSSOP−16
DT SUFFIX
CASE 948F−01
ISSUE A
16X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
S
S
ÇÇÇ
ÇÇÇ
ÉÉÉ
ÇÇÇ
ÉÉÉ
K
K1
2X
L/2
16
9
J1
B
−U−
L
SECTION N−N
J
PIN 1
IDENT.
8
1
N
0.15 (0.006) T U
S
0.25 (0.010)
A
−V−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
M
N
F
DETAIL E
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
H
D
DETAIL E
G
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DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
−−−
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.18
0.28
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.193 0.200
0.169 0.177
−−− 0.047
0.002 0.006
0.020 0.030
0.026 BSC
0.007
0.011
0.004 0.008
0.004 0.006
0.007 0.012
0.007 0.010
0.252 BSC
0_
8_
NLAS4053
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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NLAS4053/D