ON MC74HC132ADG Quad 2-input nand gate with schmitt-trigger input Datasheet

MC74HC132A
Quad 2-Input NAND Gate
with Schmitt-Trigger Inputs
High−Performance Silicon−Gate CMOS
The MC74HC132A is identical in pinout to the LS132. The device
inputs are compatible with standard CMOS outputs; with pull−up
resistors, they are compatible with LSTTL outputs.
The HC132A can be used to enhance noise immunity or to square up
slowly changing waveforms.
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MARKING
DIAGRAMS
14
Features
•
•
•
•
•
•
•
•
•
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements as Defined by JEDEC
Standard No. 7A
Chip Complexity: 72 FETs or 18 Equivalent Gates
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
A1
1
14
VCC
B1
2
13
B4
Y1
3
12
A4
A2
4
11
Y4
B2
5
10
B3
Y2
6
9
A3
GND
7
8
Y3
PDIP−14
N SUFFIX
CASE 646
14
1
MC74HC132AN
AWLYYWWG
1
14
SOIC−14
D SUFFIX
CASE 751A
14
1
HC132AG
AWLYWW
1
14
HC
132A
ALYWG
G
TSSOP−14
DT SUFFIX
CASE 948G
14
1
1
A
L, WL
Y, YY
W, WW
G or G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
FUNCTION TABLE
Inputs
Figure 1. Pin Assignment
Output
A
B
Y
L
L
H
H
L
H
L
H
H
H
H
L
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2013
May, 2013 − Rev. 15
1
Publication Order Number:
MC74HC132A/D
MC74HC132A
A1
1
3
B1
A2
2
4
6
B2
A3
Y2
5
Y = AB
9
8
B3
Y1
Y3
10
A4 12
11
B4
Y4
13
PIN 14 = VCC
PIN 7 = GND
Figure 2. Logic Diagram
ORDERING INFORMATION
Package
Shipping†
MC74HC132ANG
PDIP−14
(Pb−Free)
25 / Tape & Ammo Box
MC74HC132ADG
SOIC−14
(Pb−Free)
55 Units / Rail
MC74HC132ADR2G
SOIC−14
(Pb−Free)
2500 / Tape & Reel
MC74HC132ADTG
TSSOP−14
(Pb−Free)
96 Units / Rail
MC74HC132ADTR2G
TSSOP−14
(Pb−Free)
2500 / Tape & Reel
NLV74HC132ADG*
SOIC−14
(Pb−Free)
55 Units / Rail
NLV74HC132ADR2G*
SOIC−14
(Pb−Free)
2500 / Tape & Reel
NLV74HC132ADTG*
TSSOP−14
(Pb−Free)
96 Units / Rail
NLV74HC132ADTR2G*
TSSOP−14
(Pb−Free)
2500 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable
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2
MC74HC132A
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
VCC
Positive DC Supply Voltage
0.5 to 7.0
V
VIN
Digital Input Voltage
0.5 to 7.0
V
VOUT
DC Output Voltage
0.5 to 7.0
0.5 to VCC 0.5
V
IIK
Input Diode Current
20
mA
IOK
Output Diode Current
20
mA
IOUT
DC Output Current, per Pin
25
mA
ICC
DC Supply Current, VCC and GND Pins
75
mA
IGND
DC Ground Current per Ground Pin
75
mA
TSTG
Storage Temperature Range
65 to 150
_C
260
_C
150
_C
14−PDIP
14−SOIC
14−TSSOP
78
125
170
_C/W
PDIP
SOIC
TSSOP
750
500
450
mW
Output in 3−State
High or Low State
TL
Lead Temperature, 1 mm from Case for 10 Seconds
TJ
Junction Temperature Under Bias
qJA
Thermal Resistance
PD
Power Dissipation in Still Air at 85_C
MSL
Moisture Sensitivity
FR
Flammability Rating
Level 1
Oxygen Index: 30% − 35%
UL 94 V0 @ 0.125 in
VESD
ESD Withstand Voltage
Human Body Model (Note 1)
Machine Model (Note 2)
Charged Device Model (Note 3)
2000
100
500
V
ILatch−Up
Latch−Up Performance
Above VCC and Below GND at 85_C (Note 4)
300
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Tested to EIA/JESD22−A114−A.
2. Tested to EIA/JESD22−A115−A.
3. Tested to JESD22−C101−A.
4. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol
VCC
VIN, VOUT
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time (Figure 3)
Min
Max
Unit
2.0
6.0
V
0
VCC
V
55
125
_C
−
No Limit
(Note 5)
ns
5. When VIN 0.5 VCC, ICC >> quiescent current.
6. Unused inputs may not be left open. All inputs must be tied to a high−logic voltage level or a low−logic input voltage level.
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3
MC74HC132A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
VCC
Guaranteed Limit
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol
Parameter
VT+max
Maximum Positive−Going
Input Threshold Voltage
(Figure 5)
VT+min
V
*55_C to 25_C
85_C
125_C
Unit
VOUT = 0.1 V
|IOUT| 20 mA
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
Minimum Positive−Going
Input Threshold Voltage
(Figure 5)
VOUT = 0.1 V
|IOUT| 20 mA
2.0
4.5
6.0
1.0
2.3
3.0
0.95
2.25
2.95
0.95
2.25
2.95
V
VT–max
Maximum Negative−Going
Input Threshold Voltage
(Figure 5)
VOUT = VCC – 0.1 V
|IOUT| 20 mA
2.0
4.5
6.0
0.9
2.0
2.6
0.95
2.05
2.65
0.95
2.05
2.65
V
VT–min
Minimum Negative−Going
Input Threshold Voltage
(Figure 5)
VOUT = VCC – 0.1 V
|IOUT| 20 mA
2.0
4.5
6.0
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
VHmax
(Note 7)
Maximum Hysteresis
Voltage
(Figure 5)
VOUT = 0.1 V or VCC – 0.1 V
|IOUT| 20 mA
2.0
4.5
6.0
1.2
2.25
3.0
1.2
2.25
3.0
1.2
2.25
3.0
V
VHmin
(Note 7)
Minimum Hysteresis
Voltage
(Figure 5)
VOUT = 0.1 V or VCC – 0.1 V
|IOUT| 20 mA
2.0
4.5
6.0
0.2
0.4
0.5
0.2
0.4
0.5
0.2
0.4
0.5
V
VOH
Minimum High−Level
Output Voltage
VIN VT−min or VT+max
|IOUT| 20 mA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
VIN −VT−min or VT+max
|IOUT| 4.0 mA
|IOUT| 5.2 mA
4.5
6.0
3.98
5.48
3.84
5.34
3.7
5.2
VIN ≥ VT+max
|IOUT| 20 mA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
4.5
6.0
0.26
0.26
0.33
0.33
0.4
0.4
VOL
Maximum Low−Level
Output Voltage
Test Conditions
VIN ≥ VT+max
|IOUT| 4.0 mA
|IOUT| 5.2 mA
V
IIN
Maximum Input Leakage
Current
VIN = VCC or GND
6.0
0.1
1.0
1.0
mA
ICC
Maximum Quiescent
Supply Current
(per Package)
VIN = VCC or GND
IOUT = 0 mA
6.0
1.0
10
40
mA
7. VHmin (VT+min) (VT−max); VHmax = (VT+max) (VT−min).
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4
MC74HC132A
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)
VCC
Guaranteed Limit
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ÎÎ
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol
Parameter
V
*55_C to 25_C
85_C
125_C
Unit
tPLH,
tPHL
Maximum Propagation Delay, Input A or B to Output Y
(Figures 3 and 4)
2.0
4.5
6.0
125
25
21
155
31
26
190
38
32
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 3 and 4)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
Maximum Input Capacitance
—
10
10
10
pF
Cin
Typical @ 25°C, VCC = 5.0 V
CPD
Power Dissipation Capacitance (per Gate) (Note 8)
24
pF
8. Used to determine the no−load dynamic power consumption: P D = CPD VCC 2 f + ICC VCC .
tr
TEST POINT
tf
VCC
90%
50%
10%
INPUT
A OR B
tPHL
tPLH
OUTPUT
DEVICE
UNDER
TEST
GND
90%
50%
10%
Y
tTHL
tTLH
CL *
*Includes all probe and jig capacitance
Figure 3. Switching Waveforms
Figure 4. Test Circuit
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5
VT, TYPICAL INPUT THRESHOLD VOLTAGE
(VOLTS)
MC74HC132A
4
3
VHtyp
2
1
2
3
4
5
VCC, POWER SUPPLY VOLTAGE (VOLTS)
VHtyp = (VT+ typ) - (VT- typ)
6
Figure 5. Typical Input Threshold, VT+, VT− Versus Power Supply Voltage
VCC
VCC
VH
VH
VIN
VT+
VT-
VIN
VT+
VTGND
GND
VOH
VOH
VOUT
VOUT
VOL
VOL
VCC
VOUT
VIN
(a)A SCHMITT TRIGGER SQUARES UP INPUTS
(a)WITH SLOW RISE AND FALL TIMES
(b)A SCHMITT TRIGGER OFFERS MAXIMUM
NOISE IMMUNITY
Figure 6. Typical Schmitt−Trigger Applications
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6
MC74HC132A
PACKAGE DIMENSIONS
SOIC−14 NB
CASE 751A−03
ISSUE K
D
A
B
14
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
A3
E
H
L
1
0.25
M
DETAIL A
7
B
13X
M
b
0.25
M
C A
S
B
S
DETAIL A
h
A
X 45 _
M
A1
e
DIM
A
A1
A3
b
D
E
e
H
h
L
M
C
SEATING
PLANE
SOLDERING FOOTPRINT*
6.50
14X
1.18
1
1.27
PITCH
14X
0.58
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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7
MILLIMETERS
MIN
MAX
1.35
1.75
0.10
0.25
0.19
0.25
0.35
0.49
8.55
8.75
3.80
4.00
1.27 BSC
5.80
6.20
0.25
0.50
0.40
1.25
0_
7_
INCHES
MIN
MAX
0.054 0.068
0.004 0.010
0.008 0.010
0.014 0.019
0.337 0.344
0.150 0.157
0.050 BSC
0.228 0.244
0.010 0.019
0.016 0.049
0_
7_
MC74HC132A
PACKAGE DIMENSIONS
TSSOP−14
DT SUFFIX
CASE 948G−01
ISSUE B
14X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
S
N
2X
14
L/2
0.25 (0.010)
8
M
B
−U−
L
PIN 1
IDENT.
N
F
7
1
0.15 (0.006) T U
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
S
DETAIL E
K
A
−V−
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
K1
J J1
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
SECTION N−N
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
D
H
G
DETAIL E
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
−−−
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.50
0.60
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
14X
0.36
14X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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8
INCHES
MIN MAX
0.193 0.200
0.169 0.177
−−− 0.047
0.002 0.006
0.020 0.030
0.026 BSC
0.020 0.024
0.004 0.008
0.004 0.006
0.007 0.012
0.007 0.010
0.252 BSC
0_
8_
MC74HC132A
PACKAGE DIMENSIONS
PDIP−14
N SUFFIX
CASE 646−06
ISSUE P
14
8
1
7
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
B
A
F
L
N
C
−T−
SEATING
PLANE
H
G
D 14 PL
J
K
0.13 (0.005)
M
DIM
A
B
C
D
F
G
H
J
K
L
M
N
INCHES
MIN
MAX
0.715
0.770
0.240
0.260
0.145
0.185
0.015
0.021
0.040
0.070
0.100 BSC
0.052
0.095
0.008
0.015
0.115
0.135
0.290
0.310
−−−
10 _
0.015
0.039
MILLIMETERS
MIN
MAX
18.16
19.56
6.10
6.60
3.69
4.69
0.38
0.53
1.02
1.78
2.54 BSC
1.32
2.41
0.20
0.38
2.92
3.43
7.37
7.87
−−−
10 _
0.38
1.01
M
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MC74HC132A/D
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