AD HMC7044 Jesd204b clock generation Datasheet

High Performance, 3.2 GHz, 14-Output
Jitter Attenuator with JESD204B
HMC7044
Data Sheet
FEATURES
APPLICATIONS
Ultralow rms jitter: 44 fs typical (12 kHz to 20 MHz) at
2457.6 MHz
Noise floor: −156 dBc/Hz at 2457.6 MHz
Low phase noise: −141.7 dBc/Hz at 800 kHz, 983.04 MHz output
Up to 14 LVDS, LVPECL, or CML type device clocks (DCLKs)
from PLL2
Maximum CLKOUTx/CLKOUTx and SCLKOUTx/SCLKOUTx
frequency up to 3200 MHz
JESD204B-compatible system reference (SYSREF) pulses
25 ps analog, and ½ VCO cycle digital delay independently
programmable on each of 14 clock output channels
SPI-programmable phase noise vs. power consumption
SYSREF valid interrupt to simplify JESD204B synchronization
Narrow-band, dual core VCOs
Up to 2 buffered voltage controlled oscillator (VCXO) outputs
Up to 4 input clocks in LVDS, LVPECL, CMOS, and CML modes
Frequency holdover mode to maintain output frequency
Loss of signal (LOS) detection and hitless reference switching
4× GPIOs alarms/status indicators to determine the health of
the system
External VCO input to support up to 6000 MHz
On-board regulators for excellent PSRR
68-lead, 10 mm × 10 mm LFCSP package
JESD204B clock generation
Cellular infrastructure (multicarrier GSM, LTE, W-CDMA)
Data converter clocking
Microwave baseband cards
Phase array reference distribution
GENERAL DESCRIPTION
The HMC7044 is a high performance, dual-loop, integer-N
jitter attenuator capable of performing reference selection and
generation of ultralow phase noise frequencies for high speed data
converters with either parallel or serial (JESD204B type) interfaces.
The HMC7044 features two integer mode PLLs and overlapping
on-chip VCOs that are SPI-selectable with wide tuning ranges
around 2.5 GHz and 3 GHz, respectively. The device is designed
to meet the requirements of GSM and LTE base station designs,
and offers a wide range of clock management and distribution
features to simplify baseband and radio card clock tree designs.
The HMC7044 provides 14 low noise and configurable outputs
to offer flexibility in interfacing with many different components including data converters, field-programmable gate arrays
(FPGAs), and mixer local oscillators (LOs).
The DCLK and SYSREF clock outputs of the HMC7044 can be
configured to support signaling standards, such as CML, LVDS,
LVPECL, and LVCMOS, and different bias settings to offset
varying board insertion losses.
FUNCTIONAL BLOCK DIAGRAM
OSCIN
OSCIN
CPOUT1
PLL1
÷
CLKOUT12
CLKOUT12
SCLKOUT13
SCLKOUT13
PLL2
SYSREF
CONTROL
SYNC
SDATA
÷
CLKOUT0
CLKOUT0
SCLKOUT1
SCLKOUT1
CLKOUT2
CLKOUT2
SCLKOUT3
SCLKOUT3
14-CLOCK
DISTRIBUTION
SPI
CONTROL
INTERFACE
SLEN
13033-001
CLKIN0/RFSYNCIN
CLKIN0/RFSYNCIN
CLKIN1/FIN
CLKIN1/FIN
CLKIN2/OSCOUT0
CLKIN2/OSCOUT0
CLKIN3
CLKIN3
CPOUT2 OSCOUT1 OSCOUT1
SCLK
Figure 1.
Rev. B
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HMC7044
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Theory of Operation ...................................................................... 23
Applications ....................................................................................... 1
Detailed Block Diagram ............................................................ 24
General Description ......................................................................... 1
Dual PLL Overview.................................................................... 25
Functional Block Diagram .............................................................. 1
Component Blocks—Input PLL (PLL1).................................. 25
Table of Contents .............................................................................. 2
Component Blocks—Output PLL (PLL2) .............................. 30
Revision History ............................................................................... 2
Clock Output Network .............................................................. 31
Specifications..................................................................................... 3
Reference Buffer Details ............................................................ 38
Conditions ..................................................................................... 3
Typical Programming Sequence............................................... 38
Supply Current .............................................................................. 3
Power Supply Considerations ................................................... 39
Digital Input/Output (I/O) Electrical Specifications ............... 4
SeriaL Control Port ........................................................................ 42
PLL1 Characteristics .................................................................... 5
Serial Port Interface (SPI) Control ........................................... 42
PLL2 Characteristics .................................................................... 7
Applications Information .............................................................. 43
VCO Characteristics .................................................................... 8
PLL1 Noise Calculations ........................................................... 43
Clock Output Distribution Characteristics............................... 9
PLL2 Noise Calculations ........................................................... 43
Spur Characteristics ................................................................... 10
Phase Noise Floor and Jitter...................................................... 43
Noise and Jitter Characteristics ................................................ 10
Control Registers ............................................................................ 44
Clock Output Driver Characteristics ....................................... 11
Control Register Map ................................................................ 44
Absolute Maximum Ratings .......................................................... 13
Control Register Map Bit Descriptions ................................... 52
ESD Caution ................................................................................ 13
Evaluation PCB Schematic ............................................................ 69
Pin Configuration and Function Descriptions ........................... 14
Evaluation PCB ........................................................................... 69
Typical Performance Characteristics ........................................... 17
Outline Dimensions ....................................................................... 71
Typical Application Circuits.......................................................... 21
Ordering Guide .......................................................................... 71
Terminology .................................................................................... 22
REVISION HISTORY
11/2016—Rev. A to Rev. B
Changes to Table 1 and Endnote 4, Table 2................................... 3
Changes to Reliable Signal Swing Parameter, Table 4.................. 5
Change to PLL2 VCXO Input Parameter, Table 5 ........................ 7
Changes to Table 7 ............................................................................ 9
Added Figure 13; Renumbered Sequentially .............................. 18
Added Figure 20.............................................................................. 19
Added Figure 21, Figure 22, and Figure 23 ................................. 20
Changes to Figure 34 ...................................................................... 21
Changes to Table 15 and Table 17 ................................................ 34
Changes to Figure 47 ...................................................................... 37
Changes to Table 23 ........................................................................ 41
Changes to Table 25 ........................................................................ 46
Changes to Table 49 ........................................................................ 57
Change to Table 75 ......................................................................... 68
5/2016—Rev. 0 to Rev. A
Changes to Table 3.............................................................................4
Changes to Current Range (ICP2) Parameter, Table 5 ....................8
Changes to Table 9.......................................................................... 11
Changes to Table 10 ....................................................................... 13
Changes to LDOBYP5 Pin Description ...................................... 15
Changes to Figure 13...................................................................... 19
Changes to Figure 30...................................................................... 25
Changes to Evaluation PCB Section ............................................ 69
Added Figure 46; Renumbered Sequentially .............................. 69
Added Figure 50 ............................................................................. 71
Updated Outline Dimensions ....................................................... 71
9/2015—Revision 0: Initial Version
Rev. B | Page 2 of 72
Data Sheet
HMC7044
SPECIFICATIONS
Unless otherwise noted, fVCXO = 122.88 MHz single-ended; CLKIN0/CLKIN0, CLKIN1/CLKIN1, CLKIN2/CLKIN2, and CLKIN3/CLKIN3
differential at 122.88 MHz; fVCO = 2949.12 MHz; doubler is on; typical value is given for VCC = 3.3 V; and TA = 25°C. Minimum and maximum
values are given over the full VCC and TA (−40°C to +85°C) variation, as listed in Table 1. Note that multifunction pins, such as
CLKIN0/RFSYNCIN, are referred to either by the entire pin name or by a single function of the pin, for example, CLKIN0, when only
that function is relevant.
CONDITIONS
Table 1.
Parameter
SUPPLY VOLTAGE, VCC
VCC1_VCO
VCC2_OUT
Min
Typ
Max
Unit
Test Conditions/Comments
3.135
3.135
3.3
3.3
3.465
3.465
V
V
VCC3_SYSREF
VCC4_OUT
3.135
3.135
3.3
3.3
3.465
3.465
V
V
VCC5_PLL1
VCC6_OSCOUT
VCC7_PLL2
VCC8_OUT
3.135
3.135
3.135
3.135
3.3
3.3
3.3
3.3
3.465
3.465
3.465
3.465
V
V
V
V
VCC9_OUT
3.135
3.3
3.465
V
3.3 V ± 5%, supply voltage for VCO and VCO distribution
3.3 V ± 5%, supply voltage for Output Channel 2 and Output
Channel 3
3.3 V ± 5%, supply voltage for common SYSREF divider
3.3 V ± 5%, supply voltage for Output Channel 4, Output
Channel 5, Output Channel 6, Output Channel 7
3.3 V ± 5%, supply voltage for the LDO used in PLL1
3.3 V ± 5%, supply voltage for oscillator output path
3.3 V ± 5%, supply voltage for the LDO used in PLL2
3.3 V ± 5%, supply voltage for Output Channel 8, Output
Channel 9, Output Channel 10, and Output Channel 11
3.3 V ± 5%, supply voltage for Output Channel 0, Output
Channel 1, Output Channel 12, and Output Channel 13
−40
+25
+85
°C
TEMPERATURE
Ambient Temperature Range, TA
SUPPLY CURRENT
For detailed test conditions, see Table 22 and Table 23.
Table 2.
Parameter 1, 2
CURRENT CONSUMPTION 3
VCC1_VCO
VCC2_OUT 4
VCC3_SYSREF
VCC4_OUT4
Min
Typ
Max
Unit
157
65
12
78
225
250
37
500
mA
mA
mA
mA
VCC5_PLL1
VCC6_OSCOUT
VCC7_PLL2
VCC8_OUT4
39
0
46
124
125
80
80
500
mA
mA
mA
mA
VCC9_OUT4
65
500
mA
Total Current
586
Test Conditions/Comments
Typical value is given at TA = 25°C with two LVDS clocks at divide by 8
Typical value is given at 25°C with two LVPECL high performance clocks,
fundamental frequency of internal VCO (fO), 2 SYSREF clocks (off )
Typical value is given at 25°C with two LVPECL high performance clocks at
divide by 2, 2 SYSREF clocks (off )
Typical value is given at 25°C with two LVDS clocks at divide by 8, 2 SYSREF
clocks (off )
mA
Maximum values are guaranteed by design and characterization.
Currents include LVPECL termination currents.
Maximum values are for all circuits enabled in their worst case power consumption mode, PVT variations, and accounting for peak current draw during temporary
synchronization events.
4
Typical specification applies to a normal usage profile (Profile 1 in Table 23), where PLL1 and PLL2 are locked, but very low duty cycle currents (sync events) and some
optional features are disabled. This specification assumes output configurations as described in the test conditions/comments column.
1
2
3
Rev. B | Page 3 of 72
HMC7044
Data Sheet
DIGITAL INPUT/OUTPUT (I/O) ELECTRICAL SPECIFICATIONS
Table 3.
Parameter
DIGITAL INPUT SIGNALS (RESET, SYNC, SLEN, SCLK)
Safe Input Voltage Range 1
Input Load
Input Voltage
Input Logic High (VIH)
Input Logic Low (VIL)
SPI Bus Frequency
DIGITAL BIDIRECTIONAL SIGNALS CONFIGURED AS
INPUTS (SDATA, GPIO4, GPIO3, GPIO2, GPIO1)
Safe Input Voltage Range1
Input Capacitance
Input Resistance
Input Voltage
Input Logic High (VIH)
Input Logic Low (VIL)
Input Hysteresis
GPIO1 TO GPIO4 ALARM MUXING/DELAY
Delay from Internal Alarm/Signal to General-Purpose
Output (GPO) Driver
DIGITAL BIDIRECTIONAL SIGNALS CONFIGURED AS
OUTPUTS (SDATA, GPIO4, GPIO3, GPIO2, GPIO1)
CMOS MODE
Logic 1 Level
Logic 0 Level
Output Drive Resistance (RDRIVE)
Output Driver Delay (tDGPO)
Min
Typ
Max
Unit
+3.6
V
pF
VCC
0.5
10
V
V
MHz
+3.6
V
pF
Ω
VCC
0.24
0.2
V
V
V
Occurs around 0.85 V
2
ns
Does not include tDGPO
−0.1
0.3
1.2
0
−0.1
0.4
50G
1.22
0
1.6
1.9
0
50
1.5 + 42 ×
CLOAD
Maximum Supported DC Current1
OPEN-DRAIN MODE1
Logic 1 Level
1
Logic 0 Level
0.13
Pull-Down Impedance
Maximum Supported Sink Current
60
Guaranteed by design and characterization.
Rev. B | Page 4 of 72
2.2
0.1
V
V
Ω
ns
0.6
mA
3.6
V
0.28
V
5
Ω
mA
Test Conditions/Comments
Approximately 1.5 ns + 0.69 × RDRIVE × CLOAD
(CLOAD in nF)
External 1 kΩ pull-up resistor
3.6 V maximum permitted; specifications
set by external supply
Against a 1 kΩ external pull-up resistor to
3.3 V
Data Sheet
HMC7044
PLL1 CHARACTERISTICS
Table 4.
Parameter
PLL1 REFERENCE INPUTS
(CLKIN0/CLKIN0, CLKIN1/CLKIN1,
CLKIN2/CLKIN2, CLKIN3/CLKIN3)
Reliable Signal Swing
Differential
Single-Ended 1
Common-Mode Range
Input Impedance
Return Loss
PLL1 REFERENCE DIVIDER
8-Bit Lowest Common Multiple
(LCM) Dividers
16-Bit R Divider (R1)
PLL1 FEEDBACK DIVIDER
16-Bit N Divider (N1)
PLL1 FREQUENCY LIMITATIONS
PLL1 REF Input Frequency (fREF)
Digital LOS/LCM Frequency (fLCM)
PD1 Frequency (fPD1)
Min
Typ
Max
Unit
Test Conditions/Comments
0.375
1.4
V p-p
0.375
1.4
V p-p
0.4
2.4
V
Differential, keep signal at reference input pin
<2.8 V, measured at 800 MHz
<250 MHz; keep signal at reference input pin
<2.8 V
If user supplied, on-chip VCM is approximately
2.1 V
User selectable; differential
When terminated with 100 Ω differentially
100 to 2000
−12
1
255
1
65,535
1
65,535
0.00015
800
MHz
0.00015
0.00015
123
50
MHz
MHz
PLL1 CHARGE PUMP
Charge Pump Current Range (ICP1)
ICP1 Variation over Process Voltage
Temperature (PVT)
Source/Sink Current Mismatch
Charge Pump Current Step Size
Charge Pump Compliance Range1
PLL1 NOISE PROFILE1
Floor Figure of Merit (FOM)
Flicker FOM
Flicker Noise
Noise Floor
Total Phase Noise (Unfiltered)
PLL1 BANDWIDTH AND
ACQUISITION TIMES1
Supported Loop Bandwidths
(PLL1_BW) 5
PLL1 Slew Time 6
Ω
dB
120 to 1920
μA
±15
%
2
120
0.4 to 2.5
0.1 to 2.7
%
μA
V
V
−222
−252
Determined by formula 2
Determined by formula 3
Determined by formula 4
fLCM/225
Minimum specification set by Phase Detector 1
(PD1) low limit
Typically run at about 38.4 MHz
Minimum specification = VCXO minimum
frequency ÷ 65,535; 9.76 MHz typical
ICP1 from 0 to 15, VCXO control voltage (VTUNE) =
1.4 V
VTUNE = 1.4 V
Source/sink mismatch at 1.4 V
ICP variation less than 10%
Maintain lock in test environment
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Normalized to 1 Hz
Normalized to 1 Hz
At fOUT, fOFFSET
At fOUT, fPD1
fPD1/10
Hz
N1/
fDELTA_VCXO
sec
Typically PLL1 low BW is set by the application
and ranges between 5 Hz and 2 kHz
N1 = 10 (typical) and fDELTA_VCXO = 10 kHz (typical)
results in 1 ms of slew time
When VCXO has stopped slewing to steady
state (within 5°)
PLL1 Linear Acquisition Time
5/PLL1_BW
sec
PLL1 Phase Error at PD1
Invalidates Lock
PLL1 Lock Detect Timer Period
(tLKD) 7
±2.9
ns
4 to 226
tLCM
Rev. B | Page 5 of 72
User-selectable low phase error counts to
declare lock
HMC7044
Parameter
PLL1 BEHAVIOR ON REFERENCE
FAILURE1
LOS Assertion Delay7
Erroneously Active ICP1 Time on
Reference Failure 8
Temporary Frequency Glitch Due
to Reference Failure
Integrated Frequency Error Due to
Reference Failure
Signal Valid Time to Clear LOS 9
PLL1 VTUNE LEAKAGE SOURCES
Charge Pump Tristate Leakage
Current
Board Level XTAL Tune Input Port
Board Level Loop Filter
Components
HOLDOVER CHARACTERISTICS
VTUNE Drift Over 1 sec in Tristate
Mode
Holdover
Analog-to-Digital Converter
(ADC)/Digital-to-Analog
Converter (DAC) Resolution
ADC/DAC Code 0 Voltage
ADC/DAC Code 127 Voltage
DAC Temperature Stability
ADC/DAC Integral Nonlinearity
(INL)
Holdoff Timer Period1, 10
HOLDOVER EXIT—INITIAL PHASE
OFFSETS1
Exit Criteria = Wait for Low Phase
Error
Exit Action = None
Exit Criteria = Any 11
Exit Action = Reset Dividers
Exit Action = None
HOLDOVER EXIT CHARACTERISTICS1, 12
DAC Assisted Release Period per
Step (tDACASSIST)
DAC Assisted Release Time
Delay of Exit Criteria 13 = Wait for
Low Phase Error 14
Data Sheet
Min
Typ
Max
Unit
Test Conditions/Comments
3 + tDGPO
8
tLCM
ns
From missing signal edge to alarm on GPO
0.03
ppm
0.016
ppm
ICP1 = 1 mA, C12 = 4.6 nF, Crystek CVPD-952
VCXO
ICP1 = 1 mA, C13 = 1 μF, Crystek CVPD-952 VCXO
2 + tDGPO
0
2
3
tLOSVAL
0.2
nA
0.5
2
nA
nA
Crystek CVPD-952 VCXO
C12 = 4.6 nF, C13 = 1 μF, R9 = 11 kΩ, C15 =
unpopulated
2
mV
C12 = 4.6 nF, C13 = 1 μF, R9 = 11 kΩ,
CVPD-950 VCXO
19
mV
7-bit, monotonic, no missing code
0.28
2.71
0.07
−0.11
V
V
mV/°C
LSBs
At maximum code
Worst case across codes
1
226
tLCM
The phase offset to make up after a transition
from holdover to acquisition when using this
feature
±4
1
1/2
ns
2
tVCXO
±N1
tVCXO
Assumes N2 > 3 and dividers are reset upon
exit; note that VCXO lags at start; value applies
as the starting phase error if DAC assisted
release is used
Dividers are not reset upon exit
1/16
tLKD
Based on lock detect timer setpoint
9
tDACASSIST
Time from decision to leave holdover until in
fully natural acquisition; assumes no
interruption by LOS or user
N1/fERR_VCXO
sec
Rev. B | Page 6 of 72
Data Sheet
HMC7044
Parameter
HOLDOVER EXIT—FREQUENCY
TRANSIENTS vs. MODE
Peak Frequency Transient
DAC Assisted Release
Min
Typ
Max
2
Unit
Test Conditions/Comments
ppm
Only available if using DAC-based holdover
Guaranteed by design and characterization.
See the PLL1 Noise Calculations section for more information on how to calculate the flicker noise for PLL1.
3
See the PLL1 Noise Calculations section for more information on how to calculate the noise floor for PLL1.
4
See the PLL1 Noise Calculations section for more information on how to calculate the total phase noise (unfiltered) for PLL1.
5
Set by external components. Set the lock detect thresholds (PLL1 Lock Detect Timer[4:0] in Register 0x0028) appropriately in the SPI.
6
Depends on initial phase offset (worst case is proportional to N1) and VCXO excess tuning range available over the target (fDELTA_VCXO). For PFD rates typical of PLL1,
cycle slipping is normally insignificant.
7
tLCM is the least common multiple (LCM) of PLL1 clock input frequencies. The specification is given in multiples of tLCM.
8
If LOS triggers before the PFD edge is normally detected (more likely with high R1 values), the charge pump is more likely to disable before the next invalid
comparison occurs. Otherwise, the fast tristate circuit disables the charge pump after about 4 ns (8 ns worst case) of phase error.
9
tLOSVAL is a register value that is programmable from 1, 2, 4, …, 64 tLCM.
10
If the holdoff timer is used, the finite state machine (FSM) stays in holdover after LOS of the active reference before switching clocks, giving the original clock a chance
to return.
11
tVCXO is the VCXO clock period.
12
See the PLL1 Holdover Exit section.
13
The time required for the phases to intersect is inversely proportional to the holdover frequency error. Note that the frequency error during holdover is expected to
be much smaller than is available from the tuning range of the VCXO.
14
fERR_VCXO is the error frequency of the VCXO.
1
2
PLL2 CHARACTERISTICS
Table 5.
Parameter
PLL2 VCXO INPUT
Recommended Swing
Differential
Single-Ended (<250 MHz) 1
Common-Mode Range
VCXO Input Slew Rate
Input Capacitance
Differential Input Resistance
Return Loss
PLL2 EXTERNAL VCO INPUT
Recommended Input
Power, AC-Coupled
Differential
Single-Ended1
Return Loss
External VCO Frequency1
Common-Mode Range1
PLL2 DIVIDERS
12-Bit Reference Divider
Range (R2)
16-Bit Feedback Divider
Range (N2)
PLL2 FREQUENCY LIMITATIONS
VCXO Frequency (fVCXO)
VCXO Duty Cycle
Using Doubler1
Min
0.2
0.2
1.6
300
Typ
Max
Unit
Test Conditions/Comments
2.1
1.4
1.4
2.4
V p-p
V p-p
V
mV/ns
Differential, keep signal at OSCIN and OSCIN pins < 2.8 V
Keep signal at OSCIN and OSCIN pins < 2.8 V
If user supplied, on-chip VCM is approximately 2.1 V
Slew rates as low as 100 mV/ns are functional, but can
degrade the phase noise plateau by about 3 dB
Per side; 3 pF differential
User selectable
When terminated with 100 Ω differential
1.5
100 to 1000
−12
−6
−6
pF
Ω
dB
6
6
3200
dBm
dBm
dB
MHz
6000
2.2
MHz
V
−12
400
400
1.6
2.1
When terminated with 100 Ω differential
Fundamental mode; if < 1 GHz, set the low frequency
external VCO path bit (Register 0x0064, Bit 0)
Using external VCO ÷ 2
1
4095
8
65,535
10
500
MHz
122.88 MHz or 155 MHz are typical
40
60
%
Distortion can lead to a spur at fPD/2 offset, note that
minimum pulse width > 3 ns
Rev. B | Page 7 of 72
HMC7044
Parameter
Reference Doubler Input
Frequency
R2 Input Frequency
PD2 Frequency (fPD2)
Data Sheet
Min
10
10
0.00015
PLL2 CHARGE PUMP
Current Range (ICP2)
ICP2 Variation over PVT
Source/Sink Current
Mismatch
Current Step Size
Compliance Range
PLL2 NOISE PROFILE
Floor FOM
Flicker FOM
FOM Variation vs. PVT
FOM Degradation
PLL2 Flicker Noise
PLL2 Noise Floor
PLL2 Total Phase Noise
(Unfiltered)
PLL2 BANDWIDTH AND
ACQUISITION TIMES
Supported Loop
Bandwidths (PLL2_BW)
VCO Automatic Gain
Control (AGC) Settling
Time1
VCO Calibration Time 5
Temperature Range
Postcalibration1
PLL2 Linear Acquisition
Time
PLL2 Lock Detect Timer
Period5
Typ
Max
175
Unit
MHz
500
250
MHz
MHz
Test Conditions/Comments
Recommended at high end of the range for best phase
noise; typically 122.88 MHz × 2
160 to 2560
±25
2
μA
%
%
ICP2 setting from 0 to 15 with 160 μA step size, VTUNE = 1.4 V
VTUNE = 1.4 V
Source/sink mismatch at 1.4 V
160
0.3 to 2.45
μA
V
ICP variation less than 10%
−232
−266
±3
3
Determined by formula 2
Determined by formula 3
Determined by formula 4
dBc/Hz
dBc/Hz
dB
dB
dBc/Hz
dBc/Hz
dBc/Hz
Normalized to 1 Hz
Normalized to 1 Hz
kHz
Set by external components
20
ms
+85
tPD2
tPD2
tPD2
tPD2
°C
Time from power-up of VCO before initiating calibration;
this applies to the 100 nF/1 μF configuration of external
decoupling capacitors on the VCO supply network
N2 from 8 to 31
N2 from 32 to 256
N2 from 256 to 4095
N2 > 4095
Maintains lock from any temperature to any temperature
5/PLL2_BW
sec
After VCXO has stopped slewing to steady state
512
tPD2
Low phase error counts to declare lock
10 to 700
10
2694
779
214
139
−40
At minimum VCXO slew rate
At fOUT, fOFFSET
At fOUT, fPD2
Guaranteed by design and characterization.
See the PLL2 Noise Calculations section for more information on how to calculate the flicker noise for PLL2.
3
See the PLL2 Noise Calculations section for more information on how to calculate the noise floor for PLL2.
4
See the PLL2 Noise Calculations section for more information on how to calculate the total phase noise (unfiltered) for PLL2.
5
tPD2 is the period of Phase Detector 2.
1
2
VCO CHARACTERISTICS
Table 6.
Parameter
VOLTAGE CONTROLLED OSCILLATOR (VCO)
Frequency Tuning Range, On-Board VCOs 1
Tuning Sensitivity
Min
Typ
2150
2650
2400
Max
Unit
Test Conditions/Comments
2880
3550
3200
MHz
MHz
MHz
MHz/V
MHz/V
Low VCO typical coverage
High VCO typical coverage
Guaranteed frequency coverage 2
Low frequency VCO at 2457.6 MHz
High frequency VCO at 2949.12 MHz
38 to 44
35 to 40
Rev. B | Page 8 of 72
Data Sheet
Parameter
OPEN-LOOP VCO PHASE NOISE
fOUT = 2457.6 MHz
fOFFSET = 100 kHz
HMC7044
Min
Typ
fOFFSET = 800 kHz
fOFFSET = 1 MHz
fOFFSET = 10 MHz
Normalized Phase Noise Variation vs.
Frequency
Phase Noise Variation vs. Temperature
Phase Noise Degradation in Low
Performance Mode
1
2
Max
Unit
Test Conditions/Comments
−109
dBc/Hz
High performance mode, does not include
floor contribution due to output network
−134
−136
−156
±2
dBc/Hz
dBc/Hz
dBc/Hz
dB
±2
2
dB
dB
Sweep across both VCOs, all bands;
normalize to 2457.6 MHz
Guaranteed by design and characterization.
Although the device covers this range without any gaps, for frequencies between ~2700 Hz and 2900 Hz, using a different VCO core to synthesize the frequency can
be required as process parameters shift. Features are built into the HMC7044 to determine which core is selected for a given frequency that can fall in this range, but it
can require software to configure these circuits appropriately.
CLOCK OUTPUT DISTRIBUTION CHARACTERISTICS
Table 7.
Parameter
CLOCK OUTPUT SKEW
CLKOUTx/CLKOUTx to SCLKOUTx/SCLKOUTx
Skew within One Clock Output Pair
Any CLKOUTx/CLKOUTx to Any
SCLKOUTx/SCLKOUTx
CLOCK OUTPUT DIVIDER
12-Bit Divider Range
SYSREF CLOCK OUTPUT DIVIDER
12-Bit Divider Range
CLOCK OUTPUT ANALOG FINE DELAY
Analog Fine Delay
Adjustment Range 1
Resolution
Maximum Analog Fine Delay Frequency1
CLOCK OUTPUT COARSE DELAY (FLIP FLOP
BASED)
Coarse Delay Adjustment Range
Coarse Delay Resolution
Maximum Frequency Coarse Delay1
CLOCK OUTPUT COARSE DELAY (SLIP BASED)
Coarse Delay
Adjustment Range
Resolution
Maximum Frequency Coarse Delay
1
Min
Typ
Max
Unit
Test Conditions/Comments
15
|ps|
30
|ps|
Same pair, same type termination and
configuration
Any pair, same type termination and configuration
1
4094
1, 3, 5, and all even numbers up to 4094
1
4094
1, 3, 5 and all even numbers up to 4094; pulse
generator behavior is only supported for divide
ratios ≥ 32
135
670
ps
ps
MHz
24 delay steps, fCLKOUT = 983.04 MHz
fCLKOUT = 983.04 MHz (2949.12 MHz/3)
17
17 delay steps in ½ VCO period
169.54
3200
½ VCO
period
ps
MHz
1 to ∞
339.08
1600
VCO period
ps
MHz
25
3200
0
Guaranteed by design and characterization.
Rev. B | Page 9 of 72
fVCO = 2949.12 MHz
fVCO = 2949.12 MHz
HMC7044
Data Sheet
SPUR CHARACTERISTICS
Table 8.
Parameter
REFERENCE SPUR PERFORMANCE
At 122.88 MHz and Its Harmonics
Min
Typ
Max
−70
Unit
Test Conditions/Comments
dBc
NOISE AND JITTER CHARACTERISTICS
Table 9.
Parameter
CLOSED-LOOP PHASE NOISE—WIDE LOOP FILTER
SSB Phase Noise
At 2457.6 MHz 1
Min
Typ
Max
Unit
Test Conditions/Comments
For best integrated noise
−98.0
−111.1
−119.8
−125.2
−126.9
−131.3
−150.0
−154.0
−156.3
44.0
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
fs
Offset = 100 Hz
Offset = 1 kHz
Offset = 10 kHz
Offset = 100 kHz
Offset = 300 kHz
Offset = 1 MHz
Offset = 5 MHz
Offset = 10 MHz
Offset = 100 MHz
Integrated jitter = 12 kHz to 20 MHz
−110.4
−122.8
−131.3
−136.6
−138.3
−142.7
−157.6
−158.8
−159.2
50.0
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
fs
Offset = 100 Hz
Offset = 1 kHz
Offset = 10 kHz
Offset = 100 kHz
Offset = 300 kHz
Offset = 1 MHz
Offset = 5 MHz
Offset = 10 MHz
Offset = 100 MHz
Integrated jitter = 12 kHz to 20 MHz
For best 800 kHz offset
−100.9
−103.8
−106.9
−109.9
−132.3
−134.5
−152
−155.3
108
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
fs
Offset = 100 Hz
Offset = 1 kHz
Offset = 10 kHz
Offset = 100 kHz
Offset = 800 kHz
Offset = 1 MHz
Offset = 10 MHz
Offset = 100 MHz
Integrated jitter = 12 kHz to 20 MHz
−110.4
−113.3
−116.4
−119.4
−141.7
−143.7
−157.1
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Offset = 100 Hz
Offset = 1 kHz
Offset = 10 kHz
Offset = 100 kHz
Offset = 800 kHz
Offset = 1 MHz
Offset = 10 MHz
At 614.4 MHz1
CLOSED-LOOP PHASE NOISE—NARROW LOOP FILTER
SSB Phase Noise
At 2949.12 MHz 2
At 983.04 MHz2
Rev. B | Page 10 of 72
Data Sheet
HMC7044
Parameter
Min
OUTPUT NETWORK FLOOR FOM
CML with 100 Ω Internal Termination (CML100)
Fundamental Mode
Divide by 1 to Divide by N
Divide by 1 to Divide by N
LVPECL
Fundamental Mode
Divide by 1 to Divide by N
LVDS
Divide by 1 to Divide by N
Divide by 1 to Divide by N
PHASE NOISE DEGREDATION DUE TO HARMONICS 3
Fundamental Only
Third Harmonic
Third and Fifth Harmonics
Third, Fifth, and Seventh Harmonics
Third, Fifth, Seventh, and Ninth Harmonics
Third Through 61st Harmonics
PHASE NOISE FLOOR AND JITTER
Phase Noise Floor at fOUT
Jitter Density of Floor at fOUT
RMS Additive Jitter Due to Floor
Typ
−157.1
102
Max
Unit
dBc/Hz
fs
Test Conditions/Comments
Offset = 100 MHz
Integrated jitter 12 kHz to 20 MHz
−250
−248
−247
dBc/Hz
dBc/Hz
dBc/Hz
High performance
High performance
Low power (4 dB less power)
−250
−247
dBc/Hz
dBc/Hz
−244
−243
dBc/Hz
dBc/Hz
0.00
0.25
0.40
0.50
0.53
0.64
dB
dB
dB
dB
dB
dB
Determined by formula 4
Determined by formula 5
Determined by formula 6
dBc/Hz
sec/√Hz
sec
High performance
Low power (4 dB less power)
From fOUT and output channel FOM
PLL2 locked at 122.88 MHz × 2 × 10, wide (600 kHz) loop filter for best 12 kHz to 20 MHz jitter, CML100 high performance output buffer.
PLL2 locked at 122.88 MHz × 2 × 12, narrow loop for best 800 Hz offset, CML100 high performance output buffer.
When the harmonics of the signal are captured in the measurement bandwidth of the receiving instrument/circuit, the noise power of those harmonics can fold and
influence the overall noise. Their presence causes a decibel for decibel influence. For example, if the third harmonic is at −10 dBc, there is an additional noise
contributor of 10 dB lower than the fundamental at all offsets that folds in-band and causes a 0.2 dB hit overall. The influence of the harmonics factoring into the
degradation is primarily a function of the frequency of the buffer bandwidth relative to the third, fifth, and seventh harmonics. As the output frequency reduces, more
harmonics fall into the observation bandwidth, and the degradation worsens, but only slightly. This effect produces a penalty of 0.65 dB maximum if harmonics up to
the 61st harmonic is included.
4
See the Phase Noise Floor and Jitter section for more information on how to calculate the phase noise floor.
5
See the Phase Noise Floor and Jitter section for more information on how to calculate the jitter density of floor.
6
See the Phase Noise Floor and Jitter section for more information on how to calculate the rms additive jitter due to floor.
1
2
3
CLOCK OUTPUT DRIVER CHARACTERISTICS
Table 10.
Parameter
CML MODE (LOW POWER)
−3 dB Bandwidth
Output Rise Time
Min
Output Fall Time
Output Duty Cycle 1
Differential Output Voltage Magnitude
Common-Mode Output Voltage
CML MODE (HIGH POWER)
3 dB Bandwidth
Output Rise Time
Output Fall Time
47.5
Typ
Max
1950
175
145
185
145
50
1390
1360
VCC − 1.05
1400
250
165
255
170
52.5
Unit
MHz
ps
ps
ps
ps
%
mV p-p diff
mV p-p diff
V
MHz
ps
ps
ps
ps
Rev. B | Page 11 of 72
Test Conditions/Comments
RL = 100 Ω, 9.6 mA
Differential output voltage = 980 mV p-p diff
fCLKOUT = 245.76 MHz, 20% to 80%
fCLKOUT = 983.04 MHz, 20% to 80%
fCLKOUT = 245.76 MHz, 20% to 80%
fCLKOUT = 983.04 MHz, 20% to 80%
fCLKOUT = 1075 MHz (2150 MHz/2)
fCLKOUT = 245.76 MHz (2949.12 MHz/12)
fCLKOUT = 983.04 MHz (2949.12 MHz/3)
fCLKOUT = 245.76 MHz (2949.12 MHz/12)
RL = 100 Ω, 14.5 mA
Differential output voltage = 1410 mV p-p diff
fCLKOUT = 245.76 MHz, 20% to 80%
fCLKOUT = 983.04 MHz, 20% to 80%
fCLKOUT = 245.76 MHz, 20% to 80%
fCLKOUT = 983.04 MHz, 20% to 80%
HMC7044
Parameter
Output Duty Cycle1
Differential Output Voltage Magnitude
Data Sheet
Min
47.5
Common-Mode Output Voltage
LVPECL MODE
3 dB Bandwidth
Output Rise Time
Output Fall Time
Output Duty Cycle1
Differential Output Voltage Magnitude
47.5
Common-Mode Output Voltage
LVDS MODE (LOW POWER)
Maximum Operating Frequency
Output Rise Time
Output Fall Time
Output Duty Cycle1
Differential Output Voltage Magnitude
Common-Mode Output Voltage
LVDS MODE (HIGH POWER)
Maximum Operating Frequency
Output Rise Time
47.5
Output Fall Time
Output Duty Cycle1
Differential Output Voltage Magnitude
Common-Mode Output Voltage
CMOS MODE
Maximum Operating Frequency
Output Rise Time
Output Fall Time
Output Duty Cycle1
Output Voltage
High
Output
1
47.5
47.5
Typ
50
2000
1800
VCC − 1.6
2400
135
130
135
130
50
1760
1850
VCC − 1.3
600
135
100
135
95
50
390
1.1
Max
52.5
52.5
52.5
1700
145
105
145
100
50
750
730
1.1
600
425
420
50
52.5
52.5
VCC − 0.07
VCC − 0.5
0.07
0.5
Unit
%
mV p-p diff
mV p-p diff
V
MHz
ps
ps
ps
ps
%
mV p-p diff
mV p-p diff
V
Test Conditions/Comments
fCLKOUT = 1075 MHz (2150 MHz/2)
fCLKOUT = 245.76 MHz (2949.12 MHz/12)
fCLKOUT = 983.04 MHz (2949.12 MHz/3)
fCLKOUT = 245.76 MHz (2949.12 MHz/12)
RL = 150 Ω, 4.8 mA
Differential output voltage = 1240 mV p-p diff
fCLKOUT = 245.76 MHz, 20% to 80%
fCLKOUT = 983.04 MHz, 20% to 80%
fCLKOUT = 245.76 MHz, 20% to 80%
fCLKOUT = 983.04 MHz, 20% to 80%
fCLKOUT = 1075 MHz (2150 MHz/2)
fCLKOUT = 245.76 MHz (2949.12 MHz/12)
fCLKOUT = 983.04 MHz (2949.12 MHz/3)
fCLKOUT = 245.76 MHz (2949.12 MHz/12)
1.75 mA
Differential output voltage = 400 mV p-p diff
fCLKOUT = 245.76 MHz, 20% to 80%
fCLKOUT = 983.04 MHz, 20% to 80%
fCLKOUT = 245.76 MHz, 20% to 80%
fCLKOUT = 983.04 MHz, 20% to 80%
fCLKOUT = 1075 MHz (2150 MHz/2)
fCLKOUT = 245.76 MHz (2949.12 MHz/12)
fCLKOUT = 245.76 MHz (2949.12 MHz/12)
3.5 mA
Differential output voltage = 650 mV p-p diff
fCLKOUT = 245.76 MHz, 20% to 80%
fCLKOUT = 983.04 MHz, 20% to 80%
fCLKOUT = 245.76 MHz, 20% to 80%
fCLKOUT = 983.04 MHz, 20% to 80%
fCLKOUT = 1075 MHz (2150 MHz/2)
fCLKOUT = 245.76 MHz (2949.12 MHz/12)
fCLKOUT = 983.04 MHz (2949.12 MHz/3)
fCLKOUT = 245.76 MHz (2949.12 MHz/12)
MHz
ps
ps
%
Single-ended output voltage = 940 mV p-p diff
fCLKOUT = 245.76 MHz, 20% to 80%
fCLKOUT = 245.76 MHz, 20% to 80%
fCLKOUT = 1075 MHz (2150 MHz/2)
V
V
V
V
Load current = 1 mA
Load current = 10 mA
Load current = 1 mA
Load current = 10 mA
MHz
ps
ps
ps
ps
%
mV p-p diff
mV p-p diff
V
MHz
ps
ps
ps
ps
%
mV p-p diff
V
Guaranteed by design and characterization.
Rev. B | Page 12 of 72
Data Sheet
HMC7044
ABSOLUTE MAXIMUM RATINGS
Table 11.
Parameter
VCC1_VCO, VCC2_OUT, VCC3_SYSREF,
VCC4_OUT, VCC5_PLL1, VCC6_OSCOUT,
VCC7_PLL2, VCC8_OUT, VCC9_OUT
Maximum Junction Temperature (TJ)
Maximum Peak Reflow Temperature
Thermal Resistance (Channel to Ground
Paddle)
Storage Temperature Range
Operating Temperature Range
ESD Sensitivity Level
Human Body Model
Charged Device Model1
1
Rating
−0.3 V to +3.6 V
125°C
260°C
7°C/W
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
−65°C to +150°C
−40°C to +85°C
Class 1C
Class 3
Per JESD22-C101-F (CDM) standard.
Rev. B | Page 13 of 72
HMC7044
Data Sheet
53 SCLKOUT9
52 GPIO2
5
47
OSCIN
SYNC
6
46
LDOBYP6
BGABYP1
7
45
OSCOUT1
LDOBYP2
8
HMC7044
44
OSCOUT1
LDOBYP3
9
TOP VIEW
(Not to Scale)
43
CLKIN2/OSCOUT0
42
CLKIN2/OSCOUT0
LDOBYP4 11
41
VCC6_OSCOUT
LDOBYP5 12
40
CLKIN0/RFSYNCIN
SCLKOUT3 13
39
CLKIN0/RFSYNCIN
SCLKOUT3 14
38
VCC5_PLL1
CLKOUT2 15
37
CLKIN1/FIN
CLKOUT2 16
36
CLKIN1/FIN
VCC2_OUT 17
35
RSV
SCLKOUT5 23
SCLKOUT5 22
VCC3_SYSREF 21
SDATA 20
SLEN 18
SCLK 19
VCC1_VCO 10
CLKIN3 34
OSCIN
RESET
CLKIN3 33
48
CPOUT1 32
4
GPIO1 31
LDOBYP7
SCLKOUT1
SCLKOUT7 30
49
SCLKOUT7 29
3
CLKOUT6 28
CPOUT2
SCLKOUT1
CLKOUT6 27
VCC7_PLL2
50
VCC4_OUT 26
51
2
CLKOUT4 25
1
CLKOUT0
CLKOUT4 24
CLKOUT0
NOTES
1. EXPOSED PAD. CONNECT THE EXPOSED PAD TO A HIGH QUALITY RF/DC GROUND.
13033-002
54 SCLKOUT9
55 CLKOUT8
56 CLKOUT8
57 VCC8_OUT
58 CLKOUT10
59 CLKOUT10
60 SCLKOUT11
61 SCLKOUT11
62 GPIO3
63 GPIO4
64 SCLKOUT13
65 SCLKOUT13
66 CLKOUT12
67 CLKOUT12
68 VCC9_OUT
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 2. Pin Configuration
Table 12. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
Mnemonic
CLKOUT0
CLKOUT0
SCLKOUT1
SCLKOUT1
RESET
SYNC
BGABYP1
Type 1
O
O
O
O
I
I
8
LDOBYP2
9
LDOBYP3
10
11
VCC1_VCO
LDOBYP4
12
13
14
15
16
17
LDOBYP5
SCLKOUT3
SCLKOUT3
CLKOUT2
CLKOUT2
VCC2_OUT
O
O
O
O
P
18
SLEN
I
P
Description
True Clock Output Channel 0. Default DCLK profile.
Complementary Clock Output Channel 0. Default DCLK profile.
True Clock Output Channel 1. Default SYSREF profile.
Complementary Clock Output Channel 1. Default SYSREF profile.
Device Reset Input. Active high. For normal operation, set RESET to 0.
Synchronization Input. This pin is used for multichip synchronization. If not used, set SYNC to 0.
Band Gap Bypass Capacitor Connection. Connect a 4.7 µF capacitor to ground. This pin affects all
internally regulated supplies.
LDO Bypass 2. Connect a 4.7 µF capacitor to ground. The internal digital supply is 1.8 V. This pin is
the LDO bypass for the PLL1, PLL2, and SYSREF sections.
LDO Bypass 3. Connect a 4.7 µF capacitor to ground. This pin is the 2.8 V supply to PLL1, Phase
Frequency Detector 1 (PFD1), Charge Pump 1 (CP1), RF synchronization (RFSYNC), and Pin 36
buffers.
3.3 V Supply for VCO and VCO Distribution.
LDO Bypass 4. Connect a 1 µF capacitor to ground. This pin is the first stage regulator for the VCO
supply.
LDO Bypass 5. Connect a 100 nF capacitor to LDOBYP4. This pin is the VCO core supply voltage.
True Clock Output Channel 3. Default SYSREF profile.
Complementary Clock Output Channel 3. Default SYSREF profile.
True Clock Output Channel 2. Default DCLK profile.
Complementary Clock Output Channel 2. Default DCLK profile.
Power Supply for Clock Group 1 (Southwest)—Channel 2 and Channel 3. See the Clock Grouping,
Skew, and Crosstalk section.
SPI Latch Enable.
Rev. B | Page 14 of 72
Data Sheet
HMC7044
Pin No.
19
20
21
22
23
24
25
26
Mnemonic
SCLK
SDATA
VCC3_SYSREF
SCLKOUT5
SCLKOUT5
CLKOUT4
CLKOUT4
VCC4_OUT
Type 1
I
I/O
P
O
O
O
O
P
27
28
29
30
31
32
33
34
35
36
37
CLKOUT6
CLKOUT6
SCLKOUT7
SCLKOUT7
GPIO1
CPOUT1
CLKIN3
CLKIN3
RSV
CLKIN1/FIN
CLKIN1/FIN
O
O
O
O
I/O
O
I
I
R
I
I
38
39
40
VCC5_PLL1
CLKIN0/RFSYNCIN
CLKIN0/RFSYNCIN
P
I
I
41
42
43
VCC6_OSCOUT
CLKIN2/OSCOUT0
CLKIN2/OSCOUT0
P
I/O
I/O
44
45
46
OSCOUT1
OSCOUT1
LDOBYP6
O
O
47
48
49
OSCIN
OSCIN
LDOBYP7
I
I
50
51
52
53
54
55
56
57
CPOUT2
VCC7_PLL2
GPIO2
SCLKOUT9
SCLKOUT9
CLKOUT8
CLKOUT8
VCC8_OUT
I/O
P
I/O
O
O
O
O
P
58
59
60
61
62
63
64
CLKOUT10
CLKOUT10
SCLKOUT11
SCLKOUT11
GPIO3
GPIO4
SCLKOUT13
O
O
O
O
I/O
I/O
O
Description
SPI Clock.
SPI Data.
Power Supply for Common SYSREF Divider.
True Clock Output Channel 5. Default SYSREF profile.
Complementary Clock Output Channel 5. Default SYSREF profile.
True Clock Output Channel 4. Default DCLK profile.
Complementary Clock Output Channel 4. Default DCLK profile.
Power Supply for Clock Group 2 (South)—Channel 4, Channel 5, Channel 6, and Channel 7. See the
Clock Grouping, Skew, and Crosstalk section.
True Clock Output Channel 6. Default DCLK profile.
Complementary Clock Output Channel 6. Default DCLK profile.
True Clock Output Channel 7. Default SYSREF profile.
Complementary Clock Output Channel 7. Default SYSREF profile.
Programmable General-Purpose Input/Output 1.
PLL1 Charge Pump Output.
True Reference Clock Input 3 of PLL1.
Complementary Reference Clock Input 3 of PLL1.
Reserved Pin. This pin must be tied to ground.
True Reference Clock Input 1 of PLL1/External VCO Input for External VCO Mode.
Complementary Reference Clock Input 1 of PLL1/Complementary External VCO Input for External
VCO Mode.
Power Supply for LDO, Used for PLL1.
True Reference Clock Input 0 of PLL1/RF Synchronization Input with Deterministic Delay.
Complementary Reference Clock Input 0 of PLL1/Complementary RF Synchronization Input with
Deterministic Delay.
Power Supply for Oscillator Output Path.
True Reference Clock Input 2 (Bidirectional Pin) of PLL1/Buffered Output 0 of Oscillator Input.
Complementary Reference Clock Input 2 (Bidirectional Pin) of PLL1/Complementary Buffered
Output 0 of Oscillator Input.
True Buffered Output 1 of Oscillator Input.
Complementary Buffered Output 1 of Oscillator Input.
LDO Bypass, Connect a 4.7 µF capacitor to ground. This pin is the LDO bypass for R2, N2, Phase
Frequency Detector 2 (PFD2), Charge Pump 2 (CP2), and the PLL2 loop filter.
True Feedback Input to PLL1. This pin is a reference input to PLL2.
Complementary Feedback Input to PLL1. This pin is a reference input to PLL2.
LDO Bypass. Connect a 4.7 µF capacitor to ground. This pin is the LDO bypass for the VCXO buffer
and frequency doubler oscillator output divider.
PLL2 Charge Pump Output.
Power Supply for LDO for PLL2.
Programmable General-Purpose Input/Output 2.
True Clock Output Channel 9. Default SYSREF profile.
Complementary Clock Output Channel 9. Default SYSREF profile.
True Clock Output Channel 8. Default DCLK profile.
Complementary Clock Output Channel 8. Default DCLK profile.
Power Supply for Clock Group 3 (North)—Channel 8, Channel 9, Channel 10, and Channel 11. See
the Clock Grouping, Skew, and Crosstalk section.
True Clock Output Channel 10. Default DCLK profile.
Complementary Clock Output Channel 10. Default DCLK profile.
True Clock Output Channel 11. Default SYSREF profile.
Complementary Clock Output Channel 11. Default SYSREF profile.
Programmable General-Purpose Input/Output 3. Sleep input by default.
Programmable General-Purpose Input/Output 4. Pulse generator request by default.
True Clock Output Channel 13. Default SYSREF profile.
Rev. B | Page 15 of 72
HMC7044
Pin No.
65
66
67
68
Mnemonic
SCLKOUT13
CLKOUT12
CLKOUT12
VCC9_OUT
EP
1
Data Sheet
Type 1
O
O
O
P
Description
Complementary Clock Output Channel 13. Default SYSREF profile.
True Clock Output Channel 12. Default DCLK profile.
Complementary Clock Output Channel 12. Default DCLK profile.
Power Supply for Clock Group 0 (Northwest)—Channel 0, Channel 1, Channel 12, and Channel 13.
See the Clock Grouping, Skew, and Crosstalk section.
Exposed Pad. Connect the exposed pad to a high quality RF/dc ground.
O is output, I is input, P is power, and I/O is input/output.
Rev. B | Page 16 of 72
Data Sheet
HMC7044
TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise noted, PFD PLL1 = 7.68 MHz, PFD PLL2 = 122.88 MHz × 2; ICP1 = 1.92 mA, ICP2 = 2.56 mA (wide loop), ICP2 = 1.12 mA
(narrow loop), PLL1 loop BW ~ 70 Hz, PLL2 wide loop BW ≈ 650 kHz, PLL2 narrow loop BW ≈ 215 kHz, PLL2 narrow loop filter =
1.1 nF | 160 Ω × 33 nF; PLL2 wide loop filter = 150 pF | 430 Ω × 4.7 nF; PLL1 loop filter = 4.7 nF | 10 µF × 1.2 kΩ.
–60
–80
–90
–100
–70
1
–110
2
PLL1
CASCADED PLL1 + PLL2
–120
3
4
–130
–140
NOISE:
ANALYSIS RANGE X: BAND MARKER
ANALYSIS RANGE Y: BAND MARKER
INTG NOISE: –66dBc/20MHz
RMS NOISE: 696µrad
0.004°
RMS JITTER: 45fs
RESIDUAL FM: 1.6kHz
–150
–160
–170
–180
1
10
1k
100
6
5
10k
100k
1M
TOTAL PLL1 NOISE (SIMULATED)
PFD/CP NOISE (SIMULATED)
WENZEL REF (SIMULATED)
VCXO (SIMULATED)
TOTAL PLL1 NOISE (MEASURED)
–80
7
–90
–100
–110
–120
–130
–140
13033-003
PHASE NOISE (dBc/Hz)
–70
–60
1kHz, –107.8dBc/Hz
10kHz, –119.5dBc/Hz
100kHz, –124.7dBc/Hz
1MHz, –131.5Bc/Hz
10MHz, –153.1dBc/Hz
20MHz, –154.4dBc/Hz
20MHz, –154.4dBc/Hz
START 12kHz
STOP 20MHz
CENTER 10MHz
SPAN 20MHz
13033-008
1:
2:
3:
4:
5:
6:
7:
x:
–50
PHASE NOISE (dBc/Hz)
–40
–150
–160
10M
1
10
100
FREQUENCY (Hz)
Figure 3. Cascaded Phase Noise at 2457.6 MHz, PLL2 Wide Loop Bandwidth
–60
1
2
–110
–80
3
–120
WIDE LOOP
NARROW LOOP
–140
–150
–160
–170
4
NOISE:
ANALYSIS RANGE X: BAND MARKER
ANALYSIS RANGE Y: BAND MARKER
INTG NOISE: –56.9dBc/20MHz
RMS NOISE: 2.0µrad
.116°
RMS JITTER: 131fs
RESIDUAL FM: 1.5kHz
1k
10k
5
–90
–100
–110
–120
–130
–140
6
100k
1M
7
13033-009
–130
–150
–160
10M
1
100
10
FREQUENCY (Hz)
–120
1
–110
–125
–130
2
–120
3
4
CRYSTEK VCXO
WENZEL VCXO
–130
NOISE:
ANALYSIS RANGE X: BAND MARKER
–150 ANALYSIS RANGE Y: BAND MARKER
1k
10k
100k
1M
7
13033-004
–170
100
5
–140
20×LOG (800kHz WIDE LOOP)
20×LOG (800kHz NARROW LOOP)
800kHz WIDE LOOP
800kHz NARROW LOOP
–145
–150
–155
–160
6
INTG NOISE: –66.1dBc/20.0MHz
RMS NOISE: 702µrad
.040°
RMS JITTER: 45fs
RESIDUAL FM: 1.6kHz
–135
10M
FREQUENCY (Hz)
13033-006
–90
–100
1kHz, –110.4dBc/Hz
10kHz, –120.0dBc/Hz
100kHz, –124.9dBc/Hz
1MHz, –131.2dBc/Hz
10MHz, –153.2dBc/Hz
20MHz, –154.5dBc/Hz
20MHz, –154.5dBc/Hz
START 12kHz
STOP 20MHz
CENTER 10MHz
SPAN 20MHz
PHASE NOISE (dBc/Hz)
1:
2:
3:
4:
5:
6:
7:
x:
–80
PHASE NOISE (dBc/Hz)
100k
Figure 7. Closed-Loop Phase Noise at 122.88 MHz, PLL1 Measurement vs.
Simulated, Noisy Reference Source, ~70 Hz Loop Bandwidth, 80° Phase Margin
–70
–160
10k
1k
FREQUENCY (Hz)
Figure 4. Phase Noise at 2457.6 MHz, Narrow vs. PLL2 Wide Loop
Bandwidth
–140
1M
TOTAL PLL1 OUTPUT (SIMULATED)
PFD/CP NOISE (SIMULATED)
NOISY SOURCE (SIMULATED)
VCXO (SIMULATED)
NOISY SOURCE, OPEN LOOP (MEASURED)
TOTAL PLL1 NOISE (MEASURED)
–70
13033-005
PHASE NOISE (dBc/Hz)
–100
1kHz, –105.3dBc/Hz
10kHz, –108.5dBc/Hz
100kHz, –111.4dBc/Hz
800kHz, –134.2dBc/Hz
1MHz, –136.5dBc/Hz
10MHz, –153.3dBc/Hz
20MHz, –154.6dBc/Hz
START 12kHz
STOP 20MHz
CENTER 10MHz
SPAN 20MHz
PHASE NOISE (dBc/Hz)
1:
2:
3:
4:
5:
6:
7:
x:
–90
100k
Figure 6. Closed-Loop Phase Noise at 122.88 MHz, PLL1 Measurement vs.
Simulated, Clean Reference Source, ~70 Hz Loop Bandwidth 80° Phase Margin
–70
–80
10k
1k
FREQUENCY (Hz)
–165
–170
100
600
1100
1600
2100
2600
3100
3600
FREQUENCY (MHz)
Figure 5. PLL2 Phase Noise vs. Frequency, VCXO Quality at 2457.6 MHz,
Wide Loop Bandwidth
Rev. B | Page 17 of 72
Figure 8. Phase Noise vs. Frequency at Common Output Frequencies
HMC7044
Data Sheet
160
3.0
JITTER WIDE LOOP
JITTER NARROW LOOP
140
VCO VTUNE (V)
JITETR (fs)
120
100
80
60
HIGH VCO –40°C
HIGH VCO +25°C
HIGH VCO +85°C
LOW VCO –40°C
LOW VCO +25°C
LOW VCO +85°C
2.5
2.0
1.5
1.0
40
13033-007
3650
3450
3250
3050
0
3600
2850
3100
2650
1600
2100
2600
FREQUENCY (MHz)
2450
1100
2250
600
2050
0
100
13033-011
0.5
20
FREQUENCY (MHz)
Figure 9. 12 kHz to 20 MHz Jitter vs. Frequency, Wide Loop and Narrow
Loop at Common Output Frequencies
–100
8
–110
1
–115
–120
2
–125
3
–130
7
–135
–140
–145
–150
–155
4
NOISE:
ANALYSIS RANGE X: BAND MARKER
ANALYSIS RANGE Y: BAND MARKER
INTG NOISE: –66.4dBc/20MHz
RMS NOISE: 678µrad
.039°
RMS JITTER: 44fs
RESIDUAL FM: 1.5kHz
–160
100
1k
10k
6
5
100k
1M
13033-021
PHASE NOISE (dBc/Hz)
–105
3.5
100Hz, –99.8dBc/Hz
1kHz, –111.1dBc/Hz
10kHz, –119.8dBc/Hz
100kHz, –125.2dBc/Hz
300kHz, –126.9dBc/Hz
1MHz, –131.3Bc/Hz
10MHz, –153.1dBc/Hz
32.8MHz, –156.3dBc/Hz
START 12kHz
STOP 20MHz
CENTER 10MHz
SPAN 20MHz
LVPECL
CML100 HIGH
CML100 LOW
LVDS HIGH
CMOS (NOT IN
DIFFERENTIAL MODE)
3.0
2.5
2.0
1.5
1.0
0.5
13033-112
8:
1:
2:
3:
7:
4:
5:
6:
x:
–95
DIFFERENTIAL OUTPUT VOLTAGE (V p-p DIFF)
–90
Figure 12. VCO VTUNE vs. Frequency
0
100M
10M
1G
FREQUENCY (Hz)
Figure 10. Phase Noise, CLKOUTx/CLKOUTx = 2457.6 MHz, Optimized for Best
Integrated Jitter (12 kHz to 20 MHz)
Figure 13. Differential Output Voltage vs. Frequency at Different Modes
2.25
90
80
2865.72MHz
70
3511.86MHz
60
50
40
2115.38MHz
2627.755 MHz
30
20
10
CAP = 31 LOW VCO
CAP = 31 HIGH VCO
13033-010
CAP = 0 LOW VCO
CAP = 0 HIGH VCO
0
0
0.5
1.0
1.5
2.0
2.5
LVPECL
CML100 HIGH
CML100 LOW
LVDS HIGH
1.95
1.80
1.65
1.50
1.35
1.20
1.05
0.90
0.75
0.60
0.45
0.30
0.15
0
1.0
3.0
VCO VTUNE (V)
Figure 11. VCO Gain (KVCO) vs. VCO VTUNE
2.10
13033-012
DIFFERENTIAL OUTPUT VOLTAGE (V p-p DIFF)
100
KVCO (MHz/V)
3G
FREQUENCY (Hz)
1.5
2.0
2.5
FREQUENCY (GHz)
3.0
3.5
Figure 14. Differential Output Voltage vs. Frequency at Different Modes
Rev. B | Page 18 of 72
Data Sheet
HMC7044
30
–40°C
+25°C
+85°C
DELAY STEP SIZE (ps)
2.0
1.5
1.0
25
20
–40°C
+25°C
+85°C
15
10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
0
100M
13033-020
0.5
13033-013
DIFFERENTIAL OUTPUT POWER (V p-p DIFF)
2.5
3G
1G
FREQUENCY (Hz)
DELAY STEP
Figure 18. Analog Delay Step Size vs. Delay Step over Temperature, LVPECL
at 1474.56 MHz
0.4
800
0.3
700
600
0.2
ANALOG DELAY (ps)
0.1
0
–0.1
500
–40°C
+25°C
+85°C
400
300
200
100
–0.2
13033-017
–0.4
0.4
0
1.2
0.8
1.6
–100
FUND: FUNDAMENTAL MODE AT 2949MHz
DIS: ANALOG DELAY IS DISABLED AT 1474MHz
–200
2.0
13033-019
0
–0.3
FUND
DIS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
CLKOUT0/CLKOUT0 VOLTAGE (V)
Figure 15. LVPECL Differential Output Voltage vs. Frequency at Different
Temperatures
TIME (ns)
DELAY SETTING
Figure 19. Analog Delay vs. Delay Setting over Temperature, LVPECL
at 1474.56 MHz
Figure 16. Differential CLKOUT0/CLKOUT0 at 2457 MHz, LVPECL
30
1.0
25
DELAY STEP SIZE (ps)
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
20
15
10
–40°C
+25°C
+85°C
5
13033-018
–1.0
0
1
2
3
4
5
6
7
8
9
0
10
TIME (ns)
DELAY STEP
Figure 17. Differential CLKOUT0/CLKOUT0 Voltage at 614.4 MHz, LVPECL
13033-119
–0.8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
CLKOUT0/CLKOUT0 VOLTAGE (V)
0.8
Figure 20. Analog Delay Step Size vs Delay Step over Temperature, LVPECL
at 3072 MHz with Digital Delay = 0
Rev. B | Page 19 of 72
0.6
700
CLOCK OUPUT VOLTAGE (V)
200
100
0
1.0
–0.2
0.5
–0.4
0
–0.6
DELAY SETTING
13033-120
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
0
0
200
400
600
800
Figure 24. Output Channel Synchronization Before and After Rephase
30
2.5
0.6
–40°C
+25°C
+85°C
2.0
CLOCK OUTPUT VOLTAGE (V)
0.4
25
20
15
CLKOUT0
CLKOUT2
VALID PHASE ALARM
0.2
1.5
0
1.0
–0.2
0.5
–0.4
0
–0.6
330
13033-121
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
10
DELAY STEP
–0.5
1000
TIME (ns)
Figure 21. Analog Delay vs. Delay Setting over Temperature, LVPECL at
3072 MHz with Digital Delay = 0
DELAY STEP SIZE (ps)
1.5
335
340
345
–0.5
350
TIME (ns)
Figure 25. Output Channel Synchronization Before Rephase
Figure 22. Analog Delay Step Size vs Delay Step over Temperature, LVPECL
at 3072 MHz with Digital Delay = 1
800
0.6
2.5
0.4
2.0
0.2
1.5
0
1.0
–0.2
0.5
CLOCK OUTPUT VOLTAGE (V)
700
ANALOG DELAY (ps)
600
500
400
–40°C
+25°C
+85°C
300
200
–0.4
0
100
CLKOUT0
CLKOUT2
13033-122
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
0
DELAY SETTING
CLOCK GROUP VALID PHASE ALARM VOLTAGE (V)
–40°C
+25°C
+85°C
300
0.2
13033-015
400
2.0
Figure 23. Analog Delay vs. Delay Setting over Temperature, LVPECL at
3072 MHz with Digital Delay = 1
Rev. B | Page 20 of 72
–0.6
695
700
VALID PHASE ALARM
705
710
–0.5
715
TIME (ns)
Figure 26. Output Channel Synchronization After Rephase
CLOCK GROUP VALID PHASE ALARM VOLTAGE (V)
500
0.4
13033-016
ANALOG DELAY (ps)
600
2.5
CLKOUT0
CLKOUT2
VALID PHASE ALARM
CLOCK GROUP VALID PHASE ALARM VOLTAGE (V)
Data Sheet
13033-014
HMC7044
Data Sheet
HMC7044
TYPICAL APPLICATION CIRCUITS
HIGH
IMPEDANCE DOWNSTREAM
DEVICE
INPUT
100Ω
LVDS
OUTPUT
0.1µF
Figure 27. AC-Coupled LVDS Output Driver
HMC7044
100Ω
LVPECLCOMPATIBLE
OUTPUT
0.1µF
HIGH
IMPEDANCE DOWNSTREAM
DEVICE
INPUT
50Ω
13033-028
100Ω
0.1µF
CML
OUTPUT
DOWNSTREAM
DEVICE
(LVPECL)
50Ω
50Ω
13033-025
HMC7044
HIGH
IMPEDANCE DOWNSTREAM
DEVICE
INPUT
Figure 31. DC-Coupled LVDS Output Driver
VCC
100Ω
100Ω
13033-023
LVDS
OUTPUT
HMC7044
0.1µF
13033-022
HMC7044
GND
Figure 32. DC-Coupled LVPECL Output Driver
Figure 28. AC-Coupled CML (Configured High-Z) Output Driver
100Ω
CML
OUTPUT
HIGH
IMPEDANCE DOWNSTREAM
DEVICE
INPUT
VCCx_OUT
0.1µF
100Ω
CML
OUTPUT
Figure 33. DC-Coupled CML (Internal) Output Driver
Figure 29. AC-Coupled CML (Internal) Output Driver
0.1µF
HMC7044
SELF BIASED
REF, VCXO
INPUTS
13033-030
3.3V
DRIVER
0.1µF
13033-027
100Ω
DOWNSTREAM
DEVICE
(CML)
100Ω
HMC7044
47Ω
0.1µF
Figure 30. CLKIN0/CLKIN0, CLKIN1/CLKIN1, CLKIN2/CLKIN2, CLKIN3/CLKIN3,
and OSCIN/OSCIN Input, Differential Mode
Rev. B | Page 21 of 72
13033-031
100Ω
VCCx_OUT
HMC7044
0.1µF
13033-026
HMC7044
Figure 34. CLKIN0, CLKIN1, CLKIN2, CLKIN3, and OSCIN Input,
Single-Ended Mode
HMC7044
Data Sheet
TERMINOLOGY
Phase Jitter
An ideal sine wave can be thought of as having a continuous
and even progression of phase with time from 0° to 360° for
each cycle. Actual signals, however, display a certain amount
of variation from ideal phase progression over time. This
phenomenon is phase jitter. Although many causes can
contribute to phase jitter, one major cause is random noise,
which is characterized statistically as being Gaussian (normal)
in distribution.
This phase jitter leads to the energy of the sine wave in the
frequency domain spreading out, producing a continuous
power spectrum. This power spectrum is usually reported as
a series of values whose units are dBc/Hz at a given offset in
frequency from the sine wave (carrier). The value is a ratio
(expressed in decibels) of the power contained within a 1 Hz
bandwidth with respect to the power at the carrier frequency.
For each measurement, the offset from the carrier frequency is
also given.
Phase Noise
It is meaningful to integrate the total power contained within
some interval of offset frequencies (for example, 10 kHz to
10 MHz). This is the integrated phase noise over that frequency
offset interval and can be readily related to the time jitter due to
the phase noise within that offset frequency interval.
Phase noise has a detrimental effect on the performance of ADCs,
DACs, and RF mixers. It lowers the achievable dynamic range of
the converters and mixers, although they are affected in somewhat
different ways.
Time Jitter
Phase noise is a frequency domain phenomenon. In the time
domain, the same effect is exhibited as time jitter. When observing
a sine wave, the time of successive zero crossings varies. In a square
wave, the time jitter is a displacement of the edges from their
ideal (regular) times of occurrence. In both cases, the variations in
timing from the ideal are the time jitter. Because these variations
are random in nature, the time jitter is specified in seconds root
mean square (rms) or 1 sigma of the Gaussian distribution.
Time jitter that occurs on a sampling clock for a DAC or an
ADC decreases the signal-to-noise ratio (SNR) and dynamic
range of the converter. A sampling clock with the lowest possible
jitter provides the highest performance from a given converter.
Additive Phase Noise
Additive phase noise is the amount of phase noise that is
attributable to the device or subsystem being measured.
The phase noise of any external oscillators or clock sources is
subtracted, which makes it possible to predict the degree to
which the device impacts the total system phase noise when
used in conjunction with the various oscillators and clock
sources, each of which contributes its own phase noise to the
total. In many cases, the phase noise of one element dominates
the system phase noise. When there are multiple contributors to
phase noise, the total is the square root of the sum of squares of
the individual contributors.
Additive Time Jitter
Additive time jitter is the amount of time jitter that is attributable to
the device or subsystem being measured. The time jitter of any
external oscillators or clock sources is subtracted, which makes
it possible to predict the degree to which the device impacts the
total system time jitter when used in conjunction with the various
oscillators and clock sources, each of which contributes its own
time jitter to the total. In many cases, the time jitter of the external
oscillators and clock sources dominates the system time jitter.
Rev. B | Page 22 of 72
Data Sheet
HMC7044
THEORY OF OPERATION
The HMC7044 is a high performance, dual-loop, integer N
jitter attenuator capable of performing frequency translation,
reference selection, and generation of ultralow phase noise
references for high speed data converters with either parallel or
serial (JESD204B type) interfaces. The device is designed to
meet the requirements of demanding base station designs, and
offers a wide range of clock management and distribution
features to simplify baseband and radio card clock tree designs.
The HMC7044 uses a dual-loop architecture, where two integer
mode PLLs are connected in series to form a jitter attenuating
clock multiplier unit. The high performance dual-loop topology
of the HMC7044 enables the wireless/RF system designer to
attenuate the incoming jitter of a primary system reference
clock (for example, Common Public Radio Interface™ (CPRI)
source) and generate low phase noise, high frequency clocks to
drive data converter sample clock inputs. The HMC7044 provides
14 low noise and configurable outputs to offer flexibility in
interfacing with many different components in an RF transceiver system, such as data converters, local oscillators,
transmit/receive modules, FPGAs, and digital front-end (DFE)
ASICs.
The first PLL in the HMC7044 is designed for low bandwidth
configuration using appropriately selected external loop filter
components, and internal charge pump bias settings to achieve
less than a few hundred Hz bandwidth, typically. The exact
bandwidth roll-off points depend on the frequency spectrum of
noise that must be attenuated in the system. The first PLL locks
an external VCXO and provides the clock holdover functions
and the reference frequency to the high performance second
PLL loop. The combination of the loops provides an excellent
clock generation unit with the capability to attenuate incoming
reference clock jitter. The second PLL loop features two
overlapping on-chip VCOs that are SPI selectable with center
frequencies at 2.5 GHz and 3 GHz, respectively. Both VCOs are
designed to have wide tuning ranges for broad output frequency
coverage. The desired output frequency is set by the chosen
VCXO frequency, VCO core (higher or lower frequency core),
and the programmed second PLL feedback divider and output
channel divider values.
The HMC7044 generates up to seven DCLK and SYSREF clock
pairs per the JESD204B interface requirements. The system
designer can generate a lower number of DCLK and SYSREF
pairs, and configure the remaining output signal paths as
desired, either as DCLKs or additional SYSREFs or other
reference clocks with independent phase and frequency
adjustment. Frequency adjustment can be accomplished by
selecting the appropriate output divider values. One of the
unique features of the HMC7044 is the independent flexible
phase management of each of the 14 channels. Using a
combination of divider slip-based, digital/coarse and
analog/fine delay adjustments, each channel can be
programmed to have a different phase offset. The phase
adjustment capability allows the designer to offset board flight
time delay variations, data converter sample window matching,
and meet JESD204B synchronization challenges. The output
signal path design of the HMC7044 is implemented to ensure
both linear phase adjustment steps and minimal noise
perturbation when phase adjustment circuits are turned on.
One of the key challenges in JESD204B system design is
ensuring the synchronization of data converter frame alignment
across the system, from the FPGA or DFE to ADCs and DACs
through a large clock tree that can comprise multiple clock
generation and distribution ICs. The HMC7044 is specifically
designed to offer features to address this challenge. Using the
SYSREF valid interrupt feature, the wait time latency can be
reduced in the FPGAs. The HMC7044 raises this flag through
its GPO port when all counters are set and outputs are at the
desired phases. Additionally, an external reference-based
synchronization feature (SYNC via PLL2 or RF SYNC only in
fanout mode) synchronizes multiple devices, that is, it ensures
that all clock outputs start with same rising edge. This operation
is achieved by rephasing the SYSREF control unit deterministically, and then restarting the output dividers with this new
desired phase.
Offering excellent crosstalk, frequency isolation, and spurious
performance, the device generates independent frequencies in
both single-ended and differential formats. The four input
reference options allows up to three backup frequency sources,
with hitless switching and holdover capabilities, supporting
system redundancy and uninterrupted operation on reference
data and clock failures. The device also features dedicated
oscillator fanout mode for best clock isolation, which generates
multiple copies of the VCXO clock to be distributed across the
board with excellent frequency isolation.
Both the DCLK and SYSREF clock outputs can be configured to
support different signaling standards, including CML, LVDS,
LVPECL, and LVCMOS, and different bias conditions to offset
varying board insertion losses. The outputs can also be
programmed for ac or dc coupling and 50 Ω or 100 Ω internal
and external termination options.
The HMC7044 is programmed via a 3-wire serial port interface
(SPI) and powers up with a default configuration that generates
valid output frequencies within the VCO tuning ranges regardless
of whether a reference clock exists.
The HMC7044 is offered in a 68-lead, 10 mm ×10 mm, LFCSP
package with the exposed pad to ground.
Note that, throughout this data sheet, multifunction pins, such
as CLKIN0/RFSYNCIN, are referred to either by the entire pin
name or by a single function of the pin, for example, CLKIN0,
when only that function is relevant.
Rev. B | Page 23 of 72
Data Sheet
HMC7044
DETAILED BLOCK DIAGRAM
RFSYNCIN/
RFSYNCIN
CLKIN0/RFSYNCIN
IN0 PRESCALER
(1 TO 255)
CLKIN0/RFSYNCIN
FIN/
FIN
CLKIN1/FIN
LOS
DETECT
IN1 PRESCALER
(1 TO 255)
CLKIN1/FIN
CLKIN3
IN3 PRESCALER
(1 TO 255)
CLKIN3
CLKIN2/OSCOUT0
SPI
CLKIN2/OSCOUT0
HOLDOVER
R1 DIVIDER
(1 TO 65535)
REF
MUX
IN2 PRESCALER
(1 TO 255)
PHASE DETECTOR
CHARGE PUMP
PLL1
N1 DIVIDER
(1 TO 65535)
CPOUT2
VCXO PRESCALER
(1 TO 255)
2×
OSCOUT1
OSCOUT1
OSC DIVIDER
÷1, ÷2, ÷4, ÷8
OSCIN
2×
MUX
R2 DIVIDER
(1 TO 4095)
N2 DIVIDER
(8 TO 4095)
MUX
SCLKOUT1
SCLKOUT1
MUX
CLKOUT2
CLKOUT2
MUX
SCLKOUT3
SCLKOUT3
MUX
CLKOUT4
CLKOUT4
MUX
SCLKOUT5
SCLKOUT5
MUX
CLKOUT6
CLKOUT6
MUX
SCLKOUT7
SCLKOUT7
MUX
PHASE DETECTOR
CHARGE PUMP
PLL2
ANALOG
DELAY
ANALOG
DELAY
ANALOG
DELAY
ANALOG
DELAY
ANALOG
DELAY
ANALOG
DELAY
ANALOG
DELAY
ANALOG
DELAY
COARSE
DIGITAL
DELAY
DIVIDER
(1 TO 4094)
DIVIDER
(1 TO 4094)
FSM
SYSREF TIMER
SYNC/PULSOR
CONTROL
CYCLE
SLIP/
SYNC
FUNDAMENTAL MODE
COARSE
DIGITAL
DELAY
DIVIDER
(1 TO 4094)
CYCLE
SLIP/
SYNC
DIVIDER
(1 TO 4094)
CYCLE
SLIP/
SYNC
CYCLE
SLIP/
SYNC
DIVIDER
(1 TO 4094)
DIVIDER
(1 TO 4094)
CYCLE
SLIP/
SYNC
CYCLE
SLIP/
SYNC
DIVIDER
(1 TO 4094)
CYCLE
SLIP/
SYNC
CYCLE
SLIP/
SYNC
DIVIDER
(1 TO 4094)
DIVIDER
(1 TO 4094)
COARSE
DIGITAL
DELAY
DIVIDER
(1 TO 4094)
COARSE
DIGITAL
DELAY
FUNDAMENTAL MODE
CYCLE
SLIP/
SYNC
CYCLE
SLIP/
SYNC
FUNDAMENTAL MODE
COARSE
DIGITAL
DELAY
COARSE
DIGITAL
DELAY
FUNDAMENTAL MODE
FUNDAMENTAL MODE
COARSE
DIGITAL
DELAY
OSCINBUF
COARSE
DIGITAL
DELAY
FUNDAMENTAL MODE
FUNDAMENTAL MODE
COARSE
DIGITAL
DELAY
DIVIDER
(1 TO 4094)
DIVIDER
(1 TO 4094)
COARSE
DIGITAL
DELAY
FUNDAMENTAL MODE
CYCLE
SLIP/
SYNC
CYCLE
SLIP/
SYNC
FUNDAMENTAL MODE
DIVIDER
(1 TO 4094)
COARSE
DIGITAL
DELAY
FUNDAMENTAL MODE
MUX
ANALOG
DELAY
MUX
ANALOG
DELAY
MUX
ANALOG
DELAY
MUX
ANALOG
DELAY
MUX
ANALOG
DELAY
MUX
CLKOUT8
SCLKOUT9
SCLKOUT9
CLKOUT10
CLKOUT10
SCLKOUT11
SCLKOUT11
CLKOUT12
CLKOUT12
SCLKOUT13
SPI
ALARM GENERATION
DEVICE
CONTROL
BGA LDO LDO LDO LDO LDO LDO
BYP1 BYP2 BYP3 BYP4 BYP5 BYP6 BYP7
SDATA SCLK SLEN
GPIO1 GPIO2 GPIO3 GPIO4
SYNC RESET
Rev. B | Page 24 of 72
CLKOUT8
ANALOG
DELAY
LDOs
Figure 35. Top Level Diagram
SYNC
RFSYNCIN/
RFSYNCIN
FUNDAMENTAL MODE
FUNDAMENTAL MODE
COARSE
DIGITAL
DELAY
DIVIDER
(1 TO 4094)
FIN/FIN
GPI
SPI
TO LEAF DIVIDERS
CYCLE
SLIP/
SYNC
FUNDAMENTAL MODE
COARSE
DIGITAL
DELAY
DIVIDER EXT VCO
÷1, ÷2
CYCLE
SLIP/
SYNC
FUNDAMENTAL MODE
COARSE
DIGITAL
DELAY
VCO
MUX
SCLKOUT13
13033-032
CLK DISTRIBUTION PATH
CLKOUT0
PARTIALLY
INTEGRATED INTERNAL
LOOP
VCO
FILTER
×2
OSCINBUF
OSCIN
CLKOUT0
VCO1 ~ 2500MHz
VCO2 ~ 3000MHz
CPOUT1
Data Sheet
HMC7044
DUAL PLL OVERVIEW
The HMC7044 uses a cascade of two PLLs, referred to as a dual
loop topology. The term dual loop sometimes refers to other
architectures as well; therefore, always refer to the block diagram
shown in Figure 35 to remove any ambiguity. In this architecture,
the first PLL (PLL1) normally operates as a jitter attenuator. PLL1
locks a clean local VCXO to a relatively noisy reference using a
very narrow loop bandwidth. The loop bandwidth preserves the
average frequency of the reference signal (which is normally
correct), while rejecting the majority of its noise. The second
PLL takes this low noise VCXO and multiplies it up to the VCO
frequency (in the 2 GHz to 3 GHz range) with very little additive
noise. The architecture provides the benefits of an output frequency
locked to an input reference signal, while being insensitive to its
noise profile.
In ICs such as the HMC7044, the VCO is then connected to an
array of output channels, each with an optional RF divider and
phase control. The key feature that distinguishes an IC with
JESD204B support is the ability to ensure that all of the outputs
with their associated dividers have a user defined phase relationship
each and every time, regardless of process, voltage, or temperature.
This ability is necessary to support the JESD204B SERDES
standard for data converters, but it is also an immensely useful
feature in other applications as well, in all forms of arrayed systems
and in many test and measurement scenarios.
COMPONENT BLOCKS—INPUT PLL (PLL1)
PLL1 General Description (Jitter Attenuator)
A variety of local clocks, particularly in synchronous networks,
derive their timing from a remote node in the network. These
reference signals can arrive via a GPS or clock data recovery
(CDR) receiver, or from a variety of other sources. Often, these
derived references are relatively poor quality, in terms of spurious
content, noise, and reliability.
The function of PLL1 is to lock a clean VCXO to the average
frequency of one of these references and feed it to PLL2 to
generate a high quality clock for local use.
In addition, PLL1 monitors its active reference for failure and
smoothly takes appropriate action, switching to a redundant
reference or going into holdover as appropriate. Figure 36 shows
the architecture of PLL1 with a typical frequency configuration.
Jitter Attenuation
For the purpose of jitter attenuation, PLL1 consists of all the
usual components in a PLL: a phase/frequency detector (PFD1),
charge pump (CP1), reference divider (R1), and feedback
divider (N1). The loop filter is external to provide maximum
flexibility, and the loop bandwidth (BW) is normally configured
very narrow (20 Hz to 500 Hz) to filter any jitter and spurious
tones coming in from relatively poor references.
The noise profile of PLL1 is typically dependent on the loop
bandwidth, input reference noise, and the VCXO characteristic.
The inherent noise sources of PLL1 (the PFD, dividers, and
charge pump) are not normally observable in an application,
and are significantly more relaxed compared with PLL2.
Note that the loop filter components on the board are typically
configured to produce a certain loop bandwidth, given a fixed
PFD rate, charge pump current, and VCXO characteristic.
Adjusting any of these parameters from their nominal positions
affects the loop dynamics, which can be to the advantage of the
user (for example, to scale loop BW with charge pump current),
but it must not be performed without an analysis of the stability
of the loop. Analog Devices, Inc., provides a variety of software
tools to design the loop filter and model the effects of any
change in parameters. Contact Analog Devices for the latest
recommendation.
The lock time of PLL1 typically takes the longest duration in the
clock network, and, aside from any nonlinear slewing, takes
approximately 5/PLL1_BW (for example, 5 ms for a 1 kHz loop
BW). Fortunately, there are no requirements that PLL1 must be
locked before proceeding with PLL2, output calibration, and
phasing, which normally allows system configuration to
continue in parallel while PLL1 is settling.
Rev. B | Page 25 of 72
HMC7044
Data Sheet
LOCKDET
CYCLESLIP
FORCE
VTUNE
PLL1
FSM
FORCE VTUNE
MAINTAIN_HOLDOVER
LOS
DAC
ADC/DAC
CONTROL
RESET
61.44MHz
COMPARATOR
122.88MHz
61.44MHz
38.4MHz
9.76MHz
UP
÷R1
RST
SET
0
LCM
DIVIDERS
PFD1
D Q
TO FSMI LOCKDET
PHASE
ERROR
>~4ns?
TRISTATE
LOCKDET
MAINTAIN
HOLDOVER
RST
DOWN
CP1
LOOP
FILTER
÷N1
VCXO
122.88MHz
TO PLL2
13033-033
CYCLE SLIP
DETECTED
(TO PLL1 FSM)
Figure 36. PLL1 Architecture with a Typical Frequency Configuration
Lock Detect
The lock detect circuit in both PLL1 and PLL2 function the
same way. They count the number of consecutive clock cycles in
which the phase error at the PFD is below a threshold. Any phase
error above this threshold resets the counter, and the count is
restarted. When the count reaches its programmed limit, the
lock detect signal is issued and the clock of the counter is gated
off to reduce power/coupling until a large phase error restarts
the process.
Although the PLL2 loop BW is relatively well defined, the PLL1
loop BW can vary widely in any given application. The SPI word,
PLL1 Lock Detect Timer[4:0] in Register 0x0028, configures the
PLL1 lock detect timer and looks for 2PLL1 Lock Detect Timer[4:0]
consecutive LCM clock cycles with a phase-error <~4 ns to
issue the lock detect. Because the loop BW of PLL1 can vary
drastically depending on the application, the user must set up
the threshold such that 2PLL1 Lock Detect Timer[4:0] LCM periods is on
the order of 2× to 4× the loop time constant. For example, for
fLCM = 61.44 MHz, and a loop BW of 200 Hz, set PLL1 Lock Detect
Timer[4:0] = 19 or 20. If the value is set much higher, the lock
detect circuit takes an unnecessary length of time to indicate
lock after the phases stabilize. If the value is set much lower (for
example, much less than a loop time constant), it can improperly
indicate lock during acquisition, which can cause the PLL1
finite state machine (FSM) to improperly fall in and out of
holdover mode.
Holdover/Reference Switching Overview
When switching between redundant references, or when all
references are gone and the PLL1 is left open loop, there are
often requirements to prevent frequency deviations that can
cause downstream circuits and traffic links to overrun FIFOs
and/or lose lock themselves.
PLL1 can operate in manual or automode (via the automode
reference switching bit). In manual mode, the user selects the
active reference using Manual Mode Reference Switching[1:0]
in Register 0x0029 and determines whether to go into holdover
(via the force holdover bit). In automode, the PLL1 FSM uses
the loss of signal (LOS) information, phase error data, lock
detect, and configuration data from the SPI to determine how
to handle reference interruptions. In either mode, all status
indicators are available, but PLL1 only takes evasive action in
automode. Figure 37 shows a simplified state diagram of the
PLL1 FSM.
During reset, PLL1 is held in the initialization (INIT) state. When
reset is deasserted, during the preload state, the enabled reference
paths, the reference priority table, and LOS indicators are examined
to select the best reference, and, on the next cycle, it attempts to
lock. After the requisite number of counts has elapsed with low
phase error, lock detect is asserted and PLL1 transitions to the
locked state. When PLL1 is locked, a loss of lock, LOS on the active
reference, or a reference switch event initiated by a priority clash
transitions the FSM to enter holdover, where it tristates the CP and
potentially forces VTUNE with the holdover DAC. When a stable
clock is available and other optional conditions are met, the FSM
exits holdover. Exiting holdover is handled in one of a few different
ways, designed to minimize phase/frequency hits during the
transition. Figure 37 shows a simplification of the PLL1 FSM. In
the actual implementation, the holdover state is broken into a
number of subsections corresponding to holdover entry, stable
holdover conditions, and holdover exit. The state of the PLL1
FSM is always available for a read via the SPI (PLL1 FSM State[2:0]
bits in Register 0x0082).
Rev. B | Page 26 of 72
Data Sheet
HMC7044
RESET
PLL1 LOS Detection
The HMC7044 checks the validity of a reference by comparing
its approximate frequency vs. the VCXO. The HMC7044 supports
references at different frequencies. The first step is to divide the
available references and the VCXO to the lowest common multiple
frequency (fLCM). These divider settings are available via the SPI
control bits (CLKINx/CLKINx Input Prescaler[7:0] and OSCIN/
OSCIN Input Prescaler[7:0]). In the example shown in Figure 36,
fLCM = 61.44 MHz. The VCXO derived clock at fLCM is the main
clock to the PLL1 FSM controlling the FSM, lock detect timer,
and ADC/DAC filtering and holdover circuits. Although not
required, using the VCXO clock allows the LOS detection and
PLL1 FSM to operate at a higher rate than the PFD, allowing it to
recognize a reference failure early and enter holdover, sometimes
before a failing reference that has started to drift in either phase
or frequency (or both) can influence the PFD or CP.
INIT
PRELOAD
LOCKING
LOCKDET
LOCKED
NOT LOCKDET
REVERTIVE
AND HIGHER PRIORITY
CLOCK IS AVAILABLE
LOS ACTIVE REF
HOLDOVER
13033-034
AT LEAST ONE REFERENCE OK AND BEST
AVAILABLE REFERENCE IS SELECTED
[AND PHASES CROSSED ZERO (OPTIONAL)]
[AND DAC ASSISTED RELEASE COMPLETE (OPTIONAL)]
OR
JUST ENTERED HOLDOVER (<HOLDOFF TIMER[7:0])
AND PREVIOUS CLOCK RECOVERS
[AND DAC ASSISTED RELEASE COMPLETE (OPTIONAL)]
The dividers in the LOS block, and to some extent, R1, pose a
few challenges. The input frequencies are up to 800 MHz, with a
wide divider range. Furthermore, they are designed to tolerate
glitchy clocks without catastrophic results, because a reset phase
is not always available after an issue is detected.
Figure 37. PLL1 FSM Simplified State Diagram—
Autorevertive Reference Switching = 1
PLL1 Reference Inputs
PLL1 accepts up to four candidate references on CLKIN3/CLKIN3
to CLKIN0/CLKIN0. If all references appear valid, according to
the LOS, PLL1 uses a reference priority table to select the best
candidate. Using the PLL1 reference priority control bits, program
the highest priority clock (CLKIN0/CLKIN0, CLKIN1/CLKIN2,
CLKIN2/CLKIN2, or CLKIN3/CLKIN3), and then second
priority clock, and so on. It is not necessary to include unused
reference inputs in the reference priority table. Instead, specify
the same useful clock in multiple positions. In automode, reference
switching occurs in the preload state (see Figure 37) as PLL1
exits reset, or while PLL1 is in the holdover state.
The reference clock input pins (Pin 36, Pin 37, Pin 39, Pin 40,
Pin 42, and Pin 43) have dual functions; therefore, SPI configuration is important for proper functionality. See the PLL1
Programming Considerations section for more information
about the relevant control bits, and the Reference Buffer Details
section for interface recommendations.
When a reference fails, the sourcing circuit recognizes a fault
and disables either the clock or the buffer driving the signal to
the HMC7044. For this reason, hysteresis in the input buffers
prevents internal toggling for signal swings <~75 mV p-p
differential, which allows further elements in the PLL1 architecture
to cleanly recognize the interruption and prevent unwanted
transients in the frequency.
When all the references are divided to the same frequency, they
are compared relative to the VCXO derived path, and thus each
other. This comparison is performed by a circuit that looks for
three edges of a clock within one period of the other. If it appears
that a reference signal is too slow, its LOS flag is asserted and, in
automode, PLL1 uses this information to disqualify and/or
abandon a reference. Conversely, if it appears that the VCXO is
too slow according to any of the active references, a warning is
generated (available as one of the configurable options for the
GPO, or readable on the SPI) but no automated action occurs.
The HMC7044 monitors reference signals for three edges of a clock
within one period of the other, instead of the more intuitive two
edges, to avoid false LOS flags as clocks that are slightly out of
frequency cross each other in phase in the presence of interference,
noise, and circuit offsets. The result is that the LOS triggers when
the failing reference clock frequency is approximately an octave
from the intended frequency.
After a reference signal returns and its frequency is within an
octave of the VCXO, two to three cycles of the LOS validation
timer must expire before the LOS flag is deasserted and the
reference is considered for potential use. The LOS validation
timer is programmable between 0 LCM cycles (no hysteresis),
and 64 LCM cycles via LOS Validation Timer[2:0] in
Register 0x0015, Bits[2:0].
Rev. B | Page 27 of 72
HMC7044
Data Sheet
PLL1 Holdover Entry Shortcut
The recommended methods are as follows:
When a reference fails, the LOS circuit takes a number of LCM
clock cycles to recognize the problem and to request the PLL1
FSM enter holdover and tristate the CP. By that time, if one of
the missing edges is needed to trigger the R divider output, the
PFD and CP have already saturated, pulling current out of the
loop filter for these cycles, and disturbing the holdover frequency.
The probability of this happening decreases as the PFD rate
decreases relative to fLCM, but it is not eliminated. The HMC7044
includes a unique feature to prevent this type of frequency
runaway.
•
When in the holdover state, the user has the following two
options:
•
•
Tristate the CP
Tristate the CP and engage the holdover DAC
When in tristate mode, the HMC7044 has a very high
impedance charge pump output (~10 GΩ). This output is
normally an insignificant contributor to PLL1 VTUNE leakage,
which is determined primarily by the on-board loop filter
components and the VCXO tuning port. This mode allows the
tuning voltage to maintain itself for significant periods while in
holdover.
To accommodate indefinite periods in holdover, or to ensure
VTUNE is driven and not susceptible to drift, the second option
(set via the holdover uses DAC bit in Register 0x0029, Bit 2)
forces the VTUNE voltage to its time averaged value, obtained by
low-pass filtering the ADC value while the PLL is reporting
lock. The holdover sensing ADC and the driving DAC are seven
bits each, and have an LSB of approximately 19 mV.
PLL1 Holdover Exit
The transition out of holdover can happen in three ways and is
controlled by the Holdover Exit Criteria[1:0] bits and the Holdover
Exit Action[1:0] bits in Register 0x0016 (see the Control Register
Map Bit Descriptions section for details), which describes the
steps that the FSM takes as the HMC7044 exits holdover and
acquires lock.
•
Wait for Zero Phase Error
While the CP is still in tristate, the FSM monitors the PDF for a
cycle slip indication as the candidate reference and VCXO signal
cross each other. The crossing of the reference and VCXO phases
eventually occurs but can take a long time, as determined by the
inherent frequency error due to an imperfect holdover. Just after a
cycle slip event, the phase error at the PFD is at its minimum
value, and there is minimal glitch as the PLL reacquires. Figure 38
shows an example where the reference is removed and PLL1
goes into tristate-based holdover. After approximately 7 sec, the
reference is restored and, about a second later, the phases cross
and the PLL reacquires, all with less than 0.15 ppm of deviation
from the original frequency value.
1.0
0.8
0.6
0.4
TRISTATE HOLDOVER MODE ≈ 8 SECONDS
0.2
0
–0.2
ENABLE REFERENCE AND LOCK
–0.4
–0.6
13033-035
PLL1 Holdover Steady State
•
FREQUENCY DEVIATION FROM NOMINAL (ppm)
A sensor watches the up/down pulses from the PFD (see
Figure 35). When locked, the pulse width is small, based on any
small signal error, PFD/CP offset, and the reset delay of the PFD. If
the device is in the locked state and has a phase error that is larger
than expected (~4 ns), it is a sign that the reference has failed, and
the device immediately tristates the pump, reducing the amount
of time charge can be extracted from the loop from about five
LCM cycles (162 ns at 30.72 MHz) to <4 ns. This error indication
also invalidates the lock detect. When the FSM acknowledges
the issue, it holds the CP in tristate. When using the optional
DAC-based holdover, the FSM instructs the ADC/DAC that is
tracking the VTUNE voltage to switch from sense mode to force
mode, holding it steady to within 1 LSB (about 20 mV or 0.4 ppm)
until the HMC7044 senses a stable reference and transitions out
of holdover.
Wait for zero phase error (no divider reset): wait for LOS =
0 and low phase error at PFD (Holdover Exit Criteria[1:0] = 1,
Holdover Exit Action[1:0] = 1)
Resetting the dividers: wait for LOS = 0 and reset the
R1/N2 dividers (Holdover Exit Criteria[1:0] = 0, Holdover
Exit Action[1:0] = 0)
DAC assisted release: wait for LOS = 0, reset R1/N2, and
configure for DAC assisted release (Holdover Exit
Criteria[1:0] = 0, Holdover Exit Action[1:0] = 3)
–0.8
–1.0
0
1
2
3
4
5
6
TIME (Seconds)
7
8
9
10
Figure 38. Frequency Deviation from Nominal vs. Time of Tristate Holdover
Entry and Exit When the Phases Cross Zero
This first method of uncontrolled release suffers from an
indeterminate amount of time for the phases to cross and exit
holdover. However, if it takes 1 sec for the phases to cross, the
frequencies are off by only 1 Hz. If it takes 10 sec to cross, the
error is 0.1 Hz. If the error is so low that it takes a long time to
exit holdover, the device is effectively frequency locked. In some
applications, being open-loop for this long of a duration can be
acceptable, considering the very small frequency errors. Although
this method of holdover exit is very smooth, it can take a very
long time to occur.
Rev. B | Page 28 of 72
Data Sheet
HMC7044
If using tristate-based holdover, the second holdover exit
method is recommended. When a reference appears available
(LOS = 0), the FSM resets the R and N dividers and allows them
to restart immediately. This approach limits the maximum phase
error coming out of holdover to two VCXO cycles (about 8 ns
for typical VCXO frequencies). There is no need to wait an
undetermined amount of time (as in the first method of
uncontrolled release) to initiate the switch.
DAC Assisted Release
If using DAC-based holdover, the DAC and CP can set VTUNE
concurrently as the devices exits holdover. With the DAC output
impedance at a relatively low setting (for example, 5 Ω), the device
resets the dividers as in the second method, and then the CP
attempts to influence VTUNE. The CP fails, with the DAC sinking
the current it is trying to inject into the VTUNE node. Gradually,
the device increases the output impedance of the DAC, and the
CP gains more influence to manipulate VTUNE, pulling the phases
into alignment. Using this DAC assisted CP release method
limits the holdover exit transients to within ~1 ppm.
16
12
DAC RELEASE
8
4
0
–4
–8
–12
–16
–20
–10
0
10
20
30
40
50
TIME (ms)
60
70
80
90
80
90
20
16
20
16
12
DO NOTHING
8
4
0
–4
–8
–12
13033-236
FREQUENCY DEVIATION FROM NOMINAL (ppm)
Figure 40. DAC Assisted Release
Figure 39 to Figure 41 compare the holdover release methods:
resetting the dividers vs. DAC assisted release, and uncontrolled
release (which starts with a phase error of up to one PFD
period) as the device exits holdover and reacquires to a
reference signal.
–16
–20
–10
0
10
20
30
40
50
TIME (ms)
60
70
Figure 41. Wait for Zero Phase Error (No Divider Reset)
12
RESET DIVS
8
PLL1 Programming Considerations
Configuring Reference Inputs for PLL1 vs. Other Uses
4
0
To use the four reference clocks for PLL1, the input buffer must
be enabled and selected as a relevant path for PLL1.
–4
–8
Table 13. Input Buffer and Reference Path Settings
–12
13033-036
FREQUENCY DEVIATION FROM NOMINAL (ppm)
20
13033-136
FREQUENCY DEVIATION FROM NOMINAL (ppm)
Resetting the Dividers
–16
–20
–10
0
10
20
30
40
50
TIME (ms)
60
Figure 39. Resetting the Dividers
70
80
Bit Name
Buffer Enable
90
PLL1 Reference Path
Enable[3:0]
Description
Enable the input buffer (where x = 0,
1, 2, 3, or V for VCXO) via
Register 0x000A to Register 0x000E
Select one of four available reference
paths for PLL1
Because the CLKIN0/RFSYNCIN, CLKIN0/RFSYNCIN,
CLKIN1/FIN, and CLKIN1/FIN pins can be configured for
output network purposes, and the CLKIN2/OSCOUT0 and
CLKIN2/OSCOUT0 pins can function as oscillator outputs, the
SPI bits in Table 14 must be configured accordingly.
Rev. B | Page 29 of 72
HMC7044
Data Sheet
PLL2 has the following features:
Table 14. Reference Clock Input Bit Settings
Bit Name
CLKIN0/CLKIN0 In RF SYNC
Input Mode
CLKIN1/CLKIN1 in External
VCO Input Mode
OSCOUT0/OSCOUT0
Driver Enable
Description
0 = CLKIN0/CLKIN0 does not
function as an RF sync input
0 = CLKIN1/CLKIN1 does not
function as external VCO (FIN//FIN)
1 = OSCOUT0/OSCOUT0 buffer
does not drive CLKIN2/CLKIN2 pins
•
•
•
•
•
•
Lock detect
Frequency doubler
Partially integrated loop filter
VCO selection, external VCO use
VCO calibration
Multichip synchronization via PLL2
Lock Detect
Choosing fPD1
Although PLL1 supports a wide range of PFD frequencies,
there are trade-offs with setting the frequency too high or too
low. A few megahertz is high enough to allow the comparison
frequency to stay at an offset outside of the PLL2 loop BW and
thus suppress any coupling that manages to bypass the PLL1
loop filter.
Choosing fLCM
At a minimum, fLCM must be a common submultiple of all
available references. Typical frequencies include 122.88 MHz,
61.44 MHz, 38.4 MHz, 30.72 MHz, 3.84 MHz, and 1.92 MHz.
This fLCM clock is the main clock for the PLL1 digital logic. This
clock rate also scales the PLL1 lock detect timer speeds/thresholds,
holdover ADC averaging times, and LOS assertion and revalidation
delays. Higher frequencies slightly improve the response times to
reference interruptions, whereas lower frequencies can slightly
reduce current consumption of the device by up to ~10 mA.
Values in the 30 MHz to 70 MHz range are recommended.
Program the PLL1 lock detect timer threshold based on the
PLL1 loop BW and fLCM of the user.
The lock detect function of PLL2 behaves the same way as in
PLL1. It counts the number of consecutive PFD clock cycles
that occur with a low phase error. When it reaches a count of
512, it declares lock. The threshold of 512 is adjustable, but
because the PLL2 loop BW does not vary as much as PLL1, it is
expected that the user never needs to change this threshold.
Frequency Doubler
The user can engage a frequency doubler after the VCXO buffer
and before the reference divider (see Figure 35). The frequency
doubler assumes an approximate 50% input duty cycle, where
any duty cycle distortion can result in a spur, at fPD2/2, suppressed by the PLL2 loop filter. Use of the frequency doubler is
highly recommended to achieve the best spectral performance,
provided the PFD is kept under its 250 MHz frequency limit.
Partially Integrated Loop Filter
Although the large components for the PLL2 loop filter are off
chip, there is a small on-chip resister/capacitor (RC) section
formed with R = 80 Ω and C = 4.7 pF in series. This RC section
forms a higher order pole at ~420 MHz. For practical conditions, this filter segment does not affect the stability of the loop.
There are reserved registers, as described in the Control Register
Map Bit Descriptions section, that must be reprogrammed from
their default values. For example, Register 0x00A5 must be set
from 0x00 to 0x06.
OFF-CHIP
CP
80Ω
VCO
13033-037
4.7pF
COMPONENT BLOCKS—OUTPUT PLL (PLL2)
Figure 42. On-Chip RC Circuit
PLL2 Overview
PLL2 is a very low noise integer PLL designed to multiply the
frequency from the VCXO to the VCO. It typically operates
with a loop BW of 10 kHz to 700 kHz. Use bandwidths on the
lower end of the range to preserve the inherent VCO phase
noise at 800 kHz offset (useful in GSM-based systems), where
bandwidths on the upper end can provide the best integrated
phase noise/jitter values.
Figure 43 shows the VCO input network. Depending on the
frequency band of interest (2.5 GHz or 3.0 GHz), the user must
specify which VCO to enable via the VCO Selection[1:0] SPI
word. To use the CLKIN1/FIN pin as an external VCO signal,
program this word to 0, and set the CLKIN1/CLKIN1 in external
VCO input mode bit.
Internally, PLL2 has a number of features that allow it to
efficiently achieve a Banerjee floor FOM of −232 dBc and a
flicker FOM of −266 dBc. The combination of the on-board
VCO, an internal VCXO doubler, a low N2 minimum divide
ratio, and the ability to clock the PFD at up to 250 MHz results
in an integrated jitter (at 12 kHz to 20 MHz) of 44.0 fs typical.
Rev. B | Page 30 of 72
Data Sheet
HMC7044
VCO Selection, External VCO Use
~2.5GHz
VCO
AUTOCAL
~3.0GHz
VCO
Apply the SYNC input rising edge only once. After sensing the
rising edge on the VCXO domain, the SYNC input is ignored
for the next 16 × 6 tPD2 periods as the FSM processes the event.
After this period expires, the FSM becomes sensitive again to
the SYNC pin. If the SYNC is applied periodically, the first edge
initializes the synchronization process, and then the subsequent
edges may or may not be recognized depending on their
width/repetition rate with respect to 16 × 6 tPD2.
VCO ENABLE[1:0] = 10
TO PLL2
N2 DIVIDER
VCO ENABLE[1:0] = 01
TO
OUTPUT
NETWORK
CLKIN1/CLKIN1
IN EXTERNAL VCO
INPUT MODE = 1
DIVIDE BY 2 ON
EXTERNAL VCO ENABLE
13033-038
÷2
Figure 43. VCO Input Network
VCO Calibration
The on-board VCOs contain an AGC loop that regulates the
core voltage of the oscillator to achieve the desired swing and
thus the trade-off between phase-noise and power consumption. This AGC loop uses large external bypass capacitors to
eliminate the noise impact of the AGC loop, and therefore takes
time to settle after power-up, sleep, or after changing the VCO
Selection[1:0] setting. With the 100 nF/1 μF configuration,
settling time takes approximately 10 ms (typical).
Each of the VCOs in the HMC7044 has 32 frequency bands.
Normally, three or more subbands can synthesize any particular
frequency, and an on-board autotune algorithm selects the solution
that provides tuning margin for temperature fluctuations. Temperature compensation is applied inside to ensure the device can
be calibrated at any frequency and maintain lock as the frequency is
carried to any other frequency in the operating range.
The autotune is triggered by toggling the restart dividers/FSMs
bit in Register 0x0001, Bit 1, after R2 and N2 are programmed,
the VCXO is applied, and the VCO peak detector loop has settled.
When the VCXO is applied to the system and the R2 and N2
divide ratios are programmed, the autotune algorithm has the
information needed to find the appropriate band of the VCO.
Multichip Synchronization via PLL2
Note that the SYNC rising edge must be provided cleanly with
respect to the HMC7044 VCXO input pin (OSCIN/OSCIN).
The user normally has access to the CLKINx/CLKINx pins of
PLL1, and not to the VCXO signal directly. When PLL1 is locked,
however, the VCXO rising edge is roughly aligned to the PLL1
active reference, and, therefore, the user has indirect knowledge
of the phase of the VCXO. The VCXO is also available as an
output of the HMC7044, if the user wants to retime the SYNC
signal more directly.
The phase offset of the PLL1 active reference with respect to the
VCXO is a function of the internal delay of each path. This base
delay offset is a function of deterministic conditions (LCM, R1,
N1 divider setpoints, termination setups, and slew rates), but is also
subject to PVT variations that compress or exaggerate this offset.
For most practical purposes, the multichip synchronization
feature is limited to PLL1 reference rates <200 MHz.
CLOCK OUTPUT NETWORK
In the HMC7044, PLL1 is responsible for frequency cleanup,
redundancy, and hitless switching. PLL2 and the VCOs handle
integrated jitter and performance at an 800 kHz offset. Although
the PLL1/PLL2 and VCXO components are important, much of
the uniqueness of a JESD204B clock generation chip relates to
its array of output channels.
In a device such as the HMC7044, some of the output network
requirements include the following:
•
•
•
•
•
To synchronize multiple HMC7044 devices together, it is recommended to use the SYNC input pin. If the SYNC pin transitions
from 0 to 1 with sufficient setup/hold margin with respect to the
VCXO, this synchronization event is deterministically carried
through PLL2, up the timing chain through the N2 divider, and
then to the master SYSREF timer (see the Clock Output Network
section for more information). This mechanism of deterministic
phase adjustment allows synchronization of the SYSREF timer
and output phases of multiple HMC7044 devices.
•
•
Rev. B | Page 31 of 72
Very good phase noise floor of the DCLK channels that can
be connected to critical data converter sample clock inputs
A large number of DCLK and SYSREF channels
Deterministic phase alignment between all output channels
relative to one another
Fine phase control of synchronization channels with
respect to the DCLK channel
Frequency coverage to satisfy typical clock rates in
expectant systems
Skew between SYSREF and DCLK channels that is much
less than a DCLK period
Spur and crosstalk performance that does not impact
system budgets
HMC7044
Data Sheet
Each of the 14 output channels are logically identical. The only
distinction between the SYSREF and DCLK channels is in the
SPI configuration and in how they are used. Each channel
contains independent dividers, phase adjustment, and analog
delay circuits. This combination provides the ultimate flexibility,
cleanly accommodating nonJESD204B devices in the system.
The HMC7044 output network also supports the following
recommended features, which are sometimes critical in user
applications:
•
•
•
•
•
•
•
•
Deterministic synchronization of the output channels with
respect to an external signal, which allows multichip
synchronization and clean expansion to larger systems
Pulse generator behavior to temporarily generate a
synchronization pulse stream at user request
Flexibility to define unused JESD204B SYSREF and DCLK
channels for other purposes
Glitchless phase control of signals relative to each other
50% duty cycle clocks with odd division ratios
Multimode output buffers with a variety of swings and
termination options
Skew between all channels that is much less than a DCLK
period
Adjustable performance vs. power consumption for less
sensitive clock channels
Flexibility to use an external VCO for very high
performance application requirements
In addition to the 14 output channel dividers, there is an internal
SYSREF timer that continually operates, and the synchronization
of the output channel dividers occurs deterministically with respect
to this timer, which can be rephased externally by the user.
The pulse generator functionality of the JESD204B standard
involves temporarily generating SYSREF output pulses, with
appropriate phasing, to downstream devices. The centralized
SYSREF timer and its associated SYNC/pulse generator control
manage the process of enabling the intended SYSREF channels,
phasing them, and then disabling them for signal integrity and
power saving advantages.
SYSREF INPUT NETWORK
SYNC FROM PLL2 N DIVIDER
(DUE TO SYNC PIN EVENT)
RF SYNC
D Q
RESET
SYSREF
TIMER
VCO PATH
SYNC/
PULSE GENERATOR
CONTROL
PULSE GENERATOR REQUEST (FROM SPI, GPI, OR SYNC PIN)
SYNC REQUEST (FROM SPI OR GPI)
SYNC_FSM_STATE
OUTPUT CHANNEL × 14
LEAF
CONTROLLER
CLOCK
GATING
DIVIDER
DIGITAL DELAY
AND RETIME
13033-039
•
Figure 44. Clock Output Network Simplified Diagram
Rev. B | Page 32 of 72
Data Sheet
HMC7044
Basic Output Divider Channel
Each of the 14 output channels are logically identical, and support
divide ratios from 1 to 4094. The supported odd divide ratios
(1, 3, 5) have 50.0% duty cycle. The only distinction between a
SYSREF channel and a DCLK channel is in the SPI configuration and the typical usage of a given channel.
For basic functionality and phase control, each output path
consists of the following:
•
•
•
•
•
•
Divider—generates the logic signal of the appropriate
frequency and phase
Digital phase adjust—adjusts the phase of each channel in
increments of ½ VCO cycles
Retimer—a low noise flip flop to retime the channel,
removing any accumulated jitter
Analog fine delay—provides a number of ~25 ps delay steps
Selection mux—selects the fundamental, divider, or analog
delay, or an alternate path
Multimode output buffer—low noise LVDS, CML, CMOS,
or LVPECL
The digital phase adjuster and retimer launch on either clock
phase of the VCO, depending on the digital phase adjust setpoint
(Coarse Digital Delay[4:0]).
To support divider synchronization, arbitrary phase slips, and
pulse generator modes, the following blocks are included:
•
•
A clock gating stage pauses the clock for synchronization
or slip operations
An output channel leaf (×14) controller manages slip,
synchronization, and pulse generators with information
from the SYSREF FSM
Each channel has an array of control signals. Some of the controls
are described in Table 15.
System wide broadcast signals can be triggered from the SPI or
general-purpose input (GPI) port to issue a SYNC command
(to align dividers to the system internal SYSREF timer), issue a
pulse generator stream, (temporarily exporting SYSREF signals to
receivers), or to cause the dividers to slip a number of VCO
cycles to adjust their phases.
Individual dividers can be made sensitive to these events by
adjusting their slip enable, SYNC enable, and Start-Up Mode[1:0]
configuration, as described in Table 16.
When output buffers are configured in CMOS mode and phase
alignment is required among the outputs, additional multislip
delays must be issued for Channel 0, Channel 3, Channel 5,
Channel 6, Channel 9, Channel 10, and Channel 13. The value
of the delay must be as large as half of the selected divider ratio.
Note that this requirement of having additional multislip delays
is not needed when channels are used in LVPECL, CML or
LVDS mode.
If a channel is configured to behave as a pulse generator, to
temporarily power up and power down according to GPI, SPI,
or SYNC pin pulse generator commands, it has additional
controls to define its behavior outside of the pulse generator
chain (see Table 17).
Each divider has an additional phase offset register that adjusts
its start phase, or to influence the behavior of slip events sent
via the SPI (see Table 18).
Table 19 outlines the typical configuration combinations for a
DCLK channel relative to a SYSREF synchronization channel.
Note that other combinations are possible. Synchronization of
downstream devices can be managed manually, or by using the
pulse generator functionality of the HMC7044. See the Typical
Programming Sequence section for more information about the
differences between the two methods.
Rev. B | Page 33 of 72
HMC7044
Data Sheet
Table 15. Basic Divider Controls
Bit Name
Channel Enable
12-Bit Channel Divider[11:0]
High Performance Mode
Coarse Digital Delay[4:0]
Fine Analog Delay[4:0]
Output Mux Selection[1:0]
Description
Channel enable. If 0, the channel is disabled. If 1, the channel can be enabled depending on the settings of
Start-Up Mode[1:0], Seven Pairs of 14-Channel Outputs Enable[6:0], and sleep mode.
Divide ratio.12-bit divide ratio, split across two words (MSB and LSB). Set to 0 if not using the channel divider
(Output Mux Selection[1:0] = 2 or 3).
High performance mode. Adjusts divider and buffer bias to slightly improve swing/phase noise at the
expense of power. The performance advantage is about 1 dB, and the current penalty depends on whether
the divider is enabled.
Digital delay. Adjusts the phase of the divider signal by up to 17 ½ cycles of the VCO. This circuit is practically
noiseless; however, note that a low amount of additional current is consumed.
Analog delay. Adjusts the delay of the divider signal in increments of ~25 ps. Set Output Mux Selection[1:0] =
1 to expose this channel. Causes phase noise degradation of up to 12 dB; therefore, do not use on noise sensitive
DCLK channels.
Output mux selection. 00 = divider channel, 01 = analog delay, 10 = other channel of pair, 11 = input VCO
clock. Fundamental mode can be generated with the divider (12-Bit Channel Divider[11:0] = 1), or via Output
Mux Selection[1:0] = 10 and 12-Bit Channel Divider[11:0] = 0. Because the divider path consumes power and
degrades phase noise slightly, the fundamental mux path is recommended, but at a cost of a deterministic
skew vs. a path that is divider based. Such skew can be compensated for with delay (digital and analog) on
the divider-based path.
Table 16. Channel Features
Bit Name
Slip Enable
SYNC Enable
Start-Up Mode[1:0]
Description
Slip enable. A channel processes slip requests broadcast from the SPI or GPI (or, if multislip enable = 1, initiated
following a recognized SYNC or pulse generator startup).
SYNC enable. A channel processes synchronization events broadcast from the SPI or GPI or due to SYNC/RF SYNC (via
the SYSREF FSM) to reset its phase. This signal can be safely toggled on and off to adjust SYNC sensitivity without
risking the state of the divider.
00 = asynchronous (normal mode). The divider starts with uncontrolled phase. It is rephased by SYNC events if SYNC
enable = 1.
11 = dynamic (pulse generator mode). The divider monitors pulse generator events broadcast from the SYSREF
controller. It is powered up just before a pulse generator chain, rephased at the start, and powered down after the
pulse generator chain. This is only supported for divide ratios > 31.
Table 17. Pulse Generator Mode Behavior Options
Bit Name
Dynamic Driver Enable
Force Mute[1:0]
Description
Dynamic output buffer enable (pulse generator mode only).
0 = the output buffer is simply enabled/disabled with the main channel enable.
1 = the output buffer enable is controlled together with the channel divider, which allows it to dynamically power
down outside pulse generator events.
Force mute for dynamic mode. If 10, and the channel enable is true (channel enable = 1), the signal just before the
output buffer is asynchronously forced to Logic 0 when not generating pulses. Otherwise, if 00, outputs are forced
to float naturally to VCM. To see the effect of this, the output buffer must be enabled, which is dependent on the
dynamic driver enable and Start-Up Mode[1:0] controls. Logic 0 is supported for CML, LVPECL and CMOS driver modes.
Rev. B | Page 34 of 72
Data Sheet
HMC7044
Table 18. Multislip Configuration
Bit Name
Multislip Enable
12-Bit Multislip Digital
Delay[11:0]
Description
Allow multislip. This bit determines whether the 12-Bit Multislip Digital Delay[11:0] parameter is used for multislip
operations. Note that a multislip operation is automatically started following a SYNC or pulse generator initiation if
multislip enable = 1.
Multislip amount. If multislip enable = 1, any slip events (caused by GPI, SPI, SYNC, or pulse generator events) repeat the
number of times set by 12-Bit Multislip Digital Delay[11:0] to adjust the phase by the multislip amount × VCO cycles. A
value of 0 is not supported if multislip enable = 1. Note that phase slips are free from a noise and current perspective,
that is, no additional power is needed and with no noise degradation, but they take some time to occur. Each slip
operation takes a number of nanoseconds to complete, and thus the phases do not necessarily stabilize immediately. An
alarm is available for the user to indicate when all phase operations are complete.
Table 19. Typical Configuration Combinations
Bit Name
12-Bit Channel Divider[11:0]
Start-Up Mode Bit
Fine Analog Delay[4:0]
Coarse Digital Delay[4:0]
Slip Enable
Multislip Enable
High Performance Mode
Sync Enable
Dynamic Driver Enable
Force Mute[1:0]
Pulse Generator
SYSREF
Big
Pulse generator
Optional
Optional
Optional
Off
Off
On
On
On
DCLK
Small
Normal
Off
Optional
Optional
Optional
Optional
On
Don’t care
Don’t care
Synchronization FSM/Pulse Generator Timing
Manual SYSREF
Big
Normal
Optional
Optional
Optional
Optional
Off
On
Don’t care
Don’t care
NonJESD204B
Any
Normal
Off
Optional
Optional
Optional
Optional
Optional
Don’t care
Don’t care
Figure 46 shows the start-up behavior of an example divider
that is configured as a pulse generator, with a period matching
the internal SYSREF period.
The block diagram showing the interface of the SYNC/pulse
generator control to the divider channels and the internal
SYSREF timer is shown in Figure 44.
The SYSREF timer counts in periods defined by SYSREF
Timer[11:0], a 12-bit setting from the SPI. It sequences the enable,
reset, and startup, and disables the downstream dividers in the
event of SYNC or pulse generator requests. Program the SYSREF
timer count to a submultiple of the lowest output frequency in
the clock network, and not faster than 4 MHz. To synchronize
divider channels, it is recommended, though not required, that
the SYSREF Timer[11:0] bits be set to a related frequency that is
either a factor or multiple of other frequencies on the IC.
The pulse generator is defined with respect to the periods of
this SYSREF timer, not with respect to the output period. This
leads to timing constraint that must be considered to prevent
any runt pulses from affecting the pulse generator stream.
The startup of the pulse stream occurs a fixed number of VCO
cycles after the FSM transitions to the start phase. Disabling the
pulse generator stream where the logic path is forced to zero
comes from a combinational path, directly from the FSM.
Because the divider has the option for nearly arbitrary phase
adjustment, it provides the opportunity for the stop condition
to arrive when the pulse stream is a Logic 1, and creates a runt
pulse.
For phase offsets of zero to 50% − 8 VCO cycles, and VCO
frequencies <3 GHz, this condition is met naturally within the
design. For fanout only mode >3 GHz, it is recommended to
use digital delay or slip offsets to increase the natural phase
offset and avoid the stress condition.
The situation is avoided by never applying phase offset more
than 50% − 8 VCO cycles to an output channel configured as a
pulse generator.
Rev. B | Page 35 of 72
HMC7044
Data Sheet
RF_SYNC OR PLL2 SYNC
RESET
PULSE
GENERATOR
SETUP
NOTIFY CHANNEL FSM
WHAT TYPE OF EVENT
IS COMING
POWER DIVIDERS/SYNC BLOCKS,
PAUSE BLOCKS, RESET LATCHES
CLEAR
REMOVE LATCH RESET,
PREPARE TO START CLOCKS
WAIT
SYNC
REQUEST
START CLOCKS,
WITH CLEAN TIMING,
SMALL PIPELINE DELAY
STARTUP
PULSE
GENERATOR
TIMEOUT?
WAIT UNTIL THE NUMBER OF
PULSE GENERATOR CYCLES
EXPIRES
DONE
REMOVE POWER
13033-041
SYNC
SETUP
PULSE
GENERATOR
REQUEST
Figure 45. Synchronization FSM Flowchart
FSM STATE
STARTUP
PULSE GENERATOR = 2
DONE
DIVIDER CHANNEL
FIXED NUMBER OF VCO CYCLES
FROM STATE CHANGE TO STARTUP, AND
ANY INTENTIONAL DIGITAL/ANALOG OFFSET
FSM STATE
STARTUP
IF MUTE SIGNAL ARRIVES QUICKLY
RELATIVE TO SIGNAL TRAIN,
NO RUNT PULSE
PULSE GENERATOR = 2
DONE
IF CONTROL IS TOO LATE
RELATIVE TO SIGNAL TRAIN,
THERE IS A RUNT PULSE
13033-042
DIVIDER CHANNEL
Figure 46. Start-Up Behavior of an Example Divider Configured as a Pulse Generator
Clock Grouping, Skew, and Crosstalk
Although the output channels are logically independent, for
physical reasons, they are first grouped into pairs called clock
groups. Each clock group shares a reference, an input buffer,
and a sync retime flip flop originating from the VCO
distribution network.
The second level of grouping is according to the supply pin.
Clock Group 1 (Channel 2 and Channel 3) are on an independent supply, and the other supply pins are each responsible for
two clock groups.
As the output channels are more tightly coupled (by sharing a
clock group, or by sharing a supply pin), the skew is minimized.
However, the isolation between those channels suffers. Table 20
shows the clock grouping, and Table 21 show the typical skew
and isolation that can be expected and how it scales with distance
between output channels.
Isolation improves as either the aggressor or affected frequencies
decreases. Nevertheless, for particularly important clock channels
where spurious tones must be minimized, carefully consider
their frequency and channel configurations to isolate continuously running frequencies onto different supply domains.
Channels configured as pulse generators are normally not an
issue, because they are disabled during normal operation.
Rev. B | Page 36 of 72
Data Sheet
HMC7044
Northwest
6
Typical
Skew (ps)
±20
±15
1 GHz Isolation
Differential (dB)
90 to 100
70
±10
±10
60
45
Output Buffer Details
Figure 47 shows the clock groups by supply pin location on the
package. With appropriate supply pin bypassing, spurious noise
of the outputs is improved. Table 20 describes how the supply
pins of each of the 14 clock channels are connected within the
seven clock groups. Clock channels that are closest to each
other have the best channel to channel skew performance, but
they also have the lowest isolation from each other. Select
critical signals that require high isolation from each other from
groups with distant supply pin locations. An example of the
expected isolation and channel to channel skew performance of
the HMC7044 at 1 GHz is provided in Table 21.
GPIO2
CLKOUT8,
CLKOUT8
SCLKOUT9,
SCLKOUT9
VCC8_OUT
CLKOUT10,
CLKOUT10
SCLKOUT11,
SCLKOUT11
VCC1_VCO
CLKIN2/OSCOUT0,
CLKIN2/OSCOUT0
LDOBYP4
VCC6_OSCOUT
LDOBYP5
CLKIN0/RFSYNCIN,
CLKIN0/RFSYNCIN
SCLKOUT3,
SCLKOUT3
CLKOUT2,
CLKOUT2
VCC2_OUT
Table 21. Typical Skew and Isolation vs. Distance
Distance
Distant Supply Group
Closest Neighbor on
Different Supply Group
Shared Supply
Same Clock Group
GPIO3,
GPIO4
OSCOUT1,
OSCOUT1
VCC5_PLL1
CLKIN1/FIN,
CLKIN1/FIN
SPI
0
LDOBYB3
SOUTH
SOUTHWEST
13033-043
VCC9_OUT
LDOBYP6
LDOBYP2
CLKIN3,
CLKIN3
5
OSCIN, OSCIN
BGABYP1
CPOUT1
4
RESET AND SYNC
GPIO1
North
CPOUT2
LDOBYP7
SCLKOUT7,
SCLKOUT7
VCC8_OUT
VCC7_PLL2
CLKOUT6,
CLKOUT6
3
CLKOUT0,
CLKOUT0
SCLKOUT1,
SCLKOUT1
VCC4_OUT (CH4,
CH5, CH6, CH7
2
CLKOUT4,
CLKOUT4
South
SCLKOUT5,
SCLKOUT5
VCC4_OUT
Channel
2
3
4
5
6
7
8
9
10
11
12
13
0
1
VCC9_OUT
Clock Group
1
CLKOUT12,
CLKOUT12
SCLKOUT13,
SCLKOUT13
Location
Southwest
VCC3
SYSREF
Supply Pin
VCC2_OUT
NORTH
NORTHWEST
Table 20. Supply Pin Clock Grouping by Location
Figure 47. Clock Grouping
SYSREF Valid Interrupt
One of the challenges in a JESD204B system is to control and
minimize the latency from the primary system controller IC,
typically an ASIC or FPGA, to the data converters. To estimate
the correct amount of latency in the system, the designer must
know how long it takes for a master clock generator like the
HMC7044 to provide the correct output phases at each output
channel after receiving the synchronization request. Typically, a
period of time is required on the device to implement the
change requests on the outputs due to internal state machine
cycles, data transfers, and any propagation delays. The SYSREF
valid interrupt is a function to notify the user that the correct
output settings and phase relationships are established, allowing
the user to identify quickly that the desired SYSREF and device
clock states are presented at the outputs of the HMC7044.
The user has the flexibility to assign the SYSREF valid interrupt
to a GPO pin or to use a software flag, set via Register 0x007D,
Bit 2, which the user can poll as necessary. The flag notifies the
user when the system is configured and operating in the desired
state, or conversely when it is not ready.
Rev. B | Page 37 of 72
HMC7044
Data Sheet
REFERENCE BUFFER DETAILS
Single-Ended Operation
Input Termination Network—Common for All Input
Buffers
The buffers support single-ended signals with a slightly reduced
input sensitivity and bandwidth. If driving these buffers singleended, ac couple the unused section of the buffer to ground at
the input of the die.
The four reference input buffers to PLL1, as well as the VCXO
input buffer, share similar architecture and control features. The
input termination network is configurable to 100 Ω, 200 Ω, and
2 kΩ differentially. It is typically ac-coupled on the board, and
uses the on-chip resistive divider to set the internal commonmode voltage, VCM, to 2.1 V.
By closing the 50 Ω termination switch (see Figure 48), the
network also serves as the termination system for an LVPECL
driver. Although the input termination network for the four
PLL1 reference buffers and the VCXO input buffer is identical,
the buffer behind the network is different.
2.8V
50Ω,
100Ω,
1kΩ
5kΩ
1pF
50Ω
50Ω,
100Ω,
1kΩ
The internal supplies to these buffers are regulated from 3.3 V
to 2.8 V using on-chip regulation. With very high power
references, the signal swing can be enough to drive the signal
above the 2.8 V rail. The ESD network and parasitic diodes are
generally able to shunt the excess power, and protect the
internal circuits even above 13 dBm. Nevertheless, to protect
from latch-up concerns, the signals on reference inputs must
not exceed the 2.8 V internal supply. For a 2.1 V commonmode, 50 Ω single-ended source, this 2.8 V limit allows
~700 mV of amplitude, or 6 dBm of maximum reference power.
TYPICAL PROGRAMMING SEQUENCE
To initialize the HMC7044 to an operational state, use the
following programming procedure:
1.
13033-045
4kΩ
Maximum Signal Swing Considerations
Figure 48. On-Chip Termination Network for VCXO and Reference Buffers
PLL1 Reference Buffer Stages
The PLL1 reference buffers use a CMOS input stage, are capable
of a wide common-mode input range (0.4 V to 2.4 V), and have
hysteresis to support reliable LOS detection. These buffers are
designed to be driven reliably with an input swing of >375 mV p-p
diff (the half swing point of the LVDS standard), and support up to
800 MHz operation. For signal swings that are below 375 mV p-p
diff, the hysteresis of the buffer can engage and shut down the
signal to the internal reference paths. The exact input hysteresis
threshold varies as a function of common-mode level and input
frequency, but generally ranges from about 75 mV p-p diff to
300 mV p-p diff.
VCXO Buffer Stage
The VCXO input buffer is implemented with a bipolar input
stage to meet the stringent noise requirements of PLL2. Its
common-mode input range is tighter and, if set externally, must
be kept between 1.6 V and 2.4 V. This buffer does not have
hysteresis and is functional down to very low signal levels.
Although the buffer remains functional down to these low
signal levels, for optimal performance, keep the input power
greater than −4 dBm when driven single-ended, or −7 dBm per
side when driven differentially.
Recommendations for Normal Use
For both styles of buffer, unless there are extenuating circumstances in the application, use the 100 Ω differential termination to
control reflections, use the on-chip dc bias network to set the
common-mode level, and externally ac couple the input signals.
Do not use receiver side dc termination of the LVPECL signal.
Connect the HMC7044 to the rated power supplies. No
specific power supply sequencing is necessary.
2. Release the hardware reset by switching from Logic 1 to
Logic 0) when all supplies are stable.
3. Load the configuration updates (provided by Analog
Devices) to specific registers (see Table 74).
4. Program PLL2. Select the VCO range (high or low). Then
program the dividers (R2, N2, and reference doubler).
5. Program PLL1. Set the lock detect timer threshold based
on the PLL1 BW of the user system. Set the LCM, R1, and
N1 divider setpoints. Enable the reference and VCXO
input buffer terminations.
6. Program the SYSREF timer. Set the divide ratio (a submultiple
of the lower output channel frequency). Set the pulse
generator mode configuration, for example, selecting level
sensitive option and the number of pulses desired.
7. Program the output channels. Set the output buffer modes
(for example, LVPECL, CML, and LVDS). Set the divide
ratio, channel start-up mode, coarse/analog delays, and
performance modes.
8. Wait until the VCO peak detector loop has stabilized
(~10 ms after Step 4).
9. Ensure that the references are provided to PLL1 and the
VCXO is powered.
10. Issue a software restart to reset the system and initiate
calibration. Toggle the restart dividers/FSMs bit to 1 and
then back to 0.
11. PLL1 starts to lock in parallel with PLL2 going through its
calibration and lock procedure. Wait for PLL2 to be locked
(takes ~50 μs in typical configurations).
12. Confirm that PLL2 is locked by checking the PLL2 lock
detect bit.
Rev. B | Page 38 of 72
Data Sheet
HMC7044
13. Send a sync request via the SPI (set the reseed request bit)
to align the divider phases and send any initial pulse
generator stream.
14. Wait 6 SYSREF periods (6 × SYSREF Timer[11:0]) to allow
the outputs to phase appropriately (takes ~3 μs in typical
configurations).
15. Confirm that the outputs have all reached their phases by
checking that the clock outputs phases status bit = 1.
16. At this time, initialize any other devices in the system.
PLL1 may not be locked yet, but the small frequency offset
that can result on the output of the HMC7044 is not normally
severe enough to cause synchronization or initialization
failures. Configure slave JESD204B devices in the system to
operate with the SYSREF signal outputs from the HMC7044.
SYSREF channels from the HMC7044 can either be on
asynchronously, or dynamically, and can temporarily turn
on for a pulse generator stream.
17. Wait for PLL1 to lock. This takes ~50 ms for a 100 Hz BW
(from Step 11).
18. When all JESD204B slaves are powered and ready, send a
pulse generator request to send out a pulse generator chain
on any SYSREF channels programmed for pulse generator
mode.
The system is now initialized.
For power savings and the reduction of the crosscoupling of
frequencies on the HMC7044, shut down the SYSREF channels.
1.
2.
Program each JESD204B slave to ignore the SYSREF input
channel.
On the HMC7044, disable the individual channel enable
bits of each SYSREF channel.
To resynchronize one or more of the JESD204B slaves, use the
following procedure:
1.
2.
3.
4.
5.
Set the channel enable (and SYNC enable bit) of the
SYSREF channel of interest.
To prevent an output channel from responding to a sync
request, disable the SYNC enable mask of each channel so
that it continues to run normally without a phase
adjustment.
Issue a reseed request to phase the SYSREF channel
properly with respect to the DCLK.
Enable the JESD204B slave sensitivity to the SYSREF
channel.
If the SYSREF channel is in pulse generator mode, wait at
least 20 SYSREF periods from Step 3, and issue a pulse
generator request.
POWER SUPPLY CONSIDERATIONS
The HMC7044 contains on-board regulators to shield some of
the more sensitive supplies from external noise and interference
as much as possible. Nevertheless, the user must still take
special care to the supply noise profile of the VCC1_VCO
supply to achieve the intended performance of the device.
In general, a flat input noise of 200 nV/Hz is an equivalent
contributor to the VCO noise and causes a 3 dB increase in the
noise profile from about 100 kHz to 10 MHz when the VCO is
the dominant contributor. This increase equates to a roughly
one-to-one conversion from dBV to dBc/Hz at a 1 MHz offset,
and fOUT = 2.457 GHz, that is, 200 nV/Hz = −134 dBV, and the
performance of the VCO at 1 MHz offset at 2.4576 GHz is
~−134 dBc/Hz. The PSRR of the VCO follows its closed-loop
noise profile; therefore, as the offset moves in and the VCO
profile becomes higher, the 200 nV/Hz noise stays approximately
equal to the VCO. To stay suitably below the VCO, a supply
input with <50 nV/Hz is recommended on the VCC1_VCO pin
across the 100 kHz to 10 MHz frequency range.
The output buffers are also susceptible to supply noise, but to a
lesser extent. A noise tone of −60 dBV at a 40 MHz offset results
in a −90 dBc tone at the output of the buffers in CML mode and
−85 dBc in LVPECL mode. This result is a relatively flat frequency
response, and these numbers are measured differentially. Phase
noise/spurs caused by supply noise on the output buffers do not
scale with output frequency, whereas those on the VCO do.
Table 22 lists the supply network of the HMC7044 by pin,
showing the relevant functional blocks. Six different usage
profiles are defined for the network, not including the output
channel supplies, which are accounted for separately.
The values listed under Profile 0 to Profile 5 in Table 22 and
Table 23 are the typical currents of that block or feature. If a
number is not listed in a profile column, a typical profile does
not exist for that block or feature, but the user can mix and
match features outside of the profile list, and can determine what
the power consumption is going to be given the current listings
per feature.
Rev. B | Page 39 of 72
HMC7044
Data Sheet
Table 22. Supply Network of the HMC7044 by Pin for PLL1, PLL2, VCO, and SYSREF
Circuit Block
VCC5_PLL1
CLKIN1/CLKIN1
CLKIN1/CLKIN1 Buffer
CLKIN0/CLKIN0
CLKIN0/CLKIN0 Buffer
External VCO Path (fOUT)
External VCO Path
External RF Synchronization Path 3
Regulator to 1.8 V, Bypassed on LDOBYP2
PLL1 Functions
PLL2 Functions
SYSREF Timer
GPO Drivers in High Speed Mode 4
Regulator to 2.8 V, Bypassed on LDOBYP3
PLL1 PFD/CP
PLL1 DAC Holdover Circuits
CLKIN2/CLKIN2 Buffer
CLKIN3/CLKIN3 Buffer
Subtotal for VCC5_PLL1
VCC7_PLL2
Regulator to 2.8 V, Bypassed on LDOBYP7
PLL2 PFD, Doubler, and R2 and N2
Outputs
PLL2 Charge Pump
Regulator to 2.8 V, Bypassed on LDOBYP6
VCXO Buffer
OSCOUTx/OSCOUTx Divider/Mux 5
Subtotal for VCC7_PLL2
VCC1_VCO
VCO Distribution Network
Sync Retiming Network
VCO Regulator, Bypass to LDOBYP4 and
LDOBYP5
VCO Core
Subtotal for VCC1_VCO
VCC3_SYSREF
SYSREF Input Network3
SYSREF Counter Base
SYSREF Counter, SYNC network
Subtotal for VCC3_SYSREF
Subtotal (Without Output Paths)
1
Profile 1
2
3
4
2
5
2
2
2
5
2
Typical Current
(mA)
Comment
Used as a PLL1 reference
Extra if used as buffer for external
VCO
Used as a PLL1 reference
Extra current if used as RF
synchronization buffer 2
Extra current for divide by 2
N2, digital functions
LOS, R1, N1, FSMs
R2, N2, lock detect
18
10
3
2
10
17
1
2
5
5
2
5
18
2
2
10
17
1
2
10
2
2
2
17
17
2
7
2
2
2
23
21
46
11
2
2
21
2
21
2
2
7
2
2
2
90
2
4
2
7
2
2
2
49
2
21
2
4
2
21
2
8
2
16
2
16
8
2
16
8
2
16
2
8
49
20
49
49
4
71
8
84
8
71
0
71
71
71
163
8
71
71
8
2
16
8
57
Minimum possible value
Minimum possible value 6
0
11
12
4
27
84
155
84
0
155
12
0
20
12
265
12
0
43
0
225
0
166
12
98
Profile 0 = sleep mode; Profile 1 = power-up defaults, PLL1 with four references and PLL2 locked with internal VCO, SYSREF timer running; Profile 2 = PLL1 only, one
reference; Profile 3 = PLL2 + VCO, PLL1 disabled, Profile 4 = PLL2 with external VCO, PLL1 disabled, Profile 5 = fanout mode only, SYSREF running.
2
This is the incremental amount of current for the circuit when put in this mode. For example, the CLKIN0/CLKIN0 buffer used for PLL1 reference path is 2 mA. If it is
used as the external synchronization buffer instead, it is 2 + 5 mA.
3
The transient current in PLL2 synchronization mode can be temporarily enabled when using external synchronization.
4
The current is highly dependent on rate of input/output and load of input/output traces. For heavily loaded traces, it is recommended to use a series resistance of
~100 Ω to minimize the IR drop on the internal regulator during transitions.
5
The function varies from 8 mA to 14 mA depending on divide ratio.
6
A temporary current only.
1
Rev. B | Page 40 of 72
Data Sheet
HMC7044
Table 23. Supply Network of the HMC7044 by Pin for the Clock Output Network
Per Output Channel
Digital Regulator and Other Sources
Buffer
LVPECL
CML100
High Power
Low Power
LVDS
High Power
Low Power
CMOS
Channel Mux
Digital Delay
Off
Setpoint > 1
Analog Delay
Off
Minimum Setting
Maximum Setting
Divider Logic
0
÷1
÷2
÷3
÷4
÷5
÷6
÷8
÷16
÷32
÷2044
SYNC Logic 3
Slip Logic3
Subtotal
Comment
Typical Current (mA)
2.5
Including term currents
43
Including term currents
31
24
At 307 MHz
10
At 100 MHz, both sections
25
Included 2
0
0.5
1
2.5
Profile 1
2
3
2.5
2.5
4
2.5
43
43
43
10
Included2
3
Glitchless mode enabled
Not using divider path
3
Included2
9
9
0
Included2
27
27
31
29
32
29
30
31
32
32
4
4
0
3
9
9
0
31
32
2.5
48
89
13
92
Profile 0 = sleep mode; Profile 1 = fundamental mode; Profile 2 =SYSREF channel matched to fundamental mode; Profile 3 = LVDS—high power signal source from
other channel; Profile 4 = worst case configuration for power consumption of a channel.
2
The base current consumption of the circuit (for example, mux) is included in the buffer typical current.
3
Currents occur only temporarily during a synchronization event.
1
Rev. B | Page 41 of 72
HMC7044
Data Sheet
SERIAL CONTROL PORT
SERIAL PORT INTERFACE (SPI) CONTROL
4.
The HMC7044 can be controlled via the SPI using 24-bit
registers and three pins: serial port enable (SLEN) serial data
input/output (SDATA), and serial clock (SCLK).
5.
The 24-bit register, shown in Table 24, consists of the following:
Typical Write Cycle
•
•
•
•
A typical write cycle is shown in Figure 49, and occurs as
follows:
1-bit read/write command
2-bit multibyte field (W1, W0)
13-bit address field (A12 to A0)
8-bit data field (D7 to D0)
The host registers the 8-bit data on the next eight rising
edges of SCLK. The HMC7044 places 8-bit data (D7 to D0)
MSB first on the next eight falling edges of SCLK.
Deassertion of SLEN completes the register read cycle.
1.
The master (host) asserts both SLEN and SDATA to
indicate a read, followed by a rising edge SCLK. The slave
(HMC7044) reads SDIO on the first rising edge of SCLK
after SLEN. Setting SDATA low initiates a write.
The host places the 2-bit multibyte field to be written to
low (0) on the next two falling edges of SCLK. The
HMC7044 registers the 2-bit multibyte field on the next
two rising edges of SCLK.
The host places the13-bit address field (A12 to A0), MSB
first on SDATA on the next 13 falling edges of SCLK. The
HMC7044 registers the 13-bit address field (MSB first) on
SDIO over the next 13 rising edges of SCLK.
The host places the 8-bit data (D7 to D0) MSB first on the
next eight falling edges of SCLK. The HMC7044 register
the 8-bit data (D7 to D0) MSB first on the next eight rising
edges of SCLK.
The final rising edge of SCLK performs the internal data
transfer into the register file, updating the configuration of
the device.
Deassertion of SLEN completes the register write cycle.
Table 24. SPI Bit Map
MSB
Bit 23
R/W
Bit 22
W1
Bit 21
W0
LSB
Bits[7:0]
D7 to D0
Bits[20:8]
A12 to A0
2.
Typical Read Cycle
3.
A typical read cycle is shown in Figure 48 and occurs as follows:
3.
1
SCLK
SDATA
X
2
READ W1
3
W0
4.
5.
6.
4
5
A12
A11
16
A0
17
D7
18
D6
24
D0
13033-046
2.
The master (host) asserts both SLEN and SDATA to
indicate a read, followed by a rising edge SCLK. The slave
(HMC7044) reads SDATA on the first rising edge of SCLK
after SLEN. Setting SDATA high initiates a read.
The host places the 2-bit multibyte field to be written to
low (0) on the next two falling edges of SCLK. The
HMC7044 registers the 2-bit multibyte field on the next
two rising edges of SCLK.
The host places the 13-bit address field (A12 to A0) MSB
first on SDATA on the next 13 falling edges of SCLK. The
HMC7044 registers the 13-bit address field (MSB first) on
SDATA over the next 13 rising edges of SCLK.
SLEN
Figure 49. SPI Timing Diagram, Read Operation
1
SCLK
SDATA
X
WRITE
2
W1
3
W0
4
5
A12
A11
16
A0
17
D7
18
D6
24
D0
13033-047
1.
SLEN
Figure 50. SPI Timing Diagram, Write Operation
Rev. B | Page 42 of 72
Data Sheet
HMC7044
APPLICATIONS INFORMATION
PLL1 NOISE CALCULATIONS
Use the following equations to calculate the flicker noise, noise
floor, and total unfiltered phase noise specifications for PLL1
(see Table 4).
where:
Floor_FOM is the figure of merit at the floor frequency.
fPD2 is the phase detector frequency of PLL2.
Calculate the total phase noise (unfiltered) as follows:
PN ( f OUT , f PD2 , f OFFSET ) =
Calculate the flicker noise using the following equation:
PN(fOUT, fOFFSET) = Flicker_FOM + 20 × log(fOUT) – 10 ×
log(fOFFSET)
(1)
where:
PN() is the phase noise.
fOUT is the output frequency.
fOFFSET is the offset of noise frequency from the output carrier
frequency.
Flicker_FOM is the figure of merit at the flicker frequency.
PN ( f OUT , f PD1 ) =
Use the following equations to calculate the phase noise floor,
jitter density, and rms additive jitter due to floor specifications
(see Table 9).
Calculate the phase noise floor using the following equation:
PNFLOOR = FOMOCHAN + 10 × log(fOUT) + Harmonic
Degradation + Power Degradation
where:
fPD1 is the phase detector frequency of PLL1.
Floor_FOM is the figure of merit at the floor frequency.
Calculate the total phase noise (unfiltered) as follows:
PN ( f OUT , f PD1 , f OFFSET ) =
2
2

 PN _ Floor 
 PN _ Flicker 





10 × log  10  10  + 10  10 







(3)
where:
PN_Flicker is the phase noise at the flicker frequency.
PN_Floor is the phase noise at the floor frequency.
PLL2 NOISE CALCULATIONS
Use the following equations to calculate the flicker noise, noise
floor, and total unfiltered phase noise specifications for PLL2
(see Table 5).
Calculate the jitter density at fOUT as follows:
JITTER _ DENSITY _ FLOOR
(4)
where:
fOUT is the output frequency.
fOFFSET is the offset of noise frequency from the output carrier
frequency.
Flicker_FOM is the figure of merit at the flicker frequency.
 PN floor 10 


f
× 2π 
= 2 × 10  OUT 
(8)
where JITTER_DENSITY_FLOOR is the jitter density of floor at
fOUT.
Calculate the rms additive jitter due to floor using the following
equation:
JITTER_RMS_FLOOR = JITTER_DENSITY_FLOOR ×
√Observation Bandwidth
(9)
Calculate the noise floor as follows:
 f
PN ( f OUT , f PD2 ) = Floor_ FOM + 20 × log  OUT
 f PD2
log ( f PD2 )
(7)
where:
PNFLOOR is the phase noise floor at fOUT.
FOMOCHAN is the figure of merit of the output channel.
Harmonic Degradation is the harmonics of the signal captured
in the measurement bandwidth of the receiving
instrument/circuit. The noise power of those harmonics can
fold and influence the overall noise.
Power Degradation results when the noise floor (−174 dBm/Hz)
of the measurement system approaches the noise power in the
phase noise floor of the signal. For example, a phase noise value
of−155 dBc/Hz at 0 dBm carrier level is −155 dBm/Hz and is
easily measurable. If, however, the carrier level is −20 dBm, the
phase noise of –155 dBc/Hz is −175 dBm/Hz, and is not
measurable below the other noise sources in the system.
Calculate the flicker noise using the following equation:
PN(fOUT, fOFFSET) = Flicker_FOM + 20 × log(fOUT) – 10 ×
log(fOFFSET)
(6)
PHASE NOISE FLOOR AND JITTER
(2)

 − 10 × log ( f PD1 )







where:
PN_Flicker is the phase noise at the flicker frequency.
PN_Floor is the phase noise at the floor frequency.
Calculate the noise floor as follows:
 f
Floor_ FOM + 20 × log  OUT
 f PD1
2
2

 PN _ Floor 
 PN _ Flicker 





10
10




10 × log  10
+ 10


where Observation Bandwidth is the desired integration
bandwidth of the noise with a lower and upper bound offset
from the output carrier frequency.


 − 10 ×

(5)
Rev. B | Page 43 of 72
HMC7044
Data Sheet
CONTROL REGISTERS
CONTROL REGISTER MAP
Register addresses that are not listed in Table 25 are not used, and writing to those registers has no effect. Do not change the values of
registers that are marked as reserved. When writing to registers with bits that are marked reserved, take care to always write the default
value for the reserved bits, unless listed otherwise in the other controls subsection of Table 25.
Table 25. Control Register Map
Addr.
Register
(Hex)
Name
Global Control
Global soft
0x0000
reset control
Global
0x0001
request and
mode control
Bit 7 (MSB)
Bit 6
Bit 5
0x0004
0x0005
0x0006
0x0007
0x0008
0x0009
PLL1
0x000A
0x000B
0x000C
0x000D
0x000E
0x0014
0x0015
0x0016
Bit 3
Bit 2
Bit 1
Reserved
Reseed
request
High
performance
distribution
path
High
performance
PLLs/VCO
Force
holdover
Mute
output
drivers
Pulse
generator
request
Restart
dividers/
FSMs
Default
Value
(Hex)
Soft reset
0x00
Sleep
mode
0x00
Slip
PLL2
Reserved
request
autotune
trigger
PLL2
PLL1
RF reseeder
SYSREF
VCO Selection[1:0]
enable
enable
enable
timer
enable
Seven Pairs of 14-Channel Outputs Enable[6:0]
CLKIN1/
CLKIN0/
PLL1 Reference Path Enable[3:0]
CLKIN1 in
CLKIN0 in RF
external VCO
SYNC input
input mode
mode
Clear
Reserved
alarms
Reserved
Reserved (Scratchpad)
Disable
Reserved
SYNC at
lock
0x0002
0x0003
Bit 4
Bit 0
(LSB)
Reserved
Global
enable
control
Global mode
and enable
control
Reserved
Reserved
SYNC Pin Mode
Selection[1:0]
Global clear
alarms
Global
miscellaneous
control
CLKIN0/
CLKIN0 input
buffer control
CLKIN1/
CLKIN1 input
buffer control
CLKIN2/
CLKIN2 input
buffer control
CLKIN3/
CLKIN3 input
buffer control
OSCIN/OSCIN
input buffer
control
PLL1
reference
priority
control
PLL1 loss of
signal (LOS)
control
PLL1
holdover exit
control
0x00
0x37
0x7F
0x4F
0x00
0x00
0x00
0x01
Reserved
Input Buffer Mode[3:0]
Buffer
enable
0x07
Reserved
Input Buffer Mode[3:0]
Buffer
enable
0x07
Reserved
Input Buffer Mode[3:0]
Buffer
enable
0x07
Reserved
Input Buffer Mode[3:0]
Buffer
enable
0x07
Reserved
Input Buffer Mode[3:0]
Buffer
enable
0x07
First Priority
CLKINx/CLKINx
Input[1:0]
0xE4
Fourth Priority
CLKINx/CLKINx Input[1:0]
Third Priority CLKINx/CLKINx
Input[1:0]
Second Priority
CLKINx/CLKINx
Input[1:0]
Reserved
LOS Validation Timer[2:0]
Holdover Exit
Action[1:0]
Reserved
Rev. B | Page 44 of 72
Holdover Exit
Criteria[1:0]
0x03
0x0C
Data Sheet
Addr.
(Hex)
0x0017
0x0018
Register
Name
PLL1
holdover
DAC/ADC
control
0x0019
PLL1 LOS
mode control
0x001A
PLL1 charge
pump control
PLL1 PFD
control
0x001B
0x001C
0x001D
0x001E
0x001F
0x0020
0x0021
0x0022
0x0026
0x0027
0x0028
0x0029
0x002A
PLL2
0x0031
0x0032
0x0033
0x0034
CLKIN0/
CLKIN0 input
prescaler
control
CLKIN1/
CLKIN1 input
prescaler
control
CLKIN2/
CLKIN2 input
prescaler
control
CLKIN3/
CLKIN3 input
prescaler
control
OSCIN/OSCIN
Input
prescaler
control
PLL1
reference
divider
control (R1)
PLL1
feedback
divider
control (N1)
PLL1 lock
detect
control
PLL1
reference
switching
control
PLL1 holdoff
time control
PLL2
miscellaneou
s control
PLL2
frequency
doubler
control
PLL2
reference
divider
control (R2)
HMC7044
Bit 7 (MSB)
Reserved
Bit 6
Bit 5
Bit 4
Reserved
Bit 3
Holdover DAC Value[6:0]
ADC
tracking
disable
Reserved
Reserved
Reserved
Bit 1
Force
DAC to
holdover
in quick
mode
Holdover BW
Reduction[1:0]
LOS
bypass
input
prescaler
PLL1 CP Current[3:0]
Reserved
PLL1 PFD up
enable
PLL1 PFD
down
enable
CLKIN0/CLKIN0 Input Prescaler[7:0]
Reserved
Bit 2
PLL1 PFD
up force
Bit 0
(LSB)
PLL1 PFD
down
force
LOS uses
VCXO
prescaler
Default
Value
(Hex)
0x00
0x04
0x00
0x08
PLL1 PFD
polarity
0x18
0x04
CLKIN1/CLKIN1 Input Prescaler[7:0]
0x01
CLKIN2/CLKIN2 Input Prescaler[7:0]
0x04
CLKIN3/CLKIN3 Input Prescaler[7:0]
0x01
OSCIN/OSCIN Input Prescaler[7:0]
0x04
16-Bit R1 Divider[7:0] (LSB)
16-Bit R1 Divider[15:8] (MSB)
0x04
0x00
16-Bit N1 Divider[7:0] (LSB)
16-Bit N1 Divider[15:8] (MSB)
0x10
0x00
PLL1 lock
detect uses
slip
Bypass
debouncer
PLL1 Lock Detect Timer[4:0]
Manual Mode Reference
Switching[1:0]
Holdover
uses DAC
Autorevertive
reference
switching
0x0F
Automode
reference
switching
0x05
Holdoff Timer[7:0]
0x00
Reserved
0x01
Bypass
frequency
doubler
Reserved
12-Bit R2 Divider[7:0] (LSB)
Reserved
12-Bit R2 Divider[11:8] (MSB)
Rev. B | Page 45 of 72
0x01
0x02
0x00
HMC7044
Addr.
(Hex)
0x0035
0x0036
0x0037
0x0038
Register
Name
PLL2
feedback
divider
control (N2)
PLL2 charge
pump control
PLL2 PFD
control
0x0039
OSCOUTx/
OSCOUTx
path control
0x003A
OSCOUTx/
OSCOUTx
driver control
0x003B
Data Sheet
Bit 7 (MSB)
Bit 6
Bit 5
Bit 4
Bit 3
16-Bit N2 Divider[7:0] (LSB)
16-Bit N2 Divider[15:8] (MSB)
Reserved
Bit 2
PLL2 CP Current[3:0]
PLL2 PFD up
enable
Reserved
PLL2 PFD
down
enable
Reserved
PLL2 PFD
up force
PLL2 PFD
down
force
OSCOUTx/
OSCOUTx Divider[1:0]
Reserved
OSCOUT0/OSCOUT0 Driver
Mode[1:0]
Reserved
OSCOUT0/OSCOUT0
Driver Impedance[1:0]
Reserved
OSCOUT1/OSCOUT1 Driver
Mode[1:0]
Reserved
OSCOUT1/OSCOUT1
Driver Impedance[1:0]
PLL2
miscellaneous
control
GPIO/SDATA Control
0x0046
GPI1 control
Reserved
GPI1 Selection[3:0]
0x0047
GPI2 control
Reserved
GPI2 Selection[3:0]
0x0048
GPI3 control
Reserved
GPI3 Selection[3:0]
0x0049
GPI4 control
Reserved
GPI4 Selection[3:0]
0x0050
GPO1 control
GPO1 Selection[5:0]
0x0051
GPO2 control
GPO2 Selection[5:0]
0x0052
GPO3 control
GPO3 Selection[5:0]
0x0053
GPO4 control
GPO4 Selection[5:0]
0x0054
0x005C
0x005D
0x005E
SYSREF timer
control
SYSREF
miscellaneous
control
PLL2 PFD
polarity
0x18
OSCOUTx/
OSCOUTx
path
enable
OSCOUT0/
OSCOUT0
driver
enable
OSCOUT1/
OSCOUT1
driver
enable
0x00
GPO1
mode
GPO2
mode
GPO3
mode
GPO4
mode
SDATA
mode
GPI1
enable
GPI2
enable
GPI3
enable
GPI4
enable
GPO1
enable
GPO2
enable
GPO3
enable
GPO4
enable
SDATA
enable
Reserved
Pulse Generator Mode Selection[2:0]
Reserved
SYNC
retime
SYNC
through
PLL2
SYSREF Timer[7:0] (LSB)
SYSREF Timer[11:8] (MSB)
Reserved
Rev. B | Page 46 of 72
0x00
0x00
0x00
Reserved
Reserved
Default
Value
(Hex)
0x20
0x00
0x0F
Reserved
0x003C
SDATA
control
SYSREF/SYNC Control
0x005A Pulse
generator
control
0x005B
SYNC control
Bit 1
Bit 0
(LSB)
SYNC
polarity
0x00
0x00
0x09
0x11
0x37
0x33
0x00
0x00
0x03
0x00
0x06
0x00
0x01
0x00
Data Sheet
HMC7044
Addr.
Register
(Hex)
Name
Bit 7 (MSB)
Clock Distribution Network
External VCO
0x0064
control
0x0065
PLL1 near
lock mask
Alarm mask
control
Latched
alarm
readback
Alarm
0x007F
readback
miscellaneous
PLL1 Status Registers
PLL1 status
0x0082
registers
0x007E
0x0083
0x0084
Reserved
Bit 3
Bit 2
Bit 1
Divide by
2 on
external
VCO
enable
Reserved
PLL1 lock
acquisition
mask
Reserved
PLL1 lock
detect mask
PLL1 holdover
status mask
Sync request
mask
0x00
Analog
delay low
power
mode
0x00
PLL1 CLKINx/CLKINx LOS Mask[3:0]
PLL1 and
PLL2 lock
detect
mask
Clock
outputs
phase
status
mask
SYSREF
sync
status
mask
PLL2 lock
detect
mask
Product ID Value[7:0] (LSB)
Product ID Value[15:8] (Mid)
Product ID Value[23:16] (MSB)
PLL1 lock
detect
PLL2 lock
acquisition
latched
PLL1 lock
acquisition
latched
PLL1 holdover
status
Sync request
status
Alarm
signal
CLKINx/CLKINx LOS[3:0]
PLL2 lock
SYSREF
Clock
detect
sync
outputs
status
phases
status
CLKINx/CLKINx LOS Latched[3:0]
PLL1 and
PLL2 lock
detect
PLL1 holdover
latched
Reserved
PLL1 Best Clock[1:0]
Reserved
Holdover
comparator
value
0x0086
PLL1
active
CLKINx/
CLKINx
LOS
PLL1 Holdover Exit
Phase[1:0]
Reserved
Reserved
0x0087
PLL2 Status Registers
0x008C PLL2 status
0x008D registers
PLL2
autotune
status
PLL1 Active
CLKINx/CLKINx[1:0]
PLL1 FSM State[2:0]
PLL1 Holdover DAC Averaged Value[6:0]
PLL1 Holdover DAC Current Value[6:0]
Reserved
PLL1
VCXO
status
PLL1
holdover
ADC
status
Reserved
PLL2 autotune value
PLL2 Autotune Signed Error[7:0] (LSB)
PLL2 Autotune Signed Error[13:8] (MSB)
PLL2
autotune
error sign
PLL2 Autotune FSM State[3:0]
PLL2 SYNC FSM State[3:0]
Reserved
Rev. B | Page 47 of 72
0x00
0x10
0x51
0x16
0x30
Reserved
PLL1 lock
acquisition
Reserved
Default
Value
(Hex)
Low
frequency
external
VCO path
Reserved
0x0085
0x008F
0x0090
Bit 4
Reserved
Product ID Registers
0x0078
Product ID
0x0079
0x007A
Alarm Readback Status Registers
Readback
0x007B
register
PLL1 near
0x007C PLL1 alarm
readback
lock
0x007D Alarm
readback
0x008E
Bit 5
Analog delay
common
control
Alarm Masks Registers
PLL1 alarm
0x0070
mask control
0x0071
Bit 6
Bit 0
(LSB)
PLL1
holdover
ADC input
range
status
HMC7044
Addr.
Register
(Hex)
Name
SYSREF Status Register
SYSREF status
0x0091
register
Other Controls
0x0096
Reserved
0x0097
Reserved
0x0098
Reserved
0x0099
Reserved
0x009A Reserved
0x009B
Reserved
0x009C Reserved
0x009D
Reserved
0x009E
Reserved
0x009F
Reserved
0x00A0 Reserved
0x00A1 Reserved
0x00A2 Reserved
0x00A3 Reserved
0x00A4 Reserved
0x00A5 Reserved
0x00A6 Reserved
0x00A7 Reserved
0x00A8 Reserved
0x00A9 Reserved
0x00AB Reserved
0x00AC Reserved
0x00AD Reserved
0x00AE Reserved
0x00AF Reserved
0x00B0
Reserved
0x00B1
Reserved
0x00B2
Reserved
0x00B3
Reserved
0x00B5
Reserved
0x00B6
Reserved
0x00B7
Reserved
0x00B8
Reserved
Clock Distribution
0x00C8 Channel
Output 0
control
0x00C9
0x00CA
0x00CB
0x00CC
0x00CD
0x00CE
0x00CF
0x00D0
0x00D1
Data Sheet
Bit 7 (MSB)
Bit 6
Bit 5
Bit 4
Channel
outputs FSM
busy
Reserved
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
SYSREF FSM State[3:0]
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Clock output driver low power setting (for optimum performance, set to 0x4D instead of default value)
Clock output driver high power setting (for optimum performance, set to 0xDF instead of default value)
Reserved
Reserved
Reserved
Reserved
PLL1 more delay (PFD1, lock detect) (for optimum performance, set to 0x06 instead of default value)
Reserved
Reserved
PLL1 holdover DAC gm setting (for optimum performance, set to 0x06 instead of default value)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
VTUNE preset setting (for optimum performance, set to 0x04 instead of default value)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
High
performance
mode
SYNC
enable
Slip enable
Reserved
Force Mute[1:0]
Start-Up Mode[1:0]
Multislip
enable
Channel
enable
12-Bit Channel Divider[7:0] (LSB)
12-Bit Channel Divider[11:8] (MSB)
Fine Analog Delay[4:0]
Coarse Digital Delay[4:0]
12-Bit Multislip Digital Delay[7:0] (LSB)
Reserved
12-Bit Multislip Digital Delay[11:8] (MSB)
Output Mux
Reserved
Selection[1:0]
Dynamic
Driver Mode[1:0]
Reserved
Driver Impedance[1:0]
driver enable
Reserved
Reserved
Reserved
Reserved
Default
Value
(Hex)
0x00
0x00
0x00
0x00
0x00
0xAA
0xAA
0xAA
0xAA
0x55
0x56
0x97
0x03
0x00
0x00
0x00
0x1C
0x00
0x22
0x00
0x00
0x20
0x00
0x08
0x50
0x09
0x0D
0x00
0x00
0x00
0x00
0x00
0x00
0xF3
0x04
0x00
0x00
0x00
0x00
0x00
0x00
0x01
0x00
Rev. B | Page 48 of 72
Data Sheet
Addr.
(Hex)
0x00D2
Register
Name
Channel
Output 1
control
HMC7044
Bit 7 (MSB)
High
performance
mode
0x00D3
0x00D4
0x00D5
0x00D6
0x00D7
0x00D8
0x00D9
Force Mute[1:0]
Channel
Output 2
control
High
performance
mode
0x00DD
0x00DE
0x00DF
0x00E0
0x00E1
0x00E2
0x00E3
Channel
Output 3
control
0x00F8
0x00F9
Bit 3
Bit 2
Start-Up Mode[1:0]
Bit 1
Multislip
enable
High
performance
mode
SYNC
enable
Force Mute[1:0]
Channel
Output 4
control
High
performance
mode
SYNC
enable
0x00
0x01
0x00
0x00
0x00
0x00
0x00
12-Bit Channel Divider[7:0] (LSB)
12-Bit Channel Divider[11:8] (MSB)
Fine Analog Delay[4:0]
Coarse Digital Delay[4:0]
12-Bit Multislip Digital Delay[7:0] (LSB)
Reserved
12-Bit Multislip Digital Delay[11:8] (MSB)
Output Mux
Reserved
Selection[1:0]
Dynamic
Driver Mode[1:0]
Reserved
Driver Impedance[1:0]
driver enable
Reserved
Multislip
Channel
Slip enable
Reserved
Start-Up Mode[1:0]
enable
enable
0x08
0x00
0x00
0x00
0x00
0x00
0x00
12-Bit Channel Divider[7:0] (LSB)
12-Bit Channel Divider[11:8] (MSB)
Fine Analog Delay[4:0]
Coarse Digital Delay[4:0]
12-Bit Multislip Digital Delay[7:0] (LSB)
Reserved
12-Bit Multislip Digital Delay[11:8] (MSB)
Output Mux
Reserved
Selection[1:0]
Dynamic
Driver Mode[1:0]
Reserved
Driver Impedance[1:0]
driver enable
Reserved
Multislip
Channel
Slip enable
Reserved
Start-Up Mode[1:0]
enable
enable
0x00
0x01
0x00
0x00
0x00
0x00
0x00
12-Bit Channel Divider[7:0] (LSB)
12-Bit Channel Divider[11:8] (MSB)
Fine Analog Delay[4:0]
Coarse Digital Delay[4:0]
12-Bit Multislip Digital Delay[7:0] (LSB)
12-Bit Multislip Digital Delay[11:8] (MSB)
Output Mux
Reserved
Selection[1:0]
Dynamic
Driver Mode[1:0]
Reserved
Driver Impedance[1:0]
driver enable
Reserved
0x02
0x00
0x00
0x00
0x00
0x00
0x00
Reserved
Reserved
Reserved
Reserved
Force Mute[1:0]
Default
Value
(Hex)
0xFD
12-Bit Channel Divider[7:0] (LSB)
12-Bit Channel Divider[11:8] (MSB)
Fine Analog Delay[4:0]
Coarse Digital Delay[4:0]
12-Bit Multislip Digital Delay[7:0] (LSB)
Reserved
12-Bit Multislip Digital Delay[11:8] (MSB)
Output Mux
Reserved
Selection[1:0]
Dynamic
Driver Mode[1:0]
Reserved
Driver Impedance[1:0]
driver enable
Reserved
Multislip
Channel
Slip enable
Reserved
Start-Up Mode[1:0]
enable
enable
Reserved
Reserved
Reserved
0x00EE
0x00F1
0x00F2
0x00F3
0x00F4
0x00F5
0x00F6
0x00F7
SYNC
enable
Force Mute[1:0]
0x00E7
0x00E8
0x00E9
0x00EA
0x00EB
0x00EC
0x00ED
0x00EF
0x00F0
Bit 4
Reserved
Reserved
Reserved
Reserved
0x00E4
0x00E5
0x00E6
Bit 5
Slip enable
Reserved
Reserved
Reserved
0x00DA
0x00DB
0x00DC
Bit 6
SYNC
enable
Bit 0
(LSB)
Channel
enable
Rev. B | Page 49 of 72
0x30
0x00
0xF3
0x01
0x00
0xFD
0x30
0x00
0xF3
0x01
0x00
HMC7044
Addr.
(Hex)
0x00FA
Register
Name
Channel
Output 5
control
Data Sheet
Bit 7 (MSB)
High
performance
mode
0x00FB
0x00FC
0x00FD
0x00FE
0x00FF
0x0100
0x0101
Force Mute[1:0]
Channel
Output 6
control
0x0105
0x0106
0x0107
0x0108
0x0109
0x010A
0x010B
High
performance
mode
Channel
Output 7
control
0x0120
0x0121
Bit 3
Bit 2
Start-Up Mode[1:0]
Bit 1
Multislip
enable
High
performance
mode
SYNC
enable
Force Mute[1:0]
Channel
Output 8
control
High
performance
mode
SYNC
enable
0x00
0x01
0x00
0x00
0x00
0x00
0x00
12-Bit Channel Divider[7:0] (LSB)
12-Bit Channel Divider[11:8] (MSB)
Fine Analog Delay[4:0]
Coarse Digital Delay[4:0]
12-Bit Multislip Digital Delay[7:0] (LSB)
Reserved
12-bit Multislip Digital Delay[11:8] (MSB)
Output Mux
Reserved
Selection[1:0]
Dynamic
Driver Mode[1:0]
Reserved
Driver Impedance[1:0]
driver enable
Reserved
Multislip
Channel
Slip enable
Reserved
Start-Up Mode[1:0]
enable
enable
0x02
0x00
0x00
0x00
0x00
0x00
0x00
12-Bit Channel Divider[7:0] (LSB)
12-Bit Channel Divider[11:8] (MSB)
Fine Analog Delay[4:0]
Coarse Digital Delay[4:0]
12-Bit Multislip Digital Delay[7:0] (LSB)
Reserved
12-Bit Multislip Digital Delay[11:8] (MSB)
Output Mux
Reserved
Selection[1:0]
Dynamic
Driver Mode[1:0]
Reserved
Driver Impedance[1:0]
driver enable
Reserved
Multislip
Channel
Slip enable
Reserved
Start-Up Mode[1:0]
enable
enable
0x00
0x01
0x00
0x00
0x00
0x00
0x00
12-Bit Channel Divider[7:0] (LSB)
12-Bit Channel Divider[11:8] (MSB)
Fine Analog Delay[4:0]
Coarse Digital Delay[4:0]
12-Bit Multislip Digital Delay[7:0] (LSB)
Reserved
12-Bit Multislip Digital Delay[11:8] (MSB)
Output Mux
Reserved
Selection[1:0]
Dynamic
Driver Mode[1:0]
Reserved
Driver Impedance[1:0]
driver enable
Reserved
0x02
0x00
0x00
0x00
0x00
0x00
0x00
Reserved
Reserved
Reserved
Force Mute[1:0]
Default
Value
(Hex)
0xFD
12-Bit Channel Divider[7:0] (LSB)
12-Bit Channel Divider[11:8] (MSB)
Fine Analog Delay[4:0]
Coarse Digital Delay[4:0]
12-Bit Multislip Digital Delay[7:0] (LSB)
Reserved
12-Bit Multislip Digital Delay[11:8] (MSB)
Output Mux
Reserved
Selection[1:0]
Dynamic
Driver Mode[1:0]
Reserved
Driver Impedance[1:0]
driver enable
Reserved
Multislip
Channel
Slip enable
Reserved
Start-Up Mode[1:0]
enable
enable
Reserved
Reserved
Reserved
0x0116
0x0119
0x011A
0x011B
0x011C
0x011D
0x011E
0x011F
SYNC
enable
Force Mute[1:0]
0x010F
0x0110
0x0111
0x0112
0x0113
0x0114
0x0115
0x0117
0x0118
Bit 4
Reserved
Reserved
Reserved
Reserved
0x010C
0x010D
0x010E
Bit 5
Slip enable
Reserved
Reserved
Reserved
0x0102
0x0103
0x0104
Bit 6
SYNC
enable
Bit 0
(LSB)
Channel
enable
Rev. B | Page 50 of 72
0x30
0x00
0xF3
0x01
0x00
0xFD
0x30
0x00
0xF3
0x01
0x00
Data Sheet
Addr.
(Hex)
0x0122
Register
Name
Channel
Output 9
control
HMC7044
Bit 7 (MSB)
High
performance
mode
0x0123
0x0124
0x0125
0x0126
0x0127
0x0128
0x0129
Force Mute[1:0]
Channel
Output 10
control
High
performance
mode
0x012D
0x012E
0x012F
0x0130
0x0131
0x0132
0x0133
0x0148
0x0149
SYNC
enable
Force Mute[1:0]
Channel
Output 11
control
Bit 1
Multislip
enable
12-Bit Channel Divider[7:0] (LSB)
12-Bit Channel Divider[11:8] (MSB)
Fine Analog Delay[4:0]
Coarse Digital Delay[4:0]
12-Bit Multislip Digital Delay[7:0] (LSB)
Reserved
12-Bit Multislip Digital Delay[11:8] (MSB)
Output Mux
Reserved
Selection[1:0]
Dynamic
Driver Mode[1:0]
Reserved
Driver Impedance[1:0]
driver enable
Reserved
Multislip
Channel
Slip enable
Reserved
Start-Up Mode[1:0]
enable
enable
High
performance
mode
SYNC
enable
12-bit channel divider[11:8] (MSB)
Fine Analog Delay[4:0]
Coarse Digital Delay[4:0]
12-Bit Multislip Digital Delay[7:0] (LSB)
Reserved
12-Bit Multislip Digital Delay[11:8] (MSB)
Output mux
Reserved
selection[1:0]
Dynamic
Driver Mode[1:0]
Reserved
Driver Impedance[1:0]
driver enable
Reserved
Multislip
Channel
Slip enable
Reserved
Start-Up Mode[1:0]
enable
enable
Force Mute[1:0]
Channel
Output 12
control
High
performance
mode
SYNC
enable
0x00
0x01
0x00
0x00
0x00
0x00
0x00
0x30
0x00
0xF3
0x02
0x00
0x00
0x00
0x00
0x00
0x00
0x01
0x00
0xFD
0x00
0x01
0x00
0x00
0x00
0x00
0x00
12-Bit Channel Divider[7:0] (LSB)
12-Bit Channel Divider[11:8] (MSB)
Fine Analog Delay[4:0]
Coarse Digital Delay[4:0]
12-Bit Multislip Digital Delay[7:0] (LSB)
Reserved
12-Bit Multislip Digital Delay[11:8] (MSB)
Output Mux
Reserved
Selection[1:0]
Dynamic
Driver Mode[1:0]
Reserved
Driver Impedance[1:0]
driver enable
Reserved
0x10
0x00
0x00
0x00
0x00
0x00
0x00
Reserved
Reserved
Reserved
Force Mute[1:0]
Default
Value
(Hex)
0xFD
12-Bit Channel Divider[7:0] (LSB)
12-Bit Channel Divider[11:8] (MSB)
Fine Analog Delay[4:0]
Coarse Digital Delay[4:0]
12-Bit Multislip Digital Delay[7:0] (LSB)
Reserved
12-Bit Multislip Digital Delay[11:8] (MSB)
Output Mux
Reserved
Selection[1:0]
Dynamic
Driver Mode[1:0]
Reserved
Driver Impedance[1:0]
driver enable
Reserved
Multislip
Channel
Slip enable
Reserved
Start-Up Mode[1:0]
enable
enable
Reserved
Reserved
Reserved
0x013E
0x0141
0x0142
0x0143
0x0144
0x0145
0x0146
0x0147
Bit 3
Bit 2
Start-Up Mode[1:0]
12-Bit Channel Divider[7:0] (LSB)
0x0137
0x0138
0x0139
0x013A
0x013B
0x013C
0x013D
0x013F
0x0140
Bit 4
Reserved
Reserved
Reserved
Reserved
0x0134
0x0135
0x0136
Bit 5
Slip enable
Reserved
Reserved
Reserved
0x012A
0x012B
0x012C
Bit 6
SYNC
enable
Bit 0
(LSB)
Channel
enable
Rev. B | Page 51 of 72
0x30
0x00
0xF3
0x01
0x00
HMC7044
Addr.
(Hex)
0x014A
Register
Name
Channel
Output 13
control
Data Sheet
Bit 7 (MSB)
High
performance
mode
Bit 6
SYNC
enable
0x014B
0x014C
0x014D
0x014E
0x014F
0x0150
0x0151
Bit 5
Slip enable
Bit 4
Reserved
Bit 3
Bit 2
Start-Up Mode[1:0]
Bit 1
Multislip
enable
Bit 0
(LSB)
Channel
enable
12-Bit Channel Divider[7:0] (LSB)
12-Bit Channel Divider[11:8] (MSB)
Fine Analog Delay[4:0]
Coarse Digital Delay[4:0]
12-Bit Multislip Digital Delay[7:0] (LSB)
Reserved
12-Bit Multislip Digital Delay[11:8] (MSB)
Output Mux
Reserved
Selection[1:0]
Dynamic
Driver Mode[1:0]
Reserved
Driver Impedance[1:0]
driver enable
Reserved
Reserved
Reserved
Reserved
0x0152
Force Mute[1:0]
0x0153
Default
Value
(Hex)
0xFD
0x00
0x01
0x00
0x00
0x00
0x00
0x00
0x30
0x00
CONTROL REGISTER MAP BIT DESCRIPTIONS
Global Control (Register 0x0000 to Register 0x0009)
Table 26. Global Soft Reset Control
Address
0x0000
Bits Bit Name
[7:1] Reserved
0
Soft reset
Settings
Description
Reserved.
Resets all registers, dividers, and FSMs to default values.
Access
RW
Table 27. Global Request and Mode Control
Address
0x0001
Bits
7
Bit Name
Reseed request
6
High performance
distribution path
Settings
0
1
5
High performance
PLLs/VCO
0
1
4
Force holdover
3
2
Mute output drivers
Pulse generator request
1
0
Restart dividers/FSMs
Sleep mode
Description
Requests the centralized resync timer and FSM to reseed any of the
output dividers that are programmed to pay attention to sync events.
This signal is rising edge sensitive, and is only acknowledged if the
resync FSM has completed all events (has finished any previous pulse
generator and/or sync events, and is in the done state; SYSREF FSM
State[3:0] = 0010).
High performance distribution path select. The VCO clock distribution
path has two modes.
Power priority.
Noise priority. Provides the option for better noise floors on the
divided output signals.
High performance PLL/VCO select. The VCO has two modes of
operation.
Power priority.
Noise priority. Reduces the phase noise around the carrier.
Force PLL1 into holdover mode. A holdover request from the GPI or SPI
is debounced inside the device when transferred to the PLL1 FSM
clock domain (which is nominally at the VCXO or LCM rate). With the
debouncer enabled, the delay from force holdover assertion to the
HOLDOVER state is six clock cycles. If the debouncer is bypassed, the
delay is two clock cycles. To asynchronously tristate the charge pump,
the user can disable the up and down signals from the PFD via Bits[4:3]
(PLL1 PFD up enable, PLL1 PFD down enable) in the PLL1 PFD control
register (Register 0x001B).
Mutes the output drivers (dividers still run in the background).
Asks for a pulse stream (see the Typical Programming Sequence
section).
Resets all dividers and FSMs. Does not affect configuration registers.
Forces shutdown. PLL1 and PLL2, output network, and I/O buffers are
disabled.
Rev. B | Page 52 of 72
Access
RW
Data Sheet
Address
0x0002
HMC7044
Bits
[7:3]
2
Bit Name
Reserved
PLL2 autotune trigger
1
Slip request
0
Reserved
Settings
Description
Reserved.
Triggers an autotune if there is an error/issue when the device comes
out of reset.
Requests a slip or multislip event from all divider channels that are
sensitive to slip or multislip commands. The dividers are rising edge
sensitive and take some time to process the request, after which the
phase synchronization alarm is asserted.
Reserved.
Access
RW
Settings
Description
Reserved
Enable RF reseed for SYSREF
Internal disabled/external
High
Low
Enable internal SYSREF time reference
Master analog enable to PLL2
Master analog enable to PLL1
Reserved
Enable Channel 0 and Channel 1
Enable Channel 2 and Channel 3
Enable Channel 4 and Channel 5
Enable Channel 6 and Channel 7
Enable Channel 8 and Channel 9
Enable Channel 10 and Channel 11
Enable Channel 12 and Channel 13
Access
RW
Description
SYNC pin configuration with respect to PLL2.
Disabled.
SYNC. A rising edge is carried through PLL2. Useful for multichip
synchronization.
Pulse generator. Request a pulse generator stream from any channels
configured for dynamic startup. This behaves in the same way as a GPI
requested pulse generator.
Causes SYNC if alarm exists, otherwise causes pulse generator.
CLKIN1/CLKIN1 input is used for external VCO.
Access
RW
Table 28. Global Enable Control
Address
0x0003
0x0004
Bits
[7:6]
5
[4:3]
Bit Name
Reserved
RF reseeder enable
VCO Selection[1:0]
2
1
0
7
[6:0]
SYSREF timer enable
PLL2 enable
PLL1 enable
Reserved
Seven Pairs of 14
Channel Outputs
Enable[6:0]
00
01
10
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
RW
Table 29. Global Mode and Enable Control
Address
0x0005
Bits
[7:6]
Bit Name
SYNC Pin Mode
Selection[1:0]
Settings
00
01
10
11
5
4
[3:0]
CLKIN1/CLKIN1 in
external VCO input
mode
CLKIN0/CLKIN0 in RF
SYNC input mode
PLL1 Reference Path
Enable[3:0]
CLKIN0/CLKIN0 input is used for external RF sync.
Bit 0
Bit 1
Bit 2
Bit 3
Selects and enables the reference path for PLL1.
Enable CLKIN0/CLKIN0 input path.
Enable CLKIN1/CLKIN1 input path.
Enable CLKIN2/CLKIN2 input path.
Enable CLKIN3/CLKIN3 input path.
Rev. B | Page 53 of 72
HMC7044
Data Sheet
Table 30. Global Clear Alarms
Address
0x0006
Bits
[7:1]
0
Bit Name
Reserved
Clear alarms
Settings
Description
Reserved
Clear latched alarms
Access
RW
Settings
Description
Reserved.
Reserved. The user can write/read to this register to confirm I/Os to the
HMC7044. This register does not affect device operation.
Reserved.
PLL2 sends a sync event up N2 when lock is achieved.
This feature is disabled and SYNC is not internally generated on PLL2
lock.
Access
RW
RW
Table 31. Global Miscellaneous Control
Address
0x0007
0x0008
Bits
[7:0]
[7:0]
Bit Name
Reserved
Reserved (Scratchpad)
0x0009
[7:1]
0
Reserved
Disable SYNC at lock
0
1
RW
PLL1 (Register 0x000A to Register 0x002A)
Table 32. CLKINx/CLKINx and OSCIN/OSCIN Input Buffer Control
Address
0x000A, 0x000B, 0x000C, 0x000D, 0x000E
Bits
[7:5]
[4:1]
Bit Name
Reserved
Input Buffer Mode[3:0]
Settings
Bit 0
Bit 1
Bit 2
Bit 3
0
Buffer enable
Description
Reserved
Input buffer control
Enable internal 100 Ω termination
Enable ac coupling input mode
Enable LVPECL input mode
Enable high-Z input mode
Enable input buffer
Access
RW
Table 33. PLL1 Reference Priority Control
Address
0x0014
Bits
[7:6]
Bit Name
Fourth Priority CLKINx/CLKINx Input[1:0]
[5:4]
Third Priority CLKINx/CLKINx Input[1:0]
[3:2]
Second Priority CLKINx/CLKINx Input[1:0]
[1:0]
First Priority CLKINx/CLKINx Input[1:0]
Settings
Description
If third choice clock is not available, use the fourth
choice clock
If second choice clock is not available, use the third
choice clock
If the first choice clock is not available, use the
second choice clock
This is the first choice clock
Access
RW
Description
Reserved.
LCM cycles of LOS hysteresis. This is the number of LCM cycles to wait before
exiting LOS state when the reference input becomes valid again. 1
None.
2 cycles.
4 cycles.
8 cycles.
16 cycles.
32 cycles.
64 cycles.
128 cycles.
Access
RW
Table 34. PLL1 Loss of Signal (LOS) Control
Address
0x0015
Bits
[7:3]
[2:0]
Bit Name
Reserved
LOS Validation
Timer[2:0]
Settings
000
001
010
011
100
101
110
111
1
The LOS revalidation takes between two and three times this number of cycles. The LOS revalidation ambiguity is dependent on whether another channel is in LOS.
Rev. B | Page 54 of 72
Data Sheet
HMC7044
Table 35. PLL1 Holdover Exit Control
Address
0x0016
Bits
[7:4]
[3:2]
Bit Name
Reserved
Holdover Exit Action[1:0]
Settings
00
01
10
11
[1:0]
Holdover Exit Criteria[1:0]
X0 1
01
11
1
Description
Reserved
Action the PLL1 FSM takes as it exits holdover mode.
Reset dividers.
Do nothing.
Do nothing.
DAC assist.
Criteria the PLL1 FSM uses to exit holdover mode.
Exit holdover when LOS is gone.
Exit holdover when phase error = 0.
Exit holder immediately.
Access
RW
X means don’t care.
Table 36. PLL1 Holdover DAC/ADC Control
Address
0x0017
Bits
7
[6:0]
Bit Name
Reserved
Holdover DAC
Value[6:0]
0x0018
[7:4]
3
Reserved
ADC tracking
disable
Force DAC to
holdover in quick
mode
Holdover BW
Reduction[1:0]
2
[1:0]
Settings
Description
Reserved
In holdover mode, if ADC tracking disable is set 1, the holdover DAC control
value is set to this value (regarded as an unsigned integer value); otherwise,
the holdover average DAC value is summed by this value (regarded as twos
complement coded signed integer value)
Reserved
Disable ADC tracking; use DAC hold word
Access
RW
RW
Force DAC control value from DAC current value to computed DAC holdover
value immediately, not gradually
Reduce tracking BW
Table 37. PLL1 LOS Mode Control
Address
0x0019
Bits
[7:2]
1
Bit Name
Reserved
LOS bypass input
prescaler
0
LOS uses VCXO prescaler
Settings
Description
Reserved
Bypass LCM R divider cascade; the R1 input is the selected
CLKINx/CLKINx input
Access
RW
For very low PFD rates; cascades VCXO LCM divider after N1
Table 38. PLL1 Charge Pump Control
Address
0x001A
Bits
[7:4]
[3:0]
Bit Name
Reserved
PLL1 CP Current[3:0]
Settings
Rev. B | Page 55 of 72
Description
Reserved
PLL1 charge pump current
Access
RW
HMC7044
Data Sheet
Table 39. PLL1 PFD Control
Address
0x001B
Bits
[7:5]
4
3
2
Bit Name
Reserved
PLL1 PFD up enable
PLL1 PFD down enable
PLL1 PFD up force
1
PLL1 PFD down force
0
PLL1 PFD polarity
Settings
0
1
Description
Reserved
Enable PLL1 PFD up
Enable PLL1 PFD down
Force PLL1 charge pump up; do not assert simultaneously with PLL1
PFD down force
Force PLL1 charge pump down; do not assert simultaneously with PLL1
PFD up force
Select PFD polarity
Positive
Negative
Access
RW
Table 40. CLKINx/CLKINx and OSCIN/OSCIN Input Prescaler Control
Address
0x001C
Bits
[7:0]
Bit Name
CLKIN0/CLKIN0 Input Prescaler[7:0]
0x001D
[7:0]
0x001E
0x001F
0x0020
Settings
Description
CLKIN0/CLKIN0 Prescaler divider setpoint
Access
RW
CLKIN1/CLKIN1 Input Prescaler[7:0]
CLKIN1/CLKIN1 Prescaler divider setpoint
RW
[7:0]
CLKIN2/CLKIN2 Input Prescaler[7:0]
CLKIN2/CLKIN2 Prescaler divider setpoint
RW
[7:0]
CLKIN3/CLKIN3 Input Prescaler[7:0]
CLKIN3/CLKIN3 Prescaler divider setpoint
RW
[7:0]
OSCIN/OSCIN Input Prescaler[7:0]
OSCIN/OSCIN Prescaler divider setpoint
RW
Table 41. PLL1 Reference Divider Control (R1)
Address
0x0021
0x0022
Bits
[7:0]
[7:0]
Bit Name
16-Bit R1 Divider[7:0] (LSB)
16-Bit R1 Divider[15:8] (MSB)
Settings
Description
16-bit R1 divider setpoint LSB
16-bit R1 divider setpoint MSB
Access
RW
RW
Settings
Description
16-bit N1 divider setpoint LSB
16-bit N1 divider setpoint MSB
Access
RW
RW
Table 42. PLL1 Feedback Divider Control (N1)
Address
0x0026
0x0027
Bits
[7:0]
[7:0]
Bit Name
16-Bit N1 Divider[7:0] (LSB)
16-Bit N1 Divider[15:8] (MSB)
Table 43. PLL1 Lock Detect Control
Address
0x0028
Bits
[7:6]
5
[4:0]
Bit Name
Reserved
PLL1 lock detect uses slip
PLL1 Lock Detect Timer[4:0]
Settings
00000
00001
00010
…
11110
11111
Description
Reserved
Use the slip indicator instead of ~2 ns timer for lock detect
PLL1 lock detect center depth (LCMs); increments of
2PLL1 Lock Detect Timer[4:0] cycles
1 cycle
2 cycles
4 cycles
…
1,073,741,824 cycles
2,147,483,648 cycles
Rev. B | Page 56 of 72
Access
RW
Data Sheet
HMC7044
Table 44. PLL1 Reference Switching Control
Address
0x0029
Bits
[7:6]
5
Bit Name
Reserved
Bypass debouncer
Settings
[4:3]
Manual Mode Reference
Switching[1:0]
2
Holdover uses DAC
Autorevertive reference
switching
Automode reference switching
0
Access
RW
In holdover, selects whether PLL1 uses the DAC or tristates the
charge pump
Tristate the charge pump
Use holdover DAC
Revert to PLL1 best clock option if it becomes available again
0
1
1
Description
Reserved
Bypass the debouncer in manual mode and GPI clock/holdover
selection
If automode REF switching = 0, manual selection of
CLKINx/CLKINx input
Clock switching is automatic based on LOS/PLL1 reference
priority control register (Register 0x0014)
Table 45. PLL1 Holdoff Time Control
Address
0x002A
Bits
[7:0]
Bit Name
Holdoff Timer[7:0]
Settings
Description
PLL1 waits in holdover for 2Holdoff Timer[7:0] LCM cycles to give the abandoned
reference a chance to recover before switching to the next priority clock. If
Holdoff Timer[7:0] equals to 0, holdoff functionality is disabled and switches
directly to the next priority clock.
Access
RW
PLL2 (Register 0x0031 to Register 0x003C)
Table 46. PLL2 Miscellaneous Control
Address
0x0031
0x003C
Bits
[7:0]
[7:0]
Bit Name
Reserved
Reserved
Settings
Description
Reserved
Reserved
Access
RW
RW
Table 47. PLL2 Frequency Doubler Control
Address
0x0032
Bits
[7:1]
0
Bit Name
Reserved
Bypass frequency doubler
Settings
0
1
Description
Reserved
Bypass PLL2 frequency doubler
Enable frequency doubler before R2 divider
Bypass frequency doubler
Access
RW
Table 48. PLL2 Reference Divider Control (R2)
Address
0x0033
Bits
[7:0]
0x0034
[7:4]
[3:0]
Bit Name
12-Bit R2 Divider[7:0]
(LSB)
Reserved
12-Bit R2 Divider[11:8]
(MSB)
Settings
Description
12-bit R2 divider setpoint LSB. Divide by 1 to divide by 4095. 00000000,
00000001 = divide by 1.
Reserved.
12-Bits R2 divider setpoint MSB.
Access
RW
RW
Table 49. PLL2 Feedback Divider Control (N2)
Address
0x0035
0x0036
Bits
[7:0]
[7:0]
Bit Name
16-Bit N2 Divider[7:0] (LSB)
16-Bit N2 Divider[15:8] (MSB)
Settings
Description
16-bit N2 divider setpoint LSB.
16-bit N2 divider setpoint MSB.
Rev. B | Page 57 of 72
Access
RW
RW
HMC7044
Data Sheet
Table 50. PLL2 Charge Pump Control
Address
0x0037
Bits
[7:4]
[3:0]
Bit Name
Reserved
PLL2 CP
Current[3:0]
Settings
Description
Reserved.
These 4 bits set the magnitude of PLL2 charge pump current. Granularity is
~160 µA with full magnitude of ~2560 µA.
Access
RW
Table 51. PLL2 PFD Control
Address
0x0038
Bits
[7:5]
4
3
Bit Name
Reserved
PLL2 PFD up enable
PLL2 PFD down
enable
PLL2 PFD up force
2
1
Settings
PLL2 PFD down
force
PLL2 PFD polarity
0
0
1
Description
Reserved
Enable PLL2 PFD up
Enable PLL2 PFD down
Access
RW
Force PLL2 charge pump up; do not assert simultaneously with PLL2 PFD
down force
Force PLL2 charge pump down; do not assert simultaneously with PLL2
PFD up force
Select PFD polarity
Positive
Negative
Table 52. OSCOUTx/OSCOUTx Path Control
Address
0x0039
Bits
[7:3]
[2:1]
Bit Name
Reserved
OSCOUTx/OSCOUTx
Divider[1:0]
0
Settings
00
01
10
11
OSCOUTx/OSCOUTx
path enable
Description
Reserved
Oscillator output divider ratio
Divided by 1
Divided by 2
Divided by 4
Divided by 8
Enable the oscillator output path (divider and the internal path except
driver)
Access
RW
Table 53. OSCOUTx/OSCOUTx Driver Control
Address
0x003A,
0x003B
Bits
[7:6]
[5:4]
Bit Name
Reserved
OSCOUTx/OSCOUTx Driver Mode[1:0]
Settings 1
00
01
10
11
[3]
[2:1]
Reserved
OSCOUTx/OSCOUTx Driver
Impedance[1:0]
00
01
10
11
0
1
OSCOUTx/OSCOUTx driver enable
X means don’t care.
Rev. B | Page 58 of 72
Description
Reserved
Oscillator output driver mode selection
CML mode
LVPECL mode
LVDS mode
CMOS mode
Reserved
Oscillator output driver impedance selection for
CML mode
Internal resistor disable
Internal 100 Ω resistor enable per output pin
Reserved
Internal 50 Ω resistor enable per output pin
Enable oscillator driver
Access
RW
Data Sheet
HMC7044
GPIO/SDATA Control (Register 0x0046 to Register 0x0054)
Table 54. GPIx Control
Address
0x0046, 0x0047,
0x0048, 0x0049
Bits
[7:5]
[4:1]
Bit Name
Reserved
GPIx Selection[3:0]
Settings
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0
1
GPIx enable
Description
Reserved.
Select the GPIx functionality.
Reserved.
Force PLL1 to holdover.
Select PLL1 reference manually, Bit 1.
Select PLL1 reference manually, Bit 0.
Put the chip into sleep mode.
Issue a mute.
Select the internal VCO type manually.
Select high performance mode for PLL2 and the internal VCO.
Issue a pulse generator request.
Issue a reseed request.
Issue a restart request.
Force the chip into fanout mode.
Reserved.
Issue a slip request
Reserved.
Reserved.
GPIx function enable. Before changing the function of the pin,
disable it first, and then reenable it after the function change. 1
Access
RW
Note that it is possible to have a GPIOx pin configured as both an output and an input.
Table 55. GPOx Control
Address
0x0050, 0x0051, 0x0052, 0x0053
Bits
[7:2]
Bit Name
GPOx Selection[5:0]
Settings
000000
000001
000010
000011
000100
000101
000110
000111
001000
001001
001010
001011
001100
001101
001110
001111
010000
010001
010010
010011
010100
010101
010110
010111
Rev. B | Page 59 of 72
Description
Select the GPOx functionality
Alarm signal
SDATA from SPI communication
CLKIN3/CLKIN3 LOS for CLKIN3/CLKIN3 input
CLKIN2/CLKIN2 LOS for CLKIN2/CLKIN2input
CLKIN1/CLKIN1 LOS for CLKIN1/CLKIN1 input
CLKIN0/CLKIN0 LOS for CLKIN0/CLKIN0 input
PLL1 holdover enabled signal from PLL1
Lock detect signal from PLL1
Acquiring lock signal from PLL1
PLL1 near lock acquisition status signal from PLL1
PLL2 lock detect signal from PLL2
SYSREF sync status has not synchronized since reset
Clock outputs phase status
PLL1 and PLL2 lock detect is locked
Sync request status signal
PLL1 active CLKIN0/CLKIN0
PLL1 active CLKIN1/CLKIN1
PLL1 holdover ADC input range status
PLL1 holdover ADC input status
PLL1 VCXO status
PLL1 active CLKINx/CLKINx status
PLL1 FSM state, Bit 0
PLL1 FSM state, Bit 1
PLL1 FSM state, Bit 2
Access
RW
HMC7044
Data Sheet
Address
Bits
Bit Name
Settings
011000
011001
011010
011011
011100
011101
011110
011111
100000
100001
100010
100011
100100
100101
100110
100111
101000
101001
101010
101011
101100
101101
101110
101111
110000
110001
110010
110011
110100
110101
110110
110111
111000
111001
111010
111011
111100
111101
111110
111111
1
GPOx mode
0
1
0
GPOx enable
Description
PLL1 holdover exit phase, Bit 0
PLL1 holdover exit phase, Bit 1
Channel outputs FSM busy
SYSREF FSM state, Bit 0
SYSREF FSM state, Bit 1
SYSREF FSM state, Bit 2
SYSREF FSM state, Bit 3
Force Logic 1 to GPO
Force Logic 0 to GPO
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PLL1 holdover DAC averaged value, Bit 0
PLL1 holdover DAC averaged value, Bit 1
PLL1 holdover DAC averaged value, Bit 2
PLL1 holdover DAC averaged value, Bit 3
PLL1 holdover DAC current value, Bit 0
PLL1 holdover DAC current value, Bit 1
PLL1 holdover DAC current value, Bit 2
PLL1 holdover DAC current value, Bit 3
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Holdover comparator status
Pulse generator request status signal
Reserved
Selects the mode of GPOx driver
Open-drain mode
CMOS mode
GPOx driver enable
Access
Table 56. SDATA Control
Address
0x0054
Bits
[7:2]
1
Bit Name
Reserved
SDATA mode
Settings
0
1
0
SDATA enable
Description
Reserved
Selects the mode of SDATA driver
Open-drain mode
CMOS mode
SDATA driver enable
Rev. B | Page 60 of 72
Access
RW
Data Sheet
HMC7044
SYSREF/SYNC Control (Register 0x005A to Register 0x005E)
Table 57. Pulse Generator Control
Address
0x005A
Bits
[7:3]
[2:0]
Bit Name
Reserved
Pulse Generator
Mode
Selection[2:0]
Settings
Description
Reserved.
SYSREF output enable with pulse generator.
Level sensitive. When the GPIx is configured to issue a pulse generator
request (GPIx Selection[3:0] = 1000), or a pulse generator request is issued
through the SPI or as a SYNC pin-based pulse generator, run the pulse
generator. Otherwise, stop the pulse generator.
1 pulse.
2 pulses.
4 pulses.
8 pulses.
16 pulses.
16 pulses.
Continuous mode (50% duty cycle).
Access
RW
Settings
Description
Reserved
Access
RW
0
1
Bypass the retime (if using SYNC path with on-chip VCO)
Retime the external SYNC from Reference 0
Allow a reseed event to be through PLL2
SYNC polarity (must be 0 if not using CLKIN0/CLKIN0 as the input)
Positive
Negative
000
001
010
011
100
101
110
111
Table 58. SYNC Control
Address
0x005B
Bits
[7:3]
2
1
0
Bit Name
Reserved
SYNC retime
SYNC through PLL2
SYNC polarity
0
1
Table 59. SYSREF Timer Control
Address
0x005C
Bits
[7:0]
Bit Name
SYSREF
Timer[7:0]
(LSB)
0x005D
[7:4]
[3:0]
Reserved
SYSREF
Timer[11:8]
(MSB)
Settings
Description
12-bit SYSREF timer setpoint LSB. This sets the internal beat frequency of the
master timer, which controls synchronization and pulse generator events. Set the
12-bit timer to a submultiple of the lowest output SYSREF frequency, and
program it to be no faster than 4 MHz.
Reserved.
12-bit SYSREF timer setpoint MSB.
Access
RW
RW
Table 60. SYSREF Miscellaneous Control
Address
0x005E
Bits
[7:0]
Bit Name
Reserved
Settings
Description
Reserved
Access
RW
Clock Distribution Network (Register 0x0064 to Register 0x0065)
Table 61. External VCO Control
Address
0x0064
Bits
[7:2]
1
0
Bit Name
Reserved
Divide by 2 on external VCO enable
Low frequency external VCO path
Settings
Description
Reserved
Use divide by 2 on external VCO path
Changes bias to Class A for low frequency VCO
Rev. B | Page 61 of 72
Access
RW
HMC7044
Data Sheet
Table 62. Analog Delay Common Control
Address
0x0065
Bits
[7:1]
0
Bit Name
Reserved
Analog delay low
power mode
Settings
Description
Reserved.
Analog delay is in low power mode, which can save power for low settings of
analog delay, but is not glitchless between setpoints.
Access
RW
Alarm Masks Registers (Register 0x0070 to Register 0x0071)
Table 63. PLL1 Alarm Mask Control
Address
0x0070
Bits
7
6
Bit Name
PLL1 near lock mask
PLL1 lock acquisition mask
5
PLL1 lock detect mask
4
PLL1 holdover status mask
[3:0]
PLL1 CLKINx/CLKINx Status
Mask[3:0]
Settings
Bit 0
Description
If set, allow the PLL1 near lock signal to generate alarm signal
If set, allow the PLL1 lock acquisition signal to generate alarm
signal
If set, allow the PLL1 lock detect signal to generate alarm
signal
If set, allow the PLL1 holdover status signal to generate alarm
signal
If set, allow CLKIN0/CLKIN0 LOS to generate alarm signal
Bit 1
If set, allow CLKIN1/CLKIN1 LOS to generate alarm signal
Bit 2
If set, allow CLKIN2/CLKIN2 LOS to generate alarm signal
Bit 3
If set, allow CLKIN3/CLKIN3 LOS to generate alarm signal
Settings
Description
Reserved
If set, allow the sync request signals to generate alarm signal
If set, allow the PLL1 and PLL2 lock detect signals to generate
alarm signal
If set, allow the clock outputs phases status signal to generate
alarm signal
If set, allow the SYSREF sync status signal to generate alarm
signal
If set, allow the PLL2 lock detect signal to generate alarm
signal
Access
RW
Table 64. Alarm Mask Control
Address
0x0071
Bits
[7:5]
4
3
Bit Name
Reserved
Sync request mask
PLL1 and PLL2 lock detect mask
2
1
Clock outputs phases status
mask
SYSREF sync status mask
0
PLL2 lock detect mask
Access
RW
Product ID Registers (Register 0x0078 to Register 0x007A)
Table 65. Product ID
Address
0x0078
0x0079
0x007A
Bits
[7:0]
[7:0]
[7:0]
Bit Name
Product ID Value[7:0] (LSB)
Product ID Value[15:8] (Mid)
Product ID Value[23:16] (MSB)
Settings
Description
24-bit product ID value low
24-bit product ID value high
24-bit product ID value very high
Access
R
R
R
Alarm Readback Status Registers (Register 0x007B to Register 0x007F)
Table 66. Readback Register
Address
0x007B
Bits
[7:1]
0
Bit Name
Reserved
Alarm signal
Settings
Description
Reserved.
Readback alarm status from SPI.
Rev. B | Page 62 of 72
Access
R
Data Sheet
HMC7044
Table 67. PLL1 Alarm Readback
Address
0x007C
Bits
7
Bit Name
PLL1 near lock
6
5
4
[3:0]
PLL1 lock acquisition
PLL1 lock detect
PLL1 holdover status
CLKINx/CLKINx
LOS[3:0]
Settings
Bit 0
Description
PLL1 near locked. Declare near locked when the counter reaches 1/16 of
the programmable limit.
PLL1 acquiring lock.
PLL1 locked.
PLL1 in holdover.
CLKIN0/CLKIN0 LOS.
Bit 1
CLKIN1/CLKIN1 LOS.
Bit 2
CLKIN2/CLKIN2 LOS.
Bit 3
CLKIN3/CLKIN3 LOS.
Access
R
Table 68. Alarm Readback
Address
0x007D
Bits
[7:5]
4
3
2
1
Bit Name
Reserved
Sync request status
PLL1 and PLL2 lock
detect
Clock outputs phases
status
Settings
0
1
0
1
SYSREF sync status
0
1
0
PLL2 lock detect
1
Description
Reserved.
PLL2 locked (or disabled), but unsynchronized.
PLL1 and PLL2 lock detect status.
Either PLL1 or PLL2 is not locked or both PLL1 and PLL2 are not locked.
PLL1 and PLL2 are locked.
SYSREF alarm.
SYSREF of the HMC7044 is not valid; that is, its phase output is not stable.
SYSREF of the HMC7044 is valid and locked; that is, its phase output is
stable.
SYSREF SYNC status alarm.
The HMC7044 has been synchronized with an external sync pulse or a
sync request from the SPI.
The HMC7044 never synchronized with an external sync pulse or a sync
request from the SPI.
PLL2 near locked. Declare near locked when counter reaches 1/16 of the
programmable limit.
Access
R
Table 69. Latched Alarm Readback
Address
0x007E
Bits
7
6
5
4
[3:0]
Bit Name
Reserved
PLL2 lock acquisition latched
PLL1 lock acquisition latched
PLL1 holdover latched
CLKINx/CLKINx LOS
Latched[3:0]
Settings
Bit 0
Description
Reserved.
Readback record of PLL2 lock acquisition since the last clear event.
Readback record of PLL1 lock acquisition since the last clear event.
Readback record of PLL1 holdover since the last clear event.
Readback record of CLKIN0/CLKIN0 LOS since the last clear event.
Bit 1
Readback record of CLKIN1/CLKIN1 LOS since the last clear event.
Bit 2
Readback record of CLKIN2/CLKIN2 LOS since the last clear event.
Bit 3
Readback record of CLKIN3/CLKIN3 LOS since the last clear event.
Access
R
Table 70. Alarm Readback Miscellaneous
Address
0x007F
Bits
[7:0]
Bit Name
Reserved
Settings
Description
Reserved.
Rev. B | Page 63 of 72
Access
R
HMC7044
Data Sheet
PLL1 Status Registers (Register 0x0082 to Register 0x0087)
Table 71. PLL1 Status Registers
Address
0x0082
Bits
7
[6:5]
Bit Name
Reserved
PLL1 Best Clock[1:0]
[4:3]
PLL1 Active CLKINx/
CLKINx[1:0]
[2:0]
PLL1 FSM State[2:0]
Settings
000
001
010
011
100
101
0x0083
7
[6:0]
0x0084
7
[6:0]
0x0085
[7:4]
3
0x0086
0x0087
2
Reserved
Holdover DAC Averaged
Value[6:0]
Holdover comparator value
Holdover DAC Current
Value[6:0]
Reserved
PLL1 active CLKINx/CLKINx
LOS
PLL1 VCXO status
1
PLL1 holdover ADC status
0
PLL1 holdover ADC input
range status
[7:5]
[4:3]
Reserved
PLL1 Holdover Exit
Phase[1:0]
Reserved
Reserved
[2:0]
[7:0]
0
1
0
1
Description
Reserved
Indicates which clock the LOS/priority encoder prefers if automode
reference switching is used
Indicates which CLKINx/CLKINx input is currently in use
Sets the state PLL1 is in
Reset
Acquisition
Locked
Invalid
Holdover
DAC assisted holdover exit
Reserved
Average DAC code
Access
R
R
Holdover comparator output value (DAC output vs. PLL1 VTUNE)
Current DAC code
R
Reserved
LOS of the currently active reference
R
Indicates whether any of the enabled references appears to run
faster than the VCXO
ADC is acquiring
PLL1 VTUNE is moving quickly
PLL1 VTUNE is in range
PLL1 VTUNE is out of range
Reserved
The phase of the PLL1 holdover exit
Reserved
Reserved
R
R
PLL2 Status Registers (Register 0x008C to Register 0x0090)
Table 72. PLL2 Status Registers
Address
0x008C
Bits
[7:0]
Bit Name
PLL2 autotune value
0x008D
[7:0]
0x008E
7
PLL2 Autotune Signed
Error[7:0] (LSB)
PLL2 autotune status
6
PLL2 autotune error sign
Settings
1
0
0
1
[5:0]
PLL2 Autotune Signed
Error[13:8] (MSB)
Description
After autotune, this word is populated with the selected capacitor
bank of the VCO
14-bit PLL2 VTUNE error count, LSB
Access
R
Autotune busy
Done/not working
Sign of PLL2 autotune error
Positive
Negative
14-bit PLL2 VTUNE error count, MSB
R
Rev. B | Page 64 of 72
R
Data Sheet
Address
0x008F
Bits
[7:4]
[3:0]
HMC7044
Bit Name
PLL2 Autotune FSM
State[3:0]
Settings
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
PLL2 SYNC FSM State[3:0]
0000
0100
0110
0111
1110
1100
0x0090
[7:0]
Reserved
Description
Autotune FSM state
Idle
Startup
Startup
Reset
Reset
Reset
Measure
Wait
Wait
Update loop to state 18 times
Round
Finish
PLL2 sync carry FSM state
Idle
Power up Section A of the FSM
Power up Section B of the FSM
Sending to N2
Power down Section A of the FSM
Power down Section B of the FSM
Reserved
Access
R
R
SYSREF Status Register (Register 0x0091)
Table 73. SYSREF Status Register
Address
0x0091
Bits
[7:5]
4
[3:0]
Bit Name
Reserved
Channel outputs
FSM busy
SYSREF FSM
State[3:0]
Settings
0000
0010
0100
0101
0110
1010
1011
1100
1101
1110
1111
Description
Reserved.
One of clock outputs FSM requested clock, and it is running.
Indicates the current step of the SYSREF reseed process. Note that the three
different progressions are caused by different trigger events (reseed, pulse
generator, reserved).
Reset.
Done.
Get ready.
Get ready.
Get ready.
Running (pulse generator).
Start.
Power up.
Power up.
Power up.
Clear reset.
Rev. B | Page 65 of 72
Access
R
HMC7044
Data Sheet
Other Controls (Register 0x0096 to Register 0x00B8)
For optimum performance of the chip, Register 0x0096 to Register 0x00B8 must be programmed to a different value than their default
value.
Table 74. Reserved Registers
Address
0x0096
0x0097
0x0098
0x0099
0x009A
0x009B
0x009B
0x009C
0x009D
0x009E
0x009F
0x00A0
0x00A1
0x00A2
0x00A3
0x00A4
0x00A5
0x00A6
0x00A7
0x00A8
0x00A9
0x00AB
0x00AC
0x00AD
0x00AE
0x00AF
0x00B0
0x00B1
0x00B2
0x00B3
0x00B4
0x00B5
0x00B6
0x00B7
0x00B8
Bits
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
Bit Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Settings
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Clock output driver low power setting (set to 0x4D instead of default value)
Clock output driver high power setting (set to 0xDF instead of default value)
Reserved
Reserved
Reserved
Reserved
PLL1 more delay (PFD1, lock detect) (set to 0x06 instead of default value)
Reserved
Reserved
PLL1 holdover DAC gm setting (set to 0x06 instead of default value)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
VTUNE preset setting (set to 0x04 instead of default value)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Rev. B | Page 66 of 72
Access
RW
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RW
RW
Data Sheet
HMC7044
Clock Distribution (Register 0x00C8 to Register 0x0153)
The bit descriptions in Table 75 apply to all 14 channels.
Table 75. Channel 0 to Channel 13 Control
Address
0x00C8, 0x00D2, 0x00DC,
0x00E6, 0x00F0, 0x00FA,
0x0104, 0x010E, 0x0118,
0x0122, 0x012C, 0x0136,
0x0140, 0x014A
Bits
7
Bit Name
High performance
mode
6
SYNC enable
5
Slip enable
4
[3:2]
Reserved
Start-Up Mode[1:0]
Settings 1
00
01
10
11
1
Multislip enable
0
1
0x00C9, 0x00D3, 0x00DD,
0x00E7, 0x00F1, 0x00FB,
0x0105, 0x010F, 0x0119,
0x0123, 0x012D, 0x0137,
0x0141, 0x014B
0x00CA, 0x00D4, 0x00DE,
0x00E8, 0x00F2, 0x00FC,
0x0106, 0x0110, 0x011A,
0x0124, 0x012E, 0x0138,
0x0142, 0x014C
0x00CB, 0x00D5, 0x00DF,
0x00E9, 0x00F3, 0x00FD,
0x0107, 0x0111, 0x011B,
0x0125, 0x012F, 0x0139,
0x0143, 0x014D
0x00CC, 0x00D6, 0x00E0,
0x00EA, 0x00F4, 0x00FE,
0x0108, 0x0112, 0x011C,
0x0126, 0x0130, 0x013A,
0x0144, 0x014E
0x00CD, 0x00D7, 0x00E1,
0x00EB, 0x00F5, 0x00FF,
0x0109, 0x0113, 0x011D,
0x0127, 0x0131, 0x013B,
0x0145, 0x014F
Description
High performance mode. Adjusts the divider and buffer
bias to improve swing/phase noise at the expense of
power.
Susceptible to SYNC event. The channel can process a
SYNC event to reset its phase.
Susceptible to slip event. The channel can process a slip
request from SPI or GPI. Note that if slip enable is true
but multislip is off, a channel slips by 1 VCO cycle on an
explicit slip request broadcast from the SPI/GPI.
Reserved.
Configures the channel to normal mode with
asynchronous startup, or to a pulse generator mode
with dynamic start-up. Note that this must be set to
asynchronous mode if the channel is unused.
Asynchronous.
Reserved.
Reserved.
Dynamic.
Allow multislip operation (default = 0 for SYSREF, 1 for
DCLK).
Do not engage automatic multislip on channel startup.
Multislip events after SYNC or pulse generator request,
if slip enable, Bit = 1.
Channel enable. If this bit is 0, channel is disabled.
12-bit channel divider setpoint LSB. The divider
supports even divide ratios from 2 to 4094. The
supported odd divide ratios are 1, 3, and 5. All even and
odd divide ratios have 50.0% duty cycle.
Access
RW
0
[7:0]
Channel enable
12-Bit Channel
Divider[7:0] (LSB)
[7:4]
[3:0]
Reserved
12-Bit Channel
Divider[11:8] (MSB)
Reserved.
12-bit channel divider setpoint MSB.
RW
[7:5]
[4:0]
Reserved
Fine Analog
Delay[4:0]
Reserved.
24 fine delay steps. Step size = 25 ps. Values greater
than 23 have no effect on analog delay.
RW
[7:5]
[4:0]
Reserved
Coarse Digital
Delay[4:0]
RW
[7:0]
12-Bit Multislip
Digital Delay[7:0]
(LSB)
Reserved.
17 coarse delay steps. Step size = ½ VCO cycle. This flip
flop (FF)-based digital delay does not increase noise
level at the expense of power. Values greater than 17
have no effect on coarse delay.
12-bit multislip digital delay amount LSB.
Step size = (delay amount: MSB + LSB) × VCO cycles. If
multislip enable bit = 1, any slip events (caused by GPI,
SPI, SYNC, or pulse generator events) repeat the
number of times set by 12-Bit Multislip Digital
Delay[11:0] to adjust the phase by step size.
Rev. B | Page 67 of 72
RW
RW
HMC7044
Data Sheet
Address
0x00CE, 0x00D8, 0x00E2,
0x00EC, 0x00F6, 0x0100,
0x010A, 0x0114, 0x011E,
0x0128, 0x0132, 0x013C,
0x0146, 0x0150
0x00CF, 0x00D9, 0x00E3,
0x00ED, 0x00F7, 0x0101,
0x010B, 0x0115, 0x011F,
0x0129, 0x0133, 0x013D,
0x0147, 0x0151
Bits
[7:4]
[3:0]
Bit Name
Reserved
12-Bit Multislip
Digital Delay[11:8]
(MSB)
[7:2]
[1:0]
Reserved
Output Mux
Selection[1:0]
0x00D0, 0x00DA, 0x00E4,
0x00EE, 0x00F8, 0x0102,
0x010C, 0x0116, 0x0120,
0x012A, 0x0134, 0x013E,
0x0148, 0x0152
[7:6]
Settings 1
00
01
10
11
Force Mute[1:0]
00
01
10
11
5
[4:3]
Dynamic driver
enable
0
1
Driver Mode[1:0]
00
01
10
11
[2]
[1:0]
0x00D1, 0x00DB, 0x00E5,
0x00EF, 0x00F9, 0x0103,
0x010D, 0x0117, 0x0121,
0x012B, 0x0135, 0x013F,
0x0149, 0x0153
1
[7:0]
Reserved
Driver
Impedance[1:0]
Reserved
00
01
10
11
Description
Reserved.
12-bit multislip digital delay amount MSB.
Access
RW
Reserved.
Channel output mux selection.
Channel divider output.
Analog delay output.
Other channel of the clock group pair.
Input VCO clock (fundamental). Fundamental can also
be generated with 12-Bit Channel Divider[11:0] = 1.
Idle at Logic 0 selection (pulse generator mode only).
Force to Logic 0 or VCM.
Normal mode (selection for DCLK).
Reserved.
Force to Logic 0.
Reserved.
Dynamic driver enable (pulse generator mode only).
Driver is enabled/disabled with channel enable bit
Driver is dynamically disabled with pulse generator
events.
Output driver mode selection.
CML mode.
LVPECL mode.
LVDS mode.
CMOS mode.
Reserved.
Output driver impedance selection for CML mode.
Internal resistor disable.
Internal 100 Ω resistor enable per output pin.
Reserved.
Internal 50 Ω resistor enable per output pin.
Reserved.
RW
X means don’t care.
Rev. B | Page 68 of 72
RW
RW
Data Sheet
HMC7044
EVALUATION PCB SCHEMATIC
EVALUATION PCB
RAMP UP
3°C/SECOND MAX
217°C
150°C TO 200°C
RAMP DOWN
6°C/SECOND MAX
60 TO 180
SECONDS
480 SECONDS MAX
TIME (Second)
20 TO 40
SECONDS
13033-048
Figure 51. Pb-Free Reflow Solder Profile
Figure 52. Evaluation PCB Layout, Top Side
Rev. B | Page 69 of 72
13033-146
The typical Pb-free reflow solder profile is shown in Figure 51.
260 – 5°C/260 + 0°C
TEMPERATURE (°C)
For the circuit board used in the application, use RF circuit
design techniques. Ensure that signal lines have 50 Ω
impedance. Connect the package ground leads and exposed pad
directly to the ground plane (see Figure 52). Use a sufficient
number of via holes to connect the top and bottom ground
planes. The evaluation circuit board is available from Analog
Devices upon request.
60 TO 150
SECONDS
Data Sheet
13033-049
HMC7044
Figure 53. Evaluation PCB Layout, Bottom Side
Rev. B | Page 70 of 72
Data Sheet
HMC7044
OUTLINE DIMENSIONS
10.10
10.00 SQ
9.90
0.30
0.25
0.18
PIN 1
INDICATOR
PIN 1
INDICATOR
68
52
1
51
0.50
BSC
EXPOSED
PAD
6.40
6.30 SQ
6.20
35
17
18
8.00 REF
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
1.20 BSC
BOTTOM VIEW
03-12-2015-A
0.90
0.85
0.80
PKG-000000
34
0.60
0.50
0.40
TOP VIEW
COMPLIANT TO JEDEC STANDARDS MO-220-VNND-2
Figure 54. 68-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
10 mm × 10 mm Body, Very Thin Quad
(HCP-68-1)
Dimensions shown in millimeters
NOTE 1
NOTE 6
2.10
2.00
1.90
1.85
1.75
1.65
24.30
24.00
23.70
4.10
4.00
3.90
16.10
16.00
15.90
A
0.35
0.30
0.25
Ø 1.5 ~ 1.6
11.60
11.50
11.40
10.40
10.30
10.20
R0.3
MAX
NOTE 6
NOTE 4
10.40
10.30
10.20
TOP VIEW
Ø 1.5 MIN
A
DETAIL A
DIRECTION OF FEED
NOTE 4
1.20
1.10
1.00 NOTE 5
SECTION A-A
0.25
DETAIL A
R 0.25
02-10-2016-A
NOTES:
1. 10 SPROCKET HOLE PITCH CUMUL ATIVE TOLERANCE ± 0.20
2. CAMBER IN COMPLIANCE WITH EIA 481
3. MATERIAL: CONDUCTIVE BLACK PO LYSTYRENE
4. MEASURED ON A PLANE 0.30 mm ABOVE THE BOTTOM OF
THE POCKET
5. MEASURED FROM A PLANE ON THE INSIDE BOTTOM OF
THE POCKET TO THE TOP SURFACE OF THE CARRIER
6. POCKET POSITION RELATIVE TO SPROCKET HOLE MEASURED
AS TRUE POSITION OF POCKET, NOT POCKET HOLE
Figure 55. LFCSP Tape and Reel Outline Dimensions
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
HMC7044LP10BE
Temperature Range
–40°C to +85°C
Lead Finish
100% matte tin
MSL Rating
MSL-3
Package Description
68-Lead LFCSP_VQ
Package Option
HCP-68-1
HMC7044LP10BETR
–40°C to +85°C
100% matte tin
MSL-3
68-Lead LFCSP_VQ
HCP-68-1
EK1HMC7044LP10B
–40°C to +85°C
1
2
Evaluation Kit
E = RoHS Compliant Part.
Four-digit lot number represented by XXXX.
Rev. B | Page 71 of 72
Branding 2
7044
XXXX
7044
XXXX
HMC7044
Data Sheet
NOTES
©2015–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D13033-0-11/16(B)
Rev. B | Page 72 of 72