[AK4133] AK4133 192kHz 24bit Sample Rate Converter 1. General Description The AK4133 is an 2ch digital sample rate converter (SRC). It converts sample rate of the input audio source (from 8kHz to 192kHz) to 44.1kHz or 48kHz. It is possible also to convert 8kHz, 16kHz or 24kHz into 8kHz, 16kHz or 24kHz. The AK4133 has an internal Oscillator and does not need any external master clocks. It contributes simplifying a system configuration. The AK4133 is suitable for the application interfacing to different sample rates such as Car Audio Systems and DVD recorders. 2. 2 channels Input/Output Asynchronous Sample Rate Converter Input Sample Rate Range (FSI): Output Sample Rate (FSO): Input to Output Sample Rate Ratio: THD+N: Dynamic Range: I/F format: Oscillator for Internal Operation Clock Clock for Master Mode: Soft Mute Function Power Supply: Operating Temperature: Package: Features 8k ~ 192kHz 44.1kHz, 48kHz (@FSI=8k~192kHz) 8kHz, 16kHz, 24kHz (@FSI=8kHz, 16kHz, 24kHz) FSO/FSI= 44.1/192~6 Up to -100dB 110dB (A-weighted, Typ.) MSB justified, I2S compatible 128/256/512fso DVDD= 3.0 ~ 3.6V or 1.7 ~ 1.9V(LDO OFF Mode) 40 ~ 105ºC 20-pin QFN 4mm x 4mm (0.5mm pitch) 015015325-E-01 2016/06 -1- [AK4133] 3. Table of Contents 1. 2. 3. 4. 5. General Description ............................................................................................................................ 1 Features .............................................................................................................................................. 1 Table of Contents ................................................................................................................................ 2 Block Diagram ..................................................................................................................................... 3 Pin Configulations and Functions ....................................................................................................... 3 ■ Pin Layout ......................................................................................................................................... 3 ■ Functions ........................................................................................................................................... 4 ■ Handling of Unused Pin .................................................................................................................... 4 6. Absolute Maximum Ratings ................................................................................................................ 5 7. Recommended Operating Conditions................................................................................................. 5 8. SRC Characteristics ............................................................................................................................ 6 9. Consumption Current .......................................................................................................................... 7 ■ Internal Regurator (VSEL pin= “L”) ................................................................................................... 7 ■ External VD18 (VSEL pin= “H”) ........................................................................................................ 7 10. Filter Characteristics ........................................................................................................................ 8 ■ Sharp Roll-Off Characteristics (SD pin= “L”)..................................................................................... 8 ■ Short Delay Sharp Roll-Off Filter Characteristics (SD pin= “H”) ....................................................... 9 11. DC Characteristics........................................................................................................................... 9 12. Switching Characteristics .............................................................................................................. 10 ■ Clock................................................................................................................................................ 10 ■ Timing ...............................................................................................................................................11 ■ Timing Diagram ............................................................................................................................... 12 13. Functional Description ................................................................................................................... 15 ■ Input and Output sampling rate combination .................................................................................. 15 ■ System Clock and Audio Interface Format for Input Port ............................................................... 15 ■ System Clock for Output PORT ...................................................................................................... 17 ■ Audio Interface Format of the Output Port ...................................................................................... 17 ■ Soft Mute Function .......................................................................................................................... 18 ■ Regulator ......................................................................................................................................... 18 ■ Power Supply .................................................................................................................................. 18 ■ System Reset .................................................................................................................................. 19 ■ Clock Switch Sequence .................................................................................................................. 21 ■ Internal Status Pin ........................................................................................................................... 22 ■ Grounding ans Power Supply Decoupling ...................................................................................... 22 14. Jitter Tolerance .............................................................................................................................. 23 15. Recommended External Circuits................................................................................................... 24 16. Package ......................................................................................................................................... 25 ■ Outline Dimenstions ........................................................................................................................ 25 ■ Material & Lead Finish .................................................................................................................... 25 ■ Marking ............................................................................................................................................ 25 17. Ordering Guide .............................................................................................................................. 26 18. Revision History............................................................................................................................. 26 IMPORTANT NOTICE .......................................................................................................................... 28 015015325-E-01 2016/06 -2- [AK4133] SDTI ILRCK IBICK PCM Input Serial Audio I/F FIR COMB SRC ODIF SMUTE SD SRCE_N Block Diagram PCM Output Serial Audio I/F SMUTE SDTO OLRCK OBICK Output PORT Input PORT IDIF 4. Internal OSC REF TEST Internal Regulator CM1 CM0 OMCLK DVSS DVDD Clock Div. VD18 VSEL PDN Figure 1. AK4133 Block Diagram 5. Pin Configulations and Functions DVDD DVSS VD18 SDTO OBICK 14 13 12 11 5 TEST 20 4 SRCE_N CM1 19 Top View 3 IDIF AK4133 CM0 18 2 17 ODIF SMUTE 16 PDN 1 VSEL 15 Pin Layout SD ■ 10 OLRCK 9 OMCLK 8 SDTI 7 IBICK 6 ILRCK Figure 2. Pin Layout 015015325-E-01 2016/06 -3- [AK4133] ■ Functions No. Pin Name I/O 1 SD I 2 SMUTE I 3 4 CM0 CM1 I I 5 TEST I 6 7 8 9 ILRCK IBICK SDTI OMCLK 10 OLRCK 11 OBICK 12 SDTO I I I I O I O I O I 13 VD18 14 15 DVSS DVDD - 16 VSEL I 17 PDN I O PDN= “L” Status Function Digital Filter Select Pin “H”: Short Delay Sharp Roll-off Filter “L”: Sharp Roll-off Filter Soft Mute Pin When this pin is changed to “H”, soft mute cycle is initiated. When returning “L”, the output mute releases. Output Port Mode and OMCLK Frequency Select #0 Pin Output Port Mode and OMCLK Frequency Select #1 Pin Test pin. Must be connected to DVSS in normal use. It has a pull-down resister 100k. Channel Clock Input Pin for Input PORT Audio Serial Clock Input Pin for Input PORT Audio Serial Data Input Pin for Input PORT External Master Clock Input Channel Clock Output Pin for Output PORT in Master Mode Channel Clock Input Pin for Output PORT in Slave Mode Audio Serial Clock Output Pin for Output PORT in Master Mode Audio Serial Clock Input Pin for Output PORT in Slave Mode Audio Serial Data Output Pin for Output PORT Internal Digital Power Supply Pin, 1.7 1.9V (VSEL= “H”) Regulator Output Pin, Typ. 1.8V (VSEL= “L”) Current must not be taken from this pin. A 10μF (±30%; including the temperature characteristics) capacitor should be connected between this pin and DVSS. When this capacitor is polarized, the positive polarity pin should be connected to the VD18 pin. Digital Ground Pin Digital Power Supply Pin, 3.0 3.6V or 1.7 1.9V Internal Digital Power Supply Select Pin “H”: External Power Supply “L”: Internal Regulator Power-Down Mode Pin “H”: Power up “L”: Power down and reset The AK4133 should be reset once by bringing PDN pin = “L” upon power-up. Audio Interface Format Select Pin for Output PORT Audio Interface Format Select Pin for Input PORT Unlock Status Pin 18 ODIF I 19 IDIF I 20 SRCE_N O Note: * 1. All input pins should not be allowed to float. * 2. CM1-0, ODIF and IDIF pins must be changed when the PDN pin = “L”. ■ - “L” “L” “L” “L” - - “H” Handling of Unused Pin Classification Digital Pin Name Setting SMUTE Connect to DVSS OMCLK Connect to DVSS SRCE_N Open 015015325-E-01 2016/06 -4- [AK4133] 6. Absolute Maximum Ratings (DVSS=0V;* 3) Parameter Digital Internal Digital Input Current, Any Pin Except Supplies Digital Input Voltage (* 4) Power Supplies Symbol DVDD VD18 IIN Min. 0.3 0.3 10 VDIN 0.3 Max. 4.3 2.5 10 DVDD+0.3 or 4.3 105 150 Unit V V mA V Ambient Temperature (Power applied) (* 5) Ta ºC 40 Storage Temperature Tstg ºC 65 Note: * 3. All voltages with respect to ground. * 4. ILRCK, IBICK, SDTI, IDIF, SD, PDN, TEST, OMCLK, CM1-0, ODIF, OBICK (Slave Mode), OLRCK (Slave Mode), SMUTE and VSEL pins * 5. PCB drawing density should be 100% or more. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. 7. Recommended Operating Conditions (DVSS=0V; * 3; VSEL= “L”) Parameter Symbol Min. Typ. Power Supplies Digital DVDD 3.0 3.3 Note: * 3. All voltages with respect to ground. Max. 3.6 Unit V (DVSS=0V;* 3; VSEL= “H”) Parameter Digital Power Supplies Internal Digital (* 6) Difference Max. 1.9 1.9 Unit V V V Symbol DVDD VD18 DVDD-VD18 Min. 1.7 1.7 - Typ. 1.8 1.8 0 Note: * 3. All voltages with respect to ground. * 6. DVDD and VD18 must be connected externally. * AKM assumes no responsibility for the usage beyond the conditions in this data sheet. 015015325-E-01 2016/06 -5- [AK4133] 8. SRC Characteristics (Ta= -40 105ºC; DVDD= 3.0 3.6V at VSEL pin= “L” or DVDD= VD18= 1.7 1.9V at VSEL pin= “H”; DVSS= 0V; Signal Frequency= 1kHz; measurement bandwidth = 20Hz FSO/2; unless otherwise specified.) Parameter Symbol Min. Typ. Max. Unit Input Sample Rate FSI 8 192 kHz Output Sample Rate FSO 44.1 48 kHz Output Sample Rate (FSI: 8kHz, 16kHz, 24kHz) FSO 8 24 kHz THD+N (Input= 1kHz, 0dBFS, * 7) FSO/FSI= 48kHz/48kHz -111 dB FSO/FSI= 44.1kHz/48kHz -106 dB FSO/FSI= 48kHz/192kHz -111 dB Worst Case (FSO/FSI= 44.1kHz/96kHz) -105 dB Dynamic Range (Input= 1kHz, -60dBFS, * 7) FSO/FSI= 48kHz/48kHz 112 dB FSO/FSI= 44.1kHz/48kHz 112 dB FSO/FSI= 48kHz/192kHz 112 dB Worst Case (FSO/FSI= 44.1kHz/192kHz) 111 dB Dynamic Range (Input= 1kHz, -60dBFS, A-weighted, * 7) FSO/FSI= 48kHz/48kHz 115 dB Ratio between Input and Output Sample Rate FSO/FSI 44.1/192 6 Note: * 7. Measured by Audio Precision, System Two. 015015325-E-01 2016/06 -6- [AK4133] 9. Consumption Current ■ Internal Regurator (VSEL pin= “L”) (Ta= -40 105ºC) Parameter Symbol Min. Power Supply Current Normal operation: FSI= FSO= 48kHz at Master Mode : DVDD= 3.3V DVDD= 3.6V FSI= 96kH, FSO= 48kHz at Master Mode : DVDD=3.3V DVDD=3.6V FSI= 192kH, FSO= 48kHz at Master Mode : DVDD=3.3V DVDD=3.6V Power down: PDN = “L” (* 8) DVDD=3.6V Note: * 8. All digital input pins including clock pins are connected to DVSS. Typ. Max. Unit 6 - 8 mA mA 10 - 12 mA mA 16 - 18 mA mA 10 100 A ■ External VD18 (VSEL pin= “H”) (Ta= -40 105ºC) Parameter Symbol Min. Typ. Max. Power Supply Current Normal operation: FSI=FSO=48kHz at Master Mode: DVDD=VD18=1.8V 6 DVDD=VD18=1.9V 8 FSI=96kH, FSO=48kHz at Master Mode: DVDD=VD18=1.8V 10 DVDD=VD18=1.9V 12 FSI=192kH, FSO=48kHz at Master Mode: DVDD=VD18=1.8V 16 DVDD=VD18=1.9V 18 Power down: PDN = “L” (* 9) DVDD=VD18=1.9V 10 100 Note: * 9. Except the VSELL pin, all digital input pins including clock pins are connected to DVSS. 015015325-E-01 Unit mA mA mA mA mA mA A 2016/06 -7- [AK4133] 10. Filter Characteristics ■ Sharp Roll-Off Characteristics (SD pin= “L”) (Ta= -40 105ºC; DVDD= 3.0 3.6V at VSEL pin= “L” or DVDD= VD18= 1.7 1.9V at VSEL pin= “H”; DVSS= 0V) Parameter Symbol Min. Typ. Max. Unit Digital Filter Passband PB 0 0.4583FSI kHz 0.985 FSO/FSI 6.000 0.01dB PB 0 0.4167FSI kHz 0.714 FSO/FSI 0.985 PB 0 0.2182FSI kHz 0.536 FSO/FSI 0.714 PB 0 0.2177FSI kHz 0.492 FSO/FSI 0.536 PB 0 0.1948FSI kHz 0.324 FSO/FSI 0.492 PB 0 0.0917FSI kHz 0.246 FSO/FSI 0.324 PB 0 0.0826FSI kHz 0.1667 FSO/FSI 0.246 Stopband SB 0.5417FSI kHz 0.985 FSO/FSI 6.000 SB 0.5021FSI kHz 0.714 FSO/FSI 0.985 SB 0.2974FSI kHz 0.536 FSO/FSI 0.714 SB 0.2813FSI kHz 0.492 FSO/FSI 0.536 SB 0.2604FSI kHz 0.324 FSO/FSI 0.492 SB 0.1573FSI kHz 0.246 FSO/FSI 0.324 SB 0.1471FSI kHz 0.1667 FSO/FSI 0.246 Passband Ripple PR ±0.01 dB 0.1667 FSO/FSI 6.000 Stopband SA -92.2 dB 0.985 FSO/FSI 6.000 Attenuation SA -92.2 dB 0.714 FSO/FSI 0.985 SA -92.8 dB 0.536 FSO/FSI 0.714 SA -91.9 dB 0.492 FSO/FSI 0.536 SA -92.7 dB 0.324 FSO/FSI 0.492 SA -93.9 dB 0.246 FSO/FSI 0.324 SA -92.1 dB 0.1667 FSO/FSI 0.246 Group Delay (* 10) GD 60 1/fs Note: * 10. This value is the time from a rising edge of LRCK after L/R data is input to a rising edge of LRCK before the L/R data is output when there is no phase difference between the input and the output data. 015015325-E-01 2016/06 -8- [AK4133] ■ Short Delay Sharp Roll-Off Filter Characteristics (SD pin= “H”) (Ta= -40 105ºC; DVDD= 3.0 3.6V at VSEL pin= “L” or DVDD= VD18= 1.7 1.9V at VSEL pin= “H”; DVSS= 0V) Parameter Symbol Min. Typ. Max Unit Digital Filter Passband PB 0 0.4583FSI kHz 0.985 FSO/FSI 6.000 0.01dB PB 0 0.4167FSI kHz 0.714 FSO/FSI 0.985 PB 0 0.2182FSI kHz 0.536 FSO/FSI 0.714 PB 0 0.2177FSI kHz 0.492 FSO/FSI 0.536 PB 0 0.1948FSI kHz 0.324 FSO/FSI 0.492 PB 0 0.0917FSI kHz 0.246 FSO/FSI 0.324 PB 0 0.0826FSI kHz 0.1667 FSO/FSI 0.246 Stopband SB 0.5417FSI kHz 0.985 FSO/FSI 6.000 SB 0.5021FSI kHz 0.714 FSO/FSI 0.985 SB 0.2974FSI kHz 0.536 FSO/FSI 0.714 SB 0.2813FSI kHz 0.492 FSO/FSI 0.536 SB 0.2604FSI kHz 0.324 FSO/FSI 0.492 SB 0.1573FSI kHz 0.246 FSO/FSI 0.324 SB 0.1471FSI kHz 0.1667 FSO/FSI 0.246 Passband Ripple PR ±0.01 dB 0.1667 FSO/FSI 6.000 Stopband SA -92.8 dB 0.985 FSO/FSI 6.000 Attenuation SA -93.5 dB 0.714 FSO/FSI 0.985 SA -94.5 dB 0.536 FSO/FSI 0.714 SA -92.9 dB 0.492 FSO/FSI 0.536 SA -92.0 dB 0.324 FSO/FSI 0.492 SA -94.4 dB 0.246 FSO/FSI 0.324 SA -93.8 dB 0.1667 FSO/FSI 0.246 Group Delay (* 10) GD 18 1/fs Note: * 10. This value is the time from a rising edge of LRCK after L/R data is input to a rising edge of LRCK before the L/R data is output when there is no phase difference between the input and the output data. 11. DC Characteristics (Ta= -40 105ºC; DVDD= 3.0 3.6V at VSEL pin= “L” or DVDD= VD18= 1.7 1.9V at VSEL pin= “H”; DVSS= 0V) Parameter Symbol Min. Typ. Max. Unit High-Level Input Voltage (* 11) VIH 70%DVDD V Low-Level Input Voltage (* 11) VIL 30%DVDD V VOH V High-Level Output Voltage (Iout=400A) (* 12) DVDD0.4 VOL 0.4 V Low-Level Output Voltage (Iout= 400A) (* 12) (* 11, Except TEST pin) 10 10 A Input Leakage Current Iin TEST pin 72 10 A 100kΩ Pull down Notes: * 11. ILRCK, IBICK, SDTI, IDIF, SD, PDN, TEST, OMCLK, CM0, CM1, ODIF, OBICK (Slave Mode), OLRCK (Slave Mode), SMUTE and VSEL pins * 12. SRCE_N, SDTO, OBICK (Master Mode) and OLRCK (Master Mode) pins 015015325-E-01 2016/06 -9- [AK4133] 12. Switching Characteristics ■ Clock (Ta= -40 105ºC; DVDD= 3.0 3.6V at VSEL pin= “L” or DVDD= VD18= 1.7 1.9V at VSEL pin= “H”; CL= 20pF) Parameter Symbol Min. Typ. Max. Unit Master Clock Input (OMCLK) 128 FSO: Frequency fCLK 1.024 6.144 MHz Pulse Width Low tCLKL 80 ns Pulse Width High tCLKH 80 ns 256 FSO: Frequency fCLK 2.048 12.288 MHz Pulse Width Low tCLKL 40 ns Pulse Width High tCLKH 40 ns 512 FSO: Frequency fCLK 4.096 24.576 MHz Pulse Width Low tCLKL 20 ns Pulse Width High tCLKH 20 ns Channel Clock for Input Port (ILRCK) Frequency Normal speed Mode FSIN 8 54 kHz Double speed Mode FSID 54 108 kHz Quad speed Mode FSIQ 108 192 kHz Duty Cycle dILRCK 48 50 52 % Channel Clock for Output Port (OLRCK) Slave Mode Frequency (FSI: 8kHz~192kHz) FSO 44.1 48 kHz Frequency (FSI: 8kHz, 16kHz, 24kHz) FSO 8 24 kHz Duty Cycle dOLRCK 48 50 52 % Master Mode Frequency (FSI: 8kHz~192kHz) FSO 44.1 48 kHz Frequency (FSI: 8kHz, 16kHz, 24kHz) FSO 8 24 kHz Duty Cycle dOLRCK 50 % 015015325-E-01 2016/06 - 10 - [AK4133] ■ Timing (Ta=-40 +105C; DVDD=3.03.6V at VSEL pin=”L” or DVDD=VD18=1.7V1.9V at VSEL pin=”H”; CL=20pF) Parameter Symbol Min. Typ. Max Unit Audio Interface Timing Input PORT IBICK Period Normal speed Mode tIBCK 1/256 FSIN ns Double speed Mode tIBCK 1/128 FSID ns Quad speed Mode tIBCK 1/64 FSIQ ns IBICK Pulse Width Low tIBCKL 27 ns IBICK Pulse Width High tIBCKH 27 ns ILRCK Edge to IBICK “↑” (* 13) tILRB 15 ns IBICK “↑” to ILRCK Edge (* 13) tIBLR 15 ns SDTI Hold Time from IBICK “↑” tISDH 15 ns SDTI Setup Time to IBICK “↑” tISDS 15 ns Output PORT (Slave Mode) OBICK Period Normal speed Mode tOBCK 1/256 FSON ns OBICK Pulse Width Low tOBCKL 27 ns OBICK Pulse Width High tOBCKH 27 ns OLRCK Edge to OBICK “↑” (* 13) tOLRB 20 ns OBICK “↑” to OLRCK Edge (* 13) tOBLR 20 ns OLRCK to SDTO(MSB) (Except I2S Mode) tOLRS 20 ns OBICK “↓” to SDTO tOBSD 20 ns Output PORT (Master Mode) OBICK Frequency fOBCK 64 FSO Hz OBICK Duty dOBCK 50 % OBICK “↓” to OLRCK Edge tOMBLR -20 20 ns OBICK “↓” to SDTO tOBSD -20 20 ns Reset Timing PDN Pulse Width (* 14) tPD 150 ns PDN pin Pulse Width of Spike Noise tPDS 0 50 ns Suppressed by Input Filter (* 15) Notes: * 13. BICK rising edge must not occur at the same time as LRCK edge. * 14. The AK4133 can be rest by bringing the PDN pin = “L”. * 15. Spike noise width of “L” pulse suppressed by input filter of the PDN pin. 015015325-E-01 2016/06 - 11 - [AK4133] ■ Timing Diagram Master Clock 1/fCLK VIH OMCLK VIL tCLKH tCLKL Figure 3. OMCLK Clock Timing Input Port Clock 1/FSI VIH ILRCK VIL tILRCH tILRCL dILRCK=tILRCH(or tILRCL)FSI100 tIBCK VIH IBICK VIL tIBCKH tIBCKL Figure 4. ILRCK, IBICK Clock Timing Input Port Timing VIH ILRCK VIL tIBLR tILRB VIH IBICK VIL tISDS tISDH VIH SDTI VIL Figure 5. Input PORT Audio Interface Timing (Slave Mode) 015015325-E-01 2016/06 - 12 - [AK4133] Output Port Clock (Slave Mode) 1/FSO VIH OLRCK(I) VIL tOLRCH tOLRCL dOLRCK=tOLRCH(or tOLRCL)FSO100 tOBCK VIH OBICK(I) VIL tOBCKH tOBCKL Figure 6. OLRCK, OBICK Clock Timing (Slave Mode) Output Port Timing (Slave Mode) VIH OLRCK(I) VIL tOBLR tOLRB VIH OBICK(I) VIL tOLRS tOBSD 50%DVDD SDTO Figure 7. Output PORT Audio Interface Timing (Slave Mode) 015015325-E-01 2016/06 - 13 - [AK4133] Output Port Clock (Master Mode) 1/FSO 50%DVDD OLRCK(O) tOLRCH tOLRCL dOLRCK=tOLRCH(or tOLRCL)FSO100 1/fOBCK 50%DVDD OBICK(O) tOBCKH tOBCKL dOBCK=tOBCKH(or tOBCKL)fOBCK100 Figure 8. OLRCK, OBICK Clock Timing (Master Mode) Output Port Timing (Master Mode) 50%DVDD OLRCK(O) tOMBLR 50%DVDD OBICK(O) tOBSD 50%DVDD SDTO Figure 9. Output PORT Audio Interface Timing (Master Mode) Power-down Timing tPD VIH PDN VIL tPDS D Figure 10. Power Down and Reset Pulse 015015325-E-01 2016/06 - 14 - [AK4133] 13. Functional Description ■ Input and Output sampling rate combination The table below shows the possible combination of the input sampling rate and output sampling rate. Table 1. Combinations of FSI and FSO FSI [kHz] 8 11.025 12 16 22.05 24 32 44.1 48 88.2 96 176.4 192 8 Y Y Y - 11.025 - 12 - FSO 16 Y Y Y - [kHz] 22.05 - 24 Y Y Y - 32 - 44.1 Y Y Y Y Y Y Y Y Y Y Y Y Y 48 Y Y Y Y Y Y Y Y Y Y Y Y Y Y: Available -: Not Available ■ System Clock and Audio Interface Format for Input Port The audio interface format is controlled by the IDIF pin. The data format is MSB first in 2's complement. The SDTI input data is clocked in on a rising edge of the IBICK. The audio interface format of the input port should be changed while the PDN pin = “L”. Mode 0 IDIF Pin L 1 H Table 2. Input PORT Audio Interface Format SDTI Format ILRCK IBICK 24-bit, MSB justified Input Input 24 or 16-bit, I2S Compatible 16-bit, I2S Compatible IBICK Frequency 256FSI or 64FSI 256FSI or 64FSI 32FSI (* 16) Note: * 16. When IBICK = 32FSI, only 16-bit I2S Compatible is supported. 015015325-E-01 2016/06 - 15 - [AK4133] ILRCK 0 1 2 23 24 25 32 33 63 0 1 2 23 24 25 32 33 63 0 1 IBICK(128fs) SDTI 23 22 1 0 23 22 1 0 23 1 0 1 2 12 13 14 24 25 IBICK(64fs) 31 0 1 2 12 13 14 24 25 31 0 1 4 SDTI 23 22 12 11 10 0 23 22 20 19 18 Lch Data 0 23 Rch Data 23: MSB, 0:LSB Figure 11. Mode0 Timing (24-bit MSB) ILRCK 0 1 2 23 24 25 32 33 63 0 1 2 23 24 25 32 33 63 0 1 14 24 25 31 0 1 11 12 15 0 1 IBICK(128fs) SDTI 23 0 1 2 2 1 12 0 13 23 14 24 25 31 0 1 2 2 1 12 0 13 IBICK(64fs) SDTI 23 0 1 0 12 11 10 2 5 6 7 23 11 12 15 1 0 12 2 11 10 5 6 0 7 IBICK(32fs) SDTI 0 15 12 11 10 6 5 2 1 0 15 12 11 10 Lch Data 6 5 2 1 0 Rch Data 15: MSB, 0:LSB Figure 12. Mode1 Timing (24-bit/16-bit I2S) 015015325-E-01 2016/06 - 16 - [AK4133] ■ System Clock for Output PORT The output ports work in both master mode and slave mode. In master mode, the output port is operated with OLRCK and OBICK generated from OMCLK. OLRCK and OBICK clocks are output from the OLRCK pin and OBICK pin, respectively. In slave mode, the output port is operated by input clocks from the OLRCK pin and the OBICK pin. The OMCLK pin is not used in slave mode. It must be connected to DVSS. The CM1-0 pins select master or slave mode. Table 3. Output PORT Master/Slave Mode Control (AK4133) Mode CM1 pin CM0 pin Master / Slave OMCLK Frequency 0 1 2 3 L L H H L H L H Master Slave Master Master 256FSO Not used. (* 17) 512FSO 128FSO Note: * 17. The OMCLK pin must be connected to DVSS in slave mode. ■ Audio Interface Format of the Output Port The ODIF pin controls the audio interface mode of the output port. The data format is MSB first in 2's complement. The data is output on a falling edge of OBICK from the SDTO pin. The audio interface format of the output port should be changed while the PDN pin = “L”. Mode 0 1 ODIF pin L H Table 4. Output PORT Audio Interface Format SDTO Format OBICK (Slave) MSB justified 48fs or 32fs I2S Compatible 48fs or 32fs OBICK (Master) 64fs 64fs OLRCK 0 1 2 15 16 19 20 23 24 31 0 1 2 15 16 19 20 23 24 31 0 1 25 31 0 1 OBICK(64fs) SDTO(O) 23 22 4 19 18 0 23 22 19 4 18 Lch Data 0 Rch Data 23: MSB, 0:LSB @ 24-bit Figure 13. Mode 0 MSB Justified Timing OLRCK 0 1 2 15 16 19 20 24 25 31 0 1 2 15 16 19 20 24 OBICK(64fs) SDTO(O) 23 20 19 5 0 23 20 19 Lch Data 5 0 Rch Data 23: MSB, 0:LSB @ 24-bit Figure 14. Mode1 I2S Compatible Timing 015015325-E-01 2016/06 - 17 - [AK4133] ■ Soft Mute Function The AK4133 has soft mute function. Soft mute operation is controlled by the SMUTE pin. If the SMUTE pin is set to “H”, the SRC output data is attenuated to dB (“0”) in 1024 OLRCK cycles. When the SMUTE pin is returned to “L”, the mute is cancelled and the output attenuation level gradually changes to 0dB in 1024 OLRCK cycles. If the soft mute is cancelled before attenuating to dB after starting soft mute operation, attenuation is discontinued and the attenuation level is returned to 0dB by the same cycle. Soft mute is effective for changing the signal source without stopping the signal transmission. SMUTE 0dB (1) (2) (3) Attenuation Level dB SDTO Figure 15. Soft Mute (1) The output data is attenuated to (“0”) in 1024 OLRCK cycles by setting the SMUTE pin= “H”. (2) The attenuation level returns to 0dB in 1024 OLRCK cycles by setting the SMUTE pin= “L”. (3) If the soft mute is cancelled within 1024 OLRCK cycles, attenuation is discontinued and the attenuation level is returned to 0dB by the same cycle. ■ Regulator The AK4133 has an internal regulator which suppresses the voltage to 1.8V from DVDD (3.3V). The generated 1.8V power is used as power supply for internal circuit. When over-current is flowed to the regulator output, over-current detection circuit works. When over-voltage is flowed to the regulator output, over-voltage detection circuit works. The regulator block is powered-down and the AK4133 becomes reset state when over-current detection circuit or over-voltage detection circuit is operated. The AK4133 does not return to normal operation without a reset by the PDN pin when these detection circuits are worked. When over-current or over-voltage is detected, the PDN pin should be brought into “L” at once, and should be set to “H” again to recover normal operation. The SRCE_N pin indicates the internal status of the device. It outputs “L” in SRC normal operation, and outputs “H” when over-current or over-voltage is detected. ■ Power Supply The AK4133 supports 1.8V and 3.3V power supply voltages. Set the VSEL pin according to applying voltage. The VSEL pin should be set to “L” when using a 3.3V power supply. The internal regulator is turned ON and 1.8V power for internal circuits will be generated using 3.3V power from the DVDD pin. The VSEL pin should be set to “H” when using a 1.8V power supply. The internal regulator is turned OFF and the V18 pin becomes power supply pin for internal circuits. 015015325-E-01 2016/06 - 18 - [AK4133] ■ System Reset Bringing the PDN pin = “L” sets the AK4133 power-down mode and initializes the digital filters. The AK4133 should be reset once by bringing the PDN pin to “L” upon power-up. The internal SRC circuit is powered-up on ILRCK and OLRCK input after a power-up period of the internal regulator (PDN pin = “H”). The data output time of the SDTO pin depends on the LRCK and OLRCK input when the PDN pin = “H”. (Figure 16, Figure 17) Case 1: ILRCK and OLRCK are input when the PDN pin= “H” Case 1 External clocks (Input port) Don’t care Input Clocks 1 Input Clocks 2 Don’t care SDTI Don’t care Input Data 1 Input Data 2 Don’t care External clocks (Output port) Don’t care Output Clocks 1 Output Clocks 2 Don’t care (4) PDN (1) (2) (2) (3) < 25.2ms (Internal state) Power-down SDTO LDO Up& Ratio detection & GD “0” data (3) < 25.2ms Normal operation Normal data PD LDO Up& Ratio detection & GD “0” data Normal operation Power-down Normal data “0” data SRCE_N LDO: Internal Regurator GD: Group Delay PD: Power Down Figure 16. System Reset Case1 (1) The SDTO pin outputs “L” and the SRCE_N pin outputs “H” when the PDN pin= “L”. (2) The Internal regulator is powered up by bringing the PDN pin = “H” after operation clock is input. Then, SRC circuit is powered up and starts Ratio detection by ILRCK and OLTCK. SDTO is output after group delay period when Ratio detection is completed. Until then the SDTO outputs “L” and the SRCE_N pin outputs “H”. The time until SDTO output become enabled after setting the PDN pin to “H” is 25.2msec (Max.). (3) The SRCE_N pin outputs “L” when SDTO data output becomes enabled. (4) The statuses of the CM1-0, ODIF and IDIF pins should be changed while the PDN pin= “L”. 015015325-E-01 2016/06 - 19 - [AK4133] Case2: ILRCK and OLRCK are not input when the PDN pin= “H” Case 2 External clocks (Input port) (No Clock) SDTI External clocks (Output port) PDN (1) (Internal state) Power-down SDTO Input Clocks Don’t care (Don’t care) Input Data Don’t care (Don’t care) Output Clocks Don’t care (2) 5ms LDO Up (3) < 20.2ms wait ILRCK Ratio detection & GD “0” data Normal operation Power-down Normal data “0” data (4) SRCE_N LDO: Internal Regurator GD: Group Delay Figure 17. System Reset Case2 (1) The SDTO pin outputs “L” and the SRCE_N pin outputs “H” when the PDN pin= “L”. (2) The internal regulator is powered up by PDN pin = “H” and wait for ILRCK and OLRCK. (3) SRC circuit is powered up and sampling frequency ratio detection starts when ILRCK and OLRCK are input. SDTO output starts after group delay period when the frequency ratio detection is completed. Until then, the SDTO output is “L” and the SRCE_N pin outputs “H”. The time until SDTO output becomes enabled after ILRCK and OLPCK input is 20.2msec (Max.). (4) The SRCE_N pin outputs “L” when SDTO data output becomes enabled. 015015325-E-01 2016/06 - 20 - [AK4133] ■ Clock Switch Sequence The AK4133 must be reset by bringing the PDN pin to “L” when changing operation clocks. Clock change sequence is shown in Figure 18. External clocks (input port or output port) Clocks 1 (Don’t care) (1) PDN Clocks 2 (4) < 25.2ms (Internal state) normal operation Power down (2) SDTO LDO up & Ratio detection & GD (2) normal data SMUTE normal operation normal data (3) (5) 1024/fso 1024/fso Att.Level 0dB -dB Figure 18. Clock Change Sequence (1) Set the PDN pin to “L”, and change clock frequencies of the IDIF pin, ODIF pin and CM1-0 pins. (2) Click noise may occur when the STDO output is changed. (3) Mute the SDTO output by setting the SMUTE pin to “H” before setting the PDN pin to “L” if the click noise influences system applications. This click noise can also be prevented by setting “0” to the SDTI from GD before the PDN pin changes to “L”. It makes the data on SDTO remain as “0”. (4) Set the PDN pin to “H” after changing the clock of the IDIF pin, ODIF pin or CM1-0 pins. (5) Set the SMUTE pin to “L” to release the soft mute if the soft mute function is enabled. The AK4133 has automatic internal reset function for when ILRCK or OLRCK frequency is changed. The behavior of the device when ILRCK or OLRCK frequency is changed is shown below. ▪ When the frequency of ILRCK at input port is changed without a reset by the PDN pin. When the difference of internal oscillator clock number in one ILRCK cycle between before and after changing ILRCK frequency (FSO/FSI ratio should be stabilized) is more than 1/16 for 8cycles (*), an internal reset is made automatically and sampling frequency ratio detection is executed again. The SDTO pin outputs “L” when the internal reset is made, and SRC data is output after 162FSI(O) (FSI(O) is lower frequency between FSI and FSO). When the above condition (*) is not satisfied, the internal reset mentioned before will not be executed. It takes 5148/FSO (max. 643.5ms@FSO=8kHz) (* 18) to output normal SRC data. Distorted data may be output until normal SRC output. When ILRCK is stopped, an internal reset is executed automatically. It takes 162FSI(O) (FSI(O) is lower frequency between FSI and FSO) to output normal SRC data after ILRCK is input again. 015015325-E-01 2016/06 - 21 - [AK4133] ▪ When the frequency of OLRCK at output port is changed without a reset by the PDN pin When the difference of internal oscillator clock number in one OLRCK cycle between before and after changing OLRCK frequency (FSO/FSI ratio should be stabilized) is more than 1/16 for 8cycles (*), an internal reset is made automatically and sampling frequency ratio detection is executed again. SDTO outputs “L” when the internal reset is made, and SRC data is output after 162FSI(O) (FSI(O) is lower frequency between FSI and FSO). When the above condition (*) is not satisfied, the internal reset mentioned before will not be executed. It takes 5148/FSO (max. 643.5ms@FSO=8kHz) (* 18) to output normal SDTO data. Distorted data may be output until normal SDTO output. When OLRCK is stopped, an internal reset is executed automatically. It takes 162FSI(O) (FSI(O) is lower frequency between FSI and FSO) [sec] to output normal SDTO data after ILRCK is input again. Notes: * 18. When FSO=8kHz and FSO/FSI ratio is changed from 1/6 to 1/5.99. ■ Internal Status Pin The SRCE_N pin outputs internal state of the device. It outputs “H” while the PDN pin = “L”. SRC data is output from the SDTO pin when the PDN pin = “H” and the sampling frequency ratio detection is completed if the internal regulator is operated normally. An internal limit flag is set when an over current or over voltage flows at the internal regulator. An ORed result of the internal limit flag and an inverted flag of the ratio detection completion of SRC is output from the SRCE_N pin. Limit Flag at Regulator “L” Normal Operation “H” Over Current (Voltage) Detect Ratio Detection End Flag at SRC SRCE_N Pin Figure 19. Internal Flag and SRCE_N Pin Output ■ Grounding ans Power Supply Decoupling The AK4133 requires careful attention to power supply and grounding arrangements. Decoupling capacitors should be placed as near as possible to the supply pins. 015015325-E-01 2016/06 - 22 - [AK4133] 14. Jitter Tolerance Figure 20 shows the jitter tolerance to ILRCK and IBICK. The jitter quantity is defined by the jitter frequency and the jitter amplitude. When the jitter amplitude is 0.02UIpp or less, the AK4133 operates normally regardless of the jitter frequency. Jittter Amplitude [UIpp] 10.00 1.00 0.10 (2) 0.01 (1) 0.00 1 10 100 1000 10000 100000 Jittter Frequency [Hz] Figure 20. Jitter Tolerance This is an evaluation result with synchronous input data to ILRCK and IBICK when jitter is added. The area (1) and (2) border is the the jitter amplitude of ILRCK just before THD+N degradation starts. Please use the jitter amplitude of the area (1). (1) Normal Operation (2) There is a possibility that the output data is lost. 1UI (Unit Interval) is one cycle of IBICK. 1[UIpp] = 1/48kHz = 20.8μsec when FSI is 48kHz. 015015325-E-01 2016/06 - 23 - [AK4133] 15. Recommended External Circuits Figure 21 and Figure 22 show the system connection diagram. Digital 3.3V DSP2 Regulator: Enable 10 + + 10 OBICK 11 VD18 13 DVSS 14 0.1 DVDD 15 0.1 SDTO 12 16 VSEL OLRCK 10 17 PDN Control AK4133 OMCLK 9 SDTI 8 IBICK 7 ILRCK 6 18 ODIF Top View 19 IDIF 5 TEST 4 CM1 3 CM0 2 SMUTE 1 SD 20 SRCE_N Mater Clock DSP1 Output PORT: Master Mode Control Figure 21. Typical Connection Diagram (Output Port: Master Mode, Regulator: Enable) Digital 1.8V DSP2 10 + + OBICK 11 SDTO 12 VD18 13 16 VSEL OLRCK 10 17 PDN Control AK4133 OMCLK 9 SDTI 8 IBICK 7 ILRCK 6 18 ODIF Top View 19 IDIF 5 TEST 4 CM1 3 CM0 2 SMUTE 1 SD 20 SRCE_N DSP1 Digital 1.8V 10 0.1 DVSS 14 0.1 DVDD 15 Regulator: Disable Output PORT: Slave Mode Control Figure 22. Typical Connection Diagram (Output Port: Slave Mode, Regulator: Disable) 015015325-E-01 2016/06 - 24 - [AK4133] 16. Package ■ Outline Dimenstions 20-pin QFN (Unit: mm) * 19. The exposed pad on the bottom surface of the package must be open or connected to DVSS. ■ Material & Lead Finish Package Molding Compound: Lead Frame Material: Pin Surface Treatment: ■ Epoxy Cu Solder (Pb free) Plate Marking 4133 XXXX 1 1) 2) 3) Pin #1 indication Date Code : XXXX (4 digits) Marketing Code : 4133 015015325-E-01 2016/06 - 25 - [AK4133] 17. Ordering Guide 40 ~ 105ºC 20-pin QFN (0.5mm pitch) Evaluation Board for AK4132 AK4133VN AKD4132 18. Revision History Date (Y/M/D) 15/12/09 16/06/20 Revision 00 01 Reason First Edition Spec. Added Page Contents 1 16/06/20 01 Spec. Added 1 16/06/20 01 Spec. Added 6 16/06/20 01 Spec. Added 10 16/06/20 01 Spec. Added 10 16/06/20 01 Spec. Added 15 16/06/20 01 Spec. Added 17 16/06/20 01 Spec. Added 19 16/06/20 01 Spec. Added 20 General Description “It is possible also to convert 8kHz, 16kHz or 24kHz into 8kHz, 16kHz or 24kHz.” added Features Output Sample Rate (FSO): 8kHz, 16kHz, 24kHz (@FSI: 8kHz, 16kHz, 24kHz) added. SRC Characteristics “Output Sample Rate (FSI: 8kHz,16kHz, 24kHz) min. 8kHz, max. 24kHz” added Switching Characteristics Master Clock Input (OMCLK) 128 FSO: min.5.6448MHz min. 1.024MHz 256 FSO: min.11.2896MHz min. 2.048MHz 512 FSO: min.22.5792MHz min. 4.096MHz Switching Characteristics Channel Clock for Output Port (OLRCK) Slave Mode “Frequency (FSI: 8kHz, 16kHz, 24kHz) min.8kHz, max. 24kHz” added Master Mode Frequency (FSI: 8kHz, 16kHz, 24kHz) “min.8kHz, max. 24kHz” added Functional Description ”■Input and Output sampling rate combination” added. ■ System Clock for Output PORT The FSO column deleted from Table 3 “Output PORT Master/Slave Mode Control”. (FSO has no meaning in Table 3.) ■ System Reset Figure 16 LDO up & Ratio detection & GD 9.6ms 25.2ms ■ System Reset Figure 17 Ratio detection & GD 4.6ms 20.2ms 015015325-E-01 2016/06 - 26 - [AK4133] Date (Y/M/D) 16/06/20 Revision 01 Reason Spec. Added Page 21 Contents ■ Clock Switch Sequence Figure 18 LDO up & Ratio detection & GD 9.6ms 25.2 ms Description (Max. 116.7ms@FSO=44.1kHz) (Max. 643ms@FSO=8kHz) 16/06/20 01 Spec. Added 22 ■ Clock Switch Sequence Description (Max. 116.7ms@FSO=44.1kHz) (Max. 643ms@FSO=8kHz) 015015325-E-01 2016/06 - 27 - [AK4133] IMPORTANT NOTICE 0. Asahi Kasei Microdevices Corporation (“AKM”) reserves the right to make changes to the information contained in this document without notice. When you consider any use or application of AKM product stipulated in this document (“Product”), please make inquiries the sales office of AKM or authorized distributors as to current status of the Products. 1. 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This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of AKM. 015015325-E-01 2016/06 - 28 -