ICST ICS83841BHT 20 bit, ddr sdram 2:1 mux Datasheet

ICS83841
Integrated
Circuit
Systems, Inc.
20 BIT, DDR SDRAM 2:1 MUX
GENERAL DESCRIPTION
FEATURES
The ICS83841 is a 20 Bit, DDR SDRAM 2:1 MUX
and is a member of the HiPerClockS™ family of
HiPerClockS™ High Performance Clock Solutions from ICS. The
device has 20 host lines and each host line can
be passed to 2 data ports. The host/data ports
are compatible with single-ended SSTL-2 and the device operates from a 2.5V supply.
• Forty low skew single-ended DIMM ports
ICS
• One SSTL-2 compatible select input
• Maximum Switching Speed: 3ns
• Output skew: 180ps (maximum)
• ron = 20Ω (typical)
• Full 2.5V supply modes
Guaranteed low output skew makes the ICS83841 ideal for
demanding applications which require well defined performance
and repeatability.
• 0°C to 70°C ambient operating temperature
• Available in both standard and lead-free RoHS compliant
packages
LOGIC DIAGRAM
SIMPLIFIED SCHEMATIC
ron
DH0
DA0
Sw
Sw
DHx
DB0
DAx or DBx
RPD
ron
DH19
DA19
Sw
Sw
S
DB19
S
SW
PIN ASSIGNMENT
1
2
3
4
5
6
7
8
9
10
A
DB17
DA17
DB16
DB15
DA15
DB14
DA14
DA13
DB12
DA12
B
DA18
DH17
DH16
DA16
DH15
DH14
DB13
DH13
DH12
DB11
C
DB18
DH18
GND
GND
D
DA19
GND
E
DB19
DH19
S
F
DA0
DH0
VDD
G
H
DB0
GND
DA1
DH1
J
DB1
DH2
DH3
K
DA2
DB2
DA3
83841BH
DH11
DA11
GND
DB10
VDD
DH10
DA10
VDD
DH9
DB9
GND
DA9
DH8
DB8
GND
GND
DB3
DH4
DH5
DA6
DH6
DH7
DA8
DA4
DB4
DA5
DB5
DB6
DA7
DB7
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1
ICS83841
72-Ball TFBGA
6mm x 6mm x 1.2mm
package body
H Package
Top View
REV. A JANUARY 20, 2006
ICS83841
Integrated
Circuit
Systems, Inc.
20 BIT, DDR SDRAM 2:1 MUX
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
E8, F3, F8
VDD
C5, C6, D2, D9, G2, G9, H5, H6
GN D
E3
S
B2, B3, B5, B6, B8, B9,
C2 C9, E2, E9, F2, F9, H2,
H9, J2, J3, J5, J6, J8, J9
A2, A5, A7, A8, A10, B1,
B4, C10, D1, E10, F1, G10, H1,
J7, J10, K1, K3, K4, K6, K9
A1, A3, A4, A6, A9, B7,
B10, C1, D10, E1, F10, G1, H10,
J1, J4, K2, K5, K7, K8, K10
DH17, DH16, DH15, DH14, DH13, DH12,
DH18, DH11, DH19, DH10, DH0, DH9, DH1,
DH8, DH2, DH3, DH4, DH5, DH6, DH7
DA17, DA15, DA14, DA13, DA12, DA18,
DA16, DA11, DA19, DA10, DA0, DA9, DA1,
DA6, DA8, DA2, DA3, DA4, DA5, DA7
DB17, DB16, DB15, DB14, DB12, DB13,
DB11, DB18, DB10, DB19, DB9, DB0, DB8,
DB1, DB3, DB2, DB4, DB5, DB6, DB7
Description
Power Positive supply pins.
Power Power supply ground.
Control Input. Selects Host
Input
Por t function per Table 3.
Por t
Host por ts.
Por t
DIMM por ts.
Por t
DIMM por ts.
TABLE 2. PIN CHARACTERISTICS
Maximum
Units
CIN
Symbol Parameter
Control Pin Capacitance
Test Conditions
VI = 0V or VDD
Minimum
Typical
5
pF
CON
Channel on Capacitance
VIN = 1.5V
10
pF
TABLE 3. FUNCTION TABLE
Control Input
S
L
H
83841BH
Function
Host Por t = B DIMM Por ts
A DIMM Por t = 140Ω to GND
Host Por t = A DIMM Por ts
B DIMM Por t = 140Ω to GND
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2
REV. A JANUARY 20, 2006
ICS83841
Integrated
Circuit
Systems, Inc.
20 BIT, DDR SDRAM 2:1 MUX
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
-0.5V to +3.3V
NOTE: Stresses beyond those listed under Absolute
Inputs, VI
-0.3V to VDD + 0.3 V
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
Ports
operation of product at these conditions or any conditions be-
DC Input Clamp Current, IIK
-50mA
yond those listed in the DC Characteristics or AC Character-
Package Thermal Impedance, θJA 50.04°C/W (0 mps)
istics is not implied. Exposure to absolute maximum rating
Storage Temperature, TSTG
conditions for extended periods may affect product reliability.
-65°C to 150°C
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 2.5V ± 0.2V, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
VDD
Positive Supply Voltage
IDD
Power Supply Current
Minimum
Typical
Maximum
2.3
2.5
2.7
20
Units
V
µA
TABLE 4B. DC CHARACTERISTICS, VDD = 2.5V ± 0.2V, TA = 0°C TO 70°C
Symbol Parameter
VIH
Test Conditions
Input High Voltage
S
VIL
Input Low Voltage
S
VIK
Input Clamp Voltage
IL
Input Leakage
Current
Host Por t
DIMM Por t
On Resistance; NOTE 1
Typical
Maximum
1.6
S
rON
Minimum
Units
V
0.9
V
VDD = 2.3V; II = -18mA
-1.2
V
VDD = 2.5V; VI = VDD or GND;
S = VDD
±100
µA
±100
µA
S = GND for IIL(test)
±100
µA
30
Ω
VDD = 2.5V; VA = 0.8V; VB = 1.0V
16
20
16
20
30
VDD = 2.5V; VA = 1.7V; VB = 1.5V
NOTE 1: Measured by the current between the Host and the DIMM terminals at the indicated voltages on each side
of the switch.
Ω
TABLE 5. AC CHARACTERISTICS, VDD = 2.5V ± 0.2V, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
Propagation Delay;
From DHx or DAx/DBx
125
240
ps
tPD
NOTE 1, 3
to DAx/DBx or DHx
Output
From S to
1.2
ns
tEN
Enable Time
DHx or DAx/DBx
Output
From S to
1.2
ns
tDIS
Disable Time
DHx or DAx/DBx
Output Skew;
Any Por t to any Por t
180
ps
tOSK
NOTE 2, 3
NOTE 1: Measured from VDD/2 of the input to VDD/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDD/2.
NOTE 3: Not production tested, guaranteed by characterization.
83841BH
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3
REV. A JANUARY 20, 2006
ICS83841
Integrated
Circuit
Systems, Inc.
20 BIT, DDR SDRAM 2:1 MUX
PARAMETER MEASUREMENT INFORMATION
VDD = 1.25V ± 0.1V
SCOPE
V DD
V
DD
DAx,
DBx
2
Qx
LVCMOS
V
DD
DAy,
DBy
GND
2
tsk(o)
-1.25V ± 0.1V
This circuit is used for test purposes only,
not intended for application use.
2.5V OUTPUT LOAD AC TEST CIRCUIT
OUTPUT SKEW
S
(Low-level
enabling)
2.5V
1.25V
2.5V
1.25V
1.25V
Input
1.25V
0V
0V
FallingEdge
Skew
VOH
Rising Edge
Skew
1.25V
Output
tPZH →
1.25V
VOL
Output DAx/DBx
(See Note)
tPHZ
→
1.25V
←
VOH
VOH - 0.15V
VOL
NOTE: The output is high except when disabled by the S control.
RISING & FALLING EDGE SKEW
3-STATE OUTPUT ENABLE/DISABLE TIMES
VDD
2
DAx
VDD
2
DHx
VDD
2
DBx
VDD
2
DAx/DBx
tsk(b)
t
PD
BANK SKEW
83841BH
PROPAGATION DELAY
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4
REV. A JANUARY 20, 2006
ICS83841
Integrated
Circuit
Systems, Inc.
20 BIT, DDR SDRAM 2:1 MUX
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE
FOR A
72-BALL TFBGA
θJA by Velocity (Millimeter Feet per Second)
Two-Layer PCB, JEDEC Standard Test Boards
0
1
2
50.04°C/W
43.18°C/W
41.17°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS83841 is: 261
83841BH
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5
REV. A JANUARY 20, 2006
ICS83841
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - H SUFFIX
20 BIT, DDR SDRAM 2:1 MUX
FOR A
72-BALL TFBGA
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
FBGA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
72 Balls, 6x6mm, 10x10 Pattern
A
1.0
1.1
1.2
A1
0.165
0.2
0.235
b
0.25
0.3
0.35
D
6.00 BSC
D1
4.50 BSC
E
6.00 BSC
E1
4.50 BSC
e
0.50 BSC
REFERENCE DOCUMENT: JEDEC PUBLICATION 95, MO-195
83841BH
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6
REV. A JANUARY 20, 2006
ICS83841
Integrated
Circuit
Systems, Inc.
20 BIT, DDR SDRAM 2:1 MUX
TABLE 8. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
ICS83841BH
ICS83841BH
72-Ball TFBGA
TBD
0°C to 70°C
ICS83841BHT
ICS83841BH
72-Ball TFBGA
2500 Tape & Reel
0°C to 70°C
ICS83841BHLF
ICS83841BHLF
72-Ball, Lead Free, TFBGA
TBD
0°C to 70°C
ICS83841BHLFT
ICS83841BHLF
72-Ball, Lead Free, TFBGA
2500 Tape & Reel
0°C to 70°C
NOTE: Par ts that are ordered with an"LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements
are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
83841BH
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7
REV. A JANUARY 20, 2006
ICS83841
Integrated
Circuit
Systems, Inc.
20 BIT, DDR SDRAM 2:1 MUX
REVISION HISTORY SHEET
Rev
Table
Page
A
T8
8
83841BH
Description of Change
Ordering Information table - corrected Lead-Free marking and added
Lead-Free note.
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8
Date
1/20/06
REV. A JANUARY 20, 2006
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