Hynix HY62SF16804B-DFC 512k x16 bit 1.8v super low power full cmos slow sram Datasheet

HY62SF16804B Series
512Kx16bit full CMOS SRAM
Document Title
512K x16 bit 1.8V Super Low Power Full CMOS slow SRAM
Revision History
Revision No
00
History
Initial Release
Draft Date
May.29.2001
Remark
Preliminary
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev.00 /May.2001
Hynix Semiconductor
HY62SF16804B
Preliminary
DESCRIPTION
FEATURES
The HY62SF16804B is a high speed, super low
power and 8Mbit full CMOS SRAM organized as
512K words by 16bits. The HY62SF16804B uses
high performance full CMOS process technology
and is designed for high speed and low power
circuit technology. It is particularly well-suited for
the high density low power system application.
This device has a data retention mode that
guarantees data to remain valid at a minimum
power supply voltage of 1.2V.
• Fully static operation and Tri-state output
• TTL compatible inputs and outputs
• Battery backup(LL/SL-part)
- 1.2V(min) data retention
• Standard pin configuration
- 48-fBGA
Product
Voltage
Speed
No.
(V)
(ns)
HY62SF16804B-C
1.65~2.3 70/85/100
HY62SF16804B-I
1.65~2.3 70/85/100
Note 1. C : Commercial, I : Industrial
2. Current value is max.
Operation
Current/Icc(mA)
3
3
PIN CONNECTION ( Top View )
6
A2
B
IO9 /UB A3
A4
/CS IO1
C
IO10 IO11 A5
A6
IO2 IO3
D
Vss IO12 A17 A7
IO4 Vcc
E
Vcc IO13 Vss A16 IO5 Vss
NC
ROW
DECODER
A0
IO15 IO14 A14 A15 IO6 IO7
MEMORY ARRAY
256K x 16
A18
G
IO16 NC
A12 A13 /WE IO8
H
A18 A8
A9
A10 A11 NC
I/O1
I/O8
DATA I/O
BUFFER
A1
WRITE DRIVER
/OE A0
SENSE AMP
A
/LB
F
5
BLOCK
DECODER
4
COLUMN
DECODER
3
PRE DECODER
2
Temperature
(°C)
0~70
-40~85
BLOCK DIAGRAM
ADD INPUT
BUFFER
1
Standby Current(uA)
LL
SL
15
8
15
8
I/O9
I/O16
/CS
/OE
/LB
/UB
/WE
PIN DESCRIPTION
Pin Name
/CS
/WE
/OE
/LB
/UB
Pin Function
Chip Select
Write Enable
Output Enable
Lower Byte Control(I/O1~I/O8)
Upper Byte Control(I/O9~I/O16)
Rev.00/May. 2001
Pin Name
I/O1~I/O16
A0~A18
Vcc
Vss
NC
Pin Function
Data Inputs / Outputs
Address Inputs
Power(1.65V~2.3V)
Ground
No Connection
2
HY62SF16804B
ORDERING INFORMATION
Part No.
Speed
HY62SF16804B-DFC
70/85/100
HY62SF16804B-SFC
70/85/100
HY62SF16804B-DFI
70/85/100
HY62SF16804B-SFI
70/85/100
Note 1. C : Commercial, I : Industrial
Power
LL-part
SL-part
LL-part
SL-part
Package
fBGA
fBGA
fBGA
fBGA
Temp.
C
C
I
I
ABSOLUTE MAXIMUM RATINGS (1)
Symbol
VIN, VOUT
Vcc
Parameter
Input/Output Voltage
Power Supply
TA
Operating Temperature
Rating
-0.3 to Vcc+0.3
-0.3 to 2.6V
0 to 70
-40 to 85
-55 to 150
1.0
260 • 10
Unit
V
V
°C
°C
°C
W
°C • sec
Remark
HY62SF16804B-C
HY62SF16804B-I
TSTG
Storage Temperature
PD
Power Dissipation
TSOLDER
Ball Soldering Temperature & Time
Note
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is stress rating only and the functional operation of the device under these or
any other conditions above those indicated in the operation of this specification is not implied.
Exposure to the absolute maximum rating conditions for extended period may affect reliability.
TRUTH TABLE
/CS
/WE
/OE
/LB
/UB
Mode
H
X
L
L
L
X
X
H
H
H
X
X
H
H
L
L
X
X
H
X
L
H
L
L
H
L
L
Deselected
Deselected
Output Disabled
Output Disabled
Read
L
X
H
L
X
L
H
L
L
H
L
Write
I/O1~I/O8
High-Z
High-Z
High-Z
High-Z
DOUT
High-Z
DOUT
DIN
High-Z
DIN
I/O
I/O9~I/O16
High-Z
High-Z
High-Z
High-Z
High-Z
DOUT
DOUT
High-Z
DIN
DIN
Power
Standby
Standby
Active
Active
Active
Active
Note:
1. H=VIH, L=VIL, X=don't care(VIH or VIL)
2. UB, LB(Upper, Lower Byte enable)
These active LOW inputs allow individual bytes to be written or read.
When LB is LOW, data is written or read to the lower byte, I/O1 -I/O8.
When UB is LOW, data is written or read to the upper byte, I/O9 -I/O16.
Rev.00/May. 2001
2
HY62SF16804B
RECOMMENDED DC OPERATING CONDITION
Symbol
Vcc
Vss
VIH
VIL
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min.
1.65
0
1.4
-0.3(1)
Typ.
1.8
0
-
Max.
2.3
0
Vcc+0.3
0.4
Unit
V
V
V
V
Note : 1. VIL = -1.5V for pulse width less than 30ns
DC ELECTRICAL CHARACTERISTICS
Vcc = 1.65V~2.3V, TA = 0°C to 70°C / -40°C to 85°C
Sym
Parameter
Test Condition
ILI
Input Leakage Current
Vss < VIN < Vcc
Vss < VOUT < Vcc, /CS = VIH or
ILO
Output Leakage Current
/OE = VIH or /WE = VIL,
/UB = /LB = VIH
Operating Power Supply
Icc
/CS = VIL, VIN = VIH or VIL, II/O = 0mA
Current
Cycle Time=Min,100% duty,
II/O = 0mA, /CS = VIL,VIN = VIH or VIL
Average Operating
Icc1
Current
Cycle time = 1us, 100% duty,
II/O = 0mA, /CS < 0.2V, VIN<0.2V
/CS = VIH or /UB=/LB= VIH,
TTL Standby Current
ISB
(TTL Input)
VIN = VIH or VIL
/CS > Vcc - 0.2V or
SL
Standby Current
/UB=/LB > Vcc-0.2V,
ISB1
(CMOS Input)
VIN > Vcc-0.2V or
LL
VIN < Vss+0.2V
VOL
Output Low Voltage
IOL = 0.1mA
VOH Output High Voltage
IOH = -0.1mA
Note : 1. Typical values are at Vcc = 1.8V, TA = 25°C
2. Typical values are sampled and not 100% tested
Min.
-1
Typ.
-
Max.
1
Unit
uA
-1
-
1
uA
3
mA
-
25
mA
-
-
3
mA
-
-
0.05
mA
-
-
8
uA
-
1
15
uA
1.4
-
0.2
-
V
V
-
CAPACITANCE
(Temp = 25°C, f = 1.0MHz)
Symbol
CIN
COUT
Parameter
Input Capacitance(Add, /CS, /WE, /UB, /LB, /OE)
Output Capacitance(I/O)
Conditio
n
VIN = 0V
VI/O = 0V
Max.
Unit
8
10
pF
pF
Note : These parameters are sampled and not 100% tested
Rev.00/May. 2001
3
HY62SF16804B
AC CHARATERISTICS
Vcc = 1.65V~2.3V, TA = 0°C to 70°C / -40°C to 85°C
#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Symbol
-70
Min.
Max.
Parameter
READ CYCLE
tRC
Read Cycle Time
tAA
Address Access Time
tACS
Chip Select Access Time
tOE
Output Enable to Output Valid
tBA
/LB, /UB Access Time
tCLZ
Chip Select to Output in Low Z
tOLZ
Output Enable to Output in Low Z
tBLZ
/LB, /UB Enable to Output in Low Z
tCHZ
Chip Deselection to Output in High Z
tOHZ
Out Disable to Output in High Z
tBHZ
/LB, /UB Disable to Output in High Z
tOH
Output Hold from Address Change
WRITE CYCLE
tWC
Write Cycle Time
tCW
Chip Selection to End of Write
tAW
Address Valid to End of Write
tBW
/LB, /UB Valid to End of Write
tAS
Address Set-up Time
tWP
Write Pulse Width
tWR
Write Recovery Time
tWHZ
Write to Output in High Z
tDW
Data to Write Time Overlap
tDH
Data Hold from Write Time
tOW
Output Active from End of Write
-85
Min.
Max.
-10
Min
Max.
Unit
70
10
5
10
0
0
0
10
70
70
35
70
20
20
20
-
85
10
5
10
0
0
0
10
85
85
40
85
30
30
30
-
100
10
5
10
0
0
0
15
100
100
45
100
30
30
30
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
70
60
60
60
0
50
0
0
30
0
5
20
-
85
70
70
70
0
60
0
0
35
0
5
25
-
100
80
80
80
0
70
0
0
45
0
10
25
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AC TEST CONDITIONS
TA = 0°C to 70°C / -40°C to 85°C, unless otherwise specified
PARAMETER
Input Pulse Level
Input Rise and Fall Time
Input and Output Timing Reference Level
tCLZ,tOLZ,tBLZ,tCHZ,tOHZ,tBHZ,tWHZ,tOW
Output Load
Other
Value
0.4V to 1.6V
5ns
0.9V
CL = 5pF + 1TTL Load
CL = 30pF + 1TTL Load
AC TEST LOADS
VTM
= 1.8V
4091 Ohm
D
OUT
CL(1)
3273 Ohm
Note
1. Including jig and scope capacitance
Rev.00/May. 2001
4
HY62SF16804B
TIMING DIAGRAM
READ CYCLE 1(Note 1,4)
tRC
ADDR
tAA
tOH
tACS
/CS
tCHZ(3)
tBA
/UB ,/ LB
Data
Out
tBHZ(3)
tOE
/OE
High-Z
tOLZ(3)
tBLZ(3)
tCLZ(3)
tOHZ(3)
Data Valid
READ CYCLE 2(Note 1,2,4)
tRC
ADDR
tAA
tOH
tOH
Data
Out
Previous Data
Data Valid
READ CYCLE 3(Note 1,2,4)
/CS
/UB, /LB
tACS
tCLZ(3)
Data
Out
tCHZ(3)
Data Valid
Notes:
1. A read occurs during the overlap of a low /OE, a high /WE, a low /CS and low /UB and /or /LB
2. /OE = VIL
3. Transition is measured + 200mV from steady state voltage.
This parameter is sampled and not 100% tested.
4. /CS in high for the standby, low for active
/UB and /LB in high for the standby, low for active
Rev.00/May. 2001
5
HY62SF16804B
WRITE CYCLE 1 (1,4,8) (/WE Controlled)
tWC
ADDR
tWR(2)
tCW
/CS
tAW
tBW
/UB,/LB
tWP
/WE
tAS
Data In
tDW
High-Z
tDH
Data Valid
tWHZ(3,7)
tOW
(5)
(6)
Data
Out
WRITE CYCLE 2 (Note 1,4,8) (/CS Controlled)
tWC
ADDR
tCW
tAS
tWR(2)
/CS
tAW
tBW
/UB,/LB
tWP
/WE
tDW
Data In
Data
Out
Rev.00/May. 2001
High-Z
tDH
Data Valid
High-Z
6
HY62SF16804B
Notes:
1. A write occurs during the overlap of a low / WE, a low /CS1 and low /UB and /or /LB
2. tWR is measured from the earlier of /CS, /LB, /UB, or /WE going high to the end of write cycle.
3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the
output must not be applied.
4. If the /CS, /LB and /UB low transition occur simultaneously with the /WE low transition or after the
/WE transition, outputs remain in a high impedance state.
5. Q(data out) is the same phase with the write data of this write cycle.
6. Q(data out) is the read data of the next address.
7. Transition is measured +200mV from steady state.
This parameter is sampled and not 100% tested.
8. /CS in high for the standby, low for active
/UB and /LB in high for the standby, low for active
DATA RETENTION ELECTRIC CHARACTERISTIC
TA = 0°C to 70°C / -40°C to 85°C
Symbol
Parameter
VDR
ICCDR
tCDR
tR
Vcc for Data Retention
Data Retention Current
Chip Deselect to Data
Retention Time
Operating Recovery Time
Test Condition
/CS > Vcc - 0.2V or
/UB=/LB > Vcc-0.2V,
VIN > Vcc-0.2V or
VIN < Vss+0.2V
Vcc=1.5V, /CS > Vcc - 0.2V or
/UB=/LB > Vcc-0.2V,
VIN > Vcc-0.2V or
VIN < Vss+0.2V
LL
SL
See Data Retention Timing Diagram
Min
Typ
Max
Unit
1.2
-
2.3
V
-
1
12
uA
-
-
8
uA
0
-
-
ns
tRC(2)
-
-
ns
Notes:
1. Typical values are under the condition of TA = 25°C .
2. tRC is read cycle time.
DATA RETENTION TIMING DIAGRAM
DATA RETENTION MODE
VCC
1.65V
tCDR
tR
VIH
VDR
/CS or
/UB & /LB
/CS>Vcc-0.2V or
/UB=/LB > Vcc-0.2V
Vss
Rev.00/May. 2001
7
HY62SF16804B
PACKAGE INFORMATION
48ball Fine Pitch Ball Grid Array Package (F)
BOTTOM VIEW
TOP VIEW
B
A
A1 CORNER
INDEX AREA
6
5
4
3
2
1
A
A
B
C
D
C
C1
E
F
G
C1/2
H
B1/2
B1
SIDE VIEW
5
E1
E2
C
E
SEATING PLANE
A
4
r
3 D(DIAMETER)
Symbol
A
B
B1
C
C1
D
E
E1
E2
r
Rev.00/May. 2001
Min.
5.9
8.4
0.3
0.9
0.20
-
Typ.
0.75
3.75
6.0
5.25
8.5
0.35
1.0
0.76
0.25
-
Max.
6.1
8.6
0.4
1.10
0.30
0.08
Note
1. DIMENSIONING AND TOLERANCING PER ASME Y14. 5M-1994.
2. ALL DIMENSIONS ARE MILLIMETERS.
3. DIMENSION “ D” IS MEASURED AT THE MAXIMUM SOLDER
BALL DIAMETER IN A PLANE PARALLEL TO DATUM C.
4. PRIMARY DATUM C(SEATING PLANE) IS DEFINED BY THE
CROWN OF THE SOLDER BALLS.
5. THIS IS A CONTROLLING DIMENSION.
8
HY62SF16804B
MARKING INSTRUCTION
Package
fBGA
Marking Example
H
Y
S
F
c
s
s
t
x
x
x
x
6
8
0
4
B
y
w
w
p
K
O
R
x
Index
• HYSF6804B
: Part Name
• c
: Power Consumption
-D
-S
• ss
: Low Low Power
: Super Low Power
: Speed
- 70
- 85
- 10
: 70ns
: 85ns
: 100ns
• t
: Temperature
-C
-I
• y
: Year (ex : 0 = year 2000, 1= year 2001)
• ww
: Work Week ( ex : 12 = work week 12 )
• p
: Process Code
• xxxxx
: Lot No.
• KOR
: Origin Country
Note
- Capital Letter
- Small Letter
: Fixed Item
: Non-fixed Item
Rev.00/May. 2001
: Commercial ( 0 ~ 70 °C))
: Industrial ( --40 ~ 85 °C )
9
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