CY7C1471V33 CY7C1473V33 CY7C1475V33 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL™ Architecture Functional Description [1] Features • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles • Supports up to 133 MHz bus operations with zero wait states • Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™ devices • Internally self timed output buffer control to eliminate the need to use OE • Registered inputs for flow through operation • Byte Write capability • 3.3V/2.5V IO supply (VDDQ) • Fast clock-to-output times — 6.5 ns (for 133-MHz device) • Clock Enable (CEN) pin to enable clock and suspend operation • Synchronous self timed writes • Asynchronous Output Enable (OE) • CY7C1471V33, CY7C1473V33 available in JEDEC-standard Pb-free 100-Pin TQFP, Pb-free and non-Pb-free 165-Ball FBGA package. CY7C1475V33 available in Pb-free and non-Pb-free 209-Ball FBGA package • Three Chip Enables (CE1, CE2, CE3) for simple depth expansion • Automatic power down feature available using ZZ mode or CE deselect • IEEE 1149.1 JTAG Boundary Scan compatible • Burst Capability — linear or interleaved burst order • Low standby power The CY7C1471V33, CY7C1473V33 and CY7C1475V33 are 3.3V, 2M x 36/4M x 18/1M x 72 synchronous flow through burst SRAMs designed specifically to support unlimited true back-to-back read or write operations without the insertion of wait states. The CY7C1471V33, CY7C1473V33 and CY7C1475V33 are equipped with the advanced No Bus Latency (NoBL) logic required to enable consecutive read or write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent write-read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle.Maximum access delay from the clock rise is 6.5 ns (133-MHz device). Write operations are controlled by two or four Byte Write Select (BWX) and a Write Enable (WE) input. All writes are conducted with on-chip synchronous self timed write circuitry. Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output tri-state control. To avoid bus contention, the output drivers are synchronously tri-stated during the data portion of a write sequence. Selection Guide 133 MHz 117 MHz Unit Maximum Access Time 6.5 8.5 ns Maximum Operating Current 305 275 mA Maximum CMOS Standby Current 120 120 mA Note 1. For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines. Cypress Semiconductor Corporation Document #: 38-05288 Rev. *J • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised July 04, 2007 CY7C1471V33 CY7C1473V33 CY7C1475V33 Logic Block Diagram – CY7C1471V33 (2M x 36) ADDRESS REGISTER A0, A1, A A1 D1 A0 D0 MODE CLK CEN CE C ADV/LD C BURST LOGIC Q1 A1' A0' Q0 WRITE ADDRESS REGISTER ADV/LD BW A WRITE DRIVERS WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC BW B BW C MEMORY ARRAY S E N S E A M P S BW D WE INPUT REGISTER OE CE1 CE2 CE3 D A T A S T E E R I N G O U T P U T B U F F E R S DQs DQP A DQP B DQP C DQP D E E READ LOGIC SLEEP CONTROL ZZ Logic Block Diagram – CY7C1473V33 (4M x 18) ADDRESS REGISTER A0, A1, A A1 D1 A0 D0 MODE CLK CEN CE C ADV/LD C BURST LOGIC A1' Q1 A0' Q0 WRITE ADDRESS REGISTER ADV/LD BW A BW B WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC WRITE DRIVERS MEMORY ARRAY S E N S E A M P S WE OE CE1 CE2 CE3 ZZ Document #: 38-05288 Rev. *J D A T A S T E E R I N G O U T P U T B U F F E R S DQs DQP A DQP B E INPUT E REGISTER READ LOGIC SLEEP CONTROL Page 2 of 32 CY7C1471V33 CY7C1473V33 CY7C1475V33 Logic Block Diagram – CY7C1475V33 (1M x 72) ADDRESS REGISTER 0 A0, A1, A MODE CLK ADV/LD C C CEN A1 A1' D1 Q1 A0 A0' D0 BURST Q0 LOGIC WRITE ADDRESS REGISTER 2 WRITE ADDRESS REGISTER 1 ADV/LD BW a BW b BW c BW d BW e BW f BW g BW h WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC WRITE DRIVERS MEMORY ARRAY S E N S E A M P S O U T P U T R E G I S T E R S D A T A S T E E R I N G E O U T P U T B U F F E R S E DQ s DQ Pa DQ Pb DQ Pc DQ Pd DQ Pe DQ Pf DQ Pg DQ Ph WE INPUT E REGISTER 1 OE CE1 CE2 CE3 ZZ Document #: 38-05288 Rev. *J INPUT E REGISTER 0 READ LOGIC Sleep Control Page 3 of 32 CY7C1471V33 CY7C1473V33 CY7C1475V33 Pin Configurations A 40 41 42 43 44 45 46 47 48 49 50 A A A A A A A A A 37 A0 VSS 36 A1 VDD 35 A 39 34 A NC/144M 33 A 38 32 NC/288M 31 Document #: 38-05288 Rev. *J 81 A 82 A 83 A 84 ADV/LD 85 OE CEN 90 87 VSS 91 WE VDD 92 88 CE3 93 CLK BWA 94 89 BWC 96 BWB BWD 97 95 CE2 98 A CE1 86 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 CY7C1471V33 A BYTE D 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 MODE BYTE C DQPC DQC DQC VDDQ VSS DQC DQC DQC DQC VSS VDDQ DQC DQC NC VDD NC VSS DQD DQD VDDQ VSS DQD DQD DQD DQD VSS VDDQ DQD DQD DQPD 99 100 A 100-Pin TQFP Pinout DQPB DQB DQB VDDQ VSS DQB DQB DQB DQB VSS VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA DQA DQA VSS VDDQ DQA DQA DQPA BYTE B BYTE A Page 4 of 32 CY7C1471V33 CY7C1473V33 CY7C1475V33 Pin Configurations (continued) A 40 41 42 43 44 45 46 47 48 49 50 A A A A A A A A A 37 A0 VSS 36 A1 VDD 35 A 39 34 A NC/144M 33 A 38 32 NC/288M 31 Document #: 38-05288 Rev. *J 81 A 82 A 83 A 84 ADV/LD 85 OE CEN 90 87 VSS 91 WE VDD 92 88 CE3 93 CLK BWA 94 89 NC BWB 95 NC 97 96 CE2 98 A CE1 86 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 CY7C1473V33 A BYTE B VDDQ VSS NC NC DQB DQB VSS VDDQ DQB DQB NC VDD NC VSS DQB DQB VDDQ VSS DQB DQB DQPB NC VSS VDDQ NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 MODE NC NC NC 99 100 A 100-Pin TQFP Pinout A NC NC VDDQ VSS NC DQPA DQA DQA VSS VDDQ DQA DQA VSS NC VDD ZZ BYTE A DQA DQA VDDQ VSS DQA DQA NC NC VSS VDDQ NC NC NC Page 5 of 32 CY7C1471V33 CY7C1473V33 CY7C1475V33 Pin Configurations (continued) 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1471V33 (2M x 36) 1 2 3 4 5 6 7 8 9 10 11 A B C D E F G H J K L M N P NC/576M A CE1 BWC BWB CE3 CEN ADV/LD A A NC NC/1G A CE2 BWD BWA CLK WE OE A A NC DQPC DQC NC DQC VDDQ VDDQ VSS VDD VSS VSS VSS VSS VSS VSS VSS VDD VDDQ VDDQ NC DQB DQPB DQB DQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ DQB DQB R DQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ DQB DQB DQC NC DQD DQC NC DQD VDDQ NC VDDQ VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD VDDQ NC VDDQ DQB NC DQA DQB ZZ DQA DQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA DQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA DQD DQPD DQD NC VDDQ VDDQ VDD VSS VSS NC VSS NC/144M A A A MODE A A A VSS NC VDD VSS VDDQ VDDQ DQA NC DQA DQPA TDI NC A1 TDO A A A NC/288M TMS A0 TCK A A A A 8 9 10 11 A CY7C1473V33 (4M x 18) 1 A B C D E F G H J K L M N P R 2 3 4 5 6 7 NC/576M A CE1 BWB NC CE3 CEN ADV/LD A A NC/1G A CE2 NC BWA CLK WE OE A A NC NC NC NC DQB VDDQ VSS VDD VSS VSS VSS VSS VSS VSS VSS VDD VDDQ VDDQ VDDQ NC NC DQPA DQA NC DQB VDDQ VDD VSS VSS VSS VDD VDDQ NC DQA NC DQB VDDQ VDD VSS VSS VSS VDD VDDQ NC DQA NC NC DQB DQB NC NC VDDQ NC VDDQ VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD VDDQ NC VDDQ NC NC DQA DQA ZZ NC DQB NC VDDQ VDD VSS VSS VSS VDD VDDQ DQA NC DQB NC VDDQ VDD VSS VSS VSS VDD VDDQ DQA NC DQB DQPB NC NC VDDQ VDDQ VDD VSS VSS NC VSS NC/144M A A A MODE A A A Document #: 38-05288 Rev. *J VSS NC VDD VSS VDDQ VDDQ DQA NC NC NC TDI NC A1 TDO A A A NC/288M TMS A0 TCK A A A A Page 6 of 32 CY7C1471V33 CY7C1473V33 CY7C1475V33 Pin Configurations (continued) 209-Ball FBGA (14 x 22 x 1.76 mm) Pinout CY7C1475V33 (1M × 72) 1 2 3 4 5 6 7 8 9 10 11 A DQg DQg A CE2 A ADV/LD A CE3 A DQb DQb B DQg DQg BWSc BWSg NC WE A BWSb BWSf DQb DQb C DQg DQg BWSh BWSd NC/576M CE1 NC BWSe BWSa DQb DQb D DQg DQg VSS NC NC/1G OE NC NC VSS DQb DQb E DQPg DQPc VDDQ VDDQ VDD VDD VDD VDDQ VDDQ DQPf DQPb F DQc DQc VSS VSS VSS NC VSS VSS VSS DQf DQf G DQc DQc VDDQ VDDQ VDD NC VDD VDDQ VDDQ DQf DQf H DQc DQc VSS VSS VSS NC VSS VSS VSS DQf DQf J DQc DQc VDDQ VDDQ VDD NC VDD VDDQ VDDQ DQf DQf K NC NC CLK NC VSS CEN VSS NC NC NC NC L DQh DQh VDDQ VDDQ VDD NC VDD VDDQ VDDQ DQa DQa M DQh DQh VSS VSS VSS NC VSS VSS VSS DQa DQa N DQh DQh VDDQ VDDQ VDD NC VDD VDDQ VDDQ DQa DQa P DQh DQh VSS VSS VSS ZZ VSS VSS VSS DQa DQa R DQPd DQPh VDDQ VDDQ VDD VDD VDD VDDQ VDDQ DQPa DQPe T DQd DQd VSS NC NC MODE NC NC VSS DQe DQe U DQd DQd NC/144M A A A A A NC/288M DQe DQe V DQd DQd A A A A1 A A A DQe DQe W DQd DQd TMS TDI A A0 A TDO TCK DQe DQe Document #: 38-05288 Rev. *J Page 7 of 32 CY7C1471V33 CY7C1473V33 CY7C1475V33 Pin Definitions Name IO Description A0, A1, A InputSynchronous Address Inputs used to select one of the address locations. Sampled at the rising edge of the CLK. A[1:0] are fed to the two-bit burst counter. BWA, BWB, BWC, BWD, BWE, BWF, BWG, BWH InputSynchronous Byte Write Inputs, Active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the rising edge of CLK. WE InputSynchronous Write Enable Input, Active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal must be asserted LOW to initiate a write sequence. ADV/LD InputSynchronous Advance/Load Input. Advances the on-chip address counter or loads a new address. When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be loaded into the device for an access. After being deselected, ADV/LD should must driven LOW to load a new address. CLK InputClock Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is only recognized if CEN is active LOW. CE1 InputSynchronous Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3 to select or deselect the device. CE2 InputSynchronous Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select or deselect the device. CE3 InputSynchronous Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select or deselect the device. OE InputAsynchronous Output Enable, Asynchronous Input, Active LOW. Combined with the synchronous logic block inside the device to control the direction of the IO pins. When LOW, the IO pins are enabled to behave as outputs. When deasserted HIGH, IO pins are tri-stated, and act as input data pins. OE is masked during the data portion of a write sequence, during the first clock when emerging from a deselected state, when the device is deselected. CEN InputSynchronous Clock Enable Input, Active LOW. When asserted LOW the Clock signal is recognized by the SRAM. When deasserted HIGH the Clock signal is masked. Since deasserting CEN does not deselect the device, use CEN to extend the previous cycle when required. ZZ InputAsynchronous ZZ “Sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition with data integrity preserved. During normal operation, this pin must be LOW or left floating. ZZ pin has an internal pull down. DQs IOSynchronous Bidirectional Data IO Lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX are placed in a tri-state condition.The outputs are automatically tri-stated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of OE. DQPX IOSynchronous Bidirectional Data Parity IO Lines. Functionally, these signals are identical to DQs. During write sequences, DQPX is controlled by BWX correspondingly. MODE Input Strap Pin Mode Input. Selects the burst order of the device. When tied to Gnd selects linear burst sequence. When tied to VDD or left floating selects interleaved burst sequence. VDD Power Supply Power supply inputs to the core of the device. VDDQ VSS IO Power Supply Power supply for the IO circuitry. Ground Document #: 38-05288 Rev. *J Ground for the device. Page 8 of 32 CY7C1471V33 CY7C1473V33 CY7C1475V33 Pin Definitions (continued) Name TDO IO JTAG serial output Synchronous Description Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG feature is not used, this pin must be left unconnected. This pin is not available on TQFP packages. TDI JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature Synchronous is not used, this pin can be left floating or connected to VDD through a pull up resistor. This pin is not available on TQFP packages. TMS JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature Synchronous is not used, this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages. TCK JTAG -Clock NC - Clock input to the JTAG circuitry. If the JTAG feature is not used, this pin must be connected to VSS. This pin is not available on TQFP packages. No Connects. Not internally connected to the die. 144M, 288M, 576M, and 1G are address expansion pins and are not internally connected to the die. Functional Overview The CY7C1471V33, CY7C1473V33, and CY7C1475V33 are synchronous flow through burst SRAMs designed specifically to eliminate wait states during write-read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock signal is qualified with the Clock Enable input signal (CEN). If CEN is HIGH, the clock signal is not recognized and all internal states are maintained. All synchronous operations are qualified with CEN. Maximum access delay from the clock rise (tCDV) is 6.5 ns (133-MHz device). Accesses can be initiated by asserting all three Chip Enables (CE1, CE2, CE3) active at the rising edge of the clock. If (CEN) is active LOW and ADV/LD is asserted LOW, the address presented to the device is latched. The access can either be a read or write operation, depending on the status of the Write Enable (WE). Byte Write Select (BWX) can be used to conduct Byte Write operations. Write operations are qualified by the Write Enable (WE). All writes are simplified with on-chip synchronous self timed write circuitry. Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) simplify depth expansion. All operations (reads, writes, and deselects) are pipelined. ADV/LD must be driven LOW after the device is deselected to load a new address for the next operation. Single Read Accesses A read access is initiated when these conditions are satisfied at clock rise: • CEN is asserted LOW • CE1, CE2, and CE3 are ALL asserted active • WE is deasserted HIGH • ADV/LD is asserted LOW. The address presented to the address inputs is latched into the Address Register and presented to the memory array and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to Document #: 38-05288 Rev. *J the output buffers. The data is available within 6.5 ns (133-MHz device) provided OE is active LOW. After the first clock of the read access, the output buffers are controlled by OE and the internal control logic. OE must be driven LOW to drive out the requested data. On the subsequent clock, another operation (read/write/deselect) can be initiated. When the SRAM is deselected at clock rise by one of the chip enable signals, output is be tri-stated immediately. Burst Read Accesses The CY7C1471V33, CY7C1473V33 and CY7C1475V33 have an on-chip burst counter that enables the user to supply a single address and conduct up to four reads without reasserting the address inputs. ADV/LD must be driven LOW to load a new address into the SRAM, as described in the Single Read Access section. The sequence of the burst counter is determined by the MODE input signal. A LOW input on MODE selects a linear burst mode, a HIGH selects an interleaved burst sequence. Both burst counters use A0 and A1 in the burst sequence, and wraps around when incremented sufficiently. A HIGH input on ADV/LD increments the internal burst counter regardless of the state of chip enable inputs or WE. WE is latched at the beginning of a burst cycle. Therefore, the type of access (read or write) is maintained throughout the burst sequence. Single Write Accesses Write accesses are initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are ALL asserted active, and (3) WE is asserted LOW. The address presented to the address bus is loaded into the Address Register. The Write signals are latched into the Control Logic block. The data lines are automatically tri-stated regardless of the state of the OE input signal. This allows the external logic to present the data on DQs and DQPX. On the next clock rise the data presented to DQs and DQPX (or a subset for Byte Write operations, see “Truth Table for Read/Write” on page 12 for details) inputs is latched into the device and the write is complete. Additional accesses (read/write/deselect) can be initiated on this cycle. Page 9 of 32 CY7C1471V33 CY7C1473V33 CY7C1475V33 The data written during the write operation is controlled by BWX signals. The CY7C1471V33, CY7C1473V33, and CY7C1475V33 provides Byte Write capability that is described in the “Truth Table for Read/Write” on page 12. The input WE with the selected BWX input selectively writes to only the desired bytes. Bytes not selected during a Byte Write operation remain unaltered. A synchronous self timed write mechanism has been provided to simplify the write operations. Byte write capability is included to greatly simplify read/modify/write sequences, which can be reduced to simple byte write operations. Because the CY7C1471V33, CY7C1473V33, and CY7C1475V33 are common IO devices, data must not be driven into the device while the outputs are active. The Output Enable (OE) can be deasserted HIGH before presenting data to the DQs and DQPX inputs. Doing so tri-states the output drivers. As a safety precaution, DQs and DQPX are automatically tri-stated during the data portion of a write cycle, regardless of the state of OE. Interleaved Burst Address Table (MODE = Floating or VDD) First Address A1: A0 Second Address A1: A0 Third Address A1: A0 Fourth Address A1: A0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 Linear Burst Address Table (MODE = GND) First Address A1: A0 Second Address A1: A0 Third Address A1: A0 Fourth Address A1: A0 00 01 10 11 Burst Write Accesses 01 10 11 00 The CY7C1471V33, CY7C1473V33, and CY7C1475V33 have an on-chip burst counter that enables the user to supply a single address and conduct up to four write operations without reasserting the address inputs. ADV/LD must be driven LOW to load the initial address, as described in the Single Write Access section. When ADV/LD is driven HIGH on the subsequent clock rise, the Chip Enables (CE1, CE2, and CE3) and WE inputs are ignored and the burst counter is incremented. The correct BWX inputs must be driven in each cycle of the burst write to write the correct bytes of data. 10 11 00 01 11 00 01 10 Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected before entering the “sleep” mode. CE1, CE2, and CE3, must remain inactive for the duration of tZZREC after the ZZ input returns LOW. ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min Max Unit IDDZZ Sleep mode standby current ZZ > VDD – 0.2V 120 mA tZZS Device operation to ZZ ZZ > VDD – 0.2V 2tCYC ns tZZREC ZZ recovery time ZZ < 0.2V tZZI ZZ active to sleep current This parameter is sampled tRZZI ZZ Inactive to exit sleep current This parameter is sampled Document #: 38-05288 Rev. *J 2tCYC ns 2tCYC 0 ns ns Page 10 of 32 CY7C1471V33 CY7C1473V33 CY7C1475V33 Truth Table The truth table for CY7C1471V33, CY7C1473V33, CY7C1475V33 follows.[2, 3, 4, 5, 6, 7, 8] Operation Address CE CE 1 2 CE3 ZZ Used ADV/LD WE BWX OE CEN CLK DQ Deselect Cycle None H X X L L X X X L L->H Tri-State Deselect Cycle None X X H L L X X X L L->H Tri-State Deselect Cycle None X L X L L X X X L L->H Tri-State Tri-State Continue Deselect Cycle None X X X L H X X X L L->H External L H L L L H X L L L->H Data Out (Q) Next X X X L H X X L L L->H Data Out (Q) External L H L L L H X H L L->H Tri-State Next X X X L H X X H L L->H Tri-State External L H L L L L L X L L->H Data In (D) Write Cycle (Continue Burst) Next X X X L H X L X L L->H Data In (D) NOP/Write Abort (Begin Burst) None L H L L L L H X L L->H Tri-State Write Abort (Continue Burst) Next X X X L H X H X L L->H Tri-State Current X X X L X X X X H L->H - None X X X H X X X X X X Tri-State Read Cycle (Begin Burst) Read Cycle (Continue Burst) NOP/Dummy Read (Begin Burst) Dummy Read (Continue Burst) Write Cycle (Begin Burst) Ignore Clock Edge (Stall) Sleep Mode Notes 2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. BWX = L signifies at least one Byte Write Select is active, BWX = Valid signifies that the desired Byte Write Selects are asserted, see “Truth Table for Read/Write” on page 12 for details. 3. Write is defined by BWX, and WE. See “Truth Table for Read/Write” on page 12. 4. When a Write cycle is detected, all IOs are tri-stated, even during Byte Writes. 5. The DQs and DQPX pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 6. CEN = H, inserts wait states. 7. Device powers up deselected with the IOs in a tri-state condition, regardless of OE. 8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQPX = tri-state when OE is inactive or when the device is deselected, and DQs and DQPX = data when OE is active. Document #: 38-05288 Rev. *J Page 11 of 32 CY7C1471V33 CY7C1473V33 CY7C1475V33 Truth Table for Read/Write The read-write truth table for CY7C1471V33 follows.[2, 3, 9] Function WE BWA BWB BWC BWD Read H X X X X Write No bytes written L H H H H Write Byte A – (DQA and DQPA) L L H H H Write Byte B – (DQB and DQPB) L H L H H Write Byte C – (DQC and DQPC) L H H L H Write Byte D – (DQD and DQPD) L H H H L Write All Bytes L L L L L Truth Table for Read/Write The read-write truth table for CY7C1473V33 follows.[2, 3, 9] Function WE BWb BWa Read H X X Write – No Bytes Written L H H Write Byte a – (DQa and DQPa) L H L Write Byte b – (DQb and DQPb) L L H Write Both Bytes L L L Truth Table for Read/Write The read-write truth table for CY7C1475V33 follows.[2, 3, 9] Function WE BWx Read H X Write – No Bytes Written L H Write Byte X − (DQx and DQPx) L L Write All Bytes L All BW = L Note 9. Table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write is based on which byte write is active. Document #: 38-05288 Rev. *J Page 12 of 32 CY7C1471V33 CY7C1473V33 CY7C1475V33 IEEE 1149.1 Serial Boundary Scan (JTAG) Test Access Port (TAP) The CY7C1471V33, CY7C1473V33, and CY7C1475V33 incorporate a serial boundary scan test access port (TAP). This port operates in accordance with IEEE Standard 1149.1-1990 but does not have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM. Note that the TAP controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant TAPs. The TAP operates using JEDEC-standard 3.3V or 2.5V IO logic levels. Test Clock (TCK) The CY7C1471V33, CY7C1473V33, and CY7C1475V33 contain a TAP controller, instruction register, boundary scan register, bypass register, and ID register. Test Data-In (TDI) Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull up resistor. TDO must be left unconnected. During power up, the device comes up in a reset state, which does not interfere with the operation of the device. TAP Controller State Diagram 1 TEST-LOGIC RESET 0 RUN-TEST/ IDLE 0 1 SELECT DR-SCA N 1 SELECT IR-SCAN 0 1 The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this ball unconnected if the TAP is not used. The ball is pulled up internally, resulting in a logic HIGH level. The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information about loading the instruction register, see the TAP Controller State Diagram. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) of any register. (See TAP Controller Block Diagram.) Test Data-Out (TDO) The TDO output ball is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine. The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. (See TAP Controller State Diagram.) TAP Controller Block Diagram 0 CAPTURE-IR Bypass Register 0 SHIFT-DR 0 SHIFT-IR 1 1 EXIT1-IR 0 2 1 0 0 1 EXIT1-DR 1 TDI 0 0 0 Selection Circuitry TDO x . . . . . 2 1 0 1 EXIT2-DR Instruction Register Identification Register PAUSE-IR 1 Selection Circuitry 31 30 29 . . . 2 1 0 0 PAUSE-DR Boundary Scan Register EXIT2-IR 1 1 UPDATE-DR 1 Test MODE SELECT (TMS) 0 1 CAPTURE-DR 0 0 1 The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. 0 UPDATE-IR 1 0 The 0/1 next to each state represents the value of TMS at the rising edge of TCK. TCK TM S TAP CONTROLLER Performing a TAP Reset A RESET is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. During power up, the TAP is reset internally to ensure that TDO comes up in a High-Z state. Document #: 38-05288 Rev. *J Page 13 of 32 CY7C1471V33 CY7C1473V33 CY7C1475V33 TAP Registers Registers are connected between the TDI and TDO balls and enable data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction register. Data is serially loaded into the TDI ball on the rising edge of TCK. Data is output on the TDO ball on the falling edge of TCK. nstruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO balls as shown in the “TAP Controller Block Diagram” on page 13. During power up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section. When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary ‘01’ pattern to enable fault isolation of the board-level serial test data path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between the TDI and TDO balls. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all the input and bidirectional balls on the SRAM. The boundary scan register is loaded with the contents of the RAM IO ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO balls when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the IO ring. The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in “Identification Register Definitions” on page 18. TAP Instruction Set Overview Eight different instructions are possible with the three-bit instruction register. All combinations are listed in “Identification Codes” on page 18. Three of these instructions are listed as RESERVED and must not be used. The other five instructions are described in detail below. Document #: 38-05288 Rev. *J The TAP controller used in this SRAM is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented. The TAP controller cannot be used to load address data or control signals into the SRAM and cannot preload the IO buffers. The SRAM does not implement the 1149.1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE/PRELOAD; rather, it performs a capture of the IO ring when these instructions are executed. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO balls. To execute the instruction after it is shifted in, the TAP controller needs to be moved into the Update-IR state. EXTEST EXTEST is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all 0s. EXTEST is not implemented in this SRAM TAP controller, and therefore this device is not compliant to 1149.1. The TAP controller does recognize an all-0 instruction. When an EXTEST instruction is loaded into the instruction register, the SRAM responds as if a SAMPLE/PRELOAD instruction has been loaded. There is one difference between the two instructions. Unlike the SAMPLE/PRELOAD instruction, EXTEST places the SRAM outputs in a High-Z state. IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO balls and enables the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register during power up or whenever the TAP controller is in a test logic reset state. SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO balls when the TAP controller is in a Shift-DR state. It also places all SRAM outputs into a High-Z state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The PRELOAD portion of this instruction is not implemented, so the device TAP controller is not fully 1149.1 compliant. When the SAMPLE/PRELOAD instruction is loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and bidirectional balls is captured in the boundary scan register. The user must be aware that the TAP controller clock can only operate at a frequency up to 20 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output may undergo a transition. The TAP may then try to capture a Page 14 of 32 CY7C1471V33 CY7C1473V33 CY7C1475V33 Note that since the PRELOAD part of the command is not implemented, putting the TAP to the Update-DR state while performing a SAMPLE/PRELOAD instruction has the same effect as the Pause-DR command. signal while in transition (metastable state). This does not harm the device, but there is no guarantee as to the value that is captured. Repeatable results may not be possible. To guarantee that the boundary scan register captures the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller’s capture setup plus hold time (tCS plus tCH). BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO balls. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CLK captured in the boundary scan register. Reserved After the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO balls. These instructions are not implemented but are reserved for future use. Do not use these instructions. TAP Timing 1 2 Test Clock (TCK ) 3 t TH t TM SS t TM SH t TDIS t TDIH t TL 4 5 6 t CY C Test M ode Select (TM S) Test Data-In (TDI) t TDOV t TDOX Test Data-Out (TDO) DON’T CA RE Document #: 38-05288 Rev. *J UNDEFINED Page 15 of 32 CY7C1471V33 CY7C1473V33 CY7C1475V33 TAP AC Switching Characteristics Over the Operating Range[10, 11] Parameter Description Min Max Unit Clock tTCYC TCK Clock Cycle Time tTF TCK Clock Frequency tTH TCK Clock HIGH time 20 ns tTL TCK Clock LOW time 20 ns 50 ns 20 MHz Output Times tTDOV TCK Clock LOW to TDO Valid tTDOX TCK Clock LOW to TDO Invalid 5 ns 0 ns 5 ns Setup Times tTMSS TMS Setup to TCK Clock Rise tTDIS TDI Setup to TCK Clock Rise 5 ns tCS Capture Setup to TCK Rise 5 ns tTMSH TMS Hold after TCK Clock Rise 5 ns tTDIH TDI Hold after Clock Rise 5 ns tCH Capture Hold after Clock Rise 5 ns Hold Times Notes 10.tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register. 11.Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 ns. Document #: 38-05288 Rev. *J Page 16 of 32 CY7C1471V33 CY7C1473V33 CY7C1475V33 3.3V TAP AC Test Conditions 2.5V TAP AC Test Conditions Input pulse levels ................................................ VSS to 3.3V Input pulse levels................................................. VSS to 2.5V Input rise and fall times ................................................... 1 ns Input rise and fall time .....................................................1 ns Input timing reference levels ...........................................1.5V Input timing reference levels......................................... 1.25V Output reference levels...................................................1.5V Output reference levels ................................................ 1.25V Test load termination supply voltage...............................1.5V Test load termination supply voltage ............................ 1.25V 3.3V TAP AC Output Load Equivalent 2.5V TAP AC Output Load Equivalent 1.25V 1.5V 50Ω 50Ω TDO TDO Z O= 50Ω Z O= 50Ω 20pF 20pF TAP DC Electrical Characteristics And Operating Conditions (0°C < TA < +70°C; VDD = 3.3V ±0.165V unless otherwise noted)[12] Parameter VOH1 VOH2 VOL1 VOL2 VIH VIL IX Description Output HIGH Voltage Output HIGH Voltage Output LOW Voltage Output LOW Voltage Test Conditions Max Unit IOH = –4.0 mA, VDDQ = 3.3V 2.4 V IOH = –1.0 mA, VDDQ = 2.5V 2.0 V IOH = –100 µA VDDQ = 3.3V 2.9 V VDDQ = 2.5V 2.1 V IOL = 8.0 mA VDDQ = 3.3V 0.4 V IOL = 1.0 mA VDDQ = 2.5V 0.4 V VDDQ = 3.3V 0.2 V VDDQ = 2.5V 0.2 V IOL = 100 µA Input HIGH Voltage Input LOW Voltage Input Load Current Min GND < VIN < VDDQ VDDQ = 3.3V 2.0 VDD + 0.3 V VDDQ = 2.5V 1.7 VDD + 0.3 V VDDQ = 3.3V –0.3 0.8 V VDDQ = 2.5V –0.3 0.7 V –5 5 µA Note 12. All voltages refer to VSS (GND). Document #: 38-05288 Rev. *J Page 17 of 32 CY7C1471V33 CY7C1473V33 CY7C1475V33 Identification Register Definitions CY7C1471V33 (2Mx36) CY7C1473V33 (4Mx18) CY7C1475V33 (1Mx72) 000 000 000 01011 01011 01011 Architecture/Memory Type(23:18) 001001 001001 001001 Defines memory type and architecture Bus Width/Density(17:12) 100100 010100 110100 Defines width and density 00000110100 00000110100 00000110100 1 1 1 Instruction Field Revision Number (31:29) Device Depth (28:24) [13] Cypress JEDEC ID Code (11:1) ID Register Presence Indicator (0) Description Describes the version number Reserved for internal use Enables unique identification of SRAM vendor Indicates the presence of an ID register Scan Register Sizes Register Name Instruction Bit Size (x36) Bit Size (x18) Bit Size (x72) 3 3 3 Bypass 1 1 1 ID 32 32 32 Boundary Scan Order – 165FBGA 71 52 - - - 110 Boundary Scan Order – 209BGA Identification Codes Instruction Code Description EXTEST 000 Captures IO ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM outputs to High-Z state. This instruction is not 1149.1-compliant. IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operations. SAMPLE Z 010 Captures IO ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state. RESERVED 011 Do Not Use: This instruction is reserved for future use. SAMPLE/PRELOAD 100 Captures IO ring contents. Places the boundary scan register between TDI and TDO. Does not affect SRAM operation. This instruction does not implement 1149.1 preload function and is therefore not 1149.1 compliant. RESERVED 101 Do Not Use: This instruction is reserved for future use. RESERVED 110 Do Not Use: This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operations. Note 13. Bit #24 is “1” in the ID Register Definitions for both 2.5V and 3.3V versions of this device. Document #: 38-05288 Rev. *J Page 18 of 32 CY7C1471V33 CY7C1473V33 CY7C1475V33 Boundary Scan Exit Order (2M x 36) Bit # 165-Ball ID Bit # 165-Ball ID Bit # 165-Ball ID Bit # 165-Ball ID 1 C1 21 R3 41 J11 61 B7 2 D1 22 P2 42 K10 62 B6 3 E1 23 R4 43 J10 63 A6 4 D2 24 P6 44 H11 64 B5 5 E2 25 R6 45 G11 65 A5 6 F1 26 R8 46 F11 66 A4 7 G1 27 P3 47 E11 67 B4 8 F2 28 P4 48 D10 68 B3 9 G2 29 P8 49 D11 69 A3 10 J1 30 P9 50 C11 70 A2 11 K1 31 P10 51 G10 71 B2 12 L1 32 R9 52 F10 13 J2 33 R10 53 E10 14 M1 34 R11 54 A9 15 N1 35 N11 55 B9 16 K2 36 M11 56 A10 17 L2 37 L11 57 B10 18 M2 38 M10 58 A8 19 R1 39 L10 59 B8 20 R2 40 K11 60 A7 165-Ball ID Bit # 165-Ball ID Boundary Scan Exit Order (4M x 18) Bit # 165-Ball ID Bit # 165-Ball ID Bit # 1 D2 14 R4 27 L10 40 B10 2 E2 15 P6 28 K10 41 A8 3 F2 16 R6 29 J10 42 B8 4 G2 17 R8 30 H11 43 A7 5 J1 18 P3 31 G11 44 B7 6 K1 19 P4 32 F11 45 B6 7 L1 20 P8 33 E11 46 A6 8 M1 21 P9 34 D11 47 B5 9 N1 22 P10 35 C11 48 A4 10 R1 23 R9 36 A11 49 B3 11 R2 24 R10 37 A9 50 A3 12 R3 25 R11 38 B9 51 A2 13 P2 26 M10 39 A10 52 B2 Document #: 38-05288 Rev. *J Page 19 of 32 CY7C1471V33 CY7C1473V33 CY7C1475V33 Boundary Scan Exit Order (1M x 72) Bit # 209-Ball ID Bit # 209-Ball ID Bit # 209-Ball ID Bit # 209-Ball ID 1 A1 29 T1 57 U10 85 B11 2 A2 30 T2 58 T11 86 B10 3 B1 31 U1 59 T10 87 A11 4 B2 32 U2 60 R11 88 A10 5 C1 33 V1 61 R10 89 A7 6 C2 34 V2 62 P11 90 A5 7 D1 35 W1 63 P10 91 A9 8 D2 36 W2 64 N11 92 U8 9 E1 37 T6 65 N10 93 A6 10 E2 38 V3 66 M11 94 D6 11 F1 39 V4 67 M10 95 K6 12 F2 40 U4 68 L11 96 B6 13 G1 41 W5 69 L10 97 K3 14 G2 42 V6 70 P6 98 A8 15 H1 43 W6 71 J11 99 B4 16 H2 44 V5 72 J10 100 B3 17 J1 45 U5 73 H11 101 C3 18 J2 46 U6 74 H10 102 C4 19 L1 47 W7 75 G11 103 C8 20 L2 48 V7 76 G10 104 C9 21 M1 49 U7 77 F11 105 B9 22 M2 50 V8 78 F10 106 B8 23 N1 51 V9 79 E10 107 A4 24 N2 52 W11 80 E11 108 C6 25 P1 53 W10 81 D11 109 B7 110 A3 26 P2 54 V11 82 D10 27 R2 55 V10 83 C11 28 R1 56 U11 84 C10 Document #: 38-05288 Rev. *J Page 20 of 32 CY7C1471V33 CY7C1473V33 CY7C1475V33 Maximum Ratings DC Input Voltage ................................... –0.5V to VDD + 0.5V Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage........................................... >2001V (MIL-STD-883, Method 3015) Latch Up Current .................................................... >200 mA Operating Range Supply Voltage on VDD Relative to GND........ –0.5V to +4.6V Supply Voltage on VDDQ Relative to GND ...... –0.5V to +VDD DC Voltage Applied to Outputs in Tri-State........................................... –0.5V to VDDQ + 0.5V Ambient VDD VDDQ Temperature Commercial 0°C to +70°C 3.3V –5%/+10% 2.5V – 5% to VDD Industrial –40°C to +85°C Range Electrical Characteristics Over the Operating Range[14, 15] Parameter Description VDD Power Supply Voltage VDDQ IO Supply Voltage VOH Output HIGH Voltage Test Conditions Min Max Unit 3.135 3.6 V For 3.3V IO 3.135 VDD V For 2.5V IO 2.375 2.625 V For 3.3V IO, IOH = –4.0 mA 2.4 V For 2.5V IO, IOH = –1.0 mA 2.0 V VOL Output LOW Voltage For 3.3V IO, IOL = 8.0 mA VIH Input HIGH Voltage[14] For 3.3V IO VIL Input LOW Voltage[14] 0.4 For 2.5V IO, IOL = 1.0 mA IX Input Leakage Current except ZZ and MODE 0.4 V 2.0 VDD + 0.3V V For 2.5V IO 1.7 VDD + 0.3V V For 3.3V IO –0.3 0.8 V For 2.5V IO –0.3 0.7 V –5 5 µA GND ≤ VI ≤ VDDQ Input Current of MODE Input = VSS 5 30 µA 5 µA 7.5 ns cycle, 133 MHz 305 mA 10 ns cycle, 117 MHz 275 mA 7.5 ns cycle, 133 MHz 200 mA 10 ns cycle, 117 MHz 200 mA All speeds 120 mA 200 mA 200 mA 165 mA Input = VDD Output Leakage Current GND ≤ VI ≤ VDD, Output Disabled IDD VDD Operating Supply Current VDD = Max., IOUT = 0 mA, f = fMAX = 1/tCYC Automatic CE Power Down Current—TTL Inputs VDD = Max, Device Deselected, VIN ≥ VIH or VIN ≤ VIL f = fMAX, inputs switching ISB1 –5 ISB2 Automatic CE VDD = Max, Device Deselected, Power Down VIN ≤ 0.3V or VIN > VDD – 0.3V, Current—CMOS Inputs f = 0, inputs static ISB3 VDD = Max, Device Deselected, or 7.5 ns cycle, 133 MHz Automatic CE Power Down VIN ≤ 0.3V or VIN > VDDQ – 0.3V 10 ns cycle, 117 MHz Current—CMOS Inputs f = fMAX, inputs switching Automatic CE VDD = Max, Device Deselected, All Speeds Power Down VIN ≥ VDD – 0.3V or VIN ≤ 0.3V, Current—TTL Inputs f = 0, inputs static ISB4 µA µA –5 Input = VSS IOZ µA –30 Input = VDD Input Current of ZZ V Notes 14. Overshoot: VIH(AC) < VDD +1.5V (pulse width less than tCYC/2). Undershoot: VIL(AC) > –2V (pulse width less than tCYC/2). 15. TPower-up: assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD. Document #: 38-05288 Rev. *J Page 21 of 32 CY7C1471V33 CY7C1473V33 CY7C1475V33 Capacitance Tested initially and after any design or process change that may affect these parameters. Parameter Description Test Conditions 100 TQFP Package 165 FBGA Package 209 BGA Package Unit TA = 25°C, f = 1 MHz, VDD = 3.3V VDDQ = 2.5V 6 6 6 pF 5 5 5 pF 8 8 8 pF CADDRESS Address Input Capacitance CDATA Data Input Capacitance CCTRL Control Input Capacitance CCLK Clock Input Capacitance 6 6 6 pF CIO Input/Output Capacitance 5 5 5 pF 100 TQFP Max 165 FBGA Max 209 FBGA Max Unit 24.63 16.3 15.2 °C/W 2.28 2.1 1.7 °C/W Thermal Resistance Tested initially and after any design or process change that may affect these parameters. Parameter Description ΘJA Thermal Resistance (Junction to Ambient) ΘJC Thermal Resistance (Junction to Case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, according to EIA/JESD51. AC Test Loads and Waveforms 3.3V IO Test Load R = 317Ω 3.3V OUTPUT OUTPUT RL = 50Ω Z0 = 50Ω GND 5 pF R = 351Ω VL = 1.5V INCLUDING JIG AND SCOPE (a) ALL INPUT PULSES VDDQ 10% 90% 10% 90% ≤ 1 ns ≤ 1 ns (c) (b) 2.5V IO Test Load R = 1667Ω 2.5V OUTPUT OUTPUT RL = 50Ω Z0 = 50Ω GND 5 pF R = 1538Ω VL = 1.25V (a) Document #: 38-05288 Rev. *J ALL INPUT PULSES VDDQ INCLUDING JIG AND SCOPE (b) 10% 90% 10% 90% ≤ 1 ns ≤ 1 ns (c) Page 22 of 32 CY7C1471V33 CY7C1473V33 CY7C1475V33 Switching Characteristics Over the Operating Range. Unless otherwise noted in the following table, timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V. Test conditions shown in (a) of “AC Test Loads and Waveforms” on page 22 unless otherwise noted. Description Parameter tPOWER [16] 133 MHz Min Max 117 MHz Min Max Unit 1 1 ms Clock tCYC Clock Cycle Time 7.5 10 ns tCH Clock HIGH 2.5 3.0 ns tCL Clock LOW 2.5 3.0 ns Output Times tCDV Data Output Valid After CLK Rise tDOH Data Output Hold After CLK Rise [17, 18, 19] tCLZ Clock to Low-Z tCHZ Clock to High-Z [17, 18, 19] tOEV OE LOW to Output Valid tOELZ tOEHZ OE LOW to Output Low-Z 6.5 2.5 2.5 3.0 [17, 18, 19] OE HIGH to Output High-Z ns ns 3.0 ns 3.8 4.5 ns 3.0 3.8 ns 0 [17, 18, 19] 8.5 0 3.0 ns 4.0 ns Setup Times tAS Address Setup Before CLK Rise 1.5 1.5 ns tALS ADV/LD Setup Before CLK Rise 1.5 1.5 ns tWES WE, BWX Setup Before CLK Rise 1.5 1.5 ns tCENS CEN Setup Before CLK Rise 1.5 1.5 ns tDS Data Input Setup Before CLK Rise 1.5 1.5 ns tCES Chip Enable Setup Before CLK Rise 1.5 1.5 ns tAH Address Hold After CLK Rise 0.5 0.5 ns tALH ADV/LD Hold After CLK Rise 0.5 0.5 ns tWEH WE, BWX Hold After CLK Rise 0.5 0.5 ns tCENH CEN Hold After CLK Rise 0.5 0.5 ns tDH Data Input Hold After CLK Rise 0.5 0.5 ns tCEH Chip Enable Hold After CLK Rise 0.5 0.5 ns Hold Times Notes 16. This part has an internal voltage regulator; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially, before a read or write operation can be initiated. 17. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of“AC Test Loads and Waveforms” on page 22. Transition is measured ±200 mV from steady-state voltage. 18. At any supplied voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z before Low-Z under the same system conditions. 19. This parameter is sampled and not 100% tested. Document #: 38-05288 Rev. *J Page 23 of 32 CY7C1471V33 CY7C1473V33 CY7C1475V33 Switching Waveforms Figure 1 shows read-write timing waveform.[20, 21, 22] Figure 1. Read/Write Timing 1 2 3 t CYC 4 5 6 7 8 9 A5 A6 A7 10 CLK t CENS t CENH t CES t CEH t CH t CL CEN CE ADV/LD WE BW X A1 ADDRESS t AS A2 A4 A3 t CDV t AH t DOH t CLZ DQ D(A1) t DS D(A2) Q(A3) D(A2+1) t OEV Q(A4+1) Q(A4) t OELZ W RITE D(A1) W RITE D(A2) D(A5) Q(A6) D(A7) W RITE D(A7) DESELECT t OEHZ t DH OE COM M AND t CHZ BURST W RITE D(A2+1) READ Q(A3) READ Q(A4) DON’T CARE BURST READ Q(A4+1) t DOH W RITE D(A5) READ Q(A6) UNDEFINED Notes 20. For this waveform ZZ is tied LOW. 21. When CE is LOW, CE1 is LOW, CE2 is HIGH, and CE3 is LOW. When CE is HIGH, CE1 is HIGH, CE2 is LOW or CE3 is HIGH. 22. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional. Document #: 38-05288 Rev. *J Page 24 of 32 CY7C1471V33 CY7C1473V33 CY7C1475V33 Switching Waveforms (continued) [20, 21, 23] Figure 2 shows NOP, STALL and DESELECT Cycles waveform. Figure 2. NOP, STALL and DESELECT Cycles 1 2 A1 A2 3 4 5 A3 A4 6 7 8 9 10 CLK CEN CE ADV/LD WE BW [A:D] ADDRESS A5 t CHZ D(A1) DQ Q(A2) Q(A3) D(A4) Q(A5) t DOH COMMAND WRITE D(A1) READ Q(A2) STALL READ Q(A3) WRITE D(A4) DON’T CARE STALL NOP READ Q(A5) DESELECT CONTINUE DESELECT UNDEFINED Note 23. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrates CEN being used to create a pause. A write is not performed during this cycle. Document #: 38-05288 Rev. *J Page 25 of 32 CY7C1471V33 CY7C1473V33 CY7C1475V33 Switching Waveforms (continued) Figure 3 shows ZZ Mode timing waveform. [24, 25] Figure 3. ZZ Mode Timing CLK t ZZ I t ZZREC ZZ t ZZI SUPPLY I DDZZ t RZZI ALL INPUTS (except ZZ) Outputs (Q) DESELECT or READ Only High-Z DON’T CARE Notes 24. Device must be deselected when entering ZZ mode. See “Truth Table” on page 11 for all possible signal conditions to deselect the device. 25. DQs are in high-Z when exiting ZZ sleep mode. Document #: 38-05288 Rev. *J Page 26 of 32 CY7C1471V33 CY7C1473V33 CY7C1475V33 Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed Package Operating Part and Package Type (MHz) Ordering Code Diagram Range 133 CY7C1471V33-133AXC 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free Commercial CY7C1473V33-133AXC CY7C1471V33-133BZC 51-85165 165-Ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) CY7C1473V33-133BZC CY7C1471V33-133BZXC 51-85165 165-Ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free CY7C1473V33-133BZXC CY7C1475V33-133BGC CY7C1475V33-133BGXC CY7C1471V33-133AXI 51-85167 209-Ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) 209-Ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Pb-Free 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free lndustrial CY7C1473V33-133AXI CY7C1471V33-133BZI 51-85165 165-Ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) CY7C1473V33-133BZI CY7C1471V33-133BZXI 51-85165 165-Ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free CY7C1473V33-133BZXI CY7C1475V33-133BGI CY7C1475V33-133BGXI 117 CY7C1471V33-117AXC 51-85167 209-Ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) 209-Ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Pb-Free 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free Commercial CY7C1473V33-117AXC CY7C1471V33-117BZC 51-85165 165-Ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) CY7C1473V33-117BZC CY7C1471V33-117BZXC 51-85165 165-Ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free CY7C1473V33-117BZXC CY7C1475V33-117BGC CY7C1475V33-117BGXC CY7C1471V33-117AXI 51-85167 209-Ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) 209-Ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Pb-Free 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free lndustrial CY7C1473V33-117AXI CY7C1471V33-117BZI 51-85165 165-Ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) CY7C1473V33-117BZI CY7C1471V33-117BZXI 51-85165 165-Ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free CY7C1473V33-117BZXI CY7C1475V33-117BGI CY7C1475V33-117BGXI Document #: 38-05288 Rev. *J 51-85167 209-Ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) 209-Ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Pb-Free Page 27 of 32 CY7C1471V33 CY7C1473V33 CY7C1475V33 Package Diagrams Figure 4. 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm), 51-85050 16.00±0.20 1.40±0.05 14.00±0.10 100 81 80 1 20.00±0.10 22.00±0.20 0.30±0.08 0.65 TYP. 30 12°±1° (8X) SEE DETAIL A 51 31 50 0.20 MAX. R 0.08 MIN. 0.20 MAX. 0.10 1.60 MAX. 0° MIN. SEATING PLANE STAND-OFF 0.05 MIN. 0.15 MAX. 0.25 NOTE: 1. JEDEC STD REF MS-026 GAUGE PLANE 0°-7° R 0.08 MIN. 0.20 MAX. 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 3. DIMENSIONS IN MILLIMETERS 0.60±0.15 0.20 MIN. 1.00 REF. DETAIL Document #: 38-05288 Rev. *J A 51-85050-*B Page 28 of 32 CY7C1471V33 CY7C1473V33 CY7C1475V33 Package Diagrams (continued) Figure 5. 165-Ball FBGA (15 x 17 x 1.4 mm), 51-85165 PIN 1 CORNER BOTTOM VIEW TOP VIEW Ø0.05 M C PIN 1 CORNER Ø0.25 M C A B Ø0.45±0.05(165X) 1 2 3 4 5 6 7 8 9 10 11 11 10 9 8 7 6 5 4 3 2 1 A B B C C 1.00 A D D F F G G H J 14.00 E 17.00±0.10 E H J K L L 7.00 K M M N N P P R R A 1.00 5.00 0.35 0.15 C +0.05 -0.10 0.53±0.05 0.25 C 10.00 B 15.00±0.10 0.15(4X) SEATING PLANE Document #: 38-05288 Rev. *J 1.40 MAX. 0.36 C 51-85165-*A Page 29 of 32 CY7C1471V33 CY7C1473V33 CY7C1475V33 Package Diagrams (continued) Figure 6. 209-Ball FBGA (14 x 22 x 1.76 mm), 51-85167 51-85167-** NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology, Inc. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05288 Rev. *J Page 30 of 32 © Cypress Semiconductor Corporation, 2002-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY7C1471V33 CY7C1473V33 CY7C1475V33 Document History Page Document Title: CY7C1471V33/CY7C1473V33/CY7C1475V33, 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL™ Architecture Document Number: 38-05288 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 114675 08/06/02 PKS New Data Sheet *A 121521 02/07/03 CJM Updated features for package offering Updated ordering information Changed Advanced Information to Preliminary *B 223721 See ECN NJY Changed timing diagrams Changed logic block diagrams Modified Functional Description Modified “Functional Overview” section Added boundary scan order for all packages Included thermal numbers and capacitance values for all packages Removed 150-MHz speed grade offering Included ISB and IDD values Changed package outline for 165FBGA package and 209-Ball BGA package Removed 119-BGA package offering *C 235012 See ECN RYQ Minor Change: The data sheets do not match on the spec system and external web *D 243572 See ECN NJY Changed ball H2 from VDD to NC in the 165-Ball FBGA package in page 6 Modified capacitance values on page 21 *E 299511 See ECN SYT Removed 117-MHz Speed Bin Changed ΘJA from 16.8 to 24.63 °C/W and ΘJC from 3.3 to 2.28 °C/W for 100 TQFP Package on Page # 21 Added Pb-free information for 100-Pin TQFP, 165 FBGA and 209 BGA Packages Added comment of ‘Pb-free BG packages availability’ below the Ordering Information *F 320197 See ECN PCI Corrected part number typos in the logic block diagram on page# 2 *G 331513 See ECN PCI Address expansion pins/balls in the pinouts for all packages are modified as per JEDEC standard Added Address Expansion pins in the Pin Definitions Table Added Industrial Operating Range Modified VOL, VOH Test Conditions Updated Ordering Information Table *H 416221 See ECN RXU Converted from Preliminary to Final Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court” Removed 100MHz Speed bin & Added 117MHz Speed bin Changed the description of IX from Input Load Current to Input Leakage Current on page# 19 Changed the IX current values of MODE on page # 19 from –5 µA and 30 µA to –30 µA and 5 µA Changed the IX current values of ZZ on page # 19 from –30 µA and 5 µA to –5 µA and 30 µA Changed VIH < VDD to VIH < VDD on page # 19 Replaced Package Name column with Package Diagram in the Ordering Information table Updated the Ordering Information Table Document #: 38-05288 Rev. *J Page 31 of 32 CY7C1471V33 CY7C1473V33 CY7C1475V33 Document Title: CY7C1471V33/CY7C1473V33/CY7C1475V33, 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL™ Architecture Document Number: 38-05288 REV. ECN NO. Issue Date Orig. of Change Description of Change *I 472335 See ECN VKN Corrected the typo in the pin configuration for 209-Ball FBGA pinout (Corrected the ball name for H9 to VSS from VSSQ). Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND. Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP AC Switching Characteristics table. Updated the Ordering Information table. *J 1274732 See ECN Document #: 38-05288 Rev. *J VKN/AESA Corrected typo in the “NOP, STALL and DESELECT Cycles” waveform Page 32 of 32