Harris IH6208 8-channel cmos analog multiplexer Datasheet

IH6208
Semiconductor
T
UCT
ROD RODUC
P
E
P
T
E
E
A)
OL
UT
OBS UBSTIT HI-0509(
,
S
A
E
G509
SIBL
POS G409, D
D
April 1999
8-Channel
CMOS Analog Multiplexer
Features
Description
• Ultra Low Leakage - ID(OFF) ≤ 100pA (Typ)
• Binary Address Control (2 Address Inputs Control 2
Out of 8 Channels)
The IH6208 is a CMOS 2 of 8 multiplexer. The part is a
plug-in replacement for the DG509A. Two-line binary
decoding is used so that the 8 channels can be controlled in
pairs by the binary inputs; additionally a third input is
provided for use as a system enable. When the ENABLE
input is high (5V), the channels are sequenced by the 2 line
binary inputs, and when low (0V) all channels are off. The 2
Address inputs arecontrolled by TTL logic or CMOS logic
elements with a “0” corresponding to any voltage less than
0.8V and a “1” corresponding to any voltage greater than
2.4V. Note that the ENABLE input must be taken to 5V to
enable the system, and less than 0.8V to disable the system.
• TTL and CMOS Compatible Address Control
Part Number Information
• rDS(ON) < 400Ω Over Full Signal and Temperature
Range
• Power Supply Quiescent Current Less Than 100µA
• ±14V Analog Signal Range
• No SCR Latchup
• Break-Before-Make Switching
• Pin Compatible with DG509A, HI-509 and ADG509A
PART
NUMBER
• Internal Diode in Series with V+ for Fault Protection
Pinout
TEMP.
RANGE (oC)
PKG.
NO.
PACKAGE
IH6208MJE
-55 to 125
16 Ld CERDIP
F16.3
IH6208MJE/883B
-55 to 125
16 Ld CERDIP
F16.3
IH6208MFE/883B
-55 to 125
16 Ld Flat Pack
K16.A
IH6208CJE
0 to 70
16 Ld CERDIP
F16.3
IH6208CPE
0 to 70
16 Ld PDIP
E16.3
Functional Diagram
IH6208
(CERDIP, PDIP)
TOP VIEW
S1a
S2a
S3a
A0 1
16 A1
EN 2
15 GND
S4a
14 V+
S1b
S1a 4
13 S1b
S2b
S2a 5
12 S2b
S3b
V- 3
S3a 6
11 S3b
S4a 7
10 S4b
Da 8
9 Db
Da
Db
ADDRESS DECODER
1 OF 4
A0
ENABLE
INPUT
A1
EN
2 LINE BINARY ADDRESS INPUTS
(0 0) AND EN = 5V (EN = “1” for +5V, “0” for 0V)
ABOVE EXAMPLE SHOWS
CHANNELS 1a AND 1b ON.
S4b
TRUTH TABLE
A1
A0
EN
ON SWITCH PAIR
x
x
0
None
0
0
1
1a, 1b
0
1
1
2a, 2b
1
0
1
3a, 3b
1
1
1
4a, 4b
NOTE: A0 , A1
Logic “1” = VAH ≥ 2.4V, VENH ≥ 4.5V
Logic “0” = VAL ≤ 0.8V.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© Harris Corporation 1997
12-129
File Number
3157.2
IH6208
Absolute Maximum Ratings
Thermal Information
VIN (A, EN) to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . -15V to 15V
VS or VD to V+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V, -36V
VS to VD to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V, 36V
V+ to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18V
V- to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-18V
Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30mA
Current (Analog Source or Drain) . . . . . . . . . . . . . . . . . . . . . . 20mA
Thermal Resistance (Typical, Note 1)
θJA (oC/W) θJC (oC/W)
CERDIP Package . . . . . . . . . . . . . . . .
80
22
Ceramic Flatpack Package . . . . . . . . .
85
25
PDIP Package . . . . . . . . . . . . . . . . . . .
100
N/A
Maximum Junction Temperature (Hermetic Package) . . . . . . . . 175oC
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
Operating Conditions
Temperature Range
C Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to 70oC
M Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER
V+ = 15V, V- = -15V, VEN = +5V, Ground = 0V, Unless Otherwise Specified, (Note 4)
M SUFFIX (oC)
C SUFFIX (oC)
TEST CONDITIONS
-55
25
125
0
25
70
UNITS
180
VD = +10V, IS = -1.0mA
Sequence Each Switch On
VAL = 0.8V, VAH = 2.4V
300
300
400
350
350
450
Ω
150
VD = -10V, IS = -1.0mA
Sequence Each Switch On
VAL = 0.8V, VAH = 2.4V
300
300
400
350
350
450
Ω
20
∆rDS(ON) =
rDS ( ON ) MAX –rDS ( ON ) M I N
-----------------------------------------------------------------------------------,
rDS ( ON ) AV G
-
-
-
-
-
-
%
MEASURED
TERMINAL
NO
TESTS
PER
TEMP
TYP
25oC
S to D
8
8
SWITCH
rDS(ON)
∆rDS(ON)
VS = ±10V
IS(OFF)
ID(OFF)
ID(ON)
8
0.002
VS = 10V, VD = -10V
-
±0.5
±50
-
±1
±50
nA
8
0.002
VS = -10V, VD = 10V,
VEN = 0.8V
-
±0.5
±50
-
±1
±50
nA
2
0.03
VD = 10V, VS = -10V,
VEN = 0.8V
-
±2
±50
-
±5
±100
nA
2
0.03
VD = -10V, VS = 10V,
VEN = 0.8V
-
±2
±50
-
±5
±100
nA
8
0.1
VS(ALL) = VD = 10V,
Sequence Each Switch On
VAL = 0.8V, VAH = 2.4V
-
±2
±50
-
±5
±100
nA
8
0.1
VS(ALL) = -10V,
Sequence Each Switch On
VAL = 0.8V, VAH = 2.4V
-
±2
±50
-
±5
±100
nA
2
0.01
VA = 0V
-
-10
-30
-
-10
-30
µA
2
0.01
VA = 14V
-
10
30
-
10
30
µA
A0 , A1
2
0.01
VEN = 5V, All VA = 0V
(Address Pins)
-
-10
-30
-
-10
-30
µA
EN
1
0.01
VEN = 0V, All VA = 0V
(Address Pins)
-
-10
-30
-
-10
-30
µA
S
D
D
INPUT
IAN(ON)
A0 , A1
IAN(OFF)
IA
12-130
IH6208
Electrical Specifications
PARAMETER
V+ = 15V, V- = -15V, VEN = +5V, Ground = 0V, Unless Otherwise Specified, (Note 4) (Continued)
NO
TESTS
PER
TEMP
MEASURED
TERMINAL
TYP
25oC
TEST CONDITIONS
M SUFFIX (oC)
C SUFFIX (oC)
-55
25
125
0
25
70
UNITS
DYNAMIC
tTRANSITION
D
0.3
See Figure 1
-
1
-
-
-
-
µs
tOPEN
D
0.2
See Figure 2
-
-
-
-
-
-
µs
tEN(ON)
D
0.6
See Figure 3
-
1.5
-
-
-
-
µs
tEN(OFF)
D
0.4
See Figure 3
-
1
-
-
-
-
µs
“OFF” Isolation
D
60
VEN = 0V, RL = 200Ω,
CL = 3pF, VS = 3VRMS ,
f = 500kHz
-
-
-
-
-
-
dB
CS(OFF)
S
5
VS = 0V, VEN = 0V,
f = 140kHz to 1MHz
-
-
-
-
-
-
pF
CD(OFF)
D
12
VD = 0V, VEN = 0V,
f = 140kHz to 1MHz
-
-
-
-
-
-
pF
D to S
1
VS = 0V, VD = 0V,
VEN = 0V,
f = 140kHz to 1MHz
-
-
-
-
-
-
pF
CDS(OFF)
SUPPLY
Positive Supply
Current
V+
1
40
VEN = 5V,
All VA = 0V or 5V
-
-
200
-
-
1000
µA
Negative Supply
Current
V-
1
2
VEN = 5V,
All VA = 0V or 5V
-
-
100
-
-
1000
µA
Positive Standby
Current
V+
1
1
VEN = 0V,
All VA = 0V or 5V
-
-
100
-
-
1000
µA
Negative Standby
Current
V-
1
1
VEN = 0V,
All VA = 0V or 5V
-
-
100
-
-
1000
µA
NOTE:
2. See “Enable Input Strobing Levels” in Application Section.
Switching Information
+15V
3.0V
D1
1.4V
V+
VA
50Ω
S1a
S2a
S
IH6208 3a
S4a
S1b
A1
S2b
A0
S3b
0.8V
0
±10V
±10V
S4b
EN
GND
VOUT
0
PROBE
D2
V-
+5V
RP
-15V
S1b(ON)
VS1b
0.9VS1b
CP
PROBE IMPEDANCE
RP ≥ 1MΩ
CP ≤ 30pF
0.9VS4b
VS4b
ttrans
S4b(ON)
FIGURE 1. tTRANSITION SWITCHING TEST CIRCUIT AND WAVEFORMS
12-131
ttrans
IH6208
Switching Information
(Continued)
+15V
VA
S1b
S2b
A1
THRU
A0 IH6208S3b
S4b
EN
+5V
50%
tOPEN
0
tOPEN
0.9VO
VOUT
200Ω
GND
+0.8V
SWITCH
OUTPUT
VOUT
(SEE PINOUT)
D2
+3V
VA
-2V
35pF
VO
VS
-15V
FIGURE 2. tOPEN (BREAK-BEFORE-MAKE) SWITCHING TEST CIRCUIT AND WAVEFORMS
+5V
+15V
A1
A0
S1b
ALL
OTHERS
-5V
0V
0.1VO
IH6208
EN
S4b
VOUT
D2
VEN
200Ω
GND
VEN
tr and tf ≤ 100ns +0.8V
50%
tEN(ON)
tEN(OFF)
SWITCH
OUTPUT
VOUT
(SEE FIGURE 1)
35pF
0.9VO
VO
-5V
-15V
FIGURE 3. tON AND tOFF SWITCHING TEST CIRCUIT AND WAVEFORMS
IH6208 Application Information
ENABLE Input Strobing Levels
Using the IH6208 with Supplies Other Than ±15V
The ENABLE input on the IH6208 requires a minimum of
+4.5V to trigger to the “1” state and a maximum of +0.8V to
trigger to the “0” state. If the ENABLE input is being driven
from TTL logic, a pull-up resistor of 1kΩ to 3kΩ is required
from the gate output to +5V supply. (See Figure 4)
The IH6208 can be used with power supplies ranging from
±6V to ±16V. The switch rDS(ON) will increase as the supply
voltages decrease, however, the multiplexer error term (the
product of leakage times rDS(ON)) will remain approximately
constant since leakage decreases as the supply voltages
are reduced.
When the EN in put is driven from CMOS logic, no pullup is
necessary, see Figure 5.
The supply voltage of the CD4009 affects the switching
speed of the IH6208; the same is true for TTL supply voltage
levels. The following chart shows the effect, on ttrans for a
supply varying from +4.5V to +5.5V.
CMOS OR TTL
SUPPLY VOLTAGE
TYPICAL TTRANS
AT 25oC
+4.5V
+4.75V
+5.00V
+5.25V
+5.50V
400ns
300ns
250ns
200ns
175ns
The throughput rate can therefore be maximized by using a
+5V to +5.5V supply for the ENABLE Strobe Logic.
The examples shown in Figure 4 and 5 deal with ENABLE
strobing when expansion to more than eight channels is
required. In these cases the EN terminal acts as a fourth
address input. If eight channels or less are being
multiplexed, the EN terminal can be directly connected to
+5V logic supply to enable the IH6208 at all times.
Caution must be taken to ensure that the enable (EN)
voltage is at least 0.7V below V+ at all times. If this is not
done, the Address input strobing levels will not function
properly. This may be achieved quite simply by connecting
EN (pin 2) to V+ (pin 14) via a silicon diode as shown in
Figure 6. When using this type of configuration, a further
requirement must be met: the strobe levels of A0 and A1
must be within 2.5V of the EN voltage in order to define a
binary “1” state. For the case shown in Figure 6 the EN
voltage is 11.3V which means that logic high at A0 and A1 is
+8.8V (logic low continues to be 0.8V). In this configuration
the IH6208 cannot be driven by TTL (+5V) or CMOS (+5V)
logic. It can be driven by TTL open collector logic or CMOS
logic with +12V supplies.
If the logic and the IH6208 have common supplies, the EN
pin should again be connected to the supply through a
silicon diode. In this case, tying EN to the logic supply
directly will not work since it violates the 0.7V differential
voltage required between V+ and EN, (See Figure 7). A 1µF
capacitor can be placed across the diode to minimize
switching glitches.
12-132
IH6208
Switching Information
+5V
A0 1
1kΩ
EN
1
14
2
13
-15V 3
12
S1a 4
3
4
DM7404N
TTL LOGIC
11
5
10
6
9
7
8
+3V
0V
16 A1
15
2
14 +15V
IH6208
13 S1b
S2a 5
12 S2b
S3a 6
11 S3b
S4a 7
10 S4b
D1 8
9 D2
FIGURE 4. ENABLE INPUT STROBING FROM TTL LOGIC
+5V
1
16
2
15
14
CD4009
4 CMOS LOGIC 13
3
5
12
6
11
A0 1
EN
10
7
15
2
14 +15V
-15V 3
9
8
16 A1
S1a 4
IH6208
13 S1b
S2a 5
12 S2b
S3a 6
11 S3b
S4a 7
10 S4b
D1 8
9 D2
FIGURE 5. CMOS LOGIC DRIVING ENABLE PIN
1N914
A0 1
EN
16 A1
2
15
-12V 3
14
4
IH6208
13
5
12
6
11
7
10
A CHANNEL SOURCE INPUTS
A CHANNELS COMMON DRAIN OUTPUT = D1 8
+12V
B CHANNEL SOURCE INPUTS
9 D2 = B CHANNEL DRAIN OUTPUT (COMMON)
FIGURE 6. IH6208 CONNECTION DIAGRAM FOR LESS THAN ±15V SUPPLY OPERATION
12-133
IH6208
Switching Information
(Continued)
1N914
A0
EN
1
16
2
15
14
A1
1
16
2
15
-12V 3
3
14
S1a 4
13
S2a 5
12
S3a 6
11 S3b
6
11
S4a 7
10 S4b
7
10
D1 8
9 D2
8
9
4
CD4009A
5
IH6208
+12V
13 S1b
12 S2b
FIGURE 7. IH6208 CONNECTION DIAGRAM WITH ENABLE INPUT STROBING FOR LESS THAN ±15V SUPPLY OPERATION
Peak-to-Peak Signal Handling Capability
The IH6208 can handle input signals up to ±14V (actually
-15V to +14.3V because of the input protection diode) when
using the ±15V supplies.
The electrical specifications of the IH6208 are guaranteed
for ±10V signals, but the specifications have very minor
changes for ±14V signals. The notable changes are slightly
lower rDS(ON) and slightly higher leakages.
Schematic Diagram
S1X
S2X
S3X
S4X
S4X
1) A0’ OR A0’
2) A1’ OR A1’
V-
DX
1
2
V-
ADDRESS
DECODER
EN
EN INPUT
EN’
AND
LEVEL SHIFTER
GND
AX
V-
ADDRESS
INPUT
GND
V+
VV++
LEVEL
SHIFTER
V-
VGND
FIGURE 8. 1/ 2 IH6208 SCHEMATIC DIAGRAM
12-134
AX’
AX’
IH6208
V++
P
P
P
P
EN
N
N
N
N
EN’
P
N
V-
GND
FIGURE 9. ENABLE INPUT AND LEVEL SHIFTER
V++
P
P
AX
AX’
N
P
EN
GND
V++
AX’
N
P
N
N
V-
FIGURE 10. ADDRESS INPUT AND LEVEL SHIFTER
12-135
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