Freescale MPC5553MZQ80R2 Microcontroller Datasheet

Freescale Semiconductor
Data Sheet: Product Preview
Document Number: MPC5553
Rev. 0, 06/2006
MPC5553 Microcontroller
Data Sheet
by: Microcontroller Division
This document provides electrical specifications, pin
assignments, and package diagrams for the MPC5553
microcontroller device. For functional characteristics,
refer to the MPC5553/MPC5554 Microcontroller
Reference Manual.
1
Contents
1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.2 Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . 5
3.3 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.4 EMI (Electromagnetic Interference) Characteristics 9
3.5 ESD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 9
3.6 VRC/POR Electrical Specifications . . . . . . . . . . . . 10
3.7 Power Up/Down Sequencing. . . . . . . . . . . . . . . . . 11
3.8 DC Electrical Specifications. . . . . . . . . . . . . . . . . . 13
3.9 Oscillator & FMPLL Electrical Characteristics . . . . 19
3.10 eQADC Electrical Characteristics . . . . . . . . . . . . . 20
3.11 H7Fa Flash Memory Electrical Characteristics . . . 21
3.12 AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.13 AC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.14 Fast Ethernet AC Timing Specifications . . . . . . . . 45
4
Mechanicals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.1 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.2 Package Dimensions. . . . . . . . . . . . . . . . . . . . . . . 55
5
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Overview
The MPC5553 microcontroller (MCU) is a member of
the MPC5500 family of microcontrollers based on the
PowerPC™ Book E architecture. This family of parts
contains many new features coupled with high
performance CMOS technology to provide substantial
reduction of cost per feature and significant performance
improvement over the MPC500 family.
The host processor core of this device is compatible with
the PowerPC Book E architecture. It is 100% user mode
compatible (with floating point library) with the classic
PowerPC instruction set. The Book E architecture has
enhancements that improve the PowerPC architecture’s
fit in embedded applications. This core also has
additional instructions, including digital signal
processing (DSP) instructions, beyond the classic
This document contains information on a new product. Specifications and information herein
are subject to change without notice.
© Freescale Semiconductor, Inc., 2006. All rights reserved.
• Preliminary—Subject to Change Without Notice
Overview
PowerPC instruction set. This family of parts contains many new features coupled with high performance
CMOS technology to provide significant performance improvement over the MPC565.
The MPC5553 of the MPC5500 family has two levels of memory hierarchy. The fastest accesses are to the
8-kilobyte unified cache. The next level in the hierarchy contains the 64-kilobyte on-chip internal SRAM
and 1.5 Mbyte internal Flash memory. Both the internal SRAM and the Flash memory can hold
instructions and data. The external bus interface has been designed to support most of the standard
memories used with the MPC5xx family.
The complex I/O timer functions of the MPC5500 family are performed by an enhanced time processor
unit engine (eTPU). The eTPU engine controls 32 hardware channels. The eTPU has been enhanced over
the TPU by providing 24-bit timers, double action hardware channels, variable number of parameters per
channel, angle clock hardware, and additional control and arithmetic instructions. The eTPU can be
programmed using a high-level programming language.
The less complex timer functions of the MPC5500 family are performed by the enhanced modular
input/output system (eMIOS). The eMIOS’ 24 hardware channels are capable of single action, double
action, pulse width modulation (PWM), and modulus counter operation. Motor control capabilities include
edge-aligned and center-aligned PWM.
Off-chip communication is performed by a suite of serial protocols including controller area networks
(FlexCANs), enhanced deserial/serial peripheral interfaces (DSPI), and enhanced serial communications
interfaces (eSCIs). The DSPIs support pin reduction through hardware serialization and deserialization of
timer channels and general-purpose input/output (GPIO) signals.
The MCU of the MPC5553 has an on-chip 40-channel enhanced queued dual analog-to-digital converter
(eQADC).
The system integration unit (SIU) performs several chip-wide configuration functions. Pad configuration
and general-purpose input and output (GPIO) are controlled from the SIU. External interrupts and reset
control are also found in the SIU. The internal multiplexer submodule (SIU_DISR) provides multiplexing
of eQADC trigger sources, daisy chaining the DSPIs and external interrupt signal multiplexing.
MPC5553 Microcontroller Data Sheet, Rev. 0
2
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Ordering Information
2
Ordering Information
M PC 5553 M ZP 80 R2
Qualification Status
Core Code
Device Number
Temperature Range
Package Identifier
Operating Frequency (MHz)
Tape and Reel Status
Temperature Range
M = -40° C to 125° C
A = -55° C to 125° C
Package Identifier
ZP = 416PBGA SnPb
VR = 416PBGA Pb-free
VF = 208MAPBGA SnPb
VM = 208MAPBGA Pb-free
ZQ = 324PBGA SnPb
VZ = 324PBGA Pb-free
Operating Frequency
80 = 80MHz
112 = 112MHz
132 = 132MHz
Tape and Reel Status
R2 = Tape and Reel
(blank) = Trays
Qualification Status
P = Pre Qualification
M = Full Spec Qualified
Note: Not all options are available on all devices. Refer to Table 1.
Figure 1. MPC5500 Family Part Number Example
Table 1. Orderable Part Numbers
Freescale Part
Number
Description
Speed
(MHz)
Max Speed1
(MHz) (fMAX)
Temperature
MPC5553MVR132
MPC5553 Lead free 416 package
132
132
-40° C to 125° C
MPC5553MZP132
MPC5553 Lead 416 package
132
132
-40° C to 125° C
MPC5553MVZ132
MPC5553 Lead free 324 package
132
132
-40° C to 125° C
MPC5553MZQ132
MPC5553 Lead 324 package
132
132
-40° C to 125° C
MPC5553MVF132
MPC5553 Lead 208 package
132
132
-40° C to 125° C
MPC5553MVM132
MPC5553 Lead free 208 package
132
132
-40° C to 125° C
MPC5553MVR112
MPC5553 Lead free 416 package
112
114
-40° C to 125° C
MPC5553MZP112
MPC5553 Lead 416 package
112
114
-40° C to 125° C
MPC5553MVZ112
MPC5553 Lead free 324 package
112
114
-40° C to 125° C
MPC5553MZQ112
MPC5553 Lead 324 package
112
114
-40° C to 125° C
MPC5553MVF112
MPC5553 Lead 208 package
112
114
-40° C to 125° C
MPC5553MVM112
MPC5553 Lead free 208 package
112
114
-40° C to 125° C
MPC5553MVR80
MPC5553 Lead free 416 package
80
82
-40° C to 125° C
MPC5553MZP80
MPC5553 Lead 416 package
80
82
-40° C to 125° C
MPC5553MVZ80
MPC5553 Lead free 324 package
80
82
-40° C to 125° C
MPC5553MZQ80
MPC5553 Lead 324 package
80
82
-40° C to 125° C
MPC5553 Microcontroller Data Sheet, Rev. 0
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
3
Electrical Characteristics
Table 1. Orderable Part Numbers (continued)
MPC5553MVF80
MPC5553 Lead 208 package
80
82
-40° C to 125° C
MPC5553MVM80
MPC5553 Lead free 208 package
80
82
-40° C to 125° C
1
3
Speed is the nominal maximum frequency. Max Speed is the maximum speed allowed including any frequency
modulation. 80-MHz parts allow for 80 MHz + 2% modulation. However, 132-MHz allows only 128 MHz + 2% FM.
Electrical Characteristics
This section contains detailed information on power considerations, DC/AC electrical characteristics, and
AC timing specifications for the MCU.
3.1
Maximum Ratings
Table 2. Absolute Maximum Ratings1
Num
Characteristic
Symbol
Min
Max2
Unit
1
1.5V Core Supply Voltage 3
VDD
– 0.3
1.7
V
2
Flash Program/Erase Voltage
VPP
– 0.3
6.5
V
3
Flash Core Voltage
VDDF
– 0.3
1.7
V
4
Flash Read Voltage
VFLASH
– 0.3
4.6
V
5
SRAM Standby Voltage
VSTBY
– 0.3
1.7
V
6
Clock Synthesizer Voltage
VDDSYN
– 0.3
4.6
V
7
3.3V I/O Buffer Voltage
VDD33
–0.3
4.6
V
8
Voltage Regulator Control Input Voltage
VRC33
–0.3
4.6
V
9
Analog Supply Voltage (reference to VSSA)
VDDA
– 0.3
5.5
V
VDDE
– 0.3
4.6
V
VDDEH
– 0.3
6.5
V
–1.06
6.58
–0.37
–1.06
6.58
4.69
10
11
I/O Supply Voltage (Fast I/O Pads)
4
I/O Supply Voltage (Slow/Medium I/O Pads)
4
Voltage5
DC Input
VDDEH powered I/O Pads, except eTPUB15 and
SINB (DSPI_B_SIN)
VDDEH powered I/O Pads (eTPUB15 and SINB)
VDDE powered I/O Pads
VIN
13
Analog Reference High Voltage (reference to VRL)
VRH
– 0.3
5.5
V
14
VSS Differential Voltage
VSS – VSSA
– 0.1
0.1
V
15
VDD Differential Voltage
VDD – VDDA
– VDDA
VDD
V
16
VREF Differential Voltage
VRH – VRL
– 0.3
5.5
V
17
VRH to VDDA Differential Voltage
VRH – VDDA
– 5.5
5.5
V
18
VRL to VSSA Differential Voltage
VRL – VSSA
– 0.3
0.3
V
19
VDDEH to VDDA Differential Voltage
VDDEH – VDDA
–VDDA
VDDEH
V
20
VDDF to VDD Differential Voltage
VDDF – VDD
–0.3
0.3
V
21
This spec has been moved to Table 9, spec 43a.
22
VSSSYN to VSS Differential Voltage
VSSSYN – VSS
–0.1
0.1
V
12
V
MPC5553 Microcontroller Data Sheet, Rev. 0
4
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
Table 2. Absolute Maximum Ratings1 (continued)
Num
23
Characteristic
VRCVSS to VSS Differential Voltage
10
Min
Max2
Unit
VRCVSS – VSS
–0.1
0.1
V
IMAXD
–2
2
mA
mA
24
Maximum DC Digital Input Current
digital pins)5
25
Maximum DC Analog Input Current 11 (per pin, applies to all
analog pins)
IMAXA
–3
3
26
Maximum Operating Temperature Range 12 — Die Junction
Temperature
TJ
– 40.0
150.0
o
C
27
Storage Temperature Range
TSTG
– 55.0
150.0
o
C
o
C
28
29
Maximum Solder Temperature
Moisture Sensitivity Level
(per pin, applies to all
Symbol
13
14
TSDR
—
260.0
MSL
—
3
1
Functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are stress ratings only,
and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect device reliability or
cause permanent damage to the device.
2 Absolute maximum voltages are currently maximum burn-in voltages. Absolute maximum specifications for device stress have
not yet been determined.
3 1.5V +/– 10% for proper operation. This parameter is specified at a maximum junction temperature of 150C.
4 All functional non-supply I/O pins are clamped to VSS and VDDE or VDDEH.
5 AC signal over and undershoot of the input voltages of up to +/– 2.0 volts is permitted for a cumulative duration of 60 hours
over the complete lifetime of the device (injection current does not need to be limited for this duration).
6 Internal structures will hold the voltage above –1.0 volt if the injection current limit of 1 mA is met.
7 Internal structures will not clamp to a safe voltage. External protection must be used to ensure that voltage on the pin stays
above –0.3 volts.
8 Internal structures hold the input voltage below this maximum voltage on all pads powered by VDDEH supplies, if the maximum
injection current specification is met (1 mA for all pins) and VDDEH is within Operating Voltage specifications.
9 Internal structures hold the input voltage below this maximum voltage on all pads powered by VDDE supplies, if the maximum
injection current specification is met (1 mA for all pins) and VDDE is within Operating Voltage specifications.
10 Total injection current for all pins (including both digital and analog) must not exceed 25mA.
11 Total injection current for all analog input pins must not exceed 15mA.
12 Lifetime operation at these specification limits is not guaranteed.
13 Solder profile per CDF-AEC-Q100.
14 Moisture sensitivity per JEDEC test method A112.
3.2
Thermal Characteristics
Table 3. Thermal Characteristics
Value
Num
Characteristic
Symbol
Unit
208 MAPBGA 324 PBGA 416 PBGA
1
Junction to Ambient 1, 2
Natural Convection
(Single layer board)
RθJA
°C/W
41
30
29
2
Junction to Ambient 1, 3
Natural Convection
(Four layer board 2s2p)
RθJA
°C/W
25
21
21
MPC5553 Microcontroller Data Sheet, Rev. 0
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
5
Electrical Characteristics
Table 3. Thermal Characteristics (continued)
Value
Num
Characteristic
Symbol
Unit
208 MAPBGA 324 PBGA 416 PBGA
3
Junction to Ambient 1, 3
(@200 ft./min.,
Single layer board)
RθJMA
°C/W
33
24
23
4
Junction to Ambient 1, 3
(@200 ft./min.,
Four layer board 2s2p)
RθJMA
°C/W
22
17
18
5
Junction to Board 4
(Four layer board 2s2p)
RθJB
°C/W
15
12
13
6
Junction to Case 5
RθJC
°C/W
7
8
9
ΨJT
°C/W
2
2
2
7
1
2
3
4
5
6
Junction to Package Top
Natural Convection
6
Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specification.
Per JEDEC JESD51-6 with the board horizontal.
Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is
measured on the top surface of the board near the package.
Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate
method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature.
Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2.
3.2.1
General Notes for Specifications at Maximum Junction Temperature
An estimation of the chip junction temperature, TJ, can be obtained from the equation:
TJ = TA + (RθJA × PD)
where:
TA = ambient temperature for the package (oC)
RθJA = junction to ambient thermal resistance (oC/W)
PD = power dissipation in the package (W)
The supplied thermal resistances are provided based on JEDEC JESD51 series of standards to provide
consistent values for estimations and comparisons. The difference between the values determined on the
single-layer (1s) board and on the four-layer board with two signal layers and a power and a ground plane
(2s2p) clearly demonstrate that the effective thermal resistance of the component is not a constant. It
depends on the construction of the application board (number of planes), the effective size of the board
which cools the component, how well the component is thermally and electrically connected to the planes,
and the power being dissipated by adjacent components.
Connect all the ground and power balls to the respective planes with one via per ball. Using fewer vias to
connect the package to the planes reduces the thermal performance. Thinner planes also reduce the thermal
MPC5553 Microcontroller Data Sheet, Rev. 0
6
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
performance. When the clearance between through vias leave the planes virtually disconnected, the
thermal performance is also greatly reduced.
As a general rule, the value obtained on a single layer board is appropriate for the tightly packed printed
circuit board. The value obtained on the board with the internal planes is usually appropriate if the
application board has one oz (35 micron nominal thickness) internal planes, the components are well
separated, and the overall power dissipation on the board is less than 0.02 W/cm2.
The thermal performance of any component depends strongly on the power dissipation of surrounding
components. In addition, the ambient temperature varies widely within the application. For many natural
convection and especially closed box applications, the board temperature at the perimeter (edge) of the
package is approximately the same as the local air temperature near the device. Specifying the local
ambient conditions explicitly as the board temperature provides a more precise description of the local
ambient conditions that determine the temperature of the device.
At a known board temperature, the junction temperature is estimated using the following equation:
TJ = TB + (RθJB × PD)
where:
TJ = junction temperature (oC)
TB = board temperature at the package perimeter (oC/W)
RθJB = junction to board thermal resistance (oC/W) per JESD51-8
PD = power dissipation in the package (W)
When the heat loss from the package case to the air can be ignored, acceptable predictions of junction
temperature can be made. The application board should be similar to the thermal test condition, with the
component soldered to a board with internal planes.
Historically, the thermal resistance has frequently been expressed as the sum of a junction to case thermal
resistance and a case to ambient thermal resistance:
RθJA = RθJC + RθCA
where:
RθJA = junction to ambient thermal resistance (oC/W)
RθJC = junction to case thermal resistance (oC/W)
RθCA = case to ambient thermal resistance (oC/W)
RθJC is device related and cannot be influenced by the user. The user controls the thermal environment to
change the case to ambient thermal resistance, RθCA. For instance, the user can change the air flow around
the device, add a heat sink, change the mounting arrangement on printed circuit board, or change the
thermal dissipation on the printed circuit board surrounding the device. This description is most useful for
packages with heat sinks where some 90% of the heat flow is through the case to the heat sink to ambient.
For most packages, a better model is required.
A more accurate two-resistor thermal model can be constructed from the junction to board thermal
resistance and the junction to case thermal resistance. The junction to case covers the situation where a
heat sink will be used or where a substantial amount of heat is dissipated from the top of the package. The
junction to board thermal resistance describes the thermal performance when most of the heat is conducted
MPC5553 Microcontroller Data Sheet, Rev. 0
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
7
Electrical Characteristics
to the printed circuit board. This model can be used for either hand estimations or for a computational fluid
dynamics (CFD) thermal model.
To determine the junction temperature of the device in the application after prototypes are available, the
Thermal Characterization Parameter (ΨJT) can be used to determine the junction temperature with a
measurement of the temperature at the top center of the package case using the following equation:
TJ = TT + (ΨJT × PD)
where:
TT = thermocouple temperature on top of the package (oC)
ΨJT = thermal characterization parameter (oC/W)
PD = power dissipation in the package (W)
The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T
thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so
that the thermocouple junction rests on the package. A small amount of epoxy is placed over the
thermocouple junction and over about 1 mm of wire extending from the junction. The thermocouple wire
is placed flat against the package case to avoid measurement errors caused by cooling effects of the
thermocouple wire.
References:
Semiconductor Equipment and Materials International
805 East Middlefield Rd
Mountain View, CA 94043
(415) 964-5111
MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at
800-854-7179 or 303-397-7956.
JEDEC specifications are available on the WEB at http://www.jedec.org.
• 1. C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an
Automotive Engine Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47–54.
• 2. G. Kromann, S. Shidore, and S. Addison, “Thermal Modeling of a PBGA for Air-Cooled
Applications,” Electronic Packaging and Production, pp. 53–58, March 1998.
• 3. B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal
Resistance and Its Application in Thermal Modeling,” Proceedings of SemiTherm, San Diego,
1999, pp. 212–220.
3.3
Package
The MPC5553 is available in packaged form. Package options are listed in Section 2, “Ordering
Information.”
Refer to Section 4, “Mechanicals,” for pinouts and package drawings.
MPC5553 Microcontroller Data Sheet, Rev. 0
8
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
3.4
EMI (Electromagnetic Interference) Characteristics
Table 4. EMI Testing Specifications1
Num
Characteristic
Min. Value
Typ. Value
Max. Value
Unit
0.15
—
1000
MHz
1
Scan Range
2
Operating Frequency
—
—
132
MHz
3
VDD Operating Voltages
—
1.5
—
V
4
VDDSYN, VRC33, VDD33, VFLASH, VDDE Operating Voltages
—
3.3
—
V
5
VPP, VDDEH, VDDA Operating Voltages
—
5.0
—
V
—
142
dBuV
6
Maximum Amplitude
—
323
7
Operating Temperature
—
—
o
25
C
1
EMI testing and I/O port waveforms per SAE J1752/3 issued 1995-03. Qualification testing is performed on the MPC5554 and
applied to MPC5500 family as generic EMI performance data.
2 As measured with “single-chip” EMI program.
3 As measured with “expanded” EMI program.
3.5
ESD Characteristics
Table 5. ESD Ratings1, 2
Characteristic
Symbol
Value
Unit
2000
V
R1
1500
Ohm
C
100
pF
ESD for Human Body Model (HBM)
HBM Circuit Description
ESD for Field Induced Charge Model (FDCM)
500 (all pins)
750 (corner pins)
V
Number of Pulses per pin:
Positive Pulses (HBM)
Negative Pulses (HBM)
—
—
1
1
—
—
Interval of Pulses
—
1
second
1
2
All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits.
A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification
requirements. Complete DC parametric and functional testing shall be performed per applicable device specification at room
temperature followed by hot temperature, unless specified otherwise in the device specification
MPC5553 Microcontroller Data Sheet, Rev. 0
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
9
Electrical Characteristics
3.6
VRC/POR Electrical Specifications
Table 6. VRC/POR Electrical Specifications
Num
Characteristic
Symbol
Min
Max
Units
1
1.5V (VDD) POR Negated (Ramp Up)
1.5V (VDD) POR Asserted (Ramp Down)
V_POR15
1.1
1.1
1.35
1.35
V
2
3.3V (VDDSYN) POR Negated (Ramp Up)
3.3V (VDDSYN) POR Asserted (Ramp Down)
V_POR33
2.0
2.0
2.85
2.85
V
3
RESET Pin Supply (VDDEH6) POR Negated (Ramp Up)
RESET Pin Supply (VDDEH6) POR Asserted (Ramp Down)
V_POR5
2.0
2.0
2.85
2.85
V
4
VRC33 voltage before regulator controller allows the pass transistor
to start turning on
V_TRANS_
START
1.0
2.0
V
5
VRC33 voltage when regulator controller allows the pass transistor
to completely turn on1, 2
V_TRANS_ON
2.0
2.85
V
6
VRC33 voltage above which the regulator controller will keep the
1.5V supply in regulation3, 4
V_VRC33REG
3.0
—
V
7
Current which can be sourced by VRCCTL
11.0
—
mA
25C
9.0
—
mA
150C (Tj)
7.5
—
mA
—
1.0
V
—
50
V/ms
55.08
—
—
8
Voltage differential during power up that VDD33 can lag VDDSYN or
VDDEH6 before VDDSYN and VDDEH6 reach V_POR33 and
V_POR5 minimums respectively
9
Absolute value of Slew Rate on power supply pins
Required Gain:
Idd / I_VRCCTL (@vdd = 1.35v, fsys = 132MHz)4, 6
VDD33_LAG
BETA7
– 40C
1
2
3
4
5
6
7
8
mA
– 40C
8
10
I_VRCCTL5
25C
58.0
—
—
150C (Tj)
70.08
500
—
User must be able to supply full operating current for the 1.5V supply when the 3.3V supply reaches this range.
Current limit may be reached during ramp up and should not be treated as short circuit current.
At peak current for device.
Assumes that the Freescale recommended board requirements and transistor recommendations are met. Board signal
traces/routing from the VRCCTL package signal to the base of the external pass transistor and between the emitter of the pass
transistor to the VDD package signals should have a maximum of 100 nH inductance and minimal resistance (<1 ohm).
VRCCTL should have a nominal 1µF phase compensation capacitor to ground. VDD should have a 20 µF (nominal) bulk
capacitor (> 4 µF over all conditions, including lifetime). High frequency bypass capacitors consisting of eight 0.01 µF, two 0.1
µF, and one 1 µF capacitors should be place around the package on the VDD supply signals.
I_VRCCTL measured at the following conditions: VDD=1.35V, VRC33=3.1V, V_VRCCTL=2.2V.
Values are based on IDD from high use applications as explained in the IDD Electrical Specification.
BETA is measured on a per part basis and is calculated as IDD / I_VRCCTL and represents the worst case external transistor
BETA.
Preliminary value. Final specification pending characterization.
MPC5553 Microcontroller Data Sheet, Rev. 0
10
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
3.7
Power Up/Down Sequencing
Power sequencing between the 1.5-V power supply and VDDSYN or the RESET power supplies is
required if the user provides an external 1.5-V power supply and ties VRC33 to ground. To avoid this
power sequencing requirement, power up VRC33 within the specified operating range, even if not using
the on-chip voltage regulator controller. Refer to Section 3.7.1, “Power Up Sequence (If VRC33
Grounded)” and Section 3.7.2, “Power Down Sequence (If VRC33 Grounded).”
Another power sequencing requirement is that VDD33 must be of sufficient voltage before POR negates,
so that the values on certain pins are treated as 1s when POR does negate. Refer to Section 3.7.3, “Input
Value of Pins During POR Dependent on VDD33.”
Although there is no power sequencing required between VRC33 and VDDSYN during power up, for the
VRC stage turn-on to operate within specification, VRC33 must not lead VDDSYN by more than 600 mV
or lag by more than 100 mV. Higher spikes in the emitter current of the pass transistor will occur if VRC33
leads or lags VDDSYN by more than these amounts. The value of that higher spike in current depends on
the board power supply circuitry and the amount of board level capacitance.
Furthermore, when all of the PORs negate, the system clock will start to toggle, adding another large
increase of the current consumption from VRC33. If VRC33 lags VDDSYN by more than 100 mV, this
increased current consumption can drop VDD low enough to assert the 1.5-V POR again. Oscillations are
even possible because when the 1.5-V POR asserts, the system clock stops, causing the voltage on VDD
to rise until the 1.5-V POR negates again. Any oscillations stop when VRC33 is powered sufficiently.
When powering down, VRC33 and VDDSYN do not have a delta requirement to each other, because the
bypass capacitors internal and external to the device are already charged.
When not powering up or down, VRC33 and VDDSYN do not have a delta requirement to each other for
the VRC to operate within specification.
Although there are no power up/down sequencing requirements to prevent issues like latch-up, excessive
current spikes, etc., the state of the I/O pins during power up/down varies depending on power. Table 7
gives the pin state for the sequence cases for all pins with pad type pad_fc (fast type), and Table 8 for all
pins with pad type pad_mh (medium type) and pad_sh (slow type).
Table 7. Power Sequence Pin States (Fast Pads)
VDDE
VDD33
VDD
pad_fc (Fast)
Output Driver
State
LOW
X
X
Low
VDDE
LOW
X
High
VDDE
VDD33
LOW
High Impedance
VDDE
VDD33
VDD
Functional
Comment
Functional I/O pins are clamped to VSS and VDDE
POR asserted.
No POR asserted
MPC5553 Microcontroller Data Sheet, Rev. 0
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
11
Electrical Characteristics
Table 8. Power Sequence Pin States (Medium and Slow Pads)
VDDEH
VDD
pad_mh/pad_sh
(Medium and Slow)
Output Driver
LOW
X
Low
VDDEH
LOW
High Impedance
VDDEH
VDD
Functional
3.7.1
Comment
Functional I/O pins are clamped to VSS and VDDEH
POR asserted
No POR asserted
Power Up Sequence (If VRC33 Grounded)
In this case, the 1.5-V VDD supply must rise to 1.35-V before the 3.3-V VDDSYN and the RESET power
supplies rises above 2.0 V. This ensures that digital logic in the PLL on the 1.5-V supply will not begin to
operate below the specified operation range lower limit of 1.35 V. Since the internal 1.5-V POR is disabled,
the internal 3.3-V POR or the RESET power POR must be depended on to hold the device in reset. Since
they may negate as low as 2.0 V, it is necessary for VDD to be within spec before the 3.3-V POR and the
RESET POR negate.
VDDSYN and RESET Power
VDD
2.0V
1.35V
VDD must reach 1.35V before VDDSYN and the RESET power reach 2.0V
Figure 2. Power Up Sequence if VRC33 Grounded
3.7.2
Power Down Sequence (If VRC33 Grounded)
In this case, the only requirement is that if VDD falls below its operating range, VDDSYN or the RESET
power must fall below 2.0 V before VDD is allowed to rise back into its operating range. This ensures that
digital 1.5-V logic that is only reset by ORed_POR, which may have been affected by the 1.5V supply
falling below spec, is reset properly.
3.7.3
Input Value of Pins During POR Dependent on VDD33
In order to avoid accidentally selecting the bypass clock because PLLCFG[0:1] and RSTCFG are not
treated as 1s when POR negates, VDD33 must not lag VDDSYN and the RESET pin power (VDDEH6)
when powering the device by more than the VDD33 lag specification in Table 6. VDD33 individually can
lag either VDDSYN or the RESET pin power (VDDEH6) by more than the VDD33 lag specification.
VDD33 can lag one of the VDDSYN or VDDEH6 supplies, but cannot lag both by more than the VDD33
lag specification. This VDD33 lag specification only applies during power up. VDD33 has no lead or lag
requirements when powering down.
MPC5553 Microcontroller Data Sheet, Rev. 0
12
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
3.8
DC Electrical Specifications
Table 9. DC Electrical Specifications
Num
Characteristic
Symbol
Min
Max
Unit
1
Core Supply Voltage (average DC RMS voltage)
VDD
1.35
1.65
V
2
I/O Supply Voltage (Fast I/O)
VDDE
1.62
3.6
V
3
I/O Supply Voltage (Slow/Medium I/O)
VDDEH
3.0
5.25
V
4
3.3V I/O Buffer Voltage
VDD33
3.0
3.6
V
5
Voltage Regulator Control Input Voltage
VRC33
3.0
3.6
V
1
6
Analog Supply Voltage
VDDA
4.5
5.25
V
8
Flash Programming Voltage2
VPP
4.5
5.25
V
9
Flash Read Voltage
VFLASH
3.0
3.6
V
10
SRAM Standby Voltage3
VSTBY
0.8
1.2
V
11
Clock Synthesizer Operating Voltage
VDDSYN
3.0
3.6
V
12
Fast I/O Input High Voltage
VIH_F
0.65 *
VDDE
VDDE + 0.3
V
13
Fast I/O Input Low Voltage
VIL_F
VSS – 0.3
0.35 *
VDDE
V
14
Medium/Slow I/O Input High Voltage
VIH_S
0.65 *
VDDEH
VDDEH +
0.3
V
15
Medium/Slow I/O Input Low Voltage
VIL_S
VSS – 0.3
0.35 *
VDDEH
V
16
Fast I/O Input Hysteresis
VHYS_F
0.1 * VDDE
V
17
Medium/Slow I/O Input Hysteresis
VHYS_S
0.1 * VDDEH
V
18
Analog Input Voltage
VINDC
VSSA –
0.3
VDDA +
0.3
V
19
Fast I/O Output High Voltage (IOH_F = –2.0mA)
VOH_F
0.8 * VDDE
—
V
20
Slow/Medium I/O Output High Voltage (IOH_S = –2.0mA)
VOH_S
0.8 *
VDDEH
—
V
21
Fast I/O Output Low Voltage (IOL_F = 2.0mA)
VOL_F
—
0.2 * VDDE
V
22
Slow/Medium I/O Output Low Voltage (IOL_S = 2.0mA)
VOL_S
—
0.2 *
VDDEH
V
23
Load Capacitance (Fast I/O)4
DSC(SIU_PCR[8:9]) = 0b00
DSC(SIU_PCR[8:9]) = 0b01
DSC(SIU_PCR[8:9]) = 0b10
DSC(SIU_PCR[8:9]) = 0b11
CL
—
—
—
10
20
30
50
pF
pF
pF
pF
24
Input Capacitance (Digital Pins)
CIN
—
7
pF
25
Input Capacitance (Analog Pins)
CIN_A
—
10
pF
MPC5553 Microcontroller Data Sheet, Rev. 0
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
13
Electrical Characteristics
Table 9. DC Electrical Specifications (continued)
Num
Characteristic
Symbol
Min
Max
Unit
26
Input Capacitance (Shared digital and analog pins AN12_MA0_SDS,
AN12_MA1_SDO, AN14_MA2_SDI, and AN15_FCK)
CIN_M
—
12
pF
IDD
IDD
IDD
IDD
—
—
—
—
5509
4509
6009
4909
mA
mA
mA
mA
IDD
IDD
IDD
IDD
—
—
—
—
4609
3809
5209
4209
mA
mA
mA
mA
IDD
IDD
IDD
IDD
—
—
—
—
3509
2909
4009
3309
mA
mA
mA
mA
IDDSTBY @ 25C
VSTBY @ 0.8V
VSTBY @ 1.0V
VSTBY @ 1.2V
IDDSTBY
IDDSTBY
IDDSTBY
—
—
—
20
30
50
µA
µA
µA
IDDSTBY @ 60C
VSTBY @ 0.8V
VSTBY @ 1.0V
VSTBY @ 1.2V
IDDSTBY
IDDSTBY
IDDSTBY
—
—
—
70
100
200
µA
µA
µA
IDDSTBY @ 150C (Tj)
VSTBY @ 0.8V
VSTBY @ 1.0V
VSTBY @ 1.2V
IDDSTBY
IDDSTBY
IDDSTBY
—
—
—
1200
1500
2000
µA
µA
µA
IDD33
—
2 + values
derived
from
procedure
of Footnote
mA
27a Operating Current5 1.5V Supplies @ 132MHz:
VDD (including VDDF max current)6, 7 @1.65V Typical Use
VDD (including VDDF max current)6, 7 @1.35V Typical Use
VDD (including VDDF max current) 7, 8 @1.65V High Use
VDD (including VDDF max current)7, [email protected] High Use
27b Operating Current 51.5V Supplies @ 114MHz:
VDD (including VDDF max current)6, [email protected] Typical Use
VDD (including VDDF max current)6, [email protected] Typical Use
VDD (including VDDF max current)7, 8 @1.65V High Use
VDD (including VDDF max current)7, 8 @1.35V High Use
27c Operating Current5 1.5V Supplies @ 82MHz:
VDD (including VDDF max current)6, 7 @1.65V Typical Use
VDD (including VDDF max current)6, 7 @1.35V Typical Use
VDD (including VDDF max current)7, 8 @1.65V High Use
VDD (including VDDF max current)7, 8 @1.35V High Use
27d
28
Operating Current 3.3V Supplies @ 132MHz:
VDD3310
10
VFLASH
IVFLASH
—
10
mA
VDDSYN
IDDSYN
—
15
mA
MPC5553 Microcontroller Data Sheet, Rev. 0
14
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
Table 9. DC Electrical Specifications (continued)
Num
29
Characteristic
31
Min
Max
Unit
IDDA
IREF
IPP
—
—
—
—
20.0
1.0
25
mA
mA
mA
IDD1
IDD2
IDD3
IDD4
IDD5
IDD6
IDD7
IDD8
IDD9
—
—
—
—
—
—
—
—
—
See
Footnote
mA
mA
mA
mA
mA
mA
mA
mA
mA
IACT_F
10
20
20
110
130
170
µA
µA
µA
10
20
20
100
130
170
µA
µA
µA
10
20
150
170
µA
µA
IINACT_D
– 2.5
2.5
µA
IIC
– 2.0
2.0
mA
IINACT_A
–150
150
nA
IINACT_AD
– 2.5
2.5
µA
VSS – VSSA
– 100
100
mV
VRL
VSSA –
0.1
VSSA +
0.1
V
VRL – VSSA
–100
100
mV
VRH
VDDA –
0.1
VDDA +
0.1
V
VRH – VRL
4.5
5.25
V
Operating Current 5.0V Supplies @ 132MHz (12MHz ADCLK):
VDDA (VDDA0 + VDDA1)
Analog Reference Supply Current (VRH, VRL)
VPP
30
Symbol
Operating Current VDDE11 Supplies:
VDDEH1
VDDE2
VDDE3
VDDEH4
VDDE5
VDDEH6
VDDE7
VDDEH8
VDDEH9
Fast I/O Weak Pull Up Current12
1.62V – 1.98V
2.25V – 2.75V
3.0V – 3.6V
Fast I/O Weak Pull Down Current12
1.62V – 1.98V
2.25V – 2.75V
3.0V – 3.6V
32
Slow/Medium I/O Weak Pull Up/Down Current13
3.0V – 3.6V
4.5V – 5.5V
33
I/O Input Leakage Current14
34
DC Injection Current (per pin)
35
Analog Input Current, Channel Off15
35a Analog Input Current, Shared Analog/Digital pins
(AN12, AN13, AN14, AN15)
11
IACT_S
36
VSS Differential Voltage16
37
Analog Reference Low Voltage
38
VRL Differential Voltage
39
Analog Reference High Voltage
40
VREF Differential Voltage
41
VSSSYN to VSS Differential Voltage
VSSSYN – VSS
–50
50
mV
42
VRCVSS to VSS Differential Voltage
VRCVSS – VSS
–50
50
mV
VDDF – VDD
–100
100
mV
43
VDDF to VDD Differential
Voltage2
MPC5553 Microcontroller Data Sheet, Rev. 0
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
15
Electrical Characteristics
Table 9. DC Electrical Specifications (continued)
Num
Characteristic
43a VRC33 to VDDSYN Differential Voltage
44
Analog Input Differential Signal Range (with common mode 2.5V)
45
Operating Temperature Range — Ambient (Packaged)
46
Slew rate on power supply pins
Symbol
Min
Max
Unit
VRC33 – VDDSYN
–0.1
0.117
V
VIDIFF
– 2.5
2.5
TA
(TL to TH)
– 40.0
125.0
—
—
50
V
ο
C
V/ms
1
| VDDA0–VDDA1 | must be < 0.1V
VPP can drop to 3.0 volts during read operations.
3
During standby operation. If standby operation is not required, VSTBY can be connected to ground.
4
Applies to CLKOUT, external bus pins, and Nexus pins.
5
Maximum average RMS DC current.
6 Average current measured on Automotive benchmark.
7 Peak currents may be higher on specialized code.
8 High use current measured while running optimized SPE assembly code with all code and data 100% locked in cache (0%
miss rate) with all channels of the eMIOS and eTPU running autonomously, plus the eDMA transferring data continuously from
SRAM to SRAM. Higher currents could be seen if an “idle” loop that crosses cache lines is run from cache. Code should be
written to avoid this condition.
9 Preliminary. Final specification pending characterization.
10 Power requirements for the VDD33 supply are dependent on the frequency of operation and load of all I/O pins, and the
voltages on the I/O segments. See Table 11 for values to calculate power dissipation for specific operation.
11 Power requirements for each I/O segment are dependent on the frequency of operation and load of the I/O pins on a particular
I/O segment, and the voltage of the I/O segment. See Table 10 for values to calculate power dissipation for specific operation.
The total power consumption of an I/O segment is the sum of the individual power consumptions for each pin on the segment.
12 Absolute value of current, measured at V and V .
IL
IH
13 Absolute value of current, measured at V and V .
IL
IH
14 Weak pull up/down inactive. Measured at VDDE = 3.6 V and VDDEH = 5.25 V. Applies to pad types: pad_fc, pad_sh, and
pad_mh.
15 Maximum leakage occurs at maximum operating temperature. Leakage current decreases by approximately one-half for each
8 to 12 oC, in the ambient temperature range of 50 to 125 oC. Applies to pad types: pad_a and pad_ae.
16 VSSA refers to both VSSA0 and VSSA1. | VSSA0–VSSA1 | must be < 0.1V
17 Up to 0.6 volts during power up and power down.
2
3.8.1
I/O Pad Current Specifications
The power consumption of an I/O segment depends on the usage of the pins on a particular segment. The
power consumption is the sum of all output pin currents for a particular segment. The output pin current
can be calculated from Table 10 based on the voltage, frequency, and load on the pin. Use linear scaling to
calculate pin currents for voltage, frequency, and load parameters that fall outside the values given in
Table 10.
MPC5553 Microcontroller Data Sheet, Rev. 0
16
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
Table 10. I/O Pad Average DC Current1
Num
Pad Type
Symbol
Frequency
(MHz)
1
Slow
IDRV_SH
Drive Select /
Slew Rate
Control
Current (mA)
25
50
5.25
11
8.0
10
50
5.25
01
3.2
3
2
50
5.25
00
0.7
4
2
200
5.25
00
2.4
Medium
IDRV_MH
50
50
5.25
11
17.3
6
20
50
5.25
01
6.5
7
3.33
50
5.25
00
1.1
8
3.33
200
5.25
00
3.9
66
10
3.6
00
2.8
66
20
3.6
01
5.2
9
Fast
10
2
Voltage (V)
2
5
1
Load2
(pF)
IDRV_FC
11
66
30
3.6
10
8.5
12
66
50
3.6
11
11.0
13
66
10
1.98
00
1.6
14
66
20
1.98
01
2.9
15
66
30
1.98
10
4.2
16
66
50
1.98
11
6.7
17
56
10
3.6
00
2.4
18
56
20
3.6
01
4.4
19
56
30
3.6
10
7.2
20
56
50
3.6
11
9.3
21
56
10
1.98
00
1.3
22
56
20
1.98
01
2.5
23
56
30
1.98
10
3.5
24
56
50
1.98
11
5.7
25
40
10
3.6
00
1.7
26
40
20
3.6
01
3.1
27
40
30
3.6
10
5.1
28
40
50
3.6
11
6.6
29
40
10
1.98
00
1.0
30
40
20
1.98
01
1.8
31
40
30
1.98
10
2.5
32
40
50
1.98
11
4.0
These values are estimated from simulation and are not tested. Currents apply to output pins only.
All loads are lumped.
3.8.2
I/O Pad VDD33 Current Specifications
The power consumption of the VDD33 supply dependents on the usage of the pins on all I/O segments.
The power consumption is the sum of all input and output pin VDD33 currents for all I/O segments. The
output pin VDD33 current can be calculated from Table 11 based on the voltage, frequency, and load on
all fast (pad_fc) pins. The input pin VDD33 current can be calculated from Table 11 based on the voltage,
MPC5553 Microcontroller Data Sheet, Rev. 0
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
17
Electrical Characteristics
frequency, and load on all pad_sh and pad_sh pins. Use linear scaling to calculate pin currents for voltage,
frequency, and load parameters that fall outside the values given in Table 11.
Table 11. VDD33 Pad Average DC Current1
Num
Pad Type
Symbol
Frequency
(MHz)
Load2
(pF)
1
Slow
I33_SH
66
2
Medium
I33_MH
66
VDD33 (V)
VDDE (V)
Drive
Select
Current (mA)
0.5
3.6
5.5
NA
0.003
0.5
3.6
5.5
NA
0.003
Inputs
Outputs
66
10
3.6
3.6
00
0.35
4
66
20
3.6
3.6
01
0.53
5
66
30
3.6
3.6
10
0.62
6
66
50
3.6
3.6
11
0.79
7
66
10
3.6
1.98
00
0.35
8
66
20
3.6
1.98
01
0.44
9
66
30
3.6
1.98
10
0.53
10
66
50
3.6
1.98
11
0.7
11
56
10
3.6
3.6
00
0.30
12
56
20
3.6
3.6
01
0.45
13
56
30
3.6
3.6
10
0.52
14
56
50
3.6
3.6
11
0.67
15
56
10
3.6
1.98
00
0.30
16
56
20
3.6
1.98
01
0.37
17
56
30
3.6
1.98
10
0.45
18
56
50
3.6
1.98
11
0.60
19
40
10
3.6
3.6
00
0.21
20
40
20
3.6
3.6
01
0.31
21
40
30
3.6
3.6
10
0.37
22
40
50
3.6
3.6
11
0.48
23
40
10
3.6
1.98
00
0.21
24
40
20
3.6
1.98
01
0.27
25
40
30
3.6
1.98
10
0.32
26
40
50
3.6
1.98
11
0.42
3
Fast
I33_FC
1
These values are estimated from simulation and not tested. Currents apply to output pins only for the fast pads and to input
pins only for the slow and medium pads.
2
All loads are lumped.
MPC5553 Microcontroller Data Sheet, Rev. 0
18
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
3.9
Oscillator & FMPLL Electrical Characteristics
Table 12. HiP7 FMPLL Electrical Specifications
(VDDSYN = 3.0V to 3.6 V, VSS = VSSSYN = 0 V, TA = TL to TH)
Num
1
Characteristic
PLL Reference Frequency Range:
Crystal reference
External reference
Dual Controller (1:1 mode)
2
System Frequency 1
3
System Clock Period
4
Loss of Reference Frequency
Self Clocked Mode (SCM) Frequency
6
EXTAL Input High Voltage
Crystal Mode 5
4
All other modes (Dual Controller (1:1),
Bypass, External Reference)
7
Min.
Value
Max.
Value
fref_crystal
fref_ext
fref_1:1
8
8
24
20
20
fsys/2
fsys
fico(min) ÷ 2RFD
fMAX 2
MHz
tCYC
—
1 / fsys
ns
fLOR
100
1000
kHz
fSCM
7.4
17.5
MHz
VIHEXT
Vxtal + 0.4v
—
V
VIHEXT
((VDDE5/2) + 0.4v)
—
V
VILEXT
—
Vxtal – 0.4v
V
VILEXT
—
((VDDE5/2) – 0.4v)
V
IXTAL
0.8
3
mA
Unit
MHz
3
5
Symbol
EXTAL Input Low Voltage
Crystal Mode 6
All other modes (Dual Controller (1:1),
Bypass, External Reference)
8
XTAL Current 7
9
Total On-chip stray capacitance on XTAL
CS_XTAL
—
1.5
pF
10
Total On-chip stray capacitance on EXTAL
CS_EXTAL
—
1.5
pF
11
Crystal manufacturer’s recommended
capacitive load
CL
See crystal
specification
See crystal
specification
pF
12
Discrete load capacitance to be connected
to EXTAL
CL_EXTAL
—
2*CL – CS_EXTAL –
CPCB_EXTAL8
pF
13
Discrete load capacitance to be connected
to XTAL
CL_XTAL
—
2*CL – CS_XTAL –
CPCB_XTAL8
pF
14
PLL Lock Time9
tlpll
—
750
µs
15
Dual Controller (1:1) Clock Skew (between
CLKOUT and EXTAL) 10, 11
tskew
–2
2
ns
16
Duty Cycle of reference
tdc
40
60
%
17
Frequency un-LOCK Range
fUL
– 4.0
4.0
% fsys
18
Frequency LOCK Range
fLCK
– 2.0
2.0
% fsys
—
5.0
—
.01
19
12, 13
CLKOUT Period Jitter,
Measured at fSYS Max
Peak-to-peak Jitter
(Clock edge to clock edge)
Long Term Jitter
(Averaged over 2 ms interval)
Cjitter
% fclkout
MPC5553 Microcontroller Data Sheet, Rev. 0
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
19
Electrical Characteristics
Table 12. HiP7 FMPLL Electrical Specifications (continued)
(VDDSYN = 3.0V to 3.6 V, VSS = VSSSYN = 0 V, TA = TL to TH)
Num
Characteristic
20
Frequency Modulation Range Limit 14
(fsysMax must not be exceeded)
21
ICO Frequency.
fico=[fref*(MFD+4)]/(PREDIV+1)15
22
Predivider Output Frequency (to PLL)
Symbol
Min.
Value
Max.
Value
Unit
Cmod
0.8
2.4
%fsys
fico
48
fsys
MHz
fPREDIV
4
fMAX
MHz
1
All internal registers retain data at 0 Hz.
Up to the maximum frequency rating of the device (see Table 1).
3
“Loss of Reference Frequency” is the reference frequency detected internally, which transitions the PLL into self clocked mode.
4 Self clocked mode (SCM) frequency is the frequency that the PLL operates at when the reference frequency falls below f
LOR.
This frequency is measured on the CLKOUT pin with the divider set to divide-by-2 of the system clock. NOTE: In SCM, the
MFD and PREDIV have no effect and the RFD is bypassed.
5
This parameter is meant for those who do not use quartz crystals or resonators, but CAN osc, in crystal mode. In that case,
Vextal – Vxtal >= 400mV criteria has to be met for oscillator’s comparator to produce output clock.
6 This parameter is meant for those who do not use quartz crystals or resonators, but CAN osc, in crystal mode. In that case,
Vxtal – Vextal >= 400mV criteria has to be met for oscillator’s comparator to produce output clock.
7 I
xtal is the oscillator bias current out of the XTAL pin with both EXTAL and XTAL pins grounded.
8 C
PCB_EXTAL and CPCB_XTAL are the measured PCB stray capacitances on EXTAL and XTAL, respectively
9 This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in the
synthesizer control register (SYNCR). From power up with crystal oscillator reference, the lock time will also include the crystal
startup time.
10 PLL is operating in 1:1 PLL mode.
11 VDDE = 3.0 to 3.6V
12 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f .
sys
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the PLL circuitry via VDDSYN and VSSSYN and variation in crystal oscillator frequency increase the jitter percentage
for a given interval. CLKOUT divider set to divide-by-2.
13 Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of jitter + Cmod.
14 Modulation depth selected must not result in f
sys value greater than the fsys maximum specified value.
15 f
RFD)
sys = fico / (2
2
3.10
eQADC Electrical Characteristics
Table 13. eQADC Conversion Specifications (Operating)
Num
Characteristic
Symbol
Min
Max
Unit
FADCLK
1
12
MHz
13+2 (or 15)
14+2 (or 16)
13+128 (or 141)
14+128 (or 142)
1
ADC Clock (ADCLK) Frequency1
2
Conversion Cycles
Differential
Single Ended
CC
3
Stop Mode Recovery Time2
TSR
10
—
µs
4
Resolution3
—
1.25
—
mV
5
INL: 6 MHz ADC Clock
INL6
–4
4
Counts3
6
INL: 12 MHz ADC Clock
INL12
–8
8
Counts
ADCLK
cycles
MPC5553 Microcontroller Data Sheet, Rev. 0
20
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
Table 13. eQADC Conversion Specifications (Operating) (continued)
Num
7
8
9
10
Characteristic
DNL: 6 MHz ADC Clock
DNL: 12 MHz ADC Clock
12
13
Max
Unit
DNL6
–3 4
34
Counts
–6
4
6
4
Counts
–4
5
4
5
Counts
–8
6
8
6
Counts
OFFWC
Full Scale Gain Error with Calibration
Disruptive Input Injection
Min
DNL12
Offset Error with Calibration
11
Symbol
Current 7, 8, 9, 10
GAINWC
IINJ
–1
1
mA
Incremental Error due to injection current. All channels have
same 10kΩ < Rs <100kΩ
Channel under test has Rs=10kΩ,
IINJ=IINJMAX,IINJMIN
EINJ
–4
4
Counts
Total Unadjusted Error for single ended conversions with
calibration11, 12, 13, 14, 15
TUE
–4
4
Counts
1
Conversion characteristics vary with FADCLK rate. Reduced conversion accuracy occurs at maximum FADCLK rate. The
maximum value is based on 800KS/s and the minimum value is based on 20MHz oscillator clock frequency divided by a
maximum 16 factor.
2 Stop mode recovery time is the time from the setting of either of the enable bits in the ADC Control Register to the time that
the ADC is ready to perform conversions.
3 At VRH – VRL = 5.12 V, one lsb = 1.25 mV = one count
4 Guaranteed 10-bit monotonicity
5 The absolute value of the offset error without calibration ≤ 100 counts.
6 The absolute value of the full scale gain error without calibration ≤ 120 counts.
7 Below disruptive current conditions, the channel being stressed has conversion values of 0x3FF for analog inputs greater than
VRH and 0x000 for values less than VRL. This assumes that VRH ≤ VDDA and VRL ≥ VSSA due to the presence of the sample
amplifier. Other channels are not affected by non-disruptive conditions.
8 Exceeding limit may cause conversion error on stressed channels and on unstressed channels. Transitions within the limit do
not affect device reliability or cause permanent damage.
9 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate
resistance values using VPOSCLAMP = VDDA + 0.5V and VNEGCLAMP = – 0.3 V, then use the larger of the calculated values.
10 Condition applies to two adjacent pads on the internal pad.
11 The TUE specification will always be better than the sum of the INL, DNL, offset, and gain errors due to canceling errors.
12 TUE does not apply to differential conversions.
13 Measured at 6 MHz ADC clock. TUE with a 12 MHz ADC clock is: –16 counts < TUE < 16 counts.
14 TUE includes all internal device error such as internal reference variation (75% Ref, 25% Ref)
15
Depending on the customer input impedance, the Analog Input Leakage current (DC Electrical specification 35a) may affect
the actual TUE measured on analog channels AN12, AN13, AN14, AN15.
3.11
H7Fa Flash Memory Electrical Characteristics
Table 14. Flash Program and Erase Specifications1
Num
3
Characteristic
Double Word (64 bits) Program Time4
Min
Typ
Initial
Max2
Max3
Unit
Tdwprogram
—
10
—
500
µs
500
µs
Tpprogram
—
22
445
16 Kbyte Block Pre-program and Erase Time
T16kpperase
—
265
400
5000
ms
48 Kbyte Block Pre-program and Erase Time
T48kpperase
—
340
400
5000
ms
4
Page Program
7
9
Time4
Symbol
MPC5553 Microcontroller Data Sheet, Rev. 0
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
21
Electrical Characteristics
Table 14. Flash Program and Erase Specifications1 (continued)
Num
1
2
3
4
5
6
Characteristic
Symbol
Min
Typ
Initial
Max2
Max3
Unit
10
64 Kbyte Block Pre-program and Erase Time
T64kpperase
—
400
500
5000
ms
8
128 Kbyte Block Pre-program and Erase Time
T128kpperase
—
500
1250
15,000
ms
11
Minimum operating frequency for program and erase
operations6
—
25
—
—
—
MHz
Typical program and erase times assume nominal supply values and operation at 25 oC.
Initial factory condition: ≤ 100 program/erase cycles, 25 oC, typical supply voltage, 80MHz minimum system frequency.
The maximum erase time occurs after the specified number of program/erase cycles. This maximum value is characterized
but not guaranteed.
Actual hardware programming times. This does not include software overhead.
Page size is 256 bits (8 words).
Read frequency of the flash can be up to the maximum operating frequency of the device. There is no minimum read frequency
condition.
Table 15. Flash EEPROM Module Life (Full Temperature Range)
1
Num
Characteristic
Symbol
Min
Typical1
Unit
1a
Number of Program/Erase cycles per block for 16 Kbyte, 48 Kbyte, and 64
Kbyte blocks over the operating temperature range (TJ)
P/E
100,000
—
cycles
1b
Number of Program/Erase cycles per block for 128 Kbyte blocks over the
operating temperature range (TJ)
P/E
10,000
2
Data retention
Blocks with 0 – 1,000 P/E cycles
Blocks with 1,001 – 100,000 P/E cycles
Retention
100,000 cycles
—
years
20
5
Typical endurance is evaluated at 25C. Product qualification is performed to the minimum specification. For additional
information on the Freescale definition of Typical Endurance, please refer to Engineering Bulletin EB619 “Typical Endurance
for Nonvolatile Memory.”
Table 16 shows the FLASH_BIU settings versus frequency of operation. Refer to the device Reference
Manual for definitions of these bit-fields.
Table 16. FLASH_BIU Settings vs. Frequency of Operation
Maximum Frequency (MHz)
APC
RWSC
WWSC
DPFEN
IPFEN
PFLIM
BFEN
up to and including 82 MHz1
0b001
0b001
0b01
0b00,
0b01, or
0b112
0b00,
0b01, or
0b112
0b0000b1103
0b0, 0b14
up to and including 102 MHz5
0b001
0b010
0b01
0b00,
0b01, or
0b112
0b00,
0b01, or
0b112
0b0000b1103
0b0, 0b14
up to and including132 MHz6
0b010
0b011
0b01
0b00,
0b01, or
0b112
0b00,
0b01, or
0b112
0b0000b1103
0b0, 0b14
Default Setting after Reset
0b111
0b111
0b11
0b00
0b00
0b000
0b0
1
This setting allows for 80 MHz system clock with 2% frequency modulation.
MPC5553 Microcontroller Data Sheet, Rev. 0
22
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
2
For maximum flash performance, this should be set to 0b11.
For maximum flash performance, this should be set to 0b110.
4
For maximum flash performance, this should be set to 0b1.
5
This setting allows for 100 MHz system clock with 2% frequency modulation.
6 This setting allows for 128 MHz system clock with 2% frequency modulation.
3
3.12
3.12.1
AC Specifications
Pad AC Specifications
Table 17. Pad AC Specifications (VDDEH = 5.0V, VDDE = 1.8V)1
Num
Pad
SRC/DSC
Out Delay2, 3, 4
(ns)
Rise/Fall4, 5
(ns)
Load Drive
(pF)
1
Slow High Voltage (SH)
11
26
15
50
82
60
200
75
40
50
137
80
200
377
200
50
476
260
200
16
8
50
43
30
200
34
15
50
61
35
200
192
100
50
239
125
200
3.1
2.7
10
01
2.5
20
10
2.4
30
11
2.3
50
01
00
2
Medium High Voltage (MH)
11
01
00
3
1
2
3
4
5
Fast
00
4
Pull Up/Down (3.6V max)
—
—
7500
50
5
Pull Up/Down (5.5V max)
—
—
9000
50
These are worst case values that are estimated from simulation and not tested. The values in the table are simulated at
FSYS = 132MHz, VDD = 1.35V to 1.65V, VDDE = 1.62V to 1.98V, VDDEH = 4.5V to 5.5V, VDD33 and VDDSYN = 3.0V to 3.6V,
TA = TL to TH.
This parameter is supplied for reference and is not guaranteed by design and not tested.
Out delay is shown in Figure 3. Add a maximum of one system clock to the output delay for delay with respect to system clock.
Delay and rise/fall are measured to 20% or 80% of the respective signal.
This parameter is guaranteed by characterization before qualification rather than 100% tested.
MPC5553 Microcontroller Data Sheet, Rev. 0
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
23
Electrical Characteristics
Table 18. De-rated Pad AC Specifications (VDDEH = 3.3V, VDDE = 3.3V)1
Num
Pad
SRC/DSC
Out Delay2, 3, 4
(ns)
Rise/Fall3, 5
(ns)
Load Drive
(pF)
1
Slow High Voltage (SH)
11
39
23
50
120
87
200
101
52
50
188
111
200
507
248
50
597
312
200
23
12
50
64
44
200
50
22
50
90
50
200
261
123
50
305
156
200
3.2
2.4
10
01
2.2
20
10
2.1
30
11
2.1
50
01
00
2
Medium High Voltage (MH)
11
01
00
3
1
2
3
4
5
Fast
00
4
Pull Up/Down (3.6V max)
—
—
7500
50
5
Pull Up/Down (5.5V max)
—
—
9500
50
These are worst case values that are estimated from simulation and not tested. The values in the table are simulated at
FSYS = 132MHz, VDD = 1.35V to 1.65V, VDDE = 3.0V to 3.6V, VDDEH = 3.0V to 3.6V, VDD33 and VDDSYN = 3.0V to 3.6V,
TA = TL to TH.
This parameter is supplied for reference and is not guaranteed by design and not tested.
Delay and rise/fall are measured to 20% or 80% of the respective signal.
Out delay is shown in Figure 3. Add a maximum of one system clock to the output delay for delay with respect to system clock.
This parameter is guaranteed by characterization before qualification rather than 100% tested.
MPC5553 Microcontroller Data Sheet, Rev. 0
24
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
VDD/2
Pad
Internal Data Input Signal
Rising
Edge
Out
Delay
Falling
Edge
Out
Delay
VOH
Pad
Output
VOL
Figure 3. Pad Output Delay
3.13
AC Timing
3.13.1
Reset and Configuration Pin Timing
Table 19. Reset and Configuration Pin Timing1
Num
1
Characteristic
Symbol
Min
Max
Unit
1
RESET Pulse Width
tRPW
10
—
tCYC
2
RESET Glitch Detect Pulse Width
tGPW
2
—
tCYC
3
PLLCFG, BOOTCFG, WKPCFG, RSTCFG Setup Time to RSTOUT Valid
tRCSU
10
—
tCYC
4
PLLCFG, BOOTCFG, WKPCFG, RSTCFG Hold Time from RSTOUT Valid
tRCH
0
—
tCYC
Reset timing specified at FSYS = 132MHz, VDDEH = 3.0V to 5.25V, VDD = 1.35V to 1.65V, TA = TL to TH.
MPC5553 Microcontroller Data Sheet, Rev. 0
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
25
Electrical Characteristics
2
RESET
1
RSTOUT
3
PLLCFG
BOOTCFG
RSTCFG
WKPCFG
4
Figure 4. Reset and Configuration Pin Timing
3.13.2
IEEE 1149.1 Interface Timing
Table 20. JTAG Pin AC Electrical Characteristics1
Num
1
Characteristic
Symbol
Min
Max
Unit
1
TCK Cycle Time
tJCYC
100
—
ns
2
TCK Clock Pulse Width (Measured at VDDE/2)
tJDC
40
60
ns
3
TCK Rise and Fall Times (40% – 70%)
tTCKRISE
—
3
ns
4
TMS, TDI Data Setup Time
tTMSS, tTDIS
5
—
ns
5
TMS, TDI Data Hold Time
tTMSH, tTDIH
25
—
ns
6
TCK Low to TDO Data Valid
tTDOV
—
20
ns
7
TCK Low to TDO Data Invalid
tTDOI
0
—
ns
8
TCK Low to TDO High Impedance
tTDOHZ
—
20
ns
9
JCOMP Assertion Time
tJCMPPW
100
—
ns
10
JCOMP Setup Time to TCK Low
tJCMPS
40
—
ns
11
TCK Falling Edge to Output Valid
tBSDV
—
50
ns
12
TCK Falling Edge to Output Valid out of High Impedance
tBSDVZ
—
50
ns
13
TCK Falling Edge to Output High Impedance
tBSDHZ
—
50
ns
14
Boundary Scan Input Valid to TCK Rising Edge
tBSDST
50
—
ns
15
TCK Rising Edge to Boundary Scan Input Invalid
tBSDHT
50
—
ns
These specifications apply to JTAG boundary scan only. JTAG timing specified at VDD = 1.35V to 1.65V, VDDE = 3.0V to 3.6V,
VDD33 and VDDSYN = 3.0V to 3.6V, TA = TL to TH, and CL = 30pF with DSC = 0b10, SRC = 0b11. See Table 21 for functional
specifications.
MPC5553 Microcontroller Data Sheet, Rev. 0
26
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
TCK
2
3
2
1
3
Figure 5. JTAG Test Clock Input Timing
TCK
4
5
TMS, TDI
6
7
8
TDO
Figure 6. JTAG Test Access Port Timing
MPC5553 Microcontroller Data Sheet, Rev. 0
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
27
Electrical Characteristics
TCK
10
JCOMP
9
Figure 7. JTAG JCOMP Timing
MPC5553 Microcontroller Data Sheet, Rev. 0
28
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
TCK
11
13
Output
Signals
12
Output
Signals
14
15
Input
Signals
Figure 8. JTAG Boundary Scan Timing
MPC5553 Microcontroller Data Sheet, Rev. 0
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
29
Electrical Characteristics
3.13.3
Nexus Timing
Table 21. Nexus Debug Port Timing1
Num
1
MCKO Cycle Time
2
MCKO Duty Cycle
3
2
3
4
5
3
MCKO Low to MDO Data Valid
3
Symbol
Min
Max
Unit
tMCYC
12
8
tCYC
tMDC
40
60
%
tMDOV
–1.5
3.0
ns
4
MCKO Low to MSEO Data Valid
tMSEOV
–1.5
3.0
ns
5
3
MCKO Low to EVTO Data Valid
tEVTOV
–1.5
3.0
ns
6
EVTI Pulse Width
tEVTIPW
4.0
—
tTCYC
7
EVTO Pulse Width
tEVTOPW
1
4
tMCYC
8
TCK Cycle Time
tTCYC
4
—
tCYC
9
TCK Duty Cycle
tTDC
40
60
%
10
TDI, TMS Data Setup Time
tNTDIS, tNTMSS
8
—
ns
11
TDI, TMS Data Hold Time
tNTDIH, tNTMSH
5
—
ns
12
TCK Low to TDO Data Valid
VDDE = 2.25 to 3.0 volts
0
12
ns
VDDE = 3.0 to 3.6 volts
0
9
ns
—
—
—
13
1
Characteristic
RDY Valid to
tJOV
MCKO5
—
JTAG specifications in this table apply when used for debug functionality. All Nexus timing relative to MCKO is measured from
50% of MCKO and 50% of the respective signal. Nexus timing specified at VDD = 1.35V to 1.65V, VDDE = 2.25V to 3.6V,
VDD33 and VDDSYN = 3.0V to 3.6V, TA = TL to TH, and CL = 30pF with DSC = 0b10.
The Nexus AUX port can only run up to 82MHz. The NPC_PCR[MCKO_DIV] must be set to divide by 2 if the system frequency
is above 82MHz
MDO, MSEO, and EVTO data is held valid until next MCKO low cycle.
The maximum frequency must be limited to approximately 16 MHz (VDDE= 2.25 to 3.0 volts) or 22 MHz (VDDE= 3.0 to 3.6
volts) to meet the timing specification for tJOV of 0.2 x tJCYC as outlined in the IEEE-ISTO 5001-2003 specification.
The RDY pin timing is asynchronous to MCKO. The timing is guaranteed by design to function correctly.
1
2
MCKO
4
3
5
MDO
MSEO
EVTO
Output Data Valid
Figure 9. Nexus Output Timing
MPC5553 Microcontroller Data Sheet, Rev. 0
30
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
TCK
10
11
TMS, TDI
12
TDO
Figure 10. Nexus TDI, TMS, TDO Timing
MPC5553 Microcontroller Data Sheet, Rev. 0
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
31
Electrical Characteristics
3.13.4
External Bus Interface (EBI) Timing
Table 22. Bus Operation Timing1
#
Characteristic/Description Symbol
40 MHz
(ext. bus)2
56 MHz
(ext. bus)2
66 MHz
(ext. bus)2
Unit
Notes
—
ns
Signals are
measured at 50%
VDDE.
Min
Max
Min
Max
Min
Max
TC
25.0
—
17.9
—
15.2
1
CLKOUT Period
2
CLKOUT duty cycle
tCDC
45%
55%
45%
55%
45%
55%
TC
3
CLKOUT rise time
tCRT
—
—3
—
—3
—
—3
ns
4
CLKOUT fall time
tCFT
—
—3
—
—3
—
—3
ns
tCOH
1.06/
—
1.06/
—
1.06/
—
ns
Hold time
selectable via
SIU_ECCR[EBTS]
bit:
EBTS=0/EBTS=1
6.06/
7.0
ns
Output valid time
selectable via
SIU_ECCR[EBTS]
bit:
EBTS=0/EBTS=1
5
CLKOUT Positive Edge to
Output Signal Invalid or High
Z (Hold Time)
1.5
1.5
1.5
ADDR[8:31]
BDIP
BG4
BR5
CS[0:3]
DATA[0:31]
OE
RD_WR
TA
TEA
TS
TSIZ[0:1]
WE[0:3]/BE[0:3]
6
CLKOUT Posedge to Output
Signal Valid (Output Delay)
tCOV
—
10.06/
11.0
—
7.56/
8.5
—
ADDR[8:31]
BDIP
BG4
BR5
CS[0:3]
DATA[0:31]
OE
RD_WR
TA
TEA
TS
TSIZ[0:1]
WE[0:3]/BE[0:3]
MPC5553 Microcontroller Data Sheet, Rev. 0
32
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
Table 22. Bus Operation Timing1 (continued)
#
7
Characteristic/Description Symbol
Input Signal Valid to CLKOUT
Posedge (Setup Time)
40 MHz
(ext. bus)2
56 MHz
(ext. bus)2
66 MHz
(ext. bus)2
Unit
Min
Max
Min
Max
Min
Max
tCIS
10.0
—
7.0
—
5.0
—
ns
tCIH
1.0
—
1.0
—
1.0
—
ns
Notes
ADDR[8:31]
BB
BG5
BR5
DATA[0:31]
RD_WR
TA
TEA
TS
TSIZ[0:1]
8
CLKOUT Posedge to Input
Signal Invalid
(Hold Time)
ADDR[8:31]
BB
BG5
BR5
DATA[0:31]
RD_WR
TA
TEA
TS
TSIZ[0:1]
1
2
3
4
5
6
EBI timing specified at VDD = 1.35V to 1.65V, VDDE = 1.6V to 3.6V (unless stated otherwise), VDD33 and VDDSYN = 3.0V
to 3.6V, TA = TL to TH, and CL = 30pF with DSC = 0b10.
The external bus is limited to half the speed of the internal bus.
Refer to Fast Pad timing in Table 17 and Table 18 (different values for 1.8V vs 3.3V).
Internal Arbitration
External Arbitration
The EBTS=0 timings are only valid/ tested at VDDE=2.25-3.6V, whereas EBTS=1 timings are valid/tested at 1.6–3.6V.
Voh_f
VDDE/2
CLKOUT
Vol_f
3
2
2
4
1
Figure 11. CLKOUT Timing
MPC5553 Microcontroller Data Sheet, Rev. 0
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
33
Electrical Characteristics
VDDE/2
CLKOUT
6
5
VDDE/2
5
OUTPUT
BUS
VDDE/2
6
5
5
OUTPUT
SIGNAL
VDDE/2
6
OUTPUT
SIGNAL
VDDE/2
Figure 12. Synchronous Output Timing
MPC5553 Microcontroller Data Sheet, Rev. 0
34
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
CLKOUT
VDDE/2
7
8
INPUT
BUS
VDDE/2
7
8
INPUT
SIGNAL
VDDE/2
Figure 13. Synchronous Input Timing
MPC5553 Microcontroller Data Sheet, Rev. 0
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
35
Electrical Characteristics
3.13.5
External Interrupt Timing (IRQ Pin)
Table 23. External Interrupt Timing1
Num
Characteristic
1
IRQ Pulse Width Low
2
IRQ Pulse Width High
3
2
IRQ Edge to Edge Time
Symbol
Min
Max
Unit
tIPWL
3
—
tCYC
TIPWH
3
—
tCYC
tICYC
6
—
tCYC
1
IRQ timing specified at FSYS = 132MHz, VDD = 1.35V to 1.65V, VDDEH = 3.0V to 5.5V, VDD33 and VDDSYN = 3.0V to 3.6V,
TA = TL to TH, and CL = 200pF with SRC = 0b11.
2
Applies when IRQ pins are configured for rising edge or falling edge events, but not both.
IRQ
2
1
3
Figure 14. External Interrupt Timing
CLKOUT
4
IRQ
Figure 15. External Interrupt Setup Timing
MPC5553 Microcontroller Data Sheet, Rev. 0
36
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
3.13.6
eTPU Timing
Table 24. eTPU Timing1
Num
1
Characteristic
Symbol
Min
Max
Unit
1
eTPU Input Channel Pulse Width
tICPW
4
—
tCYC
2
eTPU Output Channel Pulse Width
tOCPW
2
—
tCYC
eTPU timing specified at FSYS = 132MHz, VDD = 1.35V to 1.65V, VDDEH = 3.0V to 5.5V, VDD33 and VDDSYN = 3.0V to 3.6V,
TA = TL to TH, and CL = 200pF with SRC = 0b11.
2
eTPU
OUTPUT
eTPU INPUT
AND TCRCLK
1
Figure 16. eTPU Timing
CLKOUT
4
eTPU
OUTPUT
3
eTPU INPUT
AND TCRCLK
Figure 17. eTPU Input/Output Timing
MPC5553 Microcontroller Data Sheet, Rev. 0
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
37
Electrical Characteristics
3.13.7
eMIOS (MTS) Timing
Table 25. MTS Timing1
Num
1
Characteristic
Symbol
Min
Max
Unit
1
eMIOS (MTS) Input Pulse Width
tMIPW
4
—
tCYC
2
eMIOS (MTS) Output Pulse Width
tMOPW
1
—
tCYC
MTS timing specified at FSYS = 132MHz, VDD = 1.35V to 1.65V, VDDEH = 3.0V to 5.5V, VDD33 and VDDSYN = 3.0V to 3.6V,
TA = TL to TH, and CL = 50pF with SRC = 0b11.
3.13.8
DSPI Timing
Table 26. DSPI Timing1
80 MHz
Num
Characteristic
112 MHz
132 MHz
Symbol
Unit
Min
Max
Min
Max
Min
Max
1
SCK Cycle TIme2,3
tSCK
25ns
2.9ms
17.9ns
2.0ms
15.2ns
1.7ms
—
2
Delay4
tCSC
23
—
15
—
13
—
ns
tASC
22
—
14
—
12
—
ns
tSDC
tSCK/2
–2ns
tSCK/2
+ 2ns
—
—
—
—
ns
tA
—
25
—
25
—
25
ns
tDIS
—
25
—
25
—
25
ns
PCS to SCK
Delay5
3
After SCK
4
SCK Duty Cycle
5
Slave Access Time
(SS active to SOUT driven)
6
Slave SOUT Disable Time
(SS inactive to SOUT High-Z or
invalid)
7
PCSx to PCSS time
tPCSC
4
—
4
—
4
—
ns
8
PCSS to PCSx time
tPASC
5
—
5
—
5
—
ns
9
Data Setup Time for Inputs
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)6
Master (MTFE = 1, CPHA = 1)
tSUI
20
2
–4
20
—
—
—
—
20
2
3
20
—
—
—
—
20
2
6
20
—
—
—
—
ns
ns
ns
ns
Data Hold Time for Inputs
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)6
Master (MTFE = 1, CPHA = 1)
tHI
–4
7
21
–4
—
—
—
—
–4
7
14
–4
—
—
—
—
–4
7
12
–4
—
—
—
—
ns
ns
ns
ns
10
MPC5553 Microcontroller Data Sheet, Rev. 0
38
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
Table 26. DSPI Timing1 (continued)
80 MHz
Num
11
12
1
2
3
4
5
6
Characteristic
112 MHz
132 MHz
Symbol
Data Valid (after SCK edge)
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA=0)
Master (MTFE = 1, CPHA=1)
tSUO
Data Hold Time for Outputs
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
tHO
Unit
Min
Max
Min
Max
Min
Max
—
—
—
—
5
25
18
5
—
—
—
—
5
25
14
5
—
—
—
—
5
25
13
5
ns
ns
ns
ns
–5
5.5
8
–5
—
—
—
—
–5
5.5
4
–5
—
—
—
—
–5
5.5
3
–5
—
—
—
—
ns
ns
ns
ns
DSPI timing specified at VDD = 1.35V to 1.65V, VDDEH = 3.0V to 5.5V, VDD33 and VDDSYN = 3.0V to 3.6V, TA = TL to TH,
and CL = 50pF with SRC = 0b11.
The minimum SCK Cycle Time restricts the baud rate selection for given system clock rate. These numbers are calculated
based on two MPC55xx devices communicating over a DSPI link.
The actual minimum SCK Cycle Time is limited by pad performance.
The maximum value is programmable in DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK]
The maximum value is programmable in DSPI_CTARx[PASC] and DSPI_CTARx[ASC]
This number is calculated assuming the SMPL_PT bit field in DSPI_MCR is set to 0b10.
2
3
PCSx
1
4
SCK Output
(CPOL=0)
4
SCK Output
(CPOL=1)
9
SIN
10
First Data
Data
12
SOUT
First Data
Last Data
11
Data
Last Data
Figure 18. DSPI Classic SPI Timing — Master, CPHA = 0
MPC5553 Microcontroller Data Sheet, Rev. 0
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
39
Electrical Characteristics
PCSx
SCK Output
(CPOL=0)
10
SCK Output
(CPOL=1)
9
Data
First Data
SIN
Last Data
12
SOUT
11
Data
First Data
Last Data
Figure 19. DSPI Classic SPI Timing — Master, CPHA = 1
3
2
SS
1
4
SCK Input
(CPOL=0)
4
SCK Input
(CPOL=1)
5
SOUT
First Data
9
SIN
12
11
Data
Last Data
Data
Last Data
6
10
First Data
Figure 20. DSPI Classic SPI Timing — Slave, CPHA = 0
MPC5553 Microcontroller Data Sheet, Rev. 0
40
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
SS
SCK Input
(CPOL=0)
SCK Input
(CPOL=1)
11
5
6
12
SOUT
First Data
9
SIN
Data
Last Data
Data
Last Data
10
First Data
Figure 21. DSPI Classic SPI Timing — Slave, CPHA = 1
3
PCSx
4
1
2
SCK Output
(CPOL=0)
4
SCK Output
(CPOL=1)
9
SIN
First Data
10
12
SOUT
First Data
Last Data
Data
11
Data
Last Data
Figure 22. DSPI Modified Transfer Format Timing — Master, CPHA = 0
MPC5553 Microcontroller Data Sheet, Rev. 0
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
41
Electrical Characteristics
PCSx
SCK Output
(CPOL=0)
SCK Output
(CPOL=1)
10
9
SIN
First Data
Last Data
Data
12
First Data
SOUT
11
Last Data
Data
Figure 23. DSPI Modified Transfer Format Timing — Master, CPHA = 1
3
2
SS
1
SCK Input
(CPOL=0)
4
4
SCK Input
(CPOL=1)
SOUT
First Data
Data
First Data
6
Last Data
10
9
SIN
12
11
5
Data
Last Data
Figure 24. DSPI Modified Transfer Format Timing — Slave, CPHA =0
MPC5553 Microcontroller Data Sheet, Rev. 0
42
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
SS
SCK Input
(CPOL=0)
SCK Input
(CPOL=1)
11
5
6
12
First Data
SOUT
9
Last Data
Data
Last Data
10
First Data
SIN
Data
Figure 25. DSPI Modified Transfer Format Timing — Slave, CPHA =1
7
8
PCSS
PCSx
Figure 26. DSPI PCS Strobe (PCSS) Timing
MPC5553 Microcontroller Data Sheet, Rev. 0
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
43
Electrical Characteristics
3.13.9
eQADC SSI Timing
Table 27. EQADC SSI Timing Characteristics (pads at 3.3V or at 5.0V) 1
CLOAD = 25pF on all outputs. Pad drive strength set to maximum.
Num
Rating
Symbol
Min
Typ
Max
Unit
1
FCK Frequency 2, 3
fFCK
1/17
—
1/2
fSYS_CLK
2
FCK Period (tFCK = 1/ fFCK)
tFCK
2
—
17
tSYS_CLK
3
Clock (FCK) High Time
tFCKHT
tSYS_CLK − 6.5
—
9* tSYS_CLK + 6.5
ns
4
Clock (FCK) Low Time
tFCKLT
tSYS_CLK − 6.5
—
8* tSYS_CLK + 6.5
ns
5
SDS Lead/Lag Time
tSDS_LL
–7.5
—
+7.5
ns
6
SDO Lead/Lag Time
tSDO_LL
–7.5
—
+7.5
ns
7
EQADC Data Setup Time (Inputs)
tEQ_SU
22
—
—
ns
8
EQADC Data Hold Time (Inputs)
tEQ_HO
1
—
—
ns
1
SS timing specified at FSYS = 132MHz, VDD = 1.35V to 1.65V, VDDEH = 3.0V to 5.5V, VDD33 and VDDSYN = 3.0V to 3.6V,
TA = TL to TH, and CL = 50pF with SRC = 0b11.
2
Maximum operating frequency is highly dependent on track delays, master pad delays, and slave pad delays.
3 FCK duty is not 50% when it is generated through the division of the system clock by an odd number.
2
3
4
FCK
5
4
SDS
25th
6
SDO
1st (MSB)
5
2nd
26th
External Device Data Sample at
FCK Falling Edge
8
7
SDI
1st (MSB) 2nd
25th
26th
EQADC Data Sample at
FCK Rising Edge
Figure 27. EQADC SSI Timing
MPC5553 Microcontroller Data Sheet, Rev. 0
44
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
3.14
Fast Ethernet AC Timing Specifications
MII signals use TTL signal levels compatible with devices operating at 3.3 V. Note that the timing
specifications for the MII signals are independent of system clock frequency (part speed designation).
3.14.1
MII Receive Signal Timing (RXD[3:0], RX_DV, RX_ER, and RX_CLK)
The receiver functions correctly up to a RX_CLK maximum frequency of 25 MHz +1%. There is no
minimum frequency requirement. In addition, the processor clock frequency must exceed 4× the RX_CLK
frequency.
Table 28 lists MII receive channel timings.
Table 28. MII Receive Signal Timing
Num
Characteristic
Min
Max
Unit
1
RXD[3:0], RX_DV, RX_ER to RX_CLK setup
5
—
ns
2
RX_CLK to RXD[3:0], RX_DV, RX_ER hold
5
—
ns
3
RX_CLK pulse width high
35%
65%
RX_CLK period
4
RX_CLK pulse width low
35%
65%
RX_CLK period
Figure 28 shows MII receive signal timings listed in Table 28.
M3
RX_CLK (input)
M4
RXD[3:0] (inputs)
RX_DV
RX_ER
M1
M2
Figure 28. MII Receive Signal Timing Diagram
MPC5553 Microcontroller Data Sheet, Rev. 0
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
45
Electrical Characteristics
3.14.2
MII Transmit Signal Timing (TXD[3:0], TX_EN, TX_ER, TX_CLK)
The transmitter functions correctly up to a TX_CLK maximum frequency of 25 MHz +1%. There is no
minimum frequency requirement. In addition, the processor clock frequency must exceed twice the
TX_CLK frequency.
The transmit outputs (TXD[3:0], TX_EN, TX_ER) can be programmed to transition from either the rising
or falling edge of TX_CLK, and the timing is the same in either case. This options allows the use of
non-compliant MII PHYs.
Refer to the ethernet chapter of the device Reference Manual for details of this option and how to enable it.
Table 29 lists MII transmit channel timings.
Table 29. MII Transmit Signal Timing
Num
Characteristic
Min
Max
Unit
5
TX_CLK to TXD[3:0], TX_EN, TX_ER invalid
5
—
ns
6
TX_CLK to TXD[3:0], TX_EN, TX_ER valid
—
25
ns
7
TX_CLK pulse width high
35%
65%
TX_CLK period
8
TX_CLK pulse width low
35%
65%
TX_CLK period
Figure 29 shows MII transmit signal timings listed in Table 29.
M7
TX_CLK (input)
M5
M8
TXD[3:0] (outputs)
TX_EN
TX_ER
M6
Figure 29. MII Transmit Signal Timing Diagram
MPC5553 Microcontroller Data Sheet, Rev. 0
46
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
3.14.3
MII Async Inputs Signal Timing (CRS and COL)
Table 30 lists MII asynchronous inputs signal timing.
Table 30. MII Async Inputs Signal Timing
Num
Characteristic
9
CRS, COL minimum pulse width
Min
Max
Unit
1.5
—
TX_CLK period
Figure 30 shows MII asynchronous input timings listed in Table 30.
CRS, COL
M9
Figure 30. MII Async Inputs Timing Diagram
3.14.4
MII Serial Management Channel Timing (MDIO and MDC)
Table 31 lists MII serial management channel timings. The FEC functions correctly with a maximum
MDC frequency of 2.5 MHz.
Table 31. MII Serial Management Channel Timing
Num
Characteristic
Min
Max
Unit
10
MDC falling edge to MDIO output invalid (minimum propagation delay)
0
—
ns
11
MDC falling edge to MDIO output valid (max prop delay)
—
25
ns
12
MDIO (input) to MDC rising edge setup
10
—
ns
13
MDIO (input) to MDC rising edge hold
0
—
ns
14
MDC pulse width high
40%
60%
MDC period
15
MDC pulse width low
40%
60%
MDC period
Figure 31 shows MII serial management channel timings listed in Table 31.
MPC5553 Microcontroller Data Sheet, Rev. 0
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
47
Electrical Characteristics
M14
M15
MDC (output)
M10
MDIO (output)
M11
MDIO (input)
M12
M13
Figure 31. MII Serial Management Channel Timing Diagram
CLKOUT
5
5
RESET
6
6
RSTOUT
Figure 32. Reset and Configuration Pin Timing
MPC5553 Microcontroller Data Sheet, Rev. 0
48
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Mechanicals
4
Mechanicals
4.1
Pinouts
4.1.1
MPC5553 416 PBGA Pinout
Figure 33, Figure 34, and Figure 35 show the pinout for the MPC5553 416 PBGA package. While the
MPC5553 and the MPC5554/MPC5565/MPC5566 are pin-compatible, the MPC5553 ball map is shown
here to highlight the balls that are not connected to any signal on the MCP5553 (the eTPUB[0:31] and
TSIZ[0:1]). The alternate Ethernet signals that are multiplexed with the data bus are not shown for the
MPC5553.
NOTE
Some pins have names that include functions that are not available on all
family members. For example, ball R25 of the 416 BGA package is named
‘SINA,’ but the MPC5553 does not have a DSPI_A module. In this case, the
SINA pin can only be used for its alternate functions of GPIO94 or PCSC2.
See the specific device reference manual for functions available on each
device in the family.
MPC5553 Microcontroller Data Sheet, Rev. 0
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
49
Mechanicals
A
B
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
VSS
VSTBY
AN37
AN11
VDDA1
AN16
AN1
AN5
VRH
AN23
AN27
AN28
AN35
VSSA0
AN15
ETRIG
1
NC_1
NC_2
NC_3
NC_4
GPIO
205
NC_5
NC_6
NC_7
NC_8 MDO10 MDO7
NC_10 NC_11 NC_12 MDO9
VDD
C VDD33
D
VSS
AN36
AN39
AN19
AN20
AN0
AN4
REF
BYPC
AN22
AN26
AN31
AN32
VSSA0
AN14
ETRIG
0
VDD
VSS
AN8
AN17
VSSA1
AN21
AN3
AN7
VRL
AN25
AN30
AN33
VDDA0
AN13
NC_9
VDD
VSS
AN38
AN9
AN10
AN18
AN2
AN6
AN24
AN29
AN34 VDDEH AN12
9
ETPUA ETPUA
30
31
ETPUA ETPUA VDDEH
E
28
29
1
MDO3
MDO2 VDDEH
8
VDD
F
ETPUA ETPUA ETPUA VDDEH
24
27
26
1
G
ETPUA ETPUA ETPUA ETPUA
23
22
25
21
Version 2.1 – 13 July 2004
ETPUA ETPUA ETPUA ETPUA
H
20
19
18
17
J
ETPUA ETPUA ETPUA ETPUA
16
15
14
13
K
ETPUA ETPUA ETPUA ETPUA
12
11
10
9
23
24
25
26
VDD
VDD33
VSS
A
MDO4
MDO0
VSS
MDO1
VSS
VDDE7
VDDE7 B
VDD
C
VSS
VDDE7
TCK
TDI
D
VDDE7
TMS
E
TDO
TEST
MSEO0 JCOMP
EVTI
EVTO F
MSEO1 MCKO
GPIO
204
NC_17 G
RDY
GPIO
203
NC_18 NC_19 H
VDDEH NC_20 NC_21 NC_22
J
6
ETPUA ETPUA ETPUA ETPUA
L
8
7
6
5
M
NC_13 NC_14 NC_15 NC_16 MDO5
MDO6
22
MDO11 MDO8
VSS
VSS
VSS
VSS
VSS
VSS
NC_23 NC_24 NC_25 NC_26 K
VDDE7 VDDE7 VDDE7 VDDE7
NC_27 NC_28 NC_29 NC_30 L
VSS
VSS
VSS
VSS
VSS
VDDE7
ETPUA ETPUA ETPUA ETPUA
4
3
2
1
VDDE2 VDDE2
VSS
VSS
VSS
VSS
VSS
VDDE7
NC_31 NC_32 NC_33
ETPUA TCRCLK
0
A
VDDE2 VDDE2
VSS
VSS
VSS
VSS
VSS
VDDE7
SOUTB PCSB3 PCSB0 PCSB1 N
N
BDIP
TEA
SINB
M
P
CS3
CS2
CS1
CS0
VDDE2 VDDE2
VSS
VSS
VSS
VSS
VSS
VSS
PCSA3 PCSB4 SCKB PCSB2 P
R
WE3
WE2
WE1
WE0
VDDE2 VDDE2
VSS
VSS
VSS
VSS
VSS
VSS
PCSB5 SOUTA
VDDE2 VDDE2 VDDE2 VDDE2
VSS
VSS
PCSA1 PCSA0 PCSA2
VDDE2 VDDE2 VDDE2 VDDE2 VDDE2
VSS
VSS
VDDE2
T VDDE2 NC_34 RD_WR VDDE2
ADDR
U
NC_35
16
TA
VDD33
V
ADDR
18
ADDR
17
TS
ADDR
8
W
ADDR
20
ADDR
19
ADDR
9
ADDR
10
Y
ADDR
22
ADDR
21
ADDR
VDDE2
11
ADDR
AA
24
ADDR
23
ADDR
13
ADDR
12
AB VDDE2
ADDR
25
ADDR
15
ADDR
14
ADDR
AC
26
ADDR
27
ADDR
31
VSS
AD
ADDR
28
ADDR
30
VSS
VDD
AE
ADDR
29
VSS
VDD
DATA
17
VSS
VDD
DATA
16
DATA
18
1
2
3
4
AF
VSS
VSS
SINA
SCKA R
VPP
PCSA4 TXDA PCSA5 VFLASH U
CNTXC RXDA RSTOUT RST
CFG
Note:
NC_36
NC_37
WKP
CFG
No connect. AC22 & AD23 reserved
VDDE2
DATA
31
DATA
8
DATA
10
VDDE2
DATA
12
DATA
29
VDD33
GPIO
207
DATA
9
DATA
11
DATA
13
DATA
15
DATA
23
DATA
0
DATA
2
DATA
4
DATA
6
OE
BR
BG
DATA
22
GPIO
206
DATA
1
DATA
3
VDDE2
DATA
5
DATA
7
7
8
9
10
11
12
13
VDD
DATA
28
DATA
24
DATA
25
DATA
27
DATA
19
DATA
21
VDDE2
DATA
20
5
6
DATA
14
BOOT
CFG1
VDDEH PLL
6
CFG1
VDD
DATA
30
DATA
26
EMIOS EMIOS EMIOS EMIOS VDDEH VDDE5 NC_36
2
8
12
21
4
VSS
EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNTXA VDDE5 NC_37
6
10
3
15
17
22
VRC
CTL
VRC
VSS
16
17
18
19
20
21
22
23
Y
XTAL
AB
VDD
VRC33
VDD
SYN
AC
VSS
VDD
EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNRXA VDDE5 CLKOUT VSS
5
9
1
13
16
19
23
15
VSS
SYN
BOOT EXTAL
AA
CFG0
PLL
CFG0
NC_38 EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNTXB CNRXB VDDE5
4
7
0
11
14
18
20
14
V
RXDB CNRXC TXDB RESET W
No connects (x = 1 to 38)
NC_X
T
24
VDD33 AD
VDD
AE
ENG
CLK
VSS
AF
25
26
Figure 33. MPC5553 416 Package
MPC5553 Microcontroller Data Sheet, Rev. 0
50
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Mechanicals
1
2
3
4
5
6
7
8
9
10
11
12
13
A
VSS
VSTBY
AN37
AN11
VDDA1
AN16
AN1
AN5
VRH
AN23
AN27
AN28
AN35
B
VDD
VSS
AN36
AN39
AN19
AN20
AN0
AN4
REF
BYPC
AN22
AN26
AN31
AN32
VDD
VSS
AN8
AN17
VSSA1
AN21
AN3
AN7
VRL
AN25
AN30
AN33
VDD
VSS
AN38
AN9
AN10
AN18
AN2
AN6
AN24
AN29
AN34
C VDD33
D
ETPUA ETPUA
30
31
E
ETPUA ETPUA VDDEH
28
29
1
F
ETPUA ETPUA ETPUA VDDEH
24
27
26
1
G
ETPUA ETPUA ETPUA ETPUA
23
22
25
21
H
ETPUA ETPUA ETPUA ETPUA
20
19
18
17
J
ETPUA ETPUA ETPUA ETPUA
16
15
14
13
K
ETPUA ETPUA ETPUA ETPUA
12
11
10
9
VSS
VSS
VSS
VSS
L
ETPUA ETPUA ETPUA ETPUA
8
7
6
5
VSS
VSS
VSS
VSS
M
ETPUA ETPUA ETPUA ETPUA
4
3
2
1
VDDE2 VDDE2
VSS
VSS
ETPUA TCRCLK
0
A
VDDE2 VDDE2
VSS
VSS
VDD
Version 2.1 – 13 July 2004
N
BDIP
TEA
P
CS3
CS2
CS1
CS0
VDDE2 VDDE2
VSS
VSS
R
WE3
WE2
WE1
WE0
VDDE2 VDDE2
VSS
VSS
VDDE2
T VDDE2 NC_34 RD_WR VDDE2
U
ADDR
NC_35
16
TA
VDD33
V
ADDR
18
ADDR
17
TS
ADDR
8
W
ADDR
20
ADDR
19
ADDR
9
ADDR
10
Y
ADDR
22
ADDR
21
ADDR
VDDE2
11
ADDR
AA
24
ADDR
23
ADDR
13
ADDR
12
AB VDDE2
ADDR
25
ADDR
15
ADDR
14
AC
ADDR
26
ADDR
27
ADDR
31
VSS
VDD
DATA
26
DATA
28
AD
ADDR
28
ADDR
30
VSS
VDD
DATA
24
DATA
25
DATA
27
DATA
29
AE
ADDR
29
VSS
VDD
DATA
17
DATA
19
DATA
21
DATA
23
AF
VSS
VDD
DATA
16
DATA
18
VDDE2
DATA
20
1
2
3
4
5
6
VSS
Note:
VSS
VDDE2 VDDE2
VDDE2 VDDE2 VDDE2
No connects (x = 1 to 38)
NC_X
NC_36
No connect. AC22 & AD23 reserved
NC_37
VDDE2 DATA
30
DATA
31
DATA
8
DATA
10
VDDE2
VDD33
GPIO
207
DATA
9
DATA
11
DATA
13
DATA
0
DATA
2
DATA
4
DATA
6
OE
BR
DATA
22
GPIO
206
DATA
1
DATA
3
7
8
9
10
VDDE2 DATA
5
11
12
DATA
7
13
Figure 34. MPC5553 416 Package, Left Side
MPC5553 Microcontroller Data Sheet, Rev. 0
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
51
Mechanicals
14
15
16
VSSA0
AN15
ETRIG
1
NC_1
NC_2
NC_3
NC_4
VSSA0
AN14
ETRIG
0
NC_5
NC_6
NC_7
NC_8 MDO10 MDO7
VDDA0
AN13
NC_9
NC_10 NC_11 NC_12 MDO9
VDDEH AN12
9
17
18
19
20
NC_13 NC_14 NC_15 NC_16 MDO5
21
22
23
24
25
26
VDD
VDD33
VSS
MDO4
MDO0
VSS
MDO1
VSS
VDDE7
VDD
C
VSS
VDDE7
TCK
TDI
D
VDDE7
TMS
TDO
TEST
E
MSEO0 JCOMP
EVTI
EVTO
F
MSEO1 MCKO
GPIO
204
NC_17 G
GPIO MDO11 MDO8
205
MDO6
MDO3
MDO2 VDDEH
8
GPIO
203
RDY
A
VDDE7 B
NC_18 NC_19 H
VDDEH NC_20 NC_21 NC_22
J
6
NC_23 NC_24 NC_25 NC_26 K
VDDE7 VDDE7 VDDE7 VDDE7
VSS
VSS
VSS
VDDE7
NC_27 NC_28 NC_29 NC_30 L
VSS
VSS
VSS
VDDE7
NC_31 NC_32 NC_33
VSS
VSS
VSS
VDDE7
SOUTB PCSB3 PCSB0 PCSB1 N
VSS
VSS
VSS
VSS
PCSA3 PCSB4 SCKB PCSB2 P
VSS
VSS
VSS
VSS
PCSB5 SOUTA
VDDE2 VDDE2
VSS
VSS
PCSA1 PCSA0 PCSA2
VDDE2 VDDE2
VSS
VSS
PCSA4 TXDA PCSA5 VFLASH U
SINA
SINB
M
SCKA R
CNTXC RXDA RSTOUT
VPP
RST
CFG
T
V
RXDB CNRXC TXDB RESET W
WKP
CFG
BOOT
CFG1
VDDEH PLL
CFG1
6
BOOT EXTAL
AA
CFG0
PLL
CFG0
XTAL
AB
VSS
VDD
VRC33
VDD
SYN
AC
VSS
VDD
DATA
15
EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNTXA VDDE5 NC_37
3
6
10
15
17
22
VDD33 AD
EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNRXA VDDE5 CLKOUT VSS
1
5
9
13
16
19
23
VDD
AE
ENG
CLK
VSS
AF
25
26
NC_38 EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNTXB CNRXB VDDE5
0
4
7
11
14
18
20
14
Y
VRC
CTL
DATA
14
BG
VSS
SYN
VDD
DATA
12
EMIOS EMIOS EMIOS EMIOS VDDEH VDDE5 NC_36
2
8
12
21
4
VRC
VSS
15
16
17
18
19
20
21
22
23
24
Figure 35. MPC5553 416 Package, Right Side
MPC5553 Microcontroller Data Sheet, Rev. 0
52
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Mechanicals
4.1.2
MPC5553 324 PBGA Pinout
Figure 36 is a pinout for the MPC5553 324 PBGA package.
A
1
2
3
4
5
VSS
VDD
VSTBY
AN37
AN11
B VDD33
VSS
6
7
VDDA1 VSSA1
8
9
10
11
12
13
14
15
16
17
18
19
20
21
AN1
AN5
VRH
VRL
AN27
AN28
AN35
VSSA0
AN12 MDO11 MDO10 MDO8
VDD
VDD33
AN0
AN4
REF
BYPC
AN23
AN26
AN31
AN32
VSSA0
AN13
MDO9
MDO7
MDO4
MDO0
VSS
VDDA0
22
VSS
A
VDD
AN36
AN39
AN19
AN16
VSS
VDD
AN8
AN17
AN20
AN21
AN3
AN7
AN22
AN25
AN30
AN33
AN14
MDO5
MDO2
MDO1
VSS
VDDE7
VDD
C
VSS
VDD
AN38
AN9
AN10
AN18
AN2
AN6
AN24
AN29
AN34 VDDEH AN15
9
MDO6
MDO3
C
ETPUA ETPUA
30
31
D
ETPUA ETPUA ETPUA
28
29
26
VDDE7 B
VSS
VDDE7
TCK
TDI
D
ETPUA ETPUA ETPUA ETPUA
E
24
27
25
21
VDDE7
TMS
TDO
TEST
E
ETPUA ETPUA ETPUA ETPUA
F
23
22
17
18
VDDE7 JCOMP
EVTI
EVTO
F
ETPUA ETPUA ETPUA ETPUA
G
20
19
14
13
RDY
Version 2.2p – 13 July 2004
ETPUA ETPUA ETPUA VDDEH
H
16
15
10
1
MCKO MSEO0 MSEO1 G
VDDEH GPIO
10
203
GPIO
204
SINB
H
ETPUA ETPUA ETPUA ETPUA
J
6
12
11
9
VSS
VSS
VSS
VSS
VSS
VDDE7
SOUTB PCSB3 PCSB0 PCSB1 J
ETPUA ETPUA ETPUA ETPUA
K
8
7
2
5
VSS
VSS
VSS
VSS
VSS
VSS
PCSA3 PCSB4 SCKB PCSB2 K
ETPUA ETPUA ETPUA ETPUA
L
4
3
0
1
VSS
VSS
VSS
VSS
VSS
VSS
PCSB5 SOUTA
M
TCRCLK
BDIP
A
CS1
N
CS3
P
ADDR
16
ADDR
RD_WR VDD33
17
R
ADDR
18
CS2
WE1
WE0
ADDR VDDE2
19
TA
ADDR
T
20
ADDR
21
ADDR
12
TS
ADDR
U
22
ADDR
23
ADDR
13
ADDR
14
ADDR
24
ADDR
25
ADDR
15
ADDR
31
V
ADDR
ADDR
W
VDDE2
26
30
ADDR
Y
28
ADDR
AA
29
AB
ADDR
27
VSS
VSS
VDD
1
2
VSS
VDD
VDDE2 VDDE2
CS0
VDD
VSS
VSS
PCSA1 PCSA0 PCSA2
VSS
VSS
VSS
PCSA4 TXDA PCSA5 VFLASH N
VSS
VSS
VDDE2
VSS
VSS
VSS
CNTXC RXDA RSTOUT
VDDE2 VDD33 VDDE2 DATA
11
VDDE2 DATA
8
VDDE2 DATA
1
DATA
VDDE2
0
3
VSS
VDDE2
RXDB
4
DATA
9
DATA
10
GPIO
207
DATA
5
DATA
7
VDDE2
GPIO
206
DATA
2
DATA
3
DATA
4
DATA
6
OE
5
6
7
8
9
DATA
12
DATA
14
EMIOS EMIOS VDDEH EMIOS EMIOS VDDE5
21
2
4
12
8
DATA
13
DATA
15
EMIOS EMIOS EMIOS EMIOS EMIOS CNTXA VDDE5
22
6
10
15
17
NC
VPP
RST
CFG
M
P
CNRXC TXDB RESET R
BOOT
CFG1
VDDEH PLL
6
CFG1
VDD
VSS
VDD
VSS
VSS
No connect. Reserved (W18 & Y19 are shorted to each other)
NC
SCKA L
VSS
WKP
CFG
Note:
SINA
VRC
CTL
VRC
VSS
VSS
SYN
T
BOOT EXTAL
U
CFG0
PLL
CFG0
XTAL
V
VDD
SYN
W
VSS
VDD
VRC33
NC
VSS
VDD
VDD33 Y
VDDE2 EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNRXA VDDE5 CLKOUT VSS
16
19
23
3
5
9
13
VDD
AA
EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNTXB CNRXB VDDE5
14
18
20
0
1
4
7
11
ENG
CLK
VSS
AB
21
22
10
11
12
13
14
15
16
17
18
19
20
Figure 36. MPC5553 324 Package
MPC5553 Microcontroller Data Sheet, Rev. 0
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
53
Mechanicals
4.1.3
MPC5553 208 MAP BGA Pinout
Figure 37 is a pinout for the MPC5553 208 MAP BGA package.
NOTE
VDDEH10 and VDDEH6 are connected internally on the 208-ball package
and are listed as VDDEH6.
1
2
3
4
A
VSS
AN9
AN11
B
VDD
VSS
AN38
AN21
C VSTBY
VDD
VSS
D VDD33
AN39
5
6
7
8
9
10
11
12
13
AN1
AN5
VRH
VRL
AN27
VSSA0
AN12
MDO2
MDO0 VDD33
VSS
A
AN0
AN4
REF
BYPC
AN22
AN25
AN28
VDDA0
AN13
MDO3
MDO1
VSS
VDD
B
AN17
AN34
AN16
AN3
AN7
AN23
AN32
AN33
AN14
AN15
VSS
MSEO0
TCK
C
VDD
VSS
AN18
AN2
AN6
AN24
AN30
AN31
AN35 VDDEH
9
VSS
TMS
EVTO
TEST
D
AN37
VDD
VDDE7
TDI
EVTI
VDDEH
6
TDO
VDDA1 VSSA1
14
15
16
E
ETPUA ETPUA
30
31
F
ETPUA ETPUA ETPUA
28
29
26
G
ETPUA ETPUA ETPUA ETPUA
24
27
25
21
VSS
VSS
VSS
VSS
SOUTB PCSB3
H
ETPUA ETPUA ETPUA ETPUA
23
22
17
18
VSS
VSS
VSS
VSS
PCSA3 PCSB4 PCSB2 PCSB1 H
J
ETPUA ETPUA ETPUA ETPUA
14
20
19
13
VSS
VSS
VSS
VSS
PCSB5 TXDA PCSA2 SCKB J
K
ETPUA ETPUA ETPUA VDDEH
16
15
7
1
VSS
VSS
VSS
VSS
CNTXC RXDA RSTOUT
L
ETPUA ETPUA ETPUA TCRCLK
12
11
6
A
AN36
8 June 2005p
TXDB CNRXC
Note:
PLL
CFG1
EMIOS EMIOS EMIOS EMIOS EMIOS CNTXA
16
17
6
8
22
VDD
VSS
VRC33
XTAL
P
EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNRXA CNRXB
14
19
23
4
3
9
11
VDD
VSS
VDD
SYN
R
EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNTXB VDDE5
15
18
20
0
1
5
7
13
ENG
CLK
VDD
VSS
T
14
15
16
P
ETPUA ETPUA
3
2
VSS
VDD
GPIO
207
VDDE2
GPIO
206
VDD
OE
1
2
3
RESET L
VRC
CTL
VDD
VSS
K
VSS
VSS
T
VPP
VDD33 EMIOS EMIOS VDDEH EMIOS EMIOS VDD33
12
4
2
10
21
ETPUA ETPUA ETPUA
8
4
0
VDD
WKP
CFG
PCSB0 G
BOOT
CFG1
N
VSS
SINB
PLL
CFG0
ETPUA ETPUA ETPUA ETPUA
10
9
1
5
CS0
MCKO JCOMP F
RXDB
M
R
No connect. R1 reserved for CS0
CS0
MSEO1 E
4
5
6
7
8
9
10
11
12
13
VSS
SYN
M
EXTAL N
Figure 37. MPC5553 208 Package
MPC5553 Microcontroller Data Sheet, Rev. 0
54
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Mechanicals
4.2
4.2.1
Package Dimensions
MPC5553 416-Pin Package
Figure 38 is a package drawing of the MPC5553 416 pin TEPBGA package.
Figure 38. MPC5553 416 TEPBGA Package
MPC5553 Microcontroller Data Sheet, Rev. 0
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
55
Mechanicals
4.2.2
MPC5553 324-Pin Package
Figure 39 is a package drawing of the MPC5553 324-pin TEPBGA package.
Figure 39. MPC5553 324 TEPBGA Package
MPC5553 Microcontroller Data Sheet, Rev. 0
56
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Mechanicals
4.2.3
MPC5553 208-Pin Package
Figure 40 is a package drawing of the MPC5553 208-pin MAP BGA package.
Figure 40. MPC5553 208 MAP BGA Package
MPC5553 Microcontroller Data Sheet, Rev. 0
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
57
Revision History
5
Revision History
Table 32 provides a revision history of this document.
Table 32. Revision History
Revision
Rev. 0
Location(s)
Substantive Change(s)
This is the first released version of this document.
MPC5553 Microcontroller Data Sheet, Rev. 0
58
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
THIS PAGE IS INTENTIONALLY BLANK
MPC5553 Microcontroller Data Sheet, Rev. 0
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
59
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Document Number: MPC5553
Rev. 0
06/2006
Preliminary—Subject to Change Without Notice