Microchip MCP6562 1.8v low-power push-pull output comparator Datasheet

MCP6561/1R/1U/2/4
1.8V Low-Power Push-Pull Output Comparator
Features
Description
• Propagation Delay at 1.8VDD:
- 56 ns (typical) High-to-Low
- 49 ns (typical) Low-to-High
• Low Quiescent Current: 100 µA (typical)
• Input Offset Voltage: ±3 mV (typical)
• Rail-to-Rail Input: VSS - 0.3V to VDD + 0.3V
• CMOS/TTL-Compatible Output
• Wide Supply Voltage Range: 1.8V to 5.5V
• Available in Single, Dual, and Quad
• Packages: SC70-5, SOT-23-5, SOIC, MSOP,
TSSOP
The Microchip Technology, Inc. MCP6561/1R/1U/2/4
families of CMOS/TTL compatible comparators are
offered in single, dual, and quad configurations.
Typical Applications
This family operates with single supply voltage of 1.8V
to 5.5V while drawing less than 100 µA/comparator of
quiescent current (typical).
•
•
•
•
•
•
•
Laptop Computers
Mobile Phones
Hand-held Electronics
RC Timers
Alarm and Monitoring Circuits
Window Comparators
Multivibrators
These comparators are optimized for low power 1.8V,
single-supply applications with greater than rail-to-rail
input operation. The internal input hysteresis eliminates
output switching due to internal input noise voltage,
reducing current draw. The push-pull output of the
MCP6561/1R/1U/2/4 family supports rail-to-rail output
swing, and interfaces with CMOS/TTL logic. The output
toggle frequency can reach a typical of 4 MHz (typical)
while limiting supply current surges and dynamic power
consumption during switching.
Package Types
MCP6561
SOT-23-5, SC70-5
-
Design Aids
+IN 3
• Microchip Advanced Part Selector (MAPS)
• Analog Demonstration and Evaluation Boards
• Application Notes
MCP6561R
5 VSS
OUTA 1
4 -IN
-INA 2
+INA 3
-
+IN 3
-
VIN+ 1
VSS 2
VIN– 3
+
MCP656X
R2
R3
14 OUTD
- +
+ -
-INB 6
OUTB 7
13 -IND
12 +IND
11 VSS
10 +INC
+INB 5
MCP6561U
SOT-23-5
VOUT
6 -INB
5 +INB
VDD 4
VDD
VDD
+ -
SOIC, TSSOP
Typical Application
VIN
7 OUTB
- +
MCP6564
SOT-23-5
+
• Open-Drain Output: MCP6566/6R/6U/7/9
4 -IN
-INA 2
+INA 3
VSS 4
OUT 1
VDD 2
Related Devices
8 VDD
5 VDD OUTA 1
+
OUT 1
VSS 2
MCP6562
SOIC, MSOP
- +
+ -
9 -INC
8 OUTC
5 VDD
4 OUT
RF
 2009-2013 Microchip Technology Inc.
DS22139C-page 1
MCP6561/1R/1U/2/4
NOTES:
DS22139C-page 2
 2009-2013 Microchip Technology Inc.
MCP6561/1R/1U/2/4
1.0
ELECTRICAL
CHARACTERISTICS
1.1
Maximum Ratings †
† Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
VDD - VSS ....................................................................... 6.5V
Analog Input (VIN) †† .....................VSS - 1.0V to VDD + 1.0V
†† See Section 4.1.2 “Input Voltage and Current Limits”
All other inputs and outputs............VSS - 0.3V to VDD + 0.3V
Difference Input voltage ......................................|VDD - VSS|
Output Short Circuit Current .................................... ±25 mA
Current at Input Pins .................................................. ±2 mA
Current at Output and Supply Pins .......................... ±50 mA
Storage temperature ................................... -65°C to +150°C
Ambient temp. with power applied .............. -40°C to +125°C
Junction temp............................................................ +150°C
ESD protection on all pins (HBM/MM)4 kV/300V
DC CHARACTERISTICS
Electrical Characteristics: Unless otherwise indicated: VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD/2, VIN- = VSS,
RL = 10 k to VDD/2 (see Figure 1-1).
Parameters
Symbol
Min
Typ
Max
Units
Conditions
VDD
1.8
—
5.5
V
IQ
60
100
130
µA
IOUT = 0
PSRR
63
70
—
dB
VCM = VSS
+10
mV
VCM = VSS (Note 1)
—
µV/°C
—
pA
VCM = VSS
—
pA
TA = +25°C, VIN- = VDD/2
Power Supply
Supply Voltage
Quiescent Current per comparator
Power Supply Rejection Ratio
Input
VOS
-10
VOS/T
—
IOS
—
3
2
1
IB
—
1
Input Offset Voltage
Input Offset Drift
Input Offset Current
Input Bias Current
VCM = VSS
—
60
—
pA
TA = +85°C, VIN- = VDD/2
—
1500
5000
pA
TA = +125°C, VIN- = VDD/2
VCM = VSS (Notes 1, 2)
VHYST
1.0
—
5.0
mV
Input Hysteresis Linear Temp. Co.
TC1
—
10
—
µV/°C
Input Hysteresis Quadratic Temp.
Co.
TC2
—
0.3
—
µV/°C2
Common-mode Input Voltage
Range
VCMR
VSS0.2
—
VDD+0.2
V
VSS0.3
—
VDD+0.3
V
VDD = 5.5V
Common-mode Rejection Ratio
CMRR
54
66
—
dB
VCM= -0.3V to VDD+0.3V, VDD = 5.5V
Input Hysteresis Voltage
VDD = 1.8V
50
63
—
dB
VCM= VDD/2 to VDD+0.3V, VDD = 5.5V
54
65
—
dB
VCM= -0.3V to VDD/2, VDD = 5.5V
Common-mode Input Impedance
ZCM
—
1013||4
—
||pF
Differential Input Impedance
ZDIFF
—
1013||2
—
||pF
High-Level Output Voltage
VOH
VDD0.7
—
—
V
IOUT = -3 mA/-8 mA with VDD = 1.8V/5.5V
(Note 3)
Low-Level Output Voltage
VOL
—
—
0.6
V
IOUT = 3 mA/8 mA with VDD = 1.8V/5.5V
(Note 3)
ISC
—
±30
—
mA
COUT
—
8
—
pF
Push-Pull Output
Short Circuit Current
Output Pin Capacitance
Note 1:
2:
3:
Note 3
The input offset voltage is the center of the input-referred trip points. The input hysteresis is the difference between the
input-referred trip points.
VHYST at different temperatures is estimated using VHYST (TA) = VHYST @ +25°C + (TA - 25°C) TC1 + (TA - 25°C)2 TC2.
Limit the output current to Absolute Maximum Rating of 50 mA.
 2009-2013 Microchip Technology Inc.
DS22139C-page 3
MCP6561/1R/1U/2/4
AC CHARACTERISTICS
Electrical Characteristics: Unless otherwise indicated: VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD/2, VIN- = VSS,
RL = 10 k to VDD/2, and CL = 25 pF. (see Figure 1-1).
Parameters
Symbol
Min
Typ
Max
Units
Conditions
High-to-Low,100 mV Overdrive
tPHL
—
56
80
ns
VCM= VDD/2, VDD = 1.8V
—
34
80
ns
VCM= VDD/2, VDD = 5.5V
Low-to-High, 100 mV Overdrive
tPLH
—
49
80
ns
VCM= VDD/2, VDD = 1.8V
—
47
80
ns
VCM= VDD/2, VDD = 5.5V
tPDS
—
±10
—
ns
Rise Time
tR
—
20
—
ns
Fall Time
tF
—
20
—
ns
Maximum Toggle Frequency
fTG
—
4
—
MHz
VDD = 5.5V
—
2
—
MHz
VDD = 1.8V
Input Voltage Noise 2
ENI
—
350
—
µVP-P
10 Hz to 10 MHz
Propagation Delay
Skew 1
Output
Propagation Delay Skew is defined as: tPDS = tPLH - tPHL.
ENI is based on SPICE simulation.
Note 1:
2:
TEMPERATURE SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated: VDD = +1.8V to +5.5V and VSS = GND.
Parameters
Symbol
Min
Typ
Max
Units
Conditions
Temperature Ranges
Specified Temperature Range
TA
-40
—
+125
°C
Operating Temperature Range
TA
-40
—
+125
°C
Storage Temperature Range
TA
-65
—
+150
°C
Thermal Package Resistances
Thermal Resistance, SC70-5
JA
—
331
—
°C/W
Thermal Resistance, SOT-23-5
JA
—
220.7
—
°C/W
Thermal Resistance, 8L-SOIC
JA
—
149.5
—
°C/W
Thermal Resistance, 8L-MSOP
JA
—
211
—
°C/W
Thermal Resistance, 14L-SOIC
JA
—
95.3
—
°C/W
Thermal Resistance, 14L-TSSOP
JA
—
100
—
°C/W
1.2
Test Circuit Configuration
This test circuit configuration is used to determine the
AC and DC specifications.
VDD
MCP656X
200 k
IOUT
200 k
200 k
VIN = VSS
200 k
VOUT
25 pF
VSS = 0V
FIGURE 1-1:
AC and DC Test Circuit for
the Push-Pull Output Comparators.
DS22139C-page 4
 2009-2013 Microchip Technology Inc.
MCP6561/1R/1U/2/4
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD /2, VIN – = GND,
RL = 10 k to VDD/2, and CL = 25 pF.
30%
40%
30%
VDD = 5.5V
VCM = VSS
Avg. = -0.9 mV
StDev = 2.1 mV
3588 units
VDD = 1.8V
VCM = VSS
Avg. = -0.1 mV
StDev = 2.1 mV
3588 units
20%
10%
-6
FIGURE 2-1:
-4
-2 0
2
VOS (mV)
4
6
8
10%
10
Input Offset Voltage.
1.0
1.5
2.0
FIGURE 2-4:
60%
2.5 3.0 3.5
VHYST (mV)
4.0
4.5
5.0
Input Hysteresis Voltage.
60%
VCM = VSS
Avg. = 0.9 µV/°C
StDev = 6.6 µV/°C
1380 Units
TA = -40°C to +125°C
Occurrences (%)
Occurrences (%)
15%
0%
-10 -8
40%
20%
VDD = 5.5V
Avg. = 3.6 mV
StDev = 0.1 mV
3588 units
5%
0%
50%
VDD = 1.8V
Avg. = 3.4 mV
StDev = 0.2 mV
3588 units
25%
Occurrences (%)
Occurrences (%)
50%
30%
20%
10%
0%
VDD = 5.5V
Avg. = 10.4 µV/°C
StDev = 0.6 µV/°C
50%
40%
VDD = 1.8V
Avg. = 12 µV/°C
StDev = 0.6 µV/°C
30%
20%
1380 Units
TA = -40°C to 125°C
VCM = VSS
10%
0%
-60 -48 -36 -24 -12 0 12 24
VOS Drift (µV/°C)
FIGURE 2-2:
36
48
60
Input Offset Voltage Drift.
0
4
6
8 10 12 14 16
VHYST Drift, TC1 (µV/°C)
18
20
FIGURE 2-5:
Input Hysteresis Voltage
Drift - Linear Temp. Co. (TC1).
7.0
VDD = 5.5V
2
30%
VIN+ = VDD /2
VOUT (V)
5.0
4.0
VIN -
VOUT
3.0
2.0
1.0
0.0
VDD = 5.5V
Time (3 µs/div)
Input vs. Output Signal, No
 2009-2013 Microchip Technology Inc.
VDD = 1.8V
2
20%
10%
Avg. = 0.25 µV/°C
StDev = 0.1 µV/°C2
2
Avg. = 0.3 µV/°C
StDev = 0.2 µV/°C2
1380 Units
TA = -40°C to +125°C
VCM = VSS
0%
-0.50
-1.0
FIGURE 2-3:
Phase Reversal.
Occurrences (%)
6.0
-0.25
0.00
0.25
0.50
0.75
2
VHYST Drift, TC2 (µV/°C )
1.00
FIGURE 2-6:
Input Hysteresis Voltage
Drift - Quadratic Temp. Co. (TC2).
DS22139C-page 5
MCP6561/1R/1U/2/4
Note: Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD /2, VIN – = GND,
RL = 10 k to VDD/2, and CL = 25 pF.
3.0
5.0
VCM = VSS
2.0
VCM = VSS
VDD= 1.8V
VHYST (mV)
V OS (mV)
4.0
1.0
0.0
-1.0
3.0
VDD= 1.8V
2.0
VDD= 5.5V
-2.0
VDD= 5.0V
-3.0
1.0
-50
-25
0
FIGURE 2-7:
Temperature.
25
50
75
Temperature (°C)
100
125
Input Offset Voltage vs.
-50
-25
0
FIGURE 2-10:
Temperature.
4.0
25
50
75
Temperature (°C)
100
125
Input Hysteresis Voltage vs.
5.0
VDD = 1.8V
TA= +125°C
TA= +125°C
4.0
TA= +85°C
VHYST (mV)
VOS (mV)
2.0
0.0
TA= +25°C
TA= -40°C
-2.0
3.0
TA= +25°C
2.0
TA= +85°C
VDD = 1.8V
-4.0
-0.3
0.0
0.3
0.6
0.9 1.2
VCM (V)
1.5
1.8
1.0
-0.3
2.1
FIGURE 2-8:
Input Offset Voltage vs.
Common-mode Input Voltage.
0.0
TA= -40°C
0.3
0.6
0.9
1.2
VCM (V)
1.5
1.8
2.1
FIGURE 2-11:
Input Hysteresis Voltage vs.
Common-mode Input Voltage.
3.0
5.0
VDD = 5.5V
4.0
TA= -40°C
1.0
VHYST (mV)
VOS (mV)
2.0
TA= +25°C
0.0
-1.0
-3.0
-1.0
TA= -40°C
TA= +25°C
TA= +85°C
TA= +125°C
2.0
TA= +85°C
-2.0
3.0
TA= +125°C
0.0
1.0
2.0
3.0
VCM (V)
4.0
5.0
FIGURE 2-9:
Input Offset Voltage vs.
Common-mode Input Voltage.
DS22139C-page 6
6.0
1.0
-0.5
0.5
1.5
VDD = 5.5V
2.5
3.5
VCM (V)
4.5
5.5
FIGURE 2-12:
Input Hysteresis Voltage vs.
Common-mode Input Voltage.
 2009-2013 Microchip Technology Inc.
MCP6561/1R/1U/2/4
Note: Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD /2, VIN – = GND,
RL = 10 k to VDD/2, and CL = 25 pF.
3.0
5.0
TA= +125°C
0.0
TA= +85°C
4.0
TA= -40°C
TA= +25°C
TA= +85°C
TA= +125°C
1.0
VHYST (mV)
VOS (mV)
2.0
-1.0
TA= +25°C
3.0
TA= -40°C
2.0
-2.0
-3.0
1.0
1.5
2.5
3.5
VDD (V)
4.5
5.5
1.5
FIGURE 2-13:
Input Offset Voltage vs.
Supply Voltage vs. Temperature.
4.5
5.5
140.0
VDD = 5.5V
Avg. = 97 µA
StDev= 4 µA
1794 units
VDD = 1.8V
Avg. = 88 µA
StDev= 4 µA
1794 units
40%
30%
20%
120.0
100.0
IQ (µA)
Occurrences (%)
3.5
VDD (V)
FIGURE 2-16:
Input Hysteresis Voltage vs.
Supply Voltage vs. Temperature.
50%
80.0
60.0
TA= -40°C
TA= +25°C
TA= +85°C
TA= +125°C
40.0
10%
20.0
0%
0.0
60
70
FIGURE 2-14:
80
90
100
IQ (µA)
110
120
130
Quiescent Current.
0.0
2.0
3.0
V DD (V)
4.0
5.0
6.0
130
VDD = 1.8V
VDD = 5.5V
120
120
110
IQ (µA)
110
100
Sweep VIN+ ,VIN- = VDD /2
90
80
Sweep VIN - ,VIN+ = VDD/2
/
70
60
-0.5
1.0
FIGURE 2-17:
Quiescent Current vs.
Supply Voltage vs Temperature.
130
IQ (µA)
2.5
Sweep VIN+ ,VIN- = VDD/2
100
90
Sweep VIN- ,VIN+ = VDD/2
80
70
0.0
0.5
1.0
VCM (V)
1.5
2.0
FIGURE 2-15:
Quiescent Current vs.
Common-mode Input Voltage.
 2009-2013 Microchip Technology Inc.
2.5
60
-1.0
0.0
1.0
2.0
3.0
VCM (V)
4.0
5.0
6.0
FIGURE 2-18:
Quiescent Current vs.
Common-mode Input Voltage.
DS22139C-page 7
MCP6561/1R/1U/2/4
Note: Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD /2, VIN – = GND,
RL = 10 k to VDD/2, and CL = 25 pF.
400
350
TA= -40°C
TA= +25°C
TA= +85°C
TA= +125°C
80
300
VDD = 5.5V
ISC (mA)
IQ (µA)
120
0dB Output Attenuation
100 mV Over-Drive
VCM = VDD /2
RL = Open
250
200
VDD = 1.8V
40
0
-40
TA= -40°C
TA= +25°C
TA= +85°C
TA= +125°C
150
-80
100
-120
50
10
10
100
100
0.0
1k
10k 100000
100k 100000
1M
10M
1000
10000
1E+07
Toggle Frequency (Hz)
0
FIGURE 2-19:
Quiescent Current vs.
Toggle Frequency.
VOL, VDD - VOH (mV)
VOL, VDD - VOH (mV)
4.0
5.0
6.0
VDD= 5.5V
VDD - VOH
800
VOL
600
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
400
200
1200
VDD - VOH
TA = 125°C
TA = 85°C
TA = 25°C
TA = -40°C
1000
800
600
400
200
0
VOL
0
3.0
FIGURE 2-20:
Output Current.
50%
tPLH
Avg. = 47 ns
StDev= 2 ns
198 units
6.0
9.0
IOUT (mA)
12.0
Output Headroom vs.
VDD= 1.8V
100 mV Over-Drive
VCM = VDD /2
0
15.0
5
FIGURE 2-23:
Current.
10
15
IOUT (mA)
20
25
Output Headroom vs.Output
50%
Occurrences (%)
0.0
Occurrences (%)
3.0
VDD (V)
1400
VDD= 1.8V
30%
2.0
FIGURE 2-22:
Short Circuit Current vs.
Supply Voltage vs. Temperature.
1000
40%
1.0
tPHL
Avg. = 54.4 ns
StDev= 2 ns
198 units
20%
10%
0%
tPHL
Avg. = 33 ns
StDev= 1 ns
198 units
40%
VDD= 5.5V
100mV Over-Drive
VCM = VDD /2
30%
tPLH
Avg. = 44.6 ns
StDev= 2.7 ns
198 units
20%
10%
0%
30
35
40
45
50
55
60
65
70
75
80
Prop. Delay (ns)
FIGURE 2-21:
Low-to-High and High-toLow Propagation Delays.
DS22139C-page 8
30
35
40
45
50
55
60
65
70
75
80
Prop. Delay (ns)
FIGURE 2-24:
Low-to-High and High-toLow Propagation Delays .
 2009-2013 Microchip Technology Inc.
MCP6561/1R/1U/2/4
Note: Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD /2, VIN – = GND,
RL = 10 k to VDD/2, and CL = 25 pF.
80
100 mV Over-Drive
VCM = VDD /2
40%
VDD = 1.8V
Avg. = -7.3 ns
StDev= 0.8 ns
198 units
30%
VDD = 5.5V
Avg. = 11.6 ns
StDev= 2 ns
198 units
20%
100 mV Over-Drive
VCM = VDD /2
70
Prop. Delay (ns)
Occurrences (%)
50%
10%
tPLH , VDD = 1.8V
tPHL
tPHL , VDD = 1.8V
60
50
40
tPLH , VDD = 5.5V
tPHL , VDD = 5.5V
30
0%
20
-20
-15
-10
-5
0
5
10
15
-50
20
-25
Prop. Delay Skew (ns)
FIGURE 2-25:
Propagation Delay Skew.
0
25
50
75
Temperature (°C)
FIGURE 2-28:
Temperature.
Propagation Delay vs.
VCM = VDD/2
120
tPHL , 10 mV Over-Drive
tPLH , 10 mV Over-Drive
Prop. Delay (ns)
Prop. Delay (ns)
VCM = VDD/2
100
80
tPHL , 100 mV Over-Drive
tPLH , 100 mV Over-Drive
60
40
20
210
tPLH , VDD = 1.8V
tPHL , VDD = 1.8V
160
tPLH , VDD = 5.5V
tPHL , VDD = 5.5V
110
60
10
1.5
2.5
FIGURE 2-26:
Supply Voltage.
3.5
V DD (V)
4.5
5.5
1
10
100
1000
Over-Drive (mV)
Propagation Delay vs.
FIGURE 2-29:
Over-Drive.
80
Propagation Delay vs. Input
80
VDD = 1.8V
100 mV Over-Drive
tPHL
70
tPLH
Prop. Delay (ns)
Prop. Delay (ns)
125
260
140
70
100
60
50
40
30
20
0.00
VDD= 5.5V
100 mV Over-Drive
60
tPHL
tPLH
50
40
30
20
0.50
1.00
VCM (V)
1.50
FIGURE 2-27:
Propagation Delay vs.
Common-mode Input Voltage.
 2009-2013 Microchip Technology Inc.
2.00
0.0
1.0
2.0
3.0
VCM (V)
4.0
5.0
6.0
FIGURE 2-30:
Propagation Delay vs.
Common-mode Input Voltage.
DS22139C-page 9
MCP6561/1R/1U/2/4
Note: Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD /2, VIN – = GND,
RL = 10 k to VDD/2, and CL = 25 pF.
1000
10
VDD = 5.5V, tPLH
VDD = 5.5V, tPHL
1
0.1
20%
15%
10%
5%
0.01
0.001
1
0%
0.01
10
0.1
1
10
10
1000
100
1000
10000
100000
1E+06
Capacitive Load (nf)
FIGURE 2-31:
Capacitive Load.
Propagation Delay vs.
-600
-400
-200
FIGURE 2-34:
Ratio (PSRR).
Occurrences (%)
10µ
1E+07
100n
1E+05
TA= -40°C
TA= +25°C
TA= +85°C
TA= +125°C
1n
1E+03
10p
1E+01
0.1p
1E-01
-0.8
-0.4
-0.2
20%
10%
0
VCM = -0.2V to VDD/2
Avg. = 0.5 mV
StDev= 0.1 mV
-5
VDD = 1.8V
3588 units
-4
-3
-2
-1
FIGURE 2-35:
Ratio (CMRR).
30%
Input Referred
78
Occurrences (%)
VCM = VSS
VDD = 1.8V to 5.5V
PSRR
CMRR
72
VCM = -0.3V to VDD + 0.3V
VDD = 5.5V
70
-25
0
25
50
75
Temperature (°C)
100
125
FIGURE 2-33:
Common-mode Rejection
Ratio and Power Supply Rejection Ratio vs.
Temperature.
DS22139C-page 10
0
1
2
3
4
5
CMRR (mV/V)
80
CMRR/PSRR (dB)
600
0%
-0.6
FIGURE 2-32:
Input Bias Current vs. Input
Voltage vs Temperature.
-50
400
VCM = -0.2V to VDD + 0.2V
Avg. = 0.6 mV
StDev= 0.1 mV
VCM = VDD/2 to VDD+ 0.2V
Avg. = 0.7 mV
StDev= 1 mV
Input Voltage (V)
74
200
Power Supply Rejection
30%
1E+09
1m
76
0
PSRR (µV/V)
10m
1E+11
Input Current (A)
VCM = VSS
Avg. = 200 µV/V
StDev= 94 µV/V
3588 units
25%
VDD = 1.8V, tPLH
VDD = 1.8V, tPHL
Occurrences (%)
Prop. Delay (µs)
100
30%
100mV Over-Drive
VCM = VDD/2
Common-mode Rejection
V CM = V DD /2 to VDD+ 0.3V
Avg. = 0.03 mV
StDev= 0.7 mV
VCM = -0.3V to VDD + 0.3V
Avg. = 0.1 mV
StDev= 0.4 mV
20%
10%
VCM = -0.3V to VDD/2
Avg. = 0.2 mV
StDev= 0.4 mV
VDD = 5.5V
3588 units
0%
-2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5
CMRR (mV/V)
FIGURE 2-36:
Ratio (CMRR).
Common-mode Rejection
 2009-2013 Microchip Technology Inc.
MCP6561/1R/1U/2/4
Note: Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD /2, VIN – = GND,
RL = 10 k to VDD/2, and CL = 25 pF.
10000
1000
VDD = 5.5V
IB @ TA=
VDD = 5.5V
1000
VIN+ = 2Vpp (sine)
IOS and IB (pA)
Output Jitter pk-pk (ns)
10000
100
10
1
IB @ TA=
100
10
1
|IOS| @ TA= 125°C
0.1
|IOS|@ TA= 85°C
0.01
0.001
0.1
100
100
1k
1000
10M
10k
100k
1M
10000 100000 1000000 1E+07
Input Frequency (Hz)
FIGURE 2-37:
Frequency.
Output Jitter vs. Input
0
1
2
3
V CM (V)
4
5
6
FIGURE 2-39:
Input Offset Current and
Input Bias Current vs. Common-mode Input
Voltage vs. Temperature.
IOS and IB (pA)
1000
100
IB
10
1
|I OS|
0.1
25
50
75
100
Temperature (°C)
125
FIGURE 2-38:
Input Offset Current and
Input Bias Current vs. Temperature.
 2009-2013 Microchip Technology Inc.
DS22139C-page 11
MCP6561/1R/1U/2/4
NOTES:
DS22139C-page 12
 2009-2013 Microchip Technology Inc.
MCP6561/1R/1U/2/4
3.0
PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
MCP6561
MCP6561U
MCP6562
MCP6564
SOT-23-5
SOT-23-5
MSOP,
SOIC
SOIC,
TSSOP
1
1
4
1
1
OUT, OUTA Digital Output (comparator A)
4
4
3
2
2
VIN–, VINA– Inverting Input (comparator A)
3
3
1
3
3
VIN+, VINA+ Non-inverting Input (comparator A)
5
2
5
8
4
VDD
Non-inverting Input (comparator B)
SC70-5,
SOT-23-5
3.1
PIN FUNCTION TABLE
MCP6561R
Description
Positive Power Supply
—
—
—
5
5
VINB+
—
—
—
6
6
VINB–
Inverting Input (comparator B)
—
—
—
7
7
OUTB
Digital Output (comparator B)
—
—
—
—
8
OUTC
Digital Output (comparator C)
—
—
—
—
9
VINC–
Inverting Input (comparator C)
—
—
—
—
10
VINC+
Non-inverting Input (comparator C)
2
5
2
4
11
VSS
—
—
—
—
12
VIND+
Negative Power Supply
Non-inverting Input (comparator D)
—
—
—
—
13
VIND–
Inverting Input (comparator D)
—
—
—
—
14
OUTD
Digital Output (comparator D)
Analog Inputs
The comparator non-inverting and inverting inputs are
high-impedance CMOS inputs with low bias currents.
3.2
Symbol
Digital Outputs
The comparator outputs are CMOS, push-pull digital
outputs. They are designed to be compatible with
CMOS and TTL logic and are capable of driving heavy
DC or capacitive loads.
 2009-2013 Microchip Technology Inc.
3.3
Power Supply (VSS and VDD)
The positive power supply pin (VDD) is 1.8V to 5.5V
higher than the negative power supply pin (VSS). For
normal operation, the other pins are at voltages
between VSS and VDD.
Typically, these parts are used in a single (positive)
supply configuration. In this case, VSS is connected to
ground and VDD is connected to the supply. VDD will
need a local bypass capacitor (typically 0.01 µF to
0.1 µF) within 2 mm of the VDD pin. These can share a
bulk capacitor with nearby analog parts (within
100 mm), but it is not required.
DS22139C-page 13
MCP6561/1R/1U/2/4
NOTES:
DS22139C-page 14
 2009-2013 Microchip Technology Inc.
MCP6561/1R/1U/2/4
4.0
APPLICATIONS INFORMATION
The MCP6561/1R/1U/2/4 family of push-pull output
comparators are fabricated on Microchip’s state-of-theart CMOS process. They are suitable for a wide range
of high speed applications requiring low power
consumption.
4.1
VDD Bond
Pad
VIN+ Bond
Pad
Bond
Pad
Input
Stage
VIN–
Comparator Inputs
4.1.1
NORMAL OPERATION
The input stage of this family of devices uses three
differential input stages in parallel: one operates at lowinput voltages, one at high-input voltages, and one at
mid-input voltage. With this topology, the input voltage
range is 0.3V above VDD and 0.3V below VSS, while
providing low offset voltage through out the Commonmode range. The input offset voltage is measured at
both VSS - 0.3V and VDD + 0.3V to ensure proper
operation.
The MCP6561/1R/1U/2/4 family has internally-set
hysteresis VHYST that is small enough to maintain input
offset accuracy and large enough to eliminate output
chattering caused by the comparator’s own input noise
voltage ENI. Figure 4-1 depicts this behavior. Input
offset voltage (VOS) is the center (average) of the
(input-referred) low-high and high-low trip points. Input
hysteresis voltage (VHYST) is the difference between
the same trip points.
VSS
Bond
Pad
FIGURE 4-2:
Structures.
Simplified Analog Input ESD
In order to prevent damage and/or improper operation
of these amplifiers, the circuits they are in must limit the
currents (and voltages) at the VIN+ and VIN– pins (see
Maximum Ratings † at the beginning of Section 1.0
“Electrical Characteristics”). Figure 4-3 shows the
recommended approach to protecting these inputs.
The internal ESD diodes prevent the input pins (VIN+
and VIN–) from going too far below ground, and the
resistors R1 and R2 limit the possible current drawn out
of the input pin. Diodes D1 and D2 prevent the input pin
(VIN+ and VIN–) from going too far above VDD. When
implemented as shown, resistors R1 and R2 also limit
the current through D1 and D2.
8
7
6
5
4
3
2
1
0
-1
-2
-3
VDD = 5.0V
VIN–
VOUT
Hysteresis
25
20
15
10
5
0
-5
-10
-15
-20
-25
-30
Input Voltage (10 mV/div)
Output Voltage (V)
VDD
Time (100 ms/div)
FIGURE 4-1:
The MCP6561/1R/1U/2/4
Comparators’ Internal Hysteresis Eliminates
Output Chatter Caused by Input Noise Voltage.
4.1.2
INPUT VOLTAGE AND CURRENT
LIMITS
The ESD protection on the inputs can be depicted as
shown in Figure 4-2. This structure was chosen to
protect the input transistors, and to minimize input bias
current (IB). The input ESD diodes clamp the inputs
when they try to go more than one diode drop below
VSS. They also clamp any voltages that go too far
above VDD; their breakdown voltage is high enough to
allow normal operation, and low enough to bypass ESD
events within the specified limits.
 2009-2013 Microchip Technology Inc.
D1
V1
+
MCP656X
–
R1
VOUT
D2
V2
R2
R3
R1 
VSS – (minimum expected V1)
2 mA
R2 
VSS – (minimum expected V2)
2 mA
FIGURE 4-3:
Inputs.
Protecting the Analog
It is also possible to connect the diodes to the left of the
resistors R1 and R2. In this case, the currents through
the diodes D1 and D2 need to be limited by some other
mechanism. The resistor then serves as in-rush current
limiter; the DC current into the input pins (VIN+ and
VIN–) should be very small.
DS22139C-page 15
MCP6561/1R/1U/2/4
A significant amount of current can flow out of the
inputs when the Common-mode voltage (VCM) is below
ground (VSS); see Figure 2-32. Applications that are
high impedance may need to limit the usable voltage
range.
4.1.3
4.3.1
Figure 4-4 shows a non-inverting circuit for singlesupply applications using just two resistors. The
resulting hysteresis diagram is shown in Figure 4-5.
PHASE REVERSAL
VDD
The MCP6561/1R/1U/2/4 comparator family uses
CMOS transistors at the input. They are designed to
prevent phase inversion when the input pins exceed
the supply voltages. Figure 2-3 shows an input voltage
exceeding both supplies with no resulting phase
inversion.
4.2
Push-Pull Output
The push-pull output is designed to be compatible with
CMOS and TTL logic, while the output transistors are
configured to give rail-to-rail output performance. They
are driven with circuitry that minimizes any switching
current (shoot-through current from supply-to-supply)
when the output is transitioned from high-to-low, or
from low-to-high (see Figure 2-15 and Figure 2-18 for
more information).
4.3
NON-INVERTING CIRCUIT
VOUT
MCP656X
+
VIN
R1
RF
FIGURE 4-4:
Non-inverting Circuit with
Hysteresis for Single-Supply.
VOUT
VDD
VOH
High-to-Low
Externally Set Hysteresis
Greater flexibility in selecting hysteresis (or input trip
points) is achieved by using external resistors.
Hysteresis reduces output chattering when one input is
slowly moving past the other. It also helps in systems
where it is best not to cycle between high and low
states too frequently (e.g., air conditioner thermostatic
control). Output chatter also increases the dynamic
supply current.
-
VREF
Low-to-High
VIN
VOL
VSS
VSS
VTHL VTLH
VDD
FIGURE 4-5:
Hysteresis Diagram for the
Non-inverting Circuit.
The trip points for Figure 4-4 and Figure 4-5 are:
EQUATION 4-1:
R1 
 R1 

VTLH = V REF  1 + -------  – V OL ------- 
RF 
RF 

R1 
R 1 

VTHL = V REF  1 + -------  – V OH ------- 
RF 
RF 

Where:
DS22139C-page 16
VTLH
=
trip voltage from low-to-high
VTHL
=
trip voltage from high-to-low
 2009-2013 Microchip Technology Inc.
MCP6561/1R/1U/2/4
4.3.2
INVERTING CIRCUIT
Where:
Figure 4-6 shows an inverting circuit for single-supply
using three resistors. The resulting hysteresis diagram
is shown in Figure 4-7.
R2 R3
R 23 = ------------------R2 + R3
R3
V 23 = -------------------  VDD
R 2 + R3
VDD
VIN
VDD
Using this simplified circuit, the trip voltage can be
calculated using the following equation:
VOUT
MCP656X
R2
EQUATION 4-2:
RF
 R 23 
V THL = V OH  ----------------------- + V 23  ----------------------


R
+
R
R
 23
23 + R F
F
RF
R3
FIGURE 4-6:
Hysteresis.
RF
 R23 
V TLH = V OL  ----------------------- + V 23  ----------------------
R
+
R
R
 23
23 + R F
F
Where:
Inverting Circuit With
VOUT
VTLH
=
trip voltage from low-to-high
VTHL
=
trip voltage from high-to-low
Figure 2-20, and Figure 2-23 can be used to determine
typical values for VOH and VOL.
VDD
VOH
Low-to-High
VOL
VSS
VSS
High-to-Low
4.4
VIN
VTLH VTHL
FIGURE 4-7:
Inverting Circuit.
VDD
Hysteresis Diagram for the
In order to determine the trip voltages (VTHL and VTLH)
for the circuit shown in Figure 4-6, R2 and R3 can be
simplified to the Thevenin equivalent circuit with
respect to VDD, as shown in Figure 4-8.
VDD
Bypass Capacitors
With this family of comparators, the power supply pin
(VDD for single supply) should have a local bypass
capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm for good
edge rate performance.
4.5
Capacitive Loads
Reasonable capacitive loads (e.g., logic gates) have
little impact on propagation delay (see Figure 2-31).
The supply current increases with increasing toggle
frequency (Figure 2-19), especially with higher
capacitive loads. The output slew rate and propagation
delay performance will be reduced with higher
capacitive loads.
MCP656X
+
VSS
VOUT
V23
R23
FIGURE 4-8:
RF
Thevenin Equivalent Circuit.
 2009-2013 Microchip Technology Inc.
DS22139C-page 17
MCP6561/1R/1U/2/4
4.6
PCB Surface Leakage
4.7
In applications where low input bias current is critical,
PCB (Printed Circuit Board) surface leakage effects
need to be considered. Surface leakage is caused by
humidity, dust or other contamination on the board.
Under low humidity conditions, a typical resistance
between nearby traces is 1012. A 5V difference would
cause 5 pA of current to flow. This is greater than the
MCP6561/1R/1U/2/4 family’s bias current at +25°C
(1 pA, typical).
The easiest way to reduce surface leakage is to use a
guard ring around sensitive pins (or traces). The guard
ring is biased at the same voltage as the sensitive pin.
An example of this type of layout is shown in
Figure 4-9.
IN-
IN+
VSS
When designing the PCB layout, it is critical to note that
analog and digital signal traces are adequately
separated to prevent signal coupling. If the comparator
output trace is at close proximity to the input traces,
then large output voltage changes from VSS to VDD, or
visa versa, may couple to the inputs and cause the
device output to oscillate. To prevent such oscillation,
the output traces must be routed away from the input
pins. The SC70-5 and SOT-23-5 are relatively immune
because the output pin OUT (pin 1) is separated by the
power pin VDD/VSS (pin 2) from the input pin +IN (as
long as the analog and digital traces remain separated
throughout the PCB). However, the pinouts for the dual
and quad packages (SOIC, MSOP, TSSOP) have OUT
and -IN pins (pin 1 and 2) close to each other. The
recommended layout for these packages is shown in
Figure 4-10.
Guard Ring
FIGURE 4-9:
Example Guard Ring Layout
for Inverting Circuit.
1.
2.
Inverting Configuration (Figures 4-6 and 4-9):
a) Connect the guard ring to the non-inverting
input pin (VIN+). This biases the guard ring
to the same reference voltage as the
comparator (e.g., VDD/2 or ground).
b) Connect the inverting pin (VIN-) to the input
pad without touching the guard ring.
Non-inverting Configuration (Figure 4-4):
a) Connect the non-inverting pin (VIN+) to the
input pad without touching the guard ring.
b) Connect the guard ring to the inverting input
pin (VIN-).
PCB Layout Technique
OUTA
VDD
-INA
OUTB
+INA
-INB
VSS
+INB
FIGURE 4-10:
4.8
Recommended Layout.
Unused Comparators
An unused amplifier in a quad package (MCP6564)
should be configured as shown in Figure 4-11. This
circuit prevents the output from toggling and causing
crosstalk. It uses the minimum number of components
and draws minimal current (see Figure 2-15 and
Figure 2-18).
¼ MCP6564
VDD
–
+
FIGURE 4-11:
DS22139C-page 18
Unused Comparators.
 2009-2013 Microchip Technology Inc.
MCP6561/1R/1U/2/4
4.9
4.9.3
Typical Applications
4.9.1
PRECISE COMPARATOR
Some applications require higher DC precision. An
easy way to solve this problem is to use an amplifier
(such as the MCP6291) to gain-up the input signal
before it reaches the comparator. Figure 4-12 shows
an example of this approach.
BISTABLE MULTIVIBRATOR
A simple bistable multivibrator design is shown in
Figure 4-14. VREF needs to be between the power
supplies (VSS = GND and VDD) to achieve oscillation.
The output duty cycle changes with VREF.
R1
R2
VREF
VDD
VDD
VREF
MCP6561
MCP6291
VOUT
VDD
VIN
R1
R2
MCP656X
VREF
FIGURE 4-12:
Comparator.
4.9.2
C1
VOUT
FIGURE 4-14:
R3
Bistable Multivibrator.
Precise Inverting
WINDOWED COMPARATOR
Figure 4-13 shows one approach to designing a
windowed comparator. The AND gate produces a logic
‘1’ when the input voltage is between VRB and VRT
(where VRT > VRB).
VDD
VRT
VIN
VRB
FIGURE 4-13:
1/2
MCP6562
1/2
MCP6562
Windowed Comparator.
 2009-2013 Microchip Technology Inc.
DS22139C-page 19
MCP6561/1R/1U/2/4
NOTES:
DS22139C-page 20
 2009-2013 Microchip Technology Inc.
MCP6561/1R/1U/2/4
5.0
DESIGN AIDS
5.3
5.1
Microchip Advanced Part Selector
(MAPS)
The following Microchip Application Note is available
on the Microchip web site at www.microchip.com and is
recommended as a supplemental reference resource:
MAPS is a software tool that helps semiconductor
professionals efficiently identify Microchip devices that
fit a particular design requirement. Available at no cost
from the Microchip web site at www.microchip.com/
maps, the MAPS is an overall selection tool for
Microchip’s product portfolio that includes Analog,
Memory, MCUs and DSCs. Using this tool you can
define a filter to sort features for a parametric search of
devices and export side-by-side technical comparison
reports. Helpful links are also provided for data sheets,
purchase, and sampling of Microchip parts.
5.2
Application Notes
• AN895, “Oscillator Circuits For RTD Temperature
Sensors”, DS00895
Analog Demonstration and
Evaluation Boards
Microchip offers a broad spectrum of Analog
Demonstration and Evaluation Boards that are
designed to help you achieve faster time to market. For
a complete listing of these boards and their
corresponding user’s guides and technical information,
visit the Microchip web site at www.microchip.com/
analogtools. Three of our boards that are especially
useful are:
• 8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board,
P/N SOIC8EV
• 14-Pin SOIC/TSSOP/DIP Evaluation Board,
P/N SOIC14EV
• 5/6-Pin SOT23 Evaluation Board, P/N VSUPEV2
 2009-2013 Microchip Technology Inc.
DS22139C-page 21
MCP6561/1R/1U/2/4
NOTES:
DS22139C-page 22
 2009-2013 Microchip Technology Inc.
MCP6561/1R/1U/2/4
6.0
PACKAGING INFORMATION
6.1
Package Marking Information
5-Lead SC-70 (MCP6561)
Example:
BC25
XXNN
5-Lead SOT-23 (MCP6561, MCP6561R, MCP6561U)
Device
XXNN
Example:
Code
MCP6561T
WBNN
MCP6561RT
WANN
MCP6561UT
WKNN
WA25
Note: Applies to 5-Lead SOT-23.
8-Lead MSOP (MCP6562)
XXXXXX
6562E
YWWNNN
302256
8-Lead SOIC (150 mil) (MCP6562)
XXXXXXXX
XXXXYYWW
NNN
Example:
MCP6562E
e3
SN^^1302
256
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
Example:
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
 2009-2013 Microchip Technology Inc.
DS22139C-page 23
MCP6561/1R/1U/2/4
Package Marking Information (Continued)
14-Lead SOIC (150 mil) (MCP6564)
Example:
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
14-Lead TSSOP (MCP6564)
MCP6564
E/SL^^
e3
1302256
Example:
XXXXXXXX
MCP6564E
YYWW
1302
NNN
256
DS22139C-page 24
 2009-2013 Microchip Technology Inc.
MCP6561/1R/1U/2/4
. # #$ # /! - 0 # 1/ %# #!#
## +22--- 2 /
D
b
3
1
2
E1
E
4
5
e
A
e
A2
c
A1
L
3#
4#
5$8 %1
44" "
5
5
56
7
(
1#
6, : #
;
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;
<
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!!1/
/
#! %%
9()*
6, =!#
"
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!!1/=!#
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(
(
(
6, 4#
;
(
.
4
9
#4#
4!
/
4!=!#
;
<
9
8
(
<
!"! #$! !% # $ !% # $ !# "'(
)*+ ) #&#,$
--# $## #&! !
 2009-2013 Microchip Technology Inc.
- *9)
DS22139C-page 25
MCP6561/1R/1U/2/4
. # #$ # /! - 0 # 1/ %# #!#
## +22--- 2 /
DS22139C-page 26
 2009-2013 Microchip Technology Inc.
MCP6561/1R/1U/2/4
!
. # #$ # /! - 0 # 1/ %# #!#
## +22--- 2 /
b
N
E
E1
3
2
1
e
e1
D
A2
A
c
φ
A1
L
L1
3#
4#
5$8 %1
44" "
5
56
7
5
(
4!1#
()*
6$# !4!1#
6, : #
<
;
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6, =!#
"
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"
<
;
6, 4#
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#! %%
)*
(
.
#4#
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<
9
.
# #
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;
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4!=!#
8
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!"! #$! !% # $ !% # $ #&! !
!# "'(
)*+ ) #&#,$
--# $##  2009-2013 Microchip Technology Inc.
- *)
DS22139C-page 27
MCP6561/1R/1U/2/4
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS22139C-page 28
 2009-2013 Microchip Technology Inc.
MCP6561/1R/1U/2/4
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
 2009-2013 Microchip Technology Inc.
DS22139C-page 29
MCP6561/1R/1U/2/4
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS22139C-page 30
 2009-2013 Microchip Technology Inc.
MCP6561/1R/1U/2/4
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
 2009-2013 Microchip Technology Inc.
DS22139C-page 31
MCP6561/1R/1U/2/4
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS22139C-page 32
 2009-2013 Microchip Technology Inc.
MCP6561/1R/1U/2/4
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
 2009-2013 Microchip Technology Inc.
DS22139C-page 33
MCP6561/1R/1U/2/4
" #$%!&'()*
. # #$ # /! - 0 # 1/ %# #!#
## +22--- 2 /
DS22139C-page 34
 2009-2013 Microchip Technology Inc.
MCP6561/1R/1U/2/4
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
 2009-2013 Microchip Technology Inc.
DS22139C-page 35
MCP6561/1R/1U/2/4
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS22139C-page 36
 2009-2013 Microchip Technology Inc.
MCP6561/1R/1U/2/4
. # #$ # /! - 0 # 1/ %# #!#
## +22--- 2 /
 2009-2013 Microchip Technology Inc.
DS22139C-page 37
MCP6561/1R/1U/2/4
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS22139C-page 38
 2009-2013 Microchip Technology Inc.
MCP6561/1R/1U/2/4
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
 2009-2013 Microchip Technology Inc.
DS22139C-page 39
MCP6561/1R/1U/2/4
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS22139C-page 40
 2009-2013 Microchip Technology Inc.
MCP6561/1R/1U/2/4
APPENDIX A:
REVISION HISTORY
Revision C (February 2013)
The following is the list of modifications:
1.
2.
Added the Analog Input (VIN) parameter in
Section 1.0 “Electrical Characteristics”.
Updated the package drawing section.
Revision B (August 2009)
The following is the list of modifications:
1.
2.
Added MCP6561U throughout the document.
Updated package drawing section.
Revision A (March 2009)
• Original Release of this Document.
 2009-2013 Microchip Technology Inc.
DS22139C-page 41
MCP6561/1R/1U/2/4
NOTES:
DS22139C-page 42
 2009-2013 Microchip Technology Inc.
MCP6561/1R/1U/2/4
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
Device:
–
X
/XX
Temperature
Range
Package
Single Comparator (Tape and Reel)
(SC70, SOT-23)
MCP6561RT: Single Comparator (Tape and Reel)
(SOT-23 only)
MCP6561UT: Single Comparator (Tape and Reel)
(SOT-23 only)
MCP6562:
Dual Comparator
MCP6562T:
Dual Comparator (Tape and Reel)
MCP6564:
Quad Comparator
MCP6564T:
Quad Comparator(Tape and Reel)
Examples:
a)
MCP6561T-E/LT:
b)
MCP6561T-E/OT:
a)
MCP6561RT-E/OT: Tape and Reel,
Extended Temperature,
5LD SOT-23 package.
a)
MCP6561UT-E/OT: Tape and Reel,
Extended Temperature,
5LD SOT-23 package.
a)
MCP6562-E/MS:
b)
MCP6562-E/SN:
a)
MCP6564T-E/SL:
b)
MCP6564T-E/ST:
MCP6561T:
Temperature Range: E
= -40C to +125C
Package:
=
=
=
=
=
=
LT
OT
MS
SN
ST
SL
Plastic Small Outline Transistor (SC70), 5-lead
Plastic Small Outline Transistor, 5-lead
Plastic Micro Small Outline Transistor, 8-lead
Plastic Small Outline Transistor, 8-lead
Plastic Thin Shrink Small Outline Transistor, 14-lead
Plastic Small Outline Transistor, 14-lead
 2009-2013 Microchip Technology Inc.
Tape and Reel,
Extended Temperature,
5LD SC70 package.
Tape and Reel,
Extended Temperature,
5LD SOT-23 package.
Extended Temperature,
8LD MSOP package.
Extended Temperature,
8LD SOIC package.
Tape and Reel,
Extended Temperature,
14LD SOIC package.
Tape and Reel,
Extended Temperature,
14LD TSSOP package.
DS22139B-page 43
MCP6561/1R/1U/2/4
NOTES:
DS22139B-page 44
 2009-2013 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash
and UNI/O are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MTP, SEEVAL and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
Analog-for-the-Digital Age, Application Maestro, BodyCom,
chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,
Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA
and Z-Scale are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
GestIC and ULPP are registered trademarks of Microchip
Technology Germany II GmbH & Co. & KG, a subsidiary of
Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2009-2013, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-62077-031-3
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
 2009-2013 Microchip Technology Inc.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS22139C-page 45
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Web Address:
www.microchip.com
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Japan - Osaka
Tel: 81-6-6152-7160
Fax: 81-6-6152-9310
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Cleveland
Independence, OH
Tel: 216-447-0464
Fax: 216-447-0643
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Santa Clara
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
China - Beijing
Tel: 86-10-8569-7000
Fax: 86-10-8528-2104
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
China - Hangzhou
Tel: 86-571-2819-3187
Fax: 86-571-2819-3189
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
China - Hong Kong SAR
Tel: 852-2943-5100
Fax: 852-2401-3431
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Taiwan - Hsin Chu
Tel: 886-3-5778-366
Fax: 886-3-5770-955
China - Shenzhen
Tel: 86-755-8864-2200
Fax: 86-755-8203-1760
Taiwan - Kaohsiung
Tel: 886-7-213-7828
Fax: 886-7-330-9305
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Taipei
Tel: 886-2-2508-8600
Fax: 886-2-2508-0102
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
DS22139C-page 46
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Japan - Tokyo
Tel: 81-3-6880- 3770
Fax: 81-3-6880-3771
11/29/12
 2009-2013 Microchip Technology Inc.