LINER LTC3736EUF-1 Dual 2-phase, no rsense synchronous controller with spread spectrum Datasheet

LTC3736-1
Dual 2-Phase, No RSENSETM,
Synchronous Controller with
Spread Spectrum
U
FEATURES
DESCRIPTIO
■
The LTC®3736-1 is a 2-phase dual synchronous stepdown switching regulator controller with tracking that
drives external complementary power MOSFETs using
few external components. The constant frequency current
mode architecture with MOSFET VDS sensing eliminates
the need for sense resistors and improves efficiency.
Power loss and noise due to the ESR of the input capacitance are minimized by operating the two controllers out
of phase.
■
■
■
■
■
■
■
■
■
■
■
■
■
Spread Spectrum Operation
Tracking Function
No Current Sense Resistors Required
Out-of-Phase Controllers Reduce Required
Input Capacitance
Wide VIN Range: 2.75V to 9.8V
Current Mode Operation
0.6V ±1.5% Voltage Reference
Low Dropout Operation: 100% Duty Cycle
Pulse Skipping Operation at Light Loads
Internal Soft-Start Circuitry
Power Good Output Voltage Monitor
Output Overvoltage Protection
Micropower Shutdown: IQ = 9µA
Tiny Low Profile (4mm × 4mm) QFN and Narrow
SSOP Packages
A unique spread spectrum architecture randomly varies
the LTC3736-1’s switching frequency from 450kHz to
580kHz, significantly reducing the peak radiated and conducted noise on both the input and output supplies,
making it easier to comply with electromagnetic interference (EMI) standards.
Pulse skipping operation provides high efficiency at light
loads. 100% duty cycle capability provides low dropout operation, extending operating time in battery-powered systems. The high switching frequencies allow for the use of
small surface mount inductors and capacitors.
U
APPLICATIO S
■
■
■
■
One or Two Lithium-Ion Powered Devices
Notebook and Palmtop Computers, PDAs
Portable Instruments
Distributed DC Power Systems
The LTC3736-1 is available in the low profile (0.75mm)
24-pin thermally enhanced (4mm × 4mm) QFN package
and 24-lead narrow SSOP packages.
, LTC and LT are registered trademarks of Linear Technology Corporation.
No RSENSE is a trademark of Linear Technology Corporation.
Protected by U.S. Patents including 5481178, 5929620, 6144194, 6580258, 6304066,
6611131, 6498466.
U
TYPICAL APPLICATIO
Output Voltage Frequency
Spectrum
Low Noise, 2-Phase, Dual Synchronous DC/DC Step-Down Converter
VIN
2.75V TO 9.8V
SENSE1+ SENSE2+
TG1
TG2
187k
+
47µF
2.2µH
SW1
SW2
LTC3736-1
BG1
VOUT1
2.5V
220pF
59k
BG2
PGND
PGND
VFB1
VFB2
ITH1
ITH2
SGND
15k
AMPLITUDE (dBm)
VIN
2.2µH
–10
10µF
×2
118k
–50
–60
–70
–80
–90
–100
+
220pF
15k
VOUT2
1.8V
FIGURE 13 CIRCUIT
SPREAD SPECTRUM
–20 VOUT = 2.5V
DISABLED
RBW = 30Hz
–30
SPREAD SPECTRUM
–40
ENABLED
47µF
59k
–110
410k
450k
490k
530k
FREQUENCY (Hz)
570k
610k
37361 TA01b
37361 TA01a
37361f
1
LTC3736-1
W W
W
AXI U
U
ABSOLUTE
RATI GS
(Note 1)
Input Supply Voltage (VIN) ........................ – 0.3V to 10V
FREQ, RUN/SS, SSDIS,
TRACK, SENSE1+, SENSE2+,
IPRG1, IPRG2 Voltages ................. – 0.3V to (VIN + 0.3V)
VFB1, VFB2, ITH1, ITH2 Voltages .................. – 0.3V to 2.4V
SW1, SW2 Voltages ............ –2V to VIN + 1V or 10V Max
PGOOD ..................................................... – 0.3V to 10V
TG1, TG2, BG1, BG2 Peak Output Current (<10µs) ..... 1A
Operating Temperature Range (Note 2) ... –40°C to 85°C
Storage Temperature Range .................. –65°C to 125°C
Junction Temperature (Note 3) ............................ 125°C
Lead Temperature (Soldering, 10 sec)
(LTC3736EGN-1) .................................................. 300°C
U
U
W
PACKAGE/ORDER I FOR ATIO
ORDER PART
NUMBER
BG1
PGND
SENSE1+
SW1
IPRG1
VFB1
TOP VIEW
LTC3736EUF-1
24 23 22 21 20 19
ITH1 1
18 SSDIS
IPRG2 2
17 TG1
FREQ 3
16 PGND
25
SGND 4
15 TG2
VIN 5
14 RUN/SS
TRACK 6
ITH2
PGOOD
SENSE2
PGND
9 10 11 12
+
8
SW2
7
VFB2
13 BG2
UF PART MARKING
3736-1
TOP VIEW
SW1
1
24 SENSE1+
IPRG1
2
23 PGND
VFB1
3
22 BG1
ITH1
4
21 SSDIS
IPRG2
5
20 TG1
FREQ
6
19 PGND
SGND
7
18 TG2
VIN
8
17 RUN/SS
TRACK
9
16 BG2
VFB2 10
15 PGND
ITH2 11
14 SENSE2+
PGOOD 12
UF PACKAGE
24-LEAD (4mm × 4mm) PLASTIC QFN
ORDER PART
NUMBER
LTC3736EGN-1
13 SW2
GN PACKAGE
24-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 37°C/W
EXPOSED PAD (PIN 25) IS PGND
MUST BE SOLDERED TO PCB
TJMAX = 125°C, θJA = 130°C/ W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications that apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VIN = 4.2V unless otherwise specified.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
500
9
3
850
20
10
µA
µA
µA
1.95
2.15
2.25
2.45
2.55
2.75
V
V
0.45
0.65
0.85
V
Main Control Loops
Input DC Supply Current
Normal Mode
Shutdown
UVLO
(Note 4)
Undervoltage Lockout Threshold
VIN Falling
VIN Rising
RUN/SS = 0V
VIN < UVLO Threshold
●
●
Shutdown Threshold at RUN/SS
Start-Up Current Source
RUN/SS = 0V
Regulated Feedback Voltage
0°C to 85°C (Note 5)
–40°C to 85°C
Output Voltage Line Regulation
2.75V < VIN < 9.8V (Note 5)
●
0.5
0.7
1
µA
0.591
0.588
0.6
0.6
0.609
0.612
V
V
0.05
0.2
mV/V
37361f
2
LTC3736-1
ELECTRICAL CHARACTERISTICS
The ● denotes specifications that apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VIN = 4.2V unless otherwise specified.
PARAMETER
CONDITIONS
Output Voltage Load Regulation
ITH = 0.9V (Note 5)
ITH = 1.7V
VFB1,2 Input Current
(Note 5)
TRACK Input Current
TRACK = 0.6V
Overvoltage Protect Threshold
Measured at VFB
MIN
0.66
Overvoltage Protect Hysteresis
TYP
MAX
UNITS
0.12
–0.12
0.5
–0.5
%
%
10
50
nA
10
50
nA
0.68
0.7
V
20
mV
Top Gate (TG) Drive 1, 2 Rise Time
CL = 3000pF
40
ns
Top Gate (TG) Drive 1, 2 Fall Time
CL = 3000pF
40
ns
Bottom Gate (BG) Drive 1, 2 Rise Time
CL = 3000pF
50
ns
Bottom Gate (BG) Drive 1, 2 Fall Time
CL = 3000pF
Maximum Current Sense Voltage
(SENSE+ – SW)(∆VSENSE(MAX))
IPRG = Floating (Note 6)
IPRG = 0V
IPRG = VIN
Soft-Start Time
Time for VFB1 to Ramp from 0.05V to 0.55V
40
●
●
●
ns
110
70
185
125
85
204
140
100
223
mV
mV
mV
0.667
0.833
1
ms
480
260
650
550
300
750
600
340
825
kHz
kHz
kHz
Spread Spectrum Oscillator
Oscillator Frequency
Spread Spectrum Frequency Range
Spread Spectrum Disabled (SSDIS = VIN)
VFREQ = Floating
VFREQ = 0V
VFREQ = VIN
●
●
●
SSDIS = GND
Minimum Switching Frequency
Maximum Switching Frequency
450
580
kHz
kHz
PGOOD Voltage Low
IPGOOD Sinking 1mA
125
mV
PGOOD Trip Level
VFB with Respect to Set Output Voltage
VFB < 0.6V, Ramping Positive
VFB < 0.6V, Ramping Negative
VFB > 0.6V, Ramping Negative
VFB > 0.6V, Ramping Positive
PGOOD Output
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: The LTC3736E-1 is guaranteed to meet specified performance
from 0°C to 70°C. Specifications over the –40°C to 85°C operating range
are assured by design, characterization and correlation with statistical
process controls.
Note 3: TJ is calculated from the ambient temperature TA and power
dissipation PD according to the following formula:
TJ = TA + (PD • θJA°C/W)
–13
–16
7
10
–10.0
–13.3
10.0
13.3
–7
–10
13
16
%
%
%
%
Note 4: Dynamic supply current is higher due to gate charge being
delivered at the switching frequency.
Note 5: The LTC3736-1 is tested in a feedback loop that servos ITH to a
specified voltage and measures the resultant VFB voltage.
Note 6: Peak current sense voltage is reduced dependent on duty cycle to
a percentage of value as shown in Figure 2.
37361f
3
LTC3736-1
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Efficiency and Power Lost vs
Load Current
10
Load Step
(Spread Spectrum Enabled)
Load Step
(Spread Spectrum Disabled)
100
FIGURE 13 CIRCUIT
VIN = 5V
95
90
1
85
80
0.1
75
70
VOUT
AC-COUPLED
100mV/DIV
EFFICIENCY (%)
POWER LOST (W)
TA = 25°C unless otherwise noted.
VOUT
AC-COUPLED
100mV/DIV
IL
2A/DIV
IL
2A/DIV
65
0.01
60
VIN = 3.3V
100µs/DIV
VOUT = 1.8V
ILOAD = 300mA TO 3A
SSDIS = GND
FIGURE 15 CIRCUIT
VOUT = 2.5V 55
VOUT = 1.8V
50
100
1000
10000
10
LOAD CURRENT (mA)
0.001
1
100µs/DIV
VIN = 3.3V
VOUT = 1.8V
ILOAD = 300mA TO 3A
SSDIS = VIN
FIGURE 15 CIRCUIT
37361 G02
37361 G03
37361 G01
Input Voltage Noise
(Spread Spectrum Disabled)
–10
FIGURE 13 CIRCUIT
–20 VIN = 5V
= 2.5V
V
–30 ROUT= 30Hz
BW
–40 SSDIS = VIN
AMPLITUDE (dBm)
AMPLITUDE (dBm)
–10
–50
–60
–70
–80
FIGURE 13 CIRCUIT
–20 VIN = 5V
= 2.5V
V
–30 ROUT= 30Hz
BW
–40 SSDIS = GND
VOUT1
2.5V
VOUT2
1.8V
–50
500mV/
DIV
–60
–70
–80
–90
–90
–100
–100
–110
410k
450k
Tracking Start-Up with Internal
Soft-Start (CSS = 0µF)
Input Voltage Noise
(Spread Spectrum Enabled)
490k
530k
FREQUENCY (Hz)
570k
610k
–110
410k
450k
490k
530k
FREQUENCY (Hz)
570k
Oscillator Frequency
vs Input Voltage
Output Voltage Ripple
VOUT1
2.5V
VOUT2
1.8V
SSDIS = VIN
CONSTANT
550kHz
OPERATION
500mV/
DIV
50mV/DIV
AC-COUPLED
SSDIS = GND
SPREAD
SPECTRUM
37361 G07
1µs/DIV
FIGURE 15 CIRCUIT
ENVELOPE OF 100 SAMPLES
37361 G20
NORMALIZED FREQUENCY SHIFT (%)
5
40ms/DIV
VIN = 5V
RLOAD1 = RLOAD2 = 1Ω
SSDIS = VIN
FIGURE 15 CIRCUIT
37361 G06
37361 G05
37361 G04
Tracking Start-Up with External
Soft-Start (CSS = 0.15µF)
610k
VIN = 5V
200µs/DIV
RLOAD1 = RLOAD2 = 1Ω
SSDIS = GND
FIGURE 15 CIRCUIT
4
SSDIS = VIN
3
2
1
0
–1
–2
–3
–4
–5
2
3
4
8
6
5
7
INPUT VOLTAGE (V)
9
10
37361 G08
37361f
4
LTC3736-1
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Efficiency and Power Lost vs
Load Current
10
100
Efficiency vs Load Current
100
FIGURE 13 CIRCUIT
VOUT = 2.5V
POWER LOST (W)
20
0.1
75
70
VIN = 5V
60
VIN = 3.3V
VIN = 4.2V 55
VIN = 7.2V
50
10
100
1000
10000
LOAD CURRENT (mA)
0.001
2
1
1.5
ITH VOLTAGE (V)
1
1.0
0.607
0.9
55
1
0.599
0.597
0.7
0.6
0.5
0.4
0.3
0.595
0.2
0.593
0.1
0
–60 –40 –20 0 20 40 60
TEMPERATURE (°C)
100
80
10
NORMALIZED FREQUENCY (%)
8
125
120
100
37361 G14
0.7
0.6
0.5
0.4
–60 –40 –20 0
20 40 60
TEMPERATURE (°C)
100
37361 G13
2.50
SSDIS = VIN
2.45
6
4
2
0
–2
–4
–6
–10
–60 –40 –20 0 20 40 60
TEMPERATURE (°C)
100
80
Undervoltage Lockout Threshold
vs Temperature
VIN RISING
2.40
2.35
2.30
VIN FALLING
2.25
2.20
2.15
–8
80
0.8
Oscillator Frequency
vs Temperature
IPRG = FLOAT
130
80
0.9
37361 G12
Maximum Current Sense Threshold
vs Temperature
10000
RUN/SS Pull-Up Current
vs Temperature
INPUT (VIN) VOLTAGE (V)
0.601
10
100
1000
LOAD CURRENT (mA)
37361 G19
0.8
0.605
0.603
SPREAD SPECTRUM
CONSTANT 550kHz
50
1.0
37361 G11
MAXIMUM CURRENT SENSE THRESHOLD (mV)
60
RUN/SS PULL-UP CURRENT (µA)
0.609
115
–60 –40 –20 0
20 40 60
TEMPERATURE (°C)
70
Shutdown (RUN) Threshold
vs Temperature
RUN/SS VOLTAGE (V)
FEEDBACK VOLTAGE (V)
Regulated Feedback Voltage
vs Temperature
135
75
37361 G10
37361 G09
0.591
20 40 60
–60 –40 –20 0
TEMPERATURE (°C)
80
65
65
0.01
0.5
85
80
0
–20
85
EFFICIENCY (%)
CURRENT LIMIT (%)
1
40
90
FIGURE 13 CIRCUIT
95 VOUT = 2.5V
VIN = 5V
90
95
80
60
100
EFFICIENCY (%)
Maximum Current Sense Voltage
vs ITH Pin Voltage
TA = 25°C unless otherwise noted.
80
100
37361 G15
2.10
20 40 60
–60 –40 –20 0
TEMPERATURE (°C)
80
100
37361 G16
37361f
5
LTC3736-1
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Shutdown Quiescent Current
vs Input Voltage
SHUTDOWN CURRENT (µA)
RUN/SS Start-Up Current
vs Input Voltage
0.9
RUN/SS = 0V
RUN/SS PIN PULL-UP CURRENT (µA)
20
18
16
14
12
10
8
6
4
2
0
2
3
4
8
6
5
7
INPUT VOLTAGE (V)
9
10
37361 G17
U
U
U
PI FU CTIO S
TA = 25°C unless otherwise noted.
RUN/SS = 0V
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
2
3
4
6
7
5
8
INPUT VOLTAGE (V)
9
10
37361 G18
(UF/GN Package)
ITH1/ITH2 (Pins 1, 8/Pins 4, 11): Current Threshold and
Error Amplifier Compensation Point. Nominal operating
range on these pins is from 0.7V to 2V. The voltage on
these pins determines the threshold of the main current
comparator.
FREQ (Pin 3/Pin 6): Frequency Filter and Adjust Pin. Normally, when spread spectrum operation is enabled (SSDIS
= GND), a capacitor (1nF to 4.7nF) is connected from this
pin to SGND or VIN to filter and smooth the changes in frequency of the LTC3736-1’s internal oscillator.
When spread spectrum operation is disabled (SSDIS = VIN),
this pin serves as a frequency adjust pin. In this mode, tying
this pin to GND selects 300kHz operation; tying this pin to
VIN selects 750kHz operation; floating this pin selects
550kHz operation.
When spread spectrum operation is enabled (SSDIS =
GND), an external voltage between approximately 0.7V and
1.5V may be applied to this pin to adjust (in an analog
manner) the LTC3736-1’s frequency.
SGND (Pin 4/Pin 7): Small-Signal Ground. This pin serves
as the ground connection for most internal circuits.
VIN (Pin 5/Pin 8): Chip Signal Power Supply. This pin
powers the entire chip except for the gate drivers. Externally
filtering this pin with a lowpass RC network (e.g.,
R = 10Ω, C = 1µF) is suggested to minimize noise pickup,
especially in high load current applications.
TRACK (Pin 6/Pin 9): Tracking Input for Second Controller. Allows the start-up of VOUT2 to “track” that of VOUT1
according to a ratio established by a resistor divider on
VOUT1 connected to the TRACK pin. For one-to-one tracking of VOUT1 and VOUT2 during start-up, a resistor divider
with a ratio equal to those connected to VFB2 from VOUT2
should be used to connect to TRACK from VOUT1.
PGOOD(Pin 9/Pin 12): Power Good Output Voltage Monitor Open-Drain Logic Output. This pin is pulled to ground
when the voltage on either feedback pin (VFB1, VFB2) is not
within ±13.3% of its nominal set point.
PGND (Pins 12, 16, 20, 25/Pins 15, 19, 23): Power Ground.
These pins serve as the ground connection for the gate
drivers and the negative input to the reverse current comparators. The Exposed Pad (UF package) must be soldered
to PCB ground.
RUN/SS (Pin 14/Pin 17): Run Control Input and Optional
External Soft-Start Input. Forcing this pin below 0.65V shuts
down the chip (both channels). Driving this pin to VIN or
releasing this pin enables the chip, using the chip’s internal soft-start. An external soft-start can be programmed by
connecting a capacitor between this pin and ground.
37361f
6
LTC3736-1
U
U
U
PI FU CTIO S
(UF/GN Package)
TG1/TG2 (Pins 17, 15/Pins 20, 18): Top (PMOS) Gate Drive
Output. These pins drive the gates of the external P-channel
MOSFETs. These pins have an output swing from PGND to
SENSE+.
SW1/SW2 (Pins 22, 10/Pins 1, 13): Switch Node Connection to Inductor. Also the negative input to differential peak
current comparator and an input to the reverse current
comparator. Normally connected to the drain of the external P-channel MOSFETs, the drain of the external N-channel
MOSFET and the inductor.
SSDIS (Pin 18/Pin 21): Spread Spectrum Disable Input. Tie
this pin to VIN to disable spread spectrum operation. In this
mode, the LTC3736-1 operates at a constant frequency
determined by the voltage on the FREQ pin. Tie this pin to
GND to enable spread spectrum operation.
IPRG1/IPRG2 (Pins 23, 2/Pins 2, 5): Three-State Pins to
Select Maximum Peak Sense Voltage Threshold. These pins
select the maximum allowed voltage drop between the
SENSE+ and SW pins (i.e., the maximum allowed drop
across the external P-channel MOSFET) for each channel.
Tie to VIN, GND or float to select 204mV, 85mV or 125mV
respectively.
BG1/BG2 (Pins 19, 13/Pins 22, 16): Bottom (NMOS) Gate
Drive Output. These pins drive the gates of the external Nchannel MOSFETs. These pins have an output swing from
PGND to SENSE+.
VFB1/VFB2 (Pins 24, 7/Pins 3, 10): Feedback Pins. Receives
the remotely sensed feedback voltage for its controller from
an external resistor divider across the output.
SENSE1+/SENSE2+ (Pins 21, 11/Pins 24, 14): Positive
Input to Differential Current Comparator. Also powers the
gate drivers. Normally connected to the source of the external P-channel MOSFET.
Exposed Pad (Pin 25/NA): The exposed pad (UF Package)
must be soldered to the PCB ground.
W
FU CTIO AL DIAGRA (Common Circuitry)
U
RVIN
VIN
UNDERVOLTAGE
LOCKOUT
CVIN
VOLTAGE
REFERENCE
VIN
(TO CONTROLLER 1, 2)
0.6V
VREF
0.7µA
SHDN
RUN/SS
EXTSS
+
tSEC = 1ms
INTSS
–
SSDIS
FREQ
SPREAD
SPECTRUM
OSCILLATOR
CLK1
CLK2
SLOPE1
SLOPE
COMP
VFB1
SLOPE2
–
UV1
+
SHDN
0.54V
IPRG1
IPRG2
PGOOD
OV1
VOLTAGE
MAXIMUM
CONTROLLED
SENSE VOLTAGE
OSCILLATOR
SELECT
IPROG1
+
UV2
IPROG2
VFB2
OV2
37361 FD
–
37361f
7
U
LTC3736-1
W
FU CTIO AL DIAGRA
U
(Controller 1)
U
VIN
SENSE1
+
CIN
RS1
CLK1
S
TG1
MP1
Q
R
SWITCHING
LOGIC
AND
BLANKING
CIRCUIT
OV1
SC1
PGND
SW1
ANTISHOOT
THROUGH
L1
VOUT1
SENSE1+
COUT1
BG1
MN1
PGND
SKIP1
IREV1
SLOPE1
SW1
–
ICMP
SENSE1+
+
IPROG1
SHDN
–
+
VFB1
R1B
EAMP
+
R1A
–
0.6V
ITH1
EXTSS
INTSS
–
RITH1
SKIP1
+
0.12V
–
VFB1
–
PGND
+
SC1
0.15V
OV1
–
VFB1
+
0.68V
OVP
IREV1
CITH1
SCP
RICMP
+
SW1
37361 CONT1
IPROG1
37361f
8
LTC3736-1
W
FU CTIO AL DIAGRA
U
(Controller 2)
SENSE2+
RS2
CLK2
S
VIN
TG2
MP2
Q
R
SWITCHING
LOGIC
AND
BLANKING
CIRCUIT
OV2
SC2
PGND
SW2
ANTISHOOT
THROUGH
L2
VOUT2
SENSE2+
COUT2
BG2
MN2
PGND
SKIP2
IREV2
SLOPE2
SW2
–
ICMP
SENSE2+
+
SHDN
–
+
R2B
VFB2
EAMP
+
R2A
VOUT1
–
TRACK
RTRACKB
0.6V
RTRACKA
ITH2
–
RITH2
SKIP2
+
SC2
+
0.12V
–
VFB2
–
PGND
CITH2
SCP
0.15V
TRACK
–
OV2
VFB2
IREV2
OVP
+
+
0.68V
SW2
37361 CONT2
IPROG2
37361f
9
U
LTC3736-1
U
OPERATIO
(Refer to Functional Diagram)
Main Control Loop
The LTC3736-1 uses a current mode architecture with the
two controllers operating 180 degrees out of phase.
During normal operation, the top external P-channel power
MOSFET is turned on when the clock for that channel sets
the RS latch, and turned off when the current comparator
(ICMP) resets the latch. The peak inductor current at which
ICMP resets the RS latch is determined by the voltage on
the ITH pin, which is driven by the output of the error
amplifier (EAMP). The VFB pin receives the output voltage
feedback signal from an external resistor divider. This
feedback signal is compared to the internal 0.6V reference
voltage by the EAMP. When the load current increases, it
causes a slight decrease in VFB relative to the 0.6V reference, which in turn causes the ITH voltage to increase until
the average inductor current matches the new load current. While the top P-channel MOSFET is off, the bottom
N-channel MOSFET is turned on until either the inductor
current starts to reverse, as indicated by the current
reversal comparator, IRCMP, or the beginning of the next
cycle.
Shutdown, Soft-Start and Tracking Start-Up
(RUN/SS and TRACK Pins)
The LTC3736-1 is shut down by pulling the RUN/SS pin
low. In shutdown, all controller functions are disabled and
the chip draws only 9µA. The TG outputs are held high (off)
and the BG outputs low (off) in shutdown. Releasing
RUN/SS allows an internal 0.7µA current source to charge
up the RUN/SS pin. When the RUN/SS pin reaches 0.65V,
the LTC3736-1’s two controllers are enabled.
The start-up of VOUT1 is controlled by the LTC3736-1’s
internal soft-start. During soft-start, the error amplifier
EAMP compares the feedback signal VFB1 to the internal
soft-start ramp (instead of the 0.6V reference), which rises
linearly from 0V to 0.6V in about 1ms. This allows the
output voltage to rise smoothly from 0V to its final value,
while maintaining control of the inductor current.
The 1ms soft-start time can be increased by connecting
the optional external soft-start capacitor CSS between the
RUN/SS and SGND pins. As the RUN/SS pin continues to
rise linearly from approximately 0.65V to 1.3V (being
charged by the internal 0.7µA current source), the EAMP
regulates the VFB1 proportionally linearly from 0V to 0.6V.
The start-up of VOUT2 is controlled by the voltage on the
TRACK pin. When the voltage on the TRACK pin is less
than the 0.6V internal reference, the LTC3736-1 regulates
the VFB2 voltage to the TRACK pin instead of the 0.6V
reference. Typically, a resistor divider on VOUT1 is connected to the TRACK pin to allow the start-up of VOUT2 to
“track” that of VOUT1. For one-to-one tracking during startup, the resistor divider would have the same ratio as the
divider on VOUT2 that is connected to VFB2.
Light Load Operation
The LTC3736-1 operates in PWM pulse skipping mode at
light loads. In this mode, the current comparator ICMP may
remain tripped for several cycles and force the external Pchannel MOSFET to stay off for the same number of cycles.
The inductor current is not allowed to reverse (discontinuous operation). This mode exhibits low output ripple as
well as low audio noise and reduced RF interference, while
providing high light load efficiency.
Spread Spectrum Operation
Switching regulators can be particularily troublesome in
applications where electromagnetic interference (EMI) is
a concern. Switching regulators operate on a cycle-bycycle basis to transfer power to an output. In most cases,
the frequency of operation is either fixed or is a constant
based on the output load. This method of conversion
creates large components of noise at the frequency of
operation (fundamental) and multiples of the operating
frequency (harmonics). Figures 1a and 1b depict the
output noise spectrum of a conventional buck switching
converter (1/2 of LTC3736-1 with spread spectrum operation disabled) with VIN = 5V, VOUT = 2.5V and IOUT = 2A.
Unlike conventional buck converters, the LTC3736-1’s
internal oscillator is designed to produce a clock pulse
whose frequency is randomly varied between 450kHz and
580kHz. This has the benefit of spreading the switching
noise over a range of frequencies, thus significantly reducing the peak noise. Figures 1c and 1d show the output
noise spectrum of the LTC3736-1 (with spread spectrum
37361f
10
LTC3736-1
U
OPERATIO
(Refer to Functional Diagram)
operation enabled) with VIN = 5V, VOUT = 2.5V and IOUT =
1A. Note the significant reduction in peak output noise
(>20dBm).
Short-Circuit Protection
When an output is shorted to ground (VFB < 0.12V), the
switching frequency of that controller is reduced to 1/5 of
the normal operating frequency. The other controller is
unaffected and maintains normal operation.
The short-circuit threshold on VFB2 is based on the smaller
of 0.12V and a fraction of the voltage on the TRACK pin.
This also allows VOUT2 to start up and track VOUT1 more
easily. Note that if V OUT1 is truly short-circuited
(VOUT1 = VFB1 = 0V), then the LTC3736-1 will try to
regulate VOUT2 to 0V if a resistor divider on VOUT1 is
connected to the TRACK pin.
–10
As a further protection, the overvoltage comparator (OV)
guards against transient overshoots, as well as other more
serious conditions that may overvoltage the output. When
the feedback voltage on the VFB pin has risen 13.33%
above the reference voltage of 0.6V, the external P-channel MOSFET is turned off and the N-channel MOSFET is
turned on until the overvoltage is cleared.
Frequency Selection (FREQ Pin)
(Spread Spectrum Operation Disabled)
The switching frequency of the LTC3736-1 can be selected
using the FREQ pin when spread spectrum operation is
disabled (SSDIS = VIN).
–10
RBW = 3kHz
–20
–20
–30
–30
–40
–40
AMPLITUDE (dBm)
AMPLITUDE (dBm)
Output Overvoltage Protection
–50
–60
–70
–80
–50
–60
–70
–80
–90
–90
–100
–100
–110
0
6M
12M
18M
FREQUENCY (Hz)
24M
30M
RBW = 30Hz
–110
410k
450k
490k
530k
FREQUENCY (Hz)
570k
37361 F01b
37361 F01a
Figure 1a. Output Noise Spectrum of Conventional Buck
Switching Converter (LTC3736-1 with Spread Spectrum
Disabled) Showing Fundamental and Harmonic Frequencies
–10
–10
–20
–30
–30
–40
–40
AMPLITUDE (dBm)
AMPLITUDE (dBm)
Figure 1b. Zoom-In of Fundamental Frequency of Conventional
Buck Switching Converter
RBW = 3kHz
–20
–50
–60
–70
–80
–60
–70
–80
–90
–90
–100
0
6M
12M
18M
FREQUENCY (Hz)
24M
30M
37361 F01c
Figure 1c. Output Noise Spectrum of the LTC3736-1 Spread
Spectrum Buck Switching Converter. Note the Reduction in
Fundamental and Harmonic Peak Spectral Amplitude
Compared to Figure 1a.
RBW = 30Hz
–50
–100
–110
610k
–110
410k
450k
490k
530k
FREQUENCY (Hz)
570k
610k
37361 F01d
Figure 1d. Zoom-In of Fundamental Frequency of the
LTC3736-1 Spread Spectrum Switching Converter. Note the
>20dB Reduction in Peak Amplitude and Spreading of the
Frequency Spectrum (Between Approximately 450kHz and
580kHz) Compared to Figure 1b.
37361f
11
(Refer to Functional Diagram)
The FREQ pin can be floated, tied to VIN or tied to SGND to
select 550kHz, 750kHz or 300kHz respectively.
The selection of switching frequency is a tradeoff between
efficiency and component size. Low frequency operation
increases efficiency by reducing MOSFET switching losses,
but requires larger inductance and/or capacitance to maintain low output ripple voltage.
Dropout Operation
When the input supply voltage (VIN) decreases towards
the output voltage, the rate of change of the inductor
current while the external P-channel MOSFET is on (ON
cycle) decreases. This reduction means that the P-channel
MOSFET will remain on for more than one oscillator cycle
if the inductor current has not ramped up to the threshold
set by the EAMP on the ITH pin. Further reduction in the
input supply voltage will eventually cause the P-channel
MOSFET to be turned on 100%; i.e., DC. The output
voltage will then be determined by the input voltage minus
the voltage drop across the P-channel MOSFET and the
inductor.
maximum sense voltage allowed across the external
P-channel MOSFET is 125mV, 85mV or 204mV for the
three respective states of the IPRG pin. The peak sense
voltages for the two controllers can be independently
selected by the IPRG1 and IPRG2 pins.
However, once the controller’s duty cycle exceeds 20%,
slope compensation begins and effectively reduces the
peak sense voltage by a scale factor given by the curve in
Figure 2.
110
100
90
80
SF = I/IMAX (%)
LTC3736-1
U
OPERATIO
70
60
50
40
30
20
10
0
0
10 20 30 40 50 60 70 80 90 100
DUTY CYCLE (%)
37361 F02
Undervoltage Lockout
To prevent operation of the external MOSFETs below safe
input voltage levels, an undervoltage lockout is incorporated
in the LTC3736-1. When the input supply voltage (VIN)
drops below 2.3V, the external P- and N-channel MOSFETs
and all internal circuitry are turned off except for the undervoltage block, which draws only a few microamperes.
Peak Current Sense Voltage Selection and Slope
Compensation (IPRG1 and IPRG2 Pins)
When a controller is operating below 20% duty cycle, the
peak current sense voltage (between the SENSE+ and SW
pins) allowed across the external P-channel MOSFET is
determined by:
∆VSENSE(MAX) =
A( VITH – 0.7 V )
10
where A is a constant determined by the state of the IPRG
pins. Floating the IPRG pin selects A = 1; tying IPRG to VIN
selects A = 5/3; tying IPRG to SGND selects A = 2/3. The
maximum value of VITH is typically about 1.98V, so the
Figure 2. Maximum Peak Current vs Duty Cycle
The peak inductor current is determined by the peak sense
voltage and the on-resistance of the external P-channel
MOSFET:
IPK =
∆VSENSE(MAX)
RDS(ON)
Power Good (PGOOD) Pin
A window comparator monitors both feedback voltages
and the open-drain PGOOD output pin is pulled low when
either or both feedback voltages are not within ±10% of
the 0.6V reference voltage. PGOOD is low when the
LTC3736-1 is shut down or in undervoltage lockout.
2-Phase Operation
Why the need for 2-phase operation? Until recently, constant frequency dual switching regulators operated both
controllers in phase (i.e., single phase operation). This
means that both topside MOSFETs (P-channel) are turned
37361f
12
LTC3736-1
U
OPERATIO
(Refer to Functional Diagram)
on at the same time, causing current pulses of up to twice
the amplitude of those from a single regulator to be drawn
from the input capacitor. These large amplitude pulses
increase the total RMS current flowing in the input capacitor, requiring the use of larger and more expensive input
capacitors, and increase both EMI and power losses in the
input capacitor and input power supply.
With 2-phase operation, the two controllers of the
LTC3736-1 are operated 180 degrees out of phase. This
effectively interleaves the current pulses coming from the
topside MOSFET switches, greatly reducing the time where
they overlap and add together. The result is a significant
reduction in the total RMS current, which in turn allows the
use of smaller, less expensive input capacitors, reduces
shielding requirements for EMI and improves real world
operating efficiency.
Figure 3 shows qualitatively example waveforms for a
single phase dual controller versus a 2-phase LTC3736-1
system. In this case, 2.5V and 1.8V outputs, each drawing
a load current of 2A, are derived from a 7V (e.g., a 2-cell
Li-Ion battery) input supply. In this example, 2-phase
Single Phase
Dual Controller
operation would reduce the RMS input capacitor current
from 1.79ARMS to 0.91ARMS. While this is an impressive
reduction by itself, remember that power losses are proportional to IRMS2, meaning that actual power wasted is
reduced by a factor of 3.86.
The reduced input ripple current also means that less
power is lost in the input power path, which could include
batteries, switches, trace/connector resistances, and protection circuitry. Improvements in both conducted and
radiated EMI also directly accrue as a result of the reduced
RMS input current and voltage. Significant cost and board
footprint savings are also realized by being able to use
smaller, less expensive, lower RMS current-rated input
capacitors.
Of course, the improvement afforded by 2-phase operation is a function of the relative duty cycles of the two
controllers, which in turn are dependent upon the input
supply voltage. Figure 4 depicts how the RMS input
current varies for single phase and 2-phase dual controllers with 2.5V and 1.8V outputs over a wide input voltage
range.
It can be readily seen that the advantages of 2-phase
operation are not limited to a narrow operating range, but
in fact extend over a wide region. A good rule of thumb for
most applications is that 2-phase operation will reduce the
input capacitor requirement to that for just one channel
operating at maximum current and 50% duty cycle.
2-Phase
Dual Controller
SW1 (V)
SW2 (V)
2.0
INPUT CAPACITOR RMS CURRENT
1.8
IL1
IL2
SINGLE PHASE
DUAL CONTROLLER
1.6
1.4
2-PHASE
DUAL CONTROLLER
1.2
1.0
0.8
0.6
0.4
VOUT1 = 2.5V/2A
VOUT2 = 1.8V/2A
0.2
0
IIN
2
37361 F03
3
4
8
6
5
7
INPUT VOLTAGE (V)
9
10
37361 F04
Figure 4. RMS Input Current Comparison
Figure 3. Example Waveforms for a Single Phase
Dual Controller vs the 2-Phase LTC3736-1
37361f
13
LTC3736-1
U
W
U U
APPLICATIO S I FOR ATIO
The typical LTC3736-1 application circuit is shown in
Figure 13. External component selection for each of the
LTC3736-1’s controllers is driven by the load requirement
and begins with the selection of the inductor (L) and the
power MOSFETs (MP and MN).
Power MOSFET Selection
Each of the LTC3736-1’s two controllers requires two
external power MOSFETs: a P-channel MOSFET for the
topside (main) switch and an N-channel MOSFET for the
bottom (synchronous) switch. Important parameters for
the power MOSFETs are the breakdown voltage VBR(DSS),
threshold voltage VGS(TH), on-resistance RDS(ON), reverse
transfer capacitance CRSS, turn-off delay tD(OFF) and the
total gate charge QG.
The gate drive voltage is the input supply voltage. Since the
LTC3736-1 is designed for operation down to low input
voltages, a sublogic level MOSFET (RDS(ON) guaranteed at
VGS = 2.5V) is required for applications that work close to
this voltage. When these MOSFETs are used, make sure
that the input supply to the LTC3736-1 is less than the
absolute maximum MOSFET V GS rating, which is
typically 8V.
The P-channel MOSFET’s on-resistance is chosen based
on the required load current. The maximum average
output load current IOUT(MAX) is equal to the peak inductor
current minus half the peak-to-peak ripple current IRIPPLE.
The LTC3736-1’s current comparator monitors the drainto-source voltage VDS of the P-channel MOSFET, which is
sensed between the SENSE+ and SW pins. The peak
inductor current is limited by the current threshold, set by
the voltage on the ITH pin of the current comparator. The
voltage on the ITH pin is internally clamped, which limits
the maximum current sense threshold ∆VSENSE(MAX) to
approximately 125mV when IPRG is floating (85mV when
IPRG is tied low; 204mV when IPRG is tied high).
The output current that the LTC3736-1 can provide is
given by:
IOUT(MAX) =
∆VSENSE(MAX) IRIPPLE
–
RDS(ON)
2
A reasonable starting point is setting ripple current IRIPPLE
to be 40% of IOUT(MAX). Rearranging the above equation
yields:
RDS(ON)(MAX) =
5 ∆VSENSE(MAX)
•
6
IOUT(MAX)
for Duty Cycle < 20%.
However, for operation above 20% duty cycle, slope
compensation has to be taken into consideration to select
the appropriate value of RDS(ON) to provide the required
amount of load current:
RDS(ON)(MAX) =
∆VSENSE(MAX)
5
• SF •
6
IOUT(MAX)
where SF is a scale factor whose value is obtained from the
curve in Figure 1.
These must be further derated to take into account the
significant variation in on-resistance with temperature.
The following equation is a good guide for determining the
required RDS(ON)MAX at 25°C (manufacturer’s specification), allowing some margin for variations in the
LTC3736-1 and external component values:
RDS(ON)(MAX) =
∆VSENSE(MAX)
5
• 0.9 • SF •
6
IOUT(MAX) • ρT
The ρT is a normalizing term accounting for the temperature variation in on-resistance, which is typically about
0.4%/°C, as shown in Figure 5. Junction to case temperature TJC is about 10°C in most applications. For a maximum ambient temperature of 70°C, using ρ80°C ~ 1.3 in
the above equation is a reasonable choice.
The power dissipated in the top and bottom MOSFETs
strongly depends on their respective duty cycles and load
current. When the LTC3736-1 is operating in continuous
mode, the duty cycles for the MOSFETs are:
VOUT
VIN
V –V
BottomN− ChannelDuty Cycle = IN OUT
VIN
Top P − ChannelDuty Cycle =
37361f
14
LTC3736-1
U
W
U U
APPLICATIO S I FOR ATIO
less than 25nC to 30nC (at 4.5VGS) and a turn-off delay
(tD(OFF)) of less than approximately 140ns. However, due
to differences in test and specification methods of various
MOSFET manufacturers, and in the variations in QG and
tD(OFF) with gate drive (VIN) voltage, the P-channel MOSFET
ultimately should be evaluated in the actual LTC3736-1
application circuit to ensure proper operation.
ρT NORMALIZED ON RESISTANCE
2.0
1.5
1.0
0.5
0
– 50
50
100
0
JUNCTION TEMPERATURE (°C)
150
37361 F05
Figure 5. RDS(ON) vs Temperature
The MOSFET power dissipations at maximum output
current are:
PTOP
V
= OUT • IOUT (MAX)2 • ρT • RDS(ON) + 2 • VIN2
VIN
• IOUT (MAX) • C RSS • fOSC
PBOT =
VIN – VOUT
• IOUT (MAX)2 • ρT • RDS(ON)
VIN
Both MOSFETs have I2R losses and the PTOP equation
includes an additional term for transition losses, which are
largest at high input voltages. The bottom MOSFET losses
are greatest at high input voltage or during a short circuit
when the bottom duty cycle is nearly 100%.
The LTC3736-1 utilizes a nonoverlapping, antishootthrough gate drive control scheme to ensure that the Pand N-channel MOSFETs are not turned on at the same
time. To function properly, the control scheme requires
that the MOSFETs used are intended for DC/DC switching
applications. Many power MOSFETs, particularly P-channel MOSFETs, are intended to be used as static switches
and therefore are slow to turn on or off.
Reasonable starting criteria for selecting the P-channel
MOSFET are that it must typically have a gate charge (QG)
Shoot-through between the P-channel and N-channel
MOSFETs can most easily be spotted by monitoring the
input supply current. As the input supply voltage increases, if the input supply current increases dramatically,
then the likely cause is shoot-through. Note that some
MOSFETs that do not work well at high input voltages (e.g.,
VIN > 5V) may work fine at lower voltages (e.g., 3.3V).
Table 1 shows a selection of P-channel MOSFETs from
different manufacturers that are known to work well in
LTC3736-1 applications.
Selecting the N-channel MOSFET is typically easier, since
for a given RDS(ON), the gate charge and turn-on and turnoff delays are much smaller than for a P-channel MOSFET.
Table 1. Selected P-Channel MOSFETs Suitable for LTC3736-1
Applications
PART
NUMBER
MANUFACTURER
TYPE
PACKAGE
Si7540DP
Siliconix
Complementary
P/N
PowerPak
SO-8
Si9801DY
Siliconix
Complementary
P/N
SO-8
FDW2520C
Fairchild
Complementary
P/N
TSSOP-8
FDW2521C
Fairchild
Complementary
P/N
TSSOP-8
Si3447BDV
Siliconix
Single P
TSOP-6
Si9803DY
Siliconix
Single P
SO-8
FDC602P
Fairchild
Single P
TSOP-6
FDC606P
Fairchild
Single P
TSOP-6
FDC638P
Fairchild
Single P
TSOP-6
FDW2502P
Fairchild
Dual P
TSSOP-8
FDS6875
Fairchild
Dual P
SO-8
HAT1054R
Hitachi
Dual P
SO-8
On Semi
Dual P
SO-8
NTMD6P02R2-D
37361f
15
LTC3736-1
U
W
U U
APPLICATIO S I FOR ATIO
Operating Frequency
Inductor Value Calculation
When spread spectrum operation is enabled (SSDIS =
GND), the frequency of the LTC3736-1 is randomly varied
over the range of frequencies between 450kHz and 580kHz.
In this case, a capacitor (1nF to 4.7nF) should be connected
between the FREQ pin and SGND (or VIN) to smooth out the
changes in frequency. This not only provides a smoother
frequency spectrum but also ensures that the switching
regulator remains stable by preventing abrupt changes
in frequency. A value of 2200pF is suitable in most
applications.
Given the desired input and output voltages, the inductor
value and operating frequency fOSC directly determine the
inductor’s peak-to-peak ripple current:
When the spread spectrum operation is disabled (SSDIS =
VIN), the LTC3736-1’s frequency may be selected from
among three discrete, constant frequencies using the FREQ
pin. Floating the FREQ pin selects 550kHz operation; tying
this pin to VIN selects 750kHz, while tying this pin to GND
selects 300kHz. Table 2 summarizes the different states in
which the FREQ pin can be used.
IRIPPLE =
VOUT ⎛ VIN – VOUT ⎞
⎜
⎟
VIN ⎝ fOSC • L ⎠
Lower ripple current reduces core losses in the inductor,
ESR losses in the output capacitors, and output voltage
ripple. Thus, highest efficiency operation is obtained at
low frequency with a small ripple current. Achieving this,
however, requires a large inductor.
A reasonable starting point is to choose a ripple current
that is about 40% of IOUT(MAX). Note that the largest ripple
current occurs at the highest input voltage. To guarantee
that ripple current does not exceed a specified maximum,
the inductor should be chosen according to:
Table 2
FREQ PIN
SSDIS PIN
FREQUENCY
0V
VIN
300kHz
Floating
VIN
550kHz
L≥
Inductor Core Selection
VIN
VIN
750kHz
Capacitor to GND
or VIN
GND
Spread Spectrum (450kHz to 580kHz)
Note that when spread spectrum operation is disabled, the
LTC3736-1 operates like the standard, constant frequency
LTC3736, except that at light loads, the LTC3736-1 operates in pulse skipping mode. This mode is not available on
the LTC3736 unless the device is synchronized to an external clock signal using its phase-locked loop (PLL). Thus,
if an LTC3736 with pulse skipping function is needed, then
the LTC3736-1 with spread spectrum disabled is the appropriate solution. Table 3 summarizes the key differences in
the available features on the LTC3736 and LTC3736-1.
Table 3
AVAILABLE FEATURES/OPTIONS
LTC3736
LTC3736-1
Selectable Constant Frequency
Yes
Yes
Spread Spectrum
No
Yes
Synchronizable (PLL)
Yes
No
®
Yes
No
Forced Continuous Mode
Yes
No
When Synchronized
Yes
Burst Mode
Pulse Skipping Mode
VIN – VOUT VOUT
•
fOSC • IRIPPLE VIN
Once the inductance value is determined, the type of
inductor must be selected. High efficiency converters
generally cannot afford the core loss found in low cost
powdered iron cores, forcing the use of ferrite, molypermalloy or Kool Mµ® cores. Actual core loss is independent
of core size for a fixed inductor value, but it is very
dependent on inductance selected. As inductance increases, core losses go down. Unfortunately, increased
inductance requires more turns of wire and therefore
copper losses will increase.
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can
concentrate on copper loss and preventing saturation.
Ferrite core material saturates “hard,” which means that
inductance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in
inductor ripple current and consequent output voltage
ripple. Do not allow the core to saturate!
Burst Mode is a registered trademark of Linear Technology Corporation.
Kool Mµ is a registered trademark of Magnetics, Inc.
37361f
16
LTC3736-1
U
W
U U
APPLICATIO S I FOR ATIO
Molypermalloy (from Magnetics, Inc.) is a very good, low
loss core material for toroids, but it is more expensive
than ferrite. A reasonable compromise from the same
manufacturer is Kool Mµ. Toroids are very space efficient,
especially when you can use several layers of wire.
Because they lack a bobbin, mounting is more difficult.
However, designs for surface mount are available which
do not increase the height significantly.
Schottky Diode Selection (Optional)
The Schottky diodes D1 and D2 in Figure 15 conduct
current during the dead time between the conduction of
the power MOSFETs . This prevents the body diode of the
bottom N-channel MOSFET from turning on and storing
charge during the dead time, which could cost as much as
1% in efficiency. A 1A Schottky diode is generally a good
size for most LTC3736-1 applications, since it conducts a
relatively small average current. Larger diodes result in
additional transition losses due to their larger junction
capacitance. This diode may be omitted if the efficiency
loss can be tolerated.
CIN and COUT Selection
The selection of CIN is simplified by the 2-phase architecture and its impact on the worst-case RMS current drawn
through the input network (battery/fuse/capacitor). It can
be shown that the worst-case capacitor RMS current
occurs when only one controller is operating. The controller with the highest (VOUT)(IOUT) product needs to be used
in the formula below to determine the maximum RMS
capacitor current requirement. Increasing the output current drawn from the other controller will actually decrease
the input RMS ripple current from its maximum value. The
out-of-phase technique typically reduces the input
capacitor’s RMS ripple current by a factor of 30% to 70%
when compared to a single phase power supply solution.
In continuous mode, the source current of the P-channel
MOSFET is a square wave of duty cycle (VOUT)/(VIN). To
prevent large voltage transients, a low ESR capacitor sized
for the maximum RMS current of one channel must be
used. The maximum RMS capacitor current is given by:
CIN Re quiredIRMS ≈
1/ 2
IMAX
VOUT )( VIN – VOUT )
(
VIN
[
]
This formula has a maximum at VIN = 2VOUT, where IRMS
= IOUT/2. This simple worst-case condition is commonly
used for design because even significant deviations do not
offer much relief. Note that capacitor manufacturers’
ripple current ratings are often based on only 2000 hours
of life. This makes it advisable to further derate the
capacitor, or to choose a capacitor rated at a higher
temperature than required. Several capacitors may be
paralleled to meet size or height requirements in the
design. Due to the high operating frequency of the
LTC3736-1, ceramic capacitors can also be used for CIN.
Always consult the manufacturer if there is any question.
The benefit of the LTC3736-1 2-phase operation can be
calculated by using the equation above for the higher power
controller and then calculating the loss that would have
resulted if both controller channels switched on at the
same time. The total RMS power lost is lower when both
controllers are operating due to the reduced overlap of
current pulses required through the input capacitor’s ESR.
This is why the input capacitor’s requirement calculated
above for the worst-case controller is adequate for the
dual controller design. Also, the input protection fuse resistance, battery resistance, and PC board trace resistance
losses are also reduced due to the reduced peak currents
in a 2-phase system. The overall benefit of a multiphase
design will only be fully realized when the source impedance of the power supply/battery is included in the efficiency testing. The sources of the P-channel MOSFETs
should be placed within 1cm of each other and share a
common CIN(s). Separating the sources and CIN may produce undesirable voltage and current resonances at VIN.
A small (0.1µF to 1µF) bypass capacitor between the chip
VIN pin and ground, placed close to the LTC3736-1, is also
suggested. A 10Ω resistor placed between CIN (C1) and
the VIN pin provides further isolation between the two
channels.
The selection of COUT is driven by the effective series
resistance (ESR). Typically, once the ESR requirement is
satisfied, the capacitance is adequate for filtering. The
output ripple (∆VOUT) is approximated by:
⎛
1 ⎞
∆VOUT ≈ IRIPPLE ⎜ ESR +
⎟
⎝
8 fCOUT ⎠
37361f
17
LTC3736-1
U
W
U U
APPLICATIO S I FOR ATIO
where f is the operating frequency, COUT is the output
capacitance and IRIPPLE is the ripple current in the inductor. The output ripple is highest at maximum input voltage
since IRIPPLE increases with input voltage.
Setting Output Voltage
The LTC3736-1 output voltages are each set by an external
feedback resistor divider carefully placed across the output, as shown in Figure 6. The regulated output voltage is
determined by:
⎛ R ⎞
VOUT = 0.6 V • ⎜ 1 + B ⎟
⎝ RA ⎠
During soft-start, the start-up of VOUT1 is controlled by
slowly ramping the positive reference to the error amplifier
from 0V to 0.6V, allowing VOUT1 to rise smoothly from 0V
to its final value. The default internal soft-start time is 1ms.
This can be increased by placing a capacitor between the
RUN/SS pin and SGND. In this case, the soft-start time will
be approximately:
tSS1 = CSS •
To improve the frequency response, a feed-forward capacitor, CFF, may be used. Great care should be taken to
route the VFB line away from noise sources, such as the
inductor or the SW line. When spread spectrum operation
is enabled, it is recommended that RA and RB be largevalued, preferably on the order of hundreds of kilohms.
Run/Soft Start Function
The RUN/SS pin is a dual purpose pin that provides the
optional external soft-start function and a means to shut
down the LTC3736-1.
Pulling the RUN/SS pin below 0.65V puts the LTC3736-1
into a low quiescent current shutdown mode (IQ = 9µA). If
RUN/SS has been pulled all the way to ground, there will
be a delay before the LTC3736-1 comes out of shutdown
and is given by:
tDELAY = 0.65V •
allows CSS to ramp up slowly providing the soft-start
function. This diode (and capacitor) can be deleted if the
external soft-start is not needed.
C SS
= 0.93 s/µF • C SS
0.7µA
This pin can be driven directly from logic as shown in
Figure 6. Diode D1 in Figure 7 reduces the start delay but
600mV
0.7µA
It is recommended that CSS have a value of at least twice
that of the frequency filtering capacitor connected to the
FREQ pin when spread sprectrum operation is enabled
(see Operation Frequency section).
Tracking
The start-up of VOUT2 is controlled by the voltage on the
TRACK pin. Normally this pin is used to allow the start-up
of VOUT2 to track that of VOUT1 as shown qualitatively in
Figures 8a and 8b. When the voltage on the TRACK pin is
less than the internal 0.6V reference, the LTC3736-1
regulates the VFB2 voltage to the TRACK pin voltage
instead of 0.6V. The start-up of VOUT2 may ratiometrically
track that of VOUT1, according to a ratio set by a resistor
divider (Figure 8c):
VOUT1
R2A
R
+ RTRACKB
=
• TRACKA
VOUT2 RTRACKA
R2B + R2A
For coincident tracking (VOUT1 = VOUT2 during start-up),
R2A/R2B = RTRACKA/RTRACKB
VOUT
3.3V OR 5V
1/2 LTC3736-1
RB
CFF
RUN/SS
D1
VFB
RA
CSS
CSS
37361 F07
37361 F06
Figure 6. Setting Output Voltage
RUN/SS
Figure 7. RUN/SS Pin Interfacing
37361f
18
LTC3736-1
U
W
U U
APPLICATIO S I FOR ATIO
The ramp time for VOUT2 to rise from 0V to its final value
is:
tSS2 = tSS1 •
RTRACKA
R1A + R1B
•
R1A
RTRACKA + RTRACKB
For coincident tracking,
tSS2 = tSS1 •
VOUT2F
VOUT1F
where VOUT1F and VOUT2F are the final, regulated values of
VOUT1 and VOUT2. VOUT1 should always be greater than
VOUT1
R1B
VOUT2
LTC3736-1
VFB1
R2B
VFB2
R1A
R2A
RTRACKB
TRACK
37361 F08a
RTRACKA
Figure 8a. Using the TRACK Pin
OUTPUT VOLTAGE
VOUT1
VOUT2 when using the TRACK pin. If no tracking function
is desired, then the TRACK pin may be tied to VIN. However, in this situation there would be no (internal nor
external) soft-start on VOUT2.
When using tracking with spread spectrum operation
enabled, the tracking resistors RTRACKA and RTRACKB
should have value at least 10 times smaller than corresponding feedback resistors R2A and R2B.
Fault Condition: Short Circuit and Current Limit
To prevent excessive heating of the bottom MOSFET,
foldback current limiting can be added to reduce the
current in proportion to the severity of the fault.
Foldback current limiting is implemented by adding diodes DFB1 and DFB2 between the output and the ITH pin as
shown in Figure 9. In a hard short (VOUT = 0V), the current
will be reduced to approximately 50% of the maximum
output current.
Low Supply Operation
Although the LTC3736-1 can function down to below
2.4V, the maximum allowable output current is reduced as
VIN decreases below 3V. Figure 10 shows the amount of
VOUT
1/2 LTC3736-1
ITH
VOUT2
R2
+
DFB1
VFB
R1
DFB2
37361 F09
Figure 9. Foldback Current Limiting
TIME
(8b) Coincident Tracking
OUTPUT VOLTAGE
VOUT1
VOUT2
TIME
37361 F08b,c
(8c) Ratiometric Tracking
NORMALIZED VOLTAGE OR CURRENT (%)
105
100
95
VREF
MAXIMUM
SENSE VOLTAGE
90
85
80
75
2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0
INPUT VOLTAGE (V)
37361 F10
Figures 8b and 8c. Two Different Modes of Output
Voltage Tracking
Figure 10. Line Regulation of VREF and
Maximum Sense Voltage for Low Input Supply
37361f
19
LTC3736-1
U
W
U U
APPLICATIO S I FOR ATIO
change as the supply is reduced down to 2.4V. Also shown
is the effect on VREF.
Minimum On-Time Considerations
Minimum on-time, tON(MIN), is the smallest amount of time
in which the LTC3736-1 is capable of turning the top
P-channel MOSFET on and then off. It is determined by
internal timing delays and the gate charge required to turn
on the top MOSFET. Low duty cycle and high frequency
applications may approach the minimum on-time limit
and care should be taken to ensure that:
tON(MIN) <
VOUT
fOSC • VIN
If the duty cycle falls below what can be accommodated
by the minimum on-time, the LTC3736-1 will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple current and ripple voltage will increase. The
minimum on-time for the LTC3736-1 is typically about
250ns. However, as the peak sense voltage (IL(PEAK) •
RDS(ON)) decreases, the minimum on-time gradually increases up to about 300ns.
Efficiency Considerations
The efficiency of a switching regulator is equal to the
output power divided by the input power times 100%. It is
often useful to analyze individual losses to determine what
is limiting efficiency and which change would produce the
most improvement. Efficiency can be expressed as:
Efficiency = 100% – (L1 + L2 + L3 + …)
where L1, L2, etc. are the individual losses as a percentage
of input power.
Although all dissipative elements in the circuit produce
losses, five main sources usually account for most of the
losses in LTC3736-1 circuits: 1) LTC3736-1 DC bias
current, 2) MOSFET gate charge current, 3) I2R losses,
and 4) transition losses.
1) The VIN (pin) current is the DC supply current, given in
the electrical characteristics, excluding MOSFET driver
currents. VIN current results in a small loss that increases with VIN.
2) MOSFET gate charge current results from switching the
gate capacitance of the power MOSFETs. Each time a
MOSFET gate is switched from low to high to low again,
a packet of charge dQ moves from SENSE+ to ground.
The resulting dQ/dt is a current out of SENSE+, which is
typically much larger than the DC supply current. In
continuous mode, IGATECHG = f • QP.
3) I2R losses are calculated from the DC resistances of the
MOSFETs and inductor. In continuous mode, the average output current flows through L but is “chopped”
between the top P-channel MOSFET and the bottom
N-channel MOSFET. The MOSFET RDS(ON)s multiplied
by duty cycle can be summed with the resistance of L
to obtain I2R losses.
4) Transition losses apply to the top external P-channel
MOSFET and increase with higher operating frequencies and input voltages. Transition losses can be estimated from:
Transition Loss = 2 (VIN)2IO(MAX)CRSS(f)
Other losses, including CIN and COUT ESR dissipative
losses and inductor core losses, generally account for less
than 2% total additional loss.
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, VOUT immediately shifts by an amount
equal to (∆ILOAD)(ESR), where ESR is the effective series
resistance of COUT. ∆ILOAD also begins to charge or discharge COUT, which generates a feedback error signal. The
regulator loop then returns VOUT to its steady-state value.
During this recovery time, VOUT can be monitored for overshoot or ringing. OPTI-LOOP compensation allows the
transient response to be optimized over a wide range of
output capacitance and ESR values.
The ITH series RC-CC filter (see Functional Diagram) sets
the dominant pole-zero loop compensation. The ITH external components shown in the Typical Application on the
front page of this data sheet will provide an adequate
starting point for most applications. The values can be
37361f
20
LTC3736-1
U
W
U U
APPLICATIO S I FOR ATIO
deliver enough current to prevent this problem if the load
switch resistance is low and it is driven quickly. The only
solution is to limit the rise time of the switch drive so that
the load rise time is limited to approximately (25)(CLOAD).
Thus a 10µF capacitor would require a 250µs rise time,
limiting the charging current to about 200mA.
modified slightly (from 0.2 to 5 times their suggested
values) to optimize transient response once the final PC
layout is done and the particular output capacitor type and
value have been determined. The output capacitors need
to be decided upon because the various types and values
determine the loop feedback factor gain and phase. An
output current pulse of 20% to 100% of full load current
having a rise time of 1µs to 10µs will produce output
voltage and ITH pin waveforms that will give a sense of the
overall loop stability. The gain of the loop will be increased
by increasing RC, and the bandwidth of the loop will be
increased by decreasing CC. The output voltage settling
behavior is related to the stability of the closed-loop
system and will demonstrate the actual overall supply
performance. For a detailed explanation of optimizing the
compensation components, including a review of control
loop theory, refer to Application Note 76.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3736-1. These items are illustrated in the layout diagram of Figure 11. Figure 12 depicts the current waveforms present in the various branches of the 2-phase dual
regulator.
1) The power loop (input capacitor, MOSFETs, inductor,
output capacitor) of each channel should be as small as
possible and isolated as much as possible from the power
loop of the other channel. Ideally, the drains of the P- and
N-channel FETs should be connected close to one another
with an input capacitor placed across the FET sources
(from the P-channel source to the N-channel source) right
COUT1
+
A second, more severe transient is caused by switching in
loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with COUT, causing a rapid drop in VOUT. No regulator can
L1
LTC3736EGN-1
1
2
3
4
5
6
7
8
9
10
11
12
SW1
IPRG1
24
SENSE1+
PGND
VFB1
BG1
ITH1
SSDIS
IPRG2
FREQ
SGND
VIN
TRACK
TG1
PGND
TG2
RUN/SS
BG2
VFB2
PGND
ITH2
SENSE2+
PGOOD
VOUT1
SW2
23
22
MN1
CVIN1
21
MP1
20
CVIN
19
VIN
18
CVIN2
17
16
MN2
MP2
15
14
13
L2
+
COUT2
VOUT2
37361 F11
BOLD LINES INDICATE HIGH CURRENT PATHS
Figure 11. LTC3736-1 Layout Diagram
37361f
21
LTC3736-1
U
W
U U
APPLICATIO S I FOR ATIO
at the FETs. It is better to have two separate, smaller valued
input capacitors (e.g., two 10µF—one for each channel)
than it is to have a single larger valued capacitor (e.g.,
22µF) that the channels share with a common connection.
2) The signal and power grounds should be kept separate.
The signal ground consists of the feedback resistor dividers, ITH compensation networks and the SGND pin.
The power grounds consist of the (–) terminal of the input
and output capacitors and the source of the N-channel
MOSFET. Each channel should have its own power ground
for its power loop (as described in (1) above). The power
grounds for the two channels should connect together at
a common point. It is most important to keep the ground
paths with high switching currents away from each other.
MP1
The PGND pins on the LTC3736-1 IC should be shorted
together and connected to the common power ground
connection (away from the switching currents).
3) Put the feedback resistors close to the VFB pins. The
trace connecting the top feedback resistor (RB) to the
output capacitor should be a Kelvin trace. The ITH compensation components should also be very close to the
LTC3736-1.
4) The current sense traces (SENSE+ and SW) should be
Kelvin connections right at the P-channel MOSFET source
and drain.
5) Keep the switch nodes (SW1, SW2) and the gate driver
nodes (TG1, TG2, BG1, BG2) away from the small-signal
components, especially the opposite channels feedback
resistors, ITH compensation components and the current
sense pins (SENSE+ and SW).
L1
VOUT1
COUT1
MN1
+
RL1
VIN
RIN
CIN
+
MP2
L2
MN2
VOUT2
COUT2
BOLD LINES INDICATE
HIGH, SWITCHING
CURRENT LINES.
KEEP LINES TO A
MINIMUM LENGTH
+
RL2
37361 F12
Figure 12. Branch Current Waveforms
37361f
22
LTC3736-1
U
TYPICAL APPLICATIO S
RFB1B
562k
CITH1A
100pF
CITH1
220pF RITH1
15k
2200pF
VIN
5V
CIN
10µF
×2
22
23
24
1
2
3
4
RVIN 10Ω
5
CITH2
CVIN 220pF
1µF
RITH2
15k
CSS
10nF CITH2B
100pF
RFB2A
453k
9
7
8
6
+ 21
SW1
IPRG1
VFB1
ITH1
IPRG2
FREQ
SENSE1
PGND
BG1
SSDIS
TG1
PGND
SGND
TG2
VIN
RUN/SS
LTC3736EUF-1
BG2
PGND
PGOOD
SENSE2+
VFB2
ITH2
TRACK
SW2
PGND
L1
1.5µH
MP1
20
19
18
17
16
MN1
Si7540DP
VOUT1
2.5V
5A
+
COUT1
150µF
15
14
13
12
11
MN2
Si7540DP
MP2
10
+
RFB1A
178k
L2
1.5µH
COUT2
150µF V
OUT2
1.8V
5A
25
RTRACKA
590Ω
RFB2B RTRACKB
909k
1.18k
37361 F13
L1, L2: VISHAY IHLP-2525CZ-01
COUT1, COUT2: SANYO 4TPB150MC
Figure 13. 2-Phase, Spread Spectrum, Dual Output Synchronous DC/DC Converter
37361f
23
LTC3736-1
U
TYPICAL APPLICATIO S
68pF
RFB1A
59k
RFB1B
187k
CITH1A
47pF
22
23
24
1
2
3
4
CITH1
470pF RITH1
22k
2200pF
VIN
3.3V
RVIN 10Ω
5
CIN
22µF
9
7
8
6
CITH2
CVIN 470pF
1µF
RITH2
22k
SENSE1+
PGND
BG1
SSDIS
TG1
PGND
15
TG2
14
VIN
RUN/SS
LTC3736EUF-1
13
BG2
12
PGND
PGOOD
+ 11
SENSE2
VFB2
ITH2
10
TRACK
SW2
PGND
SW1
IPRG1
VFB1
ITH1
IPRG2
FREQ
SGND
CSS
10nF CITH2A
47pF
RFB2A
59k
L1
1.5µH
MP1
21
20
19
18
17
16
MN1
Si7540DP
COUT1
100µF
COUT2
100µF
MN2
Si7540DP
MP2
VOUT1
2.5V
2A
VOUT2
1.8V
2A
L2
1.5µH
25
RTRACKA
590Ω
RFB2B
118k
RTRACKB
1.18k
100pF
37361 F14
L1, L2: VISHAY IHLP-2525CZ-01
COUT1, COUT2: MURATA GRM32EROJ107M
Figure 14. 2-Phase, Spread Spectrum, Dual Output Synchronous DC/DC Converter with Ceramic Output Capacitors
Efficiency vs Load Current
Load Step
Load Step
100
90
80
EFFICIENCY (%)
70
VOUT
AC-COUPLED
100mV/DIV
VOUT
AC-COUPLED
50mV/DIV
IL
1A/DIV
IL
1A/DIV
60
50
40
30
20
VOUT = 2.5V
VOUT = 1.8V
10
0
1
100
1000
10
LOAD CURRENT (mA)
100µs/DIV
VOUT = 2.5V
ILOAD = 100mA TO 1A
37361 F14c
100µs/DIV
VOUT = 1.8V
ILOAD = 100mA TO 1A
37361 F14d
10000
37361 F14b
37361f
24
LTC3736-1
U
TYPICAL APPLICATIO S
CFF1
100pF
RFB1B
187k
CITH1
220pF
RITH1
15k
2200pF
VIN
3.3V
RVIN 10Ω
CIN
22µF
CITH2
CVIN 220pF
1µF
RITH2
15k
RFB2A
59k
RTRACKA
590Ω
4.7nF
SSDIS
1
2
3
4
5
6
7
+ 24
SW1
SENSE1
IPRG1
PGND
BG1
VFB1
SSDIS
ITH1
TG1
IPRG2
PGND
FREQ
TG2
SGND
LTC3736EGN-1
5
VIN
RUN/SS
MP1
23
22
21
20
19
18
SW1
L1
1.5µH
MN1
Si7540DP
D1
MN2
Si7540DP
D2
+
COUT1
150µF
17
16
BG2
12
15
PGND
PGOOD
10
14
SENSE2+
VFB2
11
ITH2
13
9
TRACK
SW2
MP2
SW2
L2
1.5µH
RFB2B RTRACKB
118k
1.18k
CFF1
100pF
VOUT1
2.5V
3A
+
RFB1A
59k
COUT2
150µF V
OUT2
1.8V
4A
37361 F15
COUT1, COUT2: SANYO 4TPB150MC
L1, L2: VISHAY IHLP-2525CZ-01
D1, D2: OPTIONAL SCHOTTKY DIODE
Figure 15. 2-Phase, Fixed 550kHz or Spread Spectrum, Dual Output Synchronous DC/DC Converter
37361f
25
LTC3736-1
U
PACKAGE DESCRIPTIO
UF Package
24-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1697)
0.70 ±0.05
4.50 ± 0.05
2.45 ± 0.05
3.10 ± 0.05 (4 SIDES)
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
4.00 ± 0.10
(4 SIDES)
BOTTOM VIEW—EXPOSED PAD
0.23 TYP
R = 0.115
(4 SIDES)
TYP
23 24
0.75 ± 0.05
PIN 1
TOP MARK
(NOTE 6)
0.38 ± 0.10
1
2
2.45 ± 0.10
(4-SIDES)
(UF24) QFN 1103
0.200 REF
0.00 – 0.05
0.25 ± 0.05
0.50 BSC
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
37361f
26
LTC3736-1
U
PACKAGE DESCRIPTIO
GN Package
24-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.337 – .344*
(8.560 – 8.738)
24 23 22 21 20 19 18 17 16 15 1413
.033
(0.838)
REF
.045 ±.005
.229 – .244
(5.817 – 6.198)
.254 MIN
.150 – .157**
(3.810 – 3.988)
.150 – .165
1
.0165 ± .0015
2 3
4
5 6
7
8
9 10 11 12
.0250 BSC
RECOMMENDED SOLDER PAD LAYOUT
.015 ± .004
× 45°
(0.38 ± 0.10)
.0075 – .0098
(0.19 – 0.25)
.0532 – .0688
(1.35 – 1.75)
.004 – .0098
(0.102 – 0.249)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
.008 – .012
(0.203 – 0.305)
TYP
.0250
(0.635)
BSC
GN24 (SSOP) 0204
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
37361f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LTC3736-1
U
TYPICAL APPLICATIO
2-Phase, Spread Spectrum Dual Output, Synchronous DC/DC Converter
RFB1A
59k
RFB1B
187k
CITH1A
100pF
2200pF
VIN
5V
CIN
10µF
×2
4
RVIN 10Ω
5
CITH2
CVIN 220pF
1µF
RITH2
15k
9
7
8
6
SW1
IPRG1
VFB1
ITH1
IPRG2
FREQ
PGND
BG1
SSDIS
TG1
PGND
SGND
TG2
VIN
RUN/SS
LTC3736EUF-1
BG2
PGND
PGOOD
SENSE2+
VFB2
ITH2
TRACK
SW2
PGND
CSS
10nF CITH2B
100pF
RFB2A
59k
21
SENSE1+
L1
1.5µH
MP1
20
19
18
17
16
VOUT1
2.5V
2A
+
MN1
COUT1
150µF
15
14
13
12
11
MN2
+
CITH1
220pF RITH1
15k
22
23
24
1
2
3
MP2
10
L2
1.5µH
COUT2
150µF V
OUT2
1.8V
2A
25
RTRACKA
590Ω
RFB2B RTRACKB
118k
1.18k
37361 TA02
MP1, MP2: FDC638P
MN1, MN2: FDC637N
L1, L2: VISHAY IHLP-2525CZ-01
COUT1, COUT2: SANYO 4TPB150MC
RELATED PARTS
PART NUMBER
LTC1628/
LTC1628-PG
LTC1735
DESCRIPTION
Dual High Efficiency, 2-Phase Synchronous
Step-Down Controllers
High Efficiency Synchronous Step-Down Controller
LTC1772
Constant Frequency Current Mode Step-Down
DC/DC Controller
Synchronous Step-Down Controller
No RSENSETM Synchronous Step-Down Controller
LTC1773
LTC1778
LTC2923
LTC3251 Series
LTC3252
LTC3416
LTC3701
LTC3708
LTC3728/LTC3728L
LTC3736
LTC3737
LTC6902
Power Supply Tracking Controller
500mA High Efficiency, Low Noise, Inductorless
Step-Down DC/DC Converters
Dual, Low Noise, Inductorless Step-Down DC/DC Converter
4A, 4MHz, Synchronous Step-Down DC/DC Converter
with Output Tracking
2-Phase, Low Input Voltage Dual Step-Down DC/DC Controller
Fast 2-Phase, No RSENSE Buck Controller with
Output Tracking
Dual, 550kHz, 2-Phase, Synchronous Step-Down
Switching Regulator
Dual, 2-Phase, No RSENSE, Synchronous Controller with Output
Tracking
Dual, 2-Phase, No RSENSE Controller with Output Tracking
Multiphase Oscillator with Spread Spectrum Frequency
Modulation
COMMENTS
Constant Frequency, Standby, 5V and 3.3V LDOs, VIN to 36V,
28-Lead SSOP
Burst Mode Operation, 16-Pin Narrow SSOP, Fault Protection,
3.5V ≤ VIN ≤ 36V
2.5V ≤ VIN ≤ 9.8V, IOUT Up to 4A, SOT-23 Package, 550kHz
2.65V ≤ VIN ≤ 8.5V, IOUT Up to 4A, 10-Lead MSOP
Current Mode Operation Without Sense Resistor,
Fast Transient Response, 4V ≤ VIN ≤ 36V
Controls Up to Three Supplies, 10-Lead MSOP
2-Phase, Spread Spectrum Operation, 10-Pin MSOP Package
Spread Spectrum Operation, 4mm × 3mm 12-Pin DFN Package
95% Efficiency, VIN: 2.25V to 5.5V, ISD = <1µA,
TSSOP-20E Package
2.5V ≤ VIN ≤ 9.8V, 550kHz, PGOOD, PLL, 16-Lead SSOP
Constant On-Time Dual Controller, VIN Up to 36V, Very Low
Duty Cycle Operation, 5mm × 5mm QFN Package
Constant Frequency, VIN to 36V, 5V and 3.3V LDOs,
5mm × 5mm QFN or 28-Lead SSOP
VIN: 2.75V to 9.8V, IOUT Up to 5A, 4mm × 4mm QFN Package
VIN: 2.75V to 9.8V, IOUT Up to 5A, 4mm × 4mm QFN Package
Resistor Programs Nominal Frequency and Spreading;
2-, 3-, or 4-Phase Outputs; 10-Pin MSOP Package
No RSENSE is a trademark of Linear Technology Corporation.
37361f
28
Linear Technology Corporation
LT/TP 0804 1K • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2004