NTD4904N Power MOSFET 30 V, 79 A, Single N−Channel, DPAK/IPAK Features • • • • Low RDS(on) to Minimize Conduction Losses Low Capacitance to Minimize Driver Losses Optimized Gate Charge to Minimize Switching Losses These are Pb−Free Devices http://onsemi.com V(BR)DSS Applications RDS(on) MAX 3.7 mW @ 10 V 30 V • CPU Power Delivery • DC−DC Converters ID MAX 79 A 5.5 mW @ 4.5 V D MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) TA = 25°C Unit VDSS 30 V VGS "20 V ID 17.8 A TA = 100°C PD 2.6 W Continuous Drain Current (RqJA) (Note 2) TA = 25°C ID 13 A Continuous Drain Current (RqJC) (Note 1) 9.2 TA = 25°C PD 1.4 W TC = 25°C ID 79 A TC = 100°C Power Dissipation (RqJC) (Note 1) Pulsed Drain Current TA = 100°C tp=10ms Current Limited by Package PD 52 W TA = 25°C IDM 316 A TA = 25°C IDmaxPkg 90 A TJ, Tstg −55 to 175 °C Source Current (Body Diode) Drain to Source dV/dt Single Pulse Drain−to−Source Avalanche Energy (TJ = 25°C, VDD = 50 V, VGS = 10 V, L = 0.1 mH, IL(pk) = 37 A, RG = 25 W) Lead Temperature for Soldering Purposes (1/8″ from case for 10 s) 4 1 2 1 3 CASE 369AA DPAK (Bent Lead) STYLE 2 2 3 1 2 3 CASE 369AD CASE 369D IPAK IPAK (Straight Lead) (Straight Lead DPAK) 56 TC = 25°C Operating Junction and Storage Temperature 4 4 TA = 25°C Power Dissipation (RqJA) (Note 2) S 12.6 Power Dissipation (RqJA) (Note 1) Steady State N−Channel G IS 47 A dV/dt 6.0 V/ns EAS 68.4 mJ TL 260 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. MARKING DIAGRAMS & PIN ASSIGNMENTS 4 Drain 4 Drain 4 Drain YWW 49 04NG Gate−to−Source Voltage Continuous Drain Current (RqJA) (Note 1) Value YWW 49 04NG Drain−to−Source Voltage Symbol YWW 49 04NG Parameter 2 1 2 3 1 Drain 3 Gate Source Gate Drain Source 1 2 3 Gate Drain Source Y WW 4904N G = Year = Work Week = Device Code = Pb−Free Package ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. © Semiconductor Components Industries, LLC, 2009 June, 2009 − Rev. 0 1 Publication Order Number: NTD4904N/D NTD4904N THERMAL RESISTANCE MAXIMUM RATINGS Parameter Symbol Value Unit RqJC 2.9 °C/W Junction−to−Case (Drain) Junction−to−Tab (Drain) RqJC−TAB 4.3 Junction−to−Ambient − Steady State (Note 1) RqJA 57 Junction−to−Ambient − Steady State (Note 2) RqJA 108 1. Surface−mounted on FR4 board using 1 in sq pad size, 1 oz Cu. 2. Surface−mounted on FR4 board using the minimum recommended pad size. ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Parameter Symbol Test Condition Min Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = 250 mA 30 Drain−to−Source Breakdown Voltage Temperature Coefficient V(BR)DSS/TJ Typ Max Unit OFF CHARACTERISTICS Zero Gate Voltage Drain Current IDSS Gate−to−Source Leakage Current V 15 VGS = 0 V, VDS = 24 V mV/°C TJ = 25°C 1.0 TJ = 125°C 10 IGSS VDS = 0 V, VGS = "20 V VGS(TH) VGS = VDS, ID = 250 mA mA "100 nA 2.2 V ON CHARACTERISTICS (Note 3) Gate Threshold Voltage Negative Threshold Temperature Coefficient VGS(TH)/TJ Drain−to−Source On Resistance RDS(on) gFS 1.6 4.0 VGS = 10 V VGS = 4.5 V Forward Transconductance 1.0 ID = 30 A 3.0 ID = 15 A 3.0 ID = 30 A 4.0 ID = 15 A 4.0 VDS = 1.5 V, ID = 30 A mV/°C 3.7 mW 5.5 76 S 3052 pF CHARGES AND CAPACITANCES Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss Total Gate Charge QG(TOT) Threshold Gate Charge QG(TH) Gate−to−Source Charge QGS Gate−to−Drain Charge QGD Total Gate Charge QG(TOT) VGS = 0 V, f = 1.0 MHz, VDS = 15 V 976 23 16.8 VGS = 4.5 V, VDS = 15 V, ID = 30 A nC 4.4 8.2 3.0 VGS = 10 V, VDS = 15 V, ID = 30 A 41 nC 15.3 ns SWITCHING CHARACTERISTICS (Note 4) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time td(on) tr td(off) VGS = 4.5 V, VDS = 15 V, ID = 15 A, RG = 3.0 W 19.8 23.4 tf 7.5 td(on) 10.3 tr td(off) VGS = 10 V, VDS = 15 V, ID = 15 A, RG = 3.0 W tf 20 28.7 8.0 3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%. 4. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 2 ns NTD4904N ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Parameter Symbol Test Condition Min Typ Max Unit TJ = 25°C 0.84 1.1 V TJ = 125°C 0.7 DRAIN−SOURCE DIODE CHARACTERISTICS Forward Diode Voltage Reverse Recovery Time VSD tRR Charge Time ta Discharge Time tb Reverse Recovery Time VGS = 0 V, IS = 30 A ns 40.4 VGS = 0 V, dIs/dt= 100 A/ms, IS = 30 A 20.5 19.9 QRR 35 nC Source Inductance (Note 5) LS 2.48 nH Drain Inductance, DPAK LD 0.0164 Drain Inductance, IPAK (Note 5) LD Gate Inductance (Note 5) LG 4.9 Gate Resistance RG 1.0 PACKAGE PARASITIC VALUES TA = 25°C 5. Assume terminal length of 110 mils. http://onsemi.com 3 1.88 2.0 W NTD4904N TJ = 25°C 3.6 V ID, DRAIN CURRENT (AMPS) 10 V 3.4 V 3.8 V to 6 V 3.2 V 3.0 V 2.8 V 2.6 V 2.4 V 0 1 3 2 4 5 TJ = 25°C TJ = −55°C 2 3 2.5 3.5 4 Figure 2. Transfer Characteristics ID = 30 A TJ = 25°C 0.008 0.006 0.004 2.0 TJ = 125°C Figure 1. On−Region Characteristics 0.010 2.2 VDS ≥ 10 V VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) 0.012 0.002 130 120 110 100 90 80 70 60 50 40 30 20 10 0 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 3 4 5 6 7 8 9 10 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 130 120 110 100 90 80 70 60 50 40 30 20 10 0 0.006 TJ = 25°C 0.005 VGS = 4.5 V 0.004 VGS = 10 V 0.003 0.002 20 40 60 80 100 120 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) ID, DRAIN CURRENT (AMPS) Figure 3. On−Resistance vs. Gate−to−Source Voltage Figure 4. On−Resistance vs. Drain Current and Gate Voltage 10,000 VGS = 0 V ID = 30 A VGS = 10 V TJ = 150°C 1.8 IDSS, LEAKAGE (nA) RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) ID, DRAIN CURRENT (AMPS) TYPICAL PERFORMANCE CURVES 1.6 1.4 1.2 1.0 1000 TJ = 125°C 100 TJ = 85°C 0.8 0.6 −50 −25 10 0 25 50 75 100 125 150 175 5 10 15 20 25 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current vs. Drain Voltage http://onsemi.com 4 30 NTD4904N 3600 C, CAPACITANCE (pF) TJ = 25°C VGS = 0 V Ciss 3200 VGS , GATE−TO−SOURCE VOLTAGE (VOLTS) TYPICAL PERFORMANCE CURVES 2800 2400 2000 1600 Coss 1200 800 400 0 Crss 0 5 10 15 20 25 30 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 12 11 10 9 8 7 6 4 3 2 1 0 IS, SOURCE CURRENT (AMPS) t, TIME (ns) td(off) tf tr td(on) 10 VDD = 15 V VGS = 10 V ID = 30 A TJ = 25°C 0 10 RG, GATE RESISTANCE (OHMS) 10 ms 100 ms VGS = 10 V SINGLE PULSE TC = 25°C 1 ms 10 ms dc RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 40 45 20 15 10 TJ = 125°C 5 TJ = 25°C 0.8 0.9 0.5 0.6 0.7 VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) 1.0 Figure 10. Diode Forward Voltage vs. Current 1 10 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 100 EAS, SINGLE PULSE DRAIN−TO−SOURCE AVALANCHE ENERGY (mJ) I D, DRAIN CURRENT (AMPS) 100 0.1 20 25 10 15 30 35 QG, TOTAL GATE CHARGE (nC) VGS = 0 V 0 0.4 100 1000 1 5 25 Figure 9. Resistive Switching Time Variation vs. Gate Resistance 10 QGD 30 VDD = 15 V ID = 15 A VGS = 10 V 1 QGS Figure 8. Gate−To−Source and Drain−To−Source Voltage vs. Total Charge 100 1 VGS 5 Figure 7. Capacitance Variation 1000 QT 70 ID = 37 A 60 50 40 30 20 10 0 25 Figure 11. Maximum Rated Forward Biased Safe Operating Area 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) Figure 12. Maximum Avalanche Energy vs. Starting Junction Temperature http://onsemi.com 5 175 NTD4904N TYPICAL PERFORMANCE CURVES 100 R(t) (C/W) 10 50% (DUTY CYCLE) 20% 10% 5.0% 2.0% 1.0 1.0% 0.1 SINGLE PULSE 0.01 PSi TAB-A 0.001 0.000001 0.00001 0.0001 0.001 0.01 0.1 1.0 10 100 1000 PULSE TIME (s) Figure 13. FET Thermal Response 110 VDS = 1.5 V 100 90 80 GFS (S) 70 60 50 40 30 20 10 0 0 10 20 30 40 50 60 ID (A) 70 80 90 100 Figure 14. GFS vs ID ORDERING INFORMATION Package Shipping† NTD4904NT4G DPAK (Pb−Free) 2500 / Tape & Reel NTD4904N−1G IPAK (Pb−Free) 75 Units / Rail NTD4904N−35G IPAK Trimmed Lead (Pb−Free) 75 Units / Rail Order Number †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 6 NTD4904N PACKAGE DIMENSIONS DPAK CASE 369AA−01 ISSUE A −T− C B V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. SEATING PLANE E R 4 A S 1 2 3 DIM A B C D E F H J L R S U V Z Z H U F J L D 2 PL 0.13 (0.005) M T SOLDERING FOOTPRINT* 6.20 0.244 2.58 0.101 5.80 0.228 3.0 0.118 1.6 0.063 6.172 0.243 SCALE 3:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 7 INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.025 0.035 0.018 0.024 0.030 0.045 0.386 0.410 0.018 0.023 0.090 BSC 0.180 0.215 0.024 0.040 0.020 −−− 0.035 0.050 0.155 −−− MILLIMETERS MIN MAX 5.97 6.22 6.35 6.73 2.19 2.38 0.63 0.89 0.46 0.61 0.77 1.14 9.80 10.40 0.46 0.58 2.29 BSC 4.57 5.45 0.60 1.01 0.51 −−− 0.89 1.27 3.93 −−− NTD4904N PACKAGE DIMENSIONS C B V IPAK (STRAIGHT LEAD DPAK) CASE 369D−01 ISSUE B E R 4 1 2 DIM A B C D E F G H J K R S V Z Z A S NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3 −T− SEATING PLANE K J F D G H M T 3.5 MM IPAK, STRAIGHT LEAD CASE 369AD−01 ISSUE O E E2 A1 D2 D L1 NOTES: 1.. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2.. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30mm FROM TERMINAL TIP. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD GATE OR MOLD FLASH. L T SEATING PLANE A E3 L2 A1 b1 2X e A2 3X E2 b 0.13 M MILLIMETERS MIN MAX 5.97 6.35 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 2.29 BSC 0.87 1.01 0.46 0.58 8.89 9.65 4.45 5.45 0.63 1.01 0.89 1.27 3.93 −−− STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN 3 PL 0.13 (0.005) INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.090 BSC 0.034 0.040 0.018 0.023 0.350 0.380 0.180 0.215 0.025 0.040 0.035 0.050 0.155 −−− T D2 DIM A A1 A2 b b1 D D2 E E2 E3 e L L1 L2 MILLIMETERS MIN MAX 2.19 2.38 0.46 0.60 0.87 1.10 0.69 0.89 0.77 1.10 5.97 6.22 4.80 −−− 6.35 6.73 4.70 −−− 4.45 5.46 2.28 BSC 3.40 3.60 −−− 2.10 0.89 1.27 OPTIONAL CONSTRUCTION ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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