DRF100 15V, 8A, 30MHz MOSFET Driver Hybrid The DRF100 is a High-Speed Power MOSFET driver with a unique anti-ring function. It is intended to drive the gate of a power MOSFET with ≥3nF gate capacitance to 15V at frequencies up to 30MHz. It can produce output currents ≥8A RMS, while dissipating 60W. The Driver output can be configured as Inverting or Non-Inverting. FEATURES DRF100 TYPICAL APPLICATIONS • Switching Frequency: DC TO 30MHz • Output Capable of ≥ 8A RMS • MOSFET Drivers • Low Pulse Width Distortion • Power Dissipation Capability 60W • Switch Mode Power Amplifiers • Single Power Supply • Digital Output Amplifiers • 1V CMOS Schmitt Trigger Input 1V • Pulse Generators Hysteresis • Laser Diode Drivers • Inverting Non-Inverting Select • Ultrasound Transducer Drivers • RoHS Compliant • Acoustic Optical Modulators Driver Absolute Maximum Ratings Symbol VDD Parameter Ratings Supply Voltage IN, FN Input Single Voltages IO PK Output Current Peak TJMAX Operating Temperature Unit 18 V -.7 to +5.5 8 A 175 °C Driver Specifications Min Typ Max VDD Supply Voltage Parameter 8 15 18 IN Input Voltage 3 5.5 Unit V IN(R) Input Voltage Rising Edge 3 IN(F) Input Voltage Falling Edge 3 IDDQ Quiescent Current 2 mA Output Current 8 A IO Coss Output Capacitance Ciss Input Capacitance RIN Input Parallel Resistance ns 2500 pF 3 1 mΩ VT(ON) Input, Low to High Out 2.0 2.8 VT(OFF) Input, High to Low Out 1.0 1.4 TDLY Time Delay (throughput) 25 tr Rise Time 1.5 2.5 3.0 38 tf Fall Time 1.5 2.5 3.0 TD Prop. Delay 35 Microsemi Website - http://www.microsemi.com V ns ns 050-4912 Rev D 4-2009 Symbol Output Characteristics Symbol DRF100 Parameter Min Cout Output Capacitance Rout Output Resistance Lout Output Inductance 2 FMAX Operating Frequency CL=3000nF + 50Ω 30 FMAX Operating Frequency RL=50Ω 50 Typ Max 2500 pF 1 3 Unit Ω 4 nH MHz Dynamic Characteristics Symbol Parameter Min Typ Ciss Input Capacitance 2000 Coss Output Capacitance 165 Crss Reverse Transfer Capacitance 75 Max Unit pF Thermal Characteristics Symbol Parameter Ratings RθJC Thermal Resistance Junction to Case 1.44 RθJHS Thermal Resistance Junction to Heat Sink 2.53 TJSTG Storage Temperature -55 to 150 PD Maximum Power Dissipation @ TSINK = 25°C 60 PDC Total Power Dissipation @ TC = 25°C 100 Unit °C/W °C W Microsemi reserves the right to change, without notice, the specifications and information contained herein. 050-4912 Rev D 4-2009 Figure 1, DRF100 Simplified Circuit Diagram The Simplified DRF100 Circuit Diagram is illustrated above. By including the driver high speed by-pass capacitor (C Internal), the contribution to the internal parasitic loop inductance of the driver output is greatly reduced. This low parasitic approach, coupled with the Schmitt trigger input (pin 4), Kelvin signal ground (pin 5) and the Anti-Ring Function, provide improved stability and control. The IN pin (4) is applied to a Schmitt Trigger. The signal is then applied to the intermediate drivers and level shifters; this section contains proprietary circuitry designed specifically for ring abatement. The P channel and N channel power drivers provide the high current to the OUTPUT (pin 9.) DRF100 The Function (FN, pin 3) is the invert or non-invert select Pin, it is Internally held high, Normally Non-inverting. Truth Table *Referenced to SG FN (pin 3)* IN (pin 4)* Function OUTPUT HIGH HIGH Non-Invert HIGH HIGH LOW Non-Invert LOW LOW HIGH Inverting LOW LOW LOW Inverting HIGH Figure 2, DRF100 Test Circuit The Test Circuit illustrated above was used to evaluate the DRF100 (available as an evaluation Board DRF100 / EVALSW.) The input control signal is applied to the DRF100 via IN(4) and SG(5) pins using RG188. This provides excellent noise immunity and control of the signal ground currents. Microsemi’s products are covered by one or more of U.S. patents 4,895,810 5,045,903 5,089,434 5,182,234 5,019,522 5,262,336 6,503,786 5,256,583 4,748,103 5,283,202 5,231,474 5,434,095 5,528,058 6,939,743 and foreign patents. US and Foreign patents pending. All Rights Reserved. 050-4912 Rev D 4-2009 The +VDD inputs (2,6) are by-passed (C1, C2, C4-C9), this is in addition to the internal by-passing mentioned previously. The capacitors used for this function must be capable of supporting the RMS currents and frequency of the gate load. DRF100 Pin Assignments Pin 1 Ground Pin 2 U1 +Vdd Pin 3 FN Pin 4 U1 IN Pin 5 U1 SG Pin 6 U1 +Vdd Pin 7 Ground Pin 8 Source Pin 9 Drain Pin 10 Source 1.500 0.300 GAPS - 0.090" , 2 PLCS 0.275 0.200 0.370 0.200 10 9 8 0.040 0.275 0.125 R0.150 4 PLCS 0.125 0.320 Ø0.125 4 PLCS DRF100 0.250 0.250 1 0.275 LARGE LEADS - 0.200", 2 PLCS 2 3 4 5 6 0.300 7 GAPS - 0.050", 6 PLCS SMALL LEADS - 0.040", 3 PLCS MEDIUM LEADS - 0.065", 2 PLCS All dimensions are ± .005 050-4912 Rev D 4-2009 0.570 Figure 3, DRF100 Mechanical Outline .005" TYP. HALF HARD COPPER GOLD PLATED