Numonyx M36P0R9070E0ZAC 512 mbit (x16, multiple bank, multi-level, burst) flash memory 128 mbit (burst) psram, 1.8v supply, multi-chip package Datasheet

M36P0R9070E0
512 Mbit (x16, Multiple Bank, Multi-Level, Burst) Flash memory
128 Mbit (Burst) PSRAM, 1.8V supply, Multi-Chip Package
Feature summary
■
Multi-Chip Package
– 1 die of 512 Mbit (32Mb x 16, Multiple
Bank, Multi-Level, Burst) Flash Memory
– 1 die of 128Mbit (8Mb x16) PSRAM
■
Supply voltage
– VDDF = VCCP = VDDQ = 1.7 to 1.95V
– VPPF = 9V for fast program
■
Electronic signature
– Manufacturer Code: 20h
– Device Code: 8819
■
ECOPACK® package available
FBGA
TFBGA107 (ZAC)
■
Flash memory
■
■
■
■
Synchronous / Asynchronous Read
– Synchronous Burst Read mode:
108MHz, 66MHz
– Asynchronous Page Read mode
– Random Access: 96ns
Programming time
– 4.2µs typical Word program time using
Buffer Enhanced Factory Program
command
Memory organization
– Multiple bank memory array: 64 Mbit banks
– Four Extended Flash Array (EFA) Blocks of
64 Kbits
Dual operations
– program/erase in one Bank while read in
others
– No delay between read and write
operations
■
Security
– 2112-bit user programmable OTP Cells
– 64-bit unique device number
■
100,000 program/erase cycles per block
■
Common Flash Interface (CFI)
November 2007
Block locking
– All Blocks locked at power-up
– Any combination of Blocks can be locked
with zero latency
– WPF for Block Lock-Down
– Absolute Write Protection with VPPF = VSS
PSRAM
■
Access time: 70ns
■
User-selectable operating modes
– Asynchronous modes: Random Read, and
Write, Page Read
– Synchronous modes: NOR-Flash, Full
Synchronous (Burst Read and Write)
■
Asynchronous Page Read
– Page Size: 4, 8 or 16 Words
– Subsequent Read Within Page: 20ns
■
Burst Read
– Fixed Length (4, 8, 16 or 32 Words) or
Continuous
– Maximum Clock Frequency: 80MHz
■
Low Power Consumption
– Active Current: < 25mA
– Standby Current: 200µA
– Deep Power-Down Current: 10µA
■
Low Power Features
– Partial Array Self Refresh (PASR)
– Deep Power-Down (DPD) Mode
Rev 3
1/23
www.numonyx.com
1
Contents
M36P0R9070E0
Contents
1
Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1
Address inputs (A0-A24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2
Data input/output (DQ0-DQ15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3
Latch Enable (L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4
Clock (K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.5
Wait (WAIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.6
Flash Chip Enable input (EF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.7
Flash Output Enable inputs (GF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.8
Flash Write Enable (WF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.9
Flash Write Protect (WPF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.10
Flash Reset (RPF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.11
PSRAM Chip Enable input (EP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.12
PSRAM Write Enable (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.13
PSRAM Output Enable (GP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.14
PSRAM Upper Byte Enable (UBP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.15
PSRAM Lower Byte Enable (LBP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.16
PSRAM Configuration Register Enable (CRP) . . . . . . . . . . . . . . . . . . . . . 11
2.17
Deep Power-Down input (DPDF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.18
VDDF Supply Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.19
VCCP Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.20
VDDQ Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.21
VPPF Program Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.22
VSS Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2/23
M36P0R9070E0
Contents
6
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3/23
List of tables
M36P0R9070E0
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 7.
Table 8.
4/23
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Main operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
M36P0R9070E0
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
TFBGA connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
TFBGA107 8 × 11mm - 9 × 12 active ball array, 0.8mm pitch, package outline. . . . . . . . . 19
5/23
Summary description
1
M36P0R9070E0
Summary description
The M36P0R9070E0 combines two memory devices in one Multi-Chip Package:
●
512-Mbit Multiple Bank Flash memory (the M58PR512J).
●
128 Mbit PSRAM (the M69KB128AB).
The purpose of this document is to describe how the two memory components operate with
respect to each other. It should be read in conjunction with the M58PRxxxJ and
M69KB128AB datasheets, where all specifications required to operate the Flash memory
and PSRAM components are fully detailed. The M58PR512J and M69KB128AB datasheets
are available from www.numonyx.com.
Recommended operating conditions do not allow more than one memory to be active at the
same time.
The memory is offered in a Stacked TFBGA107 package. It is supplied with all the bits
erased (set to ‘1’).
Figure 1.
Logic diagram
VDDF
VDDQ
VCCP
VPPF
25
16
DQ0-DQ15
A0-A24
EF
WAIT
GF
WF
RPF
WPF
L
M36P0R9070E0
K
DPDF
EP
GP
WP
CRP
UBP
LBP
VSS
6/23
AI10845
M36P0R9070E0
Summary description
Table 1.
A0-A24
Signal names
(1)
Address Inputs
DQ0-DQ15
Common Data Input/Output
VDDQ
Common Flash and PSRAM Power Supply for I/O Buffers
VPPF
Flash Memory Optional Supply Voltage for Fast Program & Erase
VDDF
Flash Memory Power Supply
VCCP
PSRAM Power Supply
VSS
Ground
L
Latch Enable input
K
Burst Clock
WAIT
Wait Output
NC
Not Connected Internally
DU
Do Not Use as Internally Connected
Flash Memory
EF
Chip Enable input
GF
Output Enable Input
WF
Write Enable input
RPF
Reset input
WPF
Write Protect input
DPDF
Deep Power-Down
PSRAM
EP
Chip Enable Input
GP
Output Enable Input
WP
Write Enable Input
CRP
Configuration Register Enable Input
UBP
Upper Byte Enable Input
LBP
Lower Byte Enable Input
1. A23-A24 are Address Inputs for the Flash memory component only.
7/23
Summary description
Figure 2.
M36P0R9070E0
TFBGA connections (top view through package)
1
A
2
3
4
5
6
7
DU
NC
NC
NC
VCCP
DPDF
8
9
VSS
DU
B
DU
A4
A18
A19
VSS
VDDF
NC
A21
A11
C
NC
A5
LBP
A23
VSS
NC
K
A22
A12
D
VSS
A3
A17
A24
VPP
WP
EP
A9
A13
E
VSS
A2
A7
NC
WPF
L
A20
A10
A15
F
NC
A1
A6
UBP
RPF
WF
A8
A14
A16
G
VDDQ
A0
DQ8
DQ2
DQ10
DQ5
DQ13
WAIT
NC
H
VSS
GP
DQ0
DQ1
DQ3
DQ12
DQ14
DQ7
DU
J
DU
NC
GF
DQ9
DQ11
DQ4
DQ6
DQ15
VDDQ
K
NC
EF
NC
NC
NC
VCCP
NC
VDDQ
CRP
L
DU
VSS
VSS
VDDQ
VDDF
VSS
VSS
VSS
VSS
M
DU
NC
DU
DU
DU
DU
DU
DU
DU
AI11098b
8/23
M36P0R9070E0
2
Signal descriptions
Signal descriptions
See Figure 1., Logic diagram and Table 1., Signal names, for a brief overview of the signals
connected to this device.
2.1
Address inputs (A0-A24)
Addresses A0-A22 are common inputs for the Flash memory and PSRAM components.
Addresses A23 and A24 are inputs for Flash memory components only. The Address Inputs
select the cells in the memory array to access during Bus Read operations. During Bus
Write operations they control the commands sent to the Command Interface of the internal
state machine. The Flash memory is accessed through the Chip Enable signal (EF) and
through the Write Enable signal (WF), while the PSRAM is accessed through the Chip
Enable signal (EP) and the Write Enable signal (WP).
EF Low, and EP must not be Low at the same time.
2.2
Data input/output (DQ0-DQ15)
The Data I/O output the data stored at the selected address during a Bus Read operation or
input a command or the data to be programmed during a Bus Write operation.
For the PSRAM component, the upper Byte Data Inputs/Outputs (DQ8-DQ15) carry the
data to or from the upper part of the selected address when Upper Byte Enable (UBP) is
driven Low. The lower Byte Data Inputs/Outputs (DQ0-DQ7) carry the data to or from the
lower part of the selected address when Lower Byte Enable (LBP) is driven Low. When both
UBP and LBP are disabled, the Data Inputs/ Outputs are high impedance.
2.3
Latch Enable (L)
The Latch Enable pin is common to the Flash memory and PSRAM components.
For details of how the Latch Enable signal behaves, please refer to the datasheets of the
respective memory components: M69KB128AB for the PSRAM and M58PR512J for the
Flash memory.
2.4
Clock (K)
The Clock input pin is common to the Flash memory and PSRAM components.
For details of how the Clock signal behaves, please refer to the datasheets of the respective
memory components: M69KB128AB for the PSRAM and M58PR512J for the Flash
memory.
9/23
Signal descriptions
2.5
M36P0R9070E0
Wait (WAIT)
WAIT is an output pin common to the Flash memory and PSRAM components. However the
WAIT signal does not behave in the same way for the PSRAM and the Flash memory.
For details of how it behaves, please refer to the M69KB128AB datasheet for the PSRAM
and to the M58PR512J datasheet for the Flash memory.
2.6
Flash Chip Enable input (EF)
The Flash Chip Enable input activates the control logic, input buffers, decoders and sense
amplifiers of the Flash memory component selected. When Chip Enable is Low, VIL, and
Reset is High, VIH, the device is in active mode. When Chip Enable is at VIH the
corresponding Flash memory are deselected, the outputs are high impedance and the
power consumption is reduced to the standby level.
It is not allowed to have EF at VIL and EP at VIL at the same time. Only one memory
component can be enabled at a time.
2.7
Flash Output Enable inputs (GF)
The Output Enable pins control the data outputs during Flash memory Bus Read
operations.
2.8
Flash Write Enable (WF)
The Write Enable controls the Bus Write operation of the Flash memory Command
Interface. The data and address inputs are latched on the rising edge of Chip Enable or
Write Enable whichever occurs first.
2.9
Flash Write Protect (WPF)
Write Protect is an input that gives an additional hardware protection for each block. When
Write Protect is Low, VIL, Lock-Down is enabled and the protection status of the LockedDown blocks cannot be changed. When Write Protect is at High, VIH, Lock-Down is disabled
and the Locked-Down blocks can be locked or unlocked. (See the Lock Status Table in the
M58PR512J datasheet).
10/23
M36P0R9070E0
2.10
Signal descriptions
Flash Reset (RPF)
The Reset input provides a hardware reset of the Flash memories. When Reset is at VIL, the
memory is in Reset mode: the outputs are high impedance and the current consumption is
reduced to the Reset Supply Current IDD2. Refer to the M58PRxxxJ datasheet, for the value
of IDD2. After Reset all blocks are in the Locked state and the Configuration Register is
reset. When Reset is at VIH, the device is in normal operation. Exiting Reset mode the
device enters Asynchronous Read mode, but a negative transition of Chip Enable or Latch
Enable is required to ensure valid data outputs.
The Reset pin can be interfaced with 3V logic without any additional circuitry. It can be tied
to VRPH (refer to the M58PRxxxJ datasheet).
2.11
PSRAM Chip Enable input (EP)
The Chip Enable input activates the PSRAM when driven Low (asserted). When deasserted
(VIH), the device is disabled, and goes automatically in low-power Standby mode or Deep
Power-down mode.
2.12
PSRAM Write Enable (WP)
Write Enable, WP, controls the Bus Write operation of the PSRAM. When asserted (VIL), the
device is in Write mode and Write operations can be performed either to the configuration
registers or to the memory array.
2.13
PSRAM Output Enable (GP)
Output Enable, GP, provides a high speed tri-state control, allowing fast read/write cycles to
be achieved with the common I/O data bus.
2.14
PSRAM Upper Byte Enable (UBP)
The Upper Byte En-able, UBP, gates the data on the Upper Byte Data Inputs/Outputs (DQ8DQ15) to or from the upper part of the selected address during a Write or Read operation.
2.15
PSRAM Lower Byte Enable (LBP)
The Lower Byte Enable, LBP, gates the data on the Lower Byte Data Inputs/Outputs (DQ0DQ7) to or from the lower part of the selected address during a Write or Read operation.
If both LBP and UBP are disabled (High) during an operation, the device will disable the data
bus from receiving or transmitting data. Although the device will seem to be deselected, it
remains in an active mode as long as EP remains Low.
2.16
PSRAM Configuration Register Enable (CRP)
When this signal is driven High, VIH, Write operations load either the value of the Refresh
Configuration Register (RCR) or the Bus configuration register (BCR).
11/23
Signal descriptions
2.17
M36P0R9070E0
Deep Power-Down input (DPDF)
The Deep Power-Down input is used to place the device in a Deep Power-Down
mode.When the device is in Deep Power-Down mode, the memory cannot be modified and
data is protected.
For further details on how the Deep Power-Down input signal works, please refer to the
M58PR512J datasheet.
2.18
VDDF Supply Voltages
VDDF provides the power supply to the internal cores of the Flash memory. It is the main
power supply for all Flash memory operations (Read, Program and Erase).
2.19
VCCP Supply Voltage
VCCP provides the power supply to the internal core of the PSRAM device. It is the main
power supply for all PSRAM operations.
2.20
VDDQ Supply Voltage
VDDQ provides the power supply for the Flash memory and PSRAM I/O pins. This allows all
Outputs to be powered independently of the Flash memory and SRAM core power supplies,
VDDF and VCCP.
2.21
VPPF Program Supply Voltage
VPPF is both a control input and a power supply pin for the Flash memory. The two functions
are selected by the voltage range applied to the pin.
If VPPF is kept in a low voltage range (0V to VDDQ) VPPF is seen as a control input. In this
case a voltage lower than VPPLK gives an absolute protection against Program or Erase,
while VPPF > VPP1 enables these functions (see the M58PRxxxJ datasheet for the relevant
values). VPPF is only sampled at the beginning of a Program or Erase; a change in its value
after the operation has started does not have any effect and Program or Erase operations
continue.
If VPPF is in the range of VPPH it acts as a power supply pin. In this condition VPPF must be
stable until the Program/Erase algorithm is completed.
12/23
M36P0R9070E0
2.22
Signal descriptions
VSS Ground
VSS is the common ground reference for all voltage measurements in the Flash (core and
I/O Buffers) and PSRAM chips. It must be connected to the system ground.
Note:
Each Flash memory device in a system should have their supply voltage (VDDF) and the
program supply voltage VPPF decoupled with a 0.1µF ceramic capacitor close to the pin
(high frequency, inherently low inductance capacitors should be as close as possible to the
package). See Figure 5., AC measurement load circuit. The PCB track widths should be
sufficient to carry the required VPPF program and erase currents.
13/23
Functional description
3
M36P0R9070E0
Functional description
The PSRAM and Flash memory components have separate power supplies but share the
same grounds. They are distinguished by two Chip Enable inputs: EF for Flash and EP for
the PSRAM.
Recommended operating conditions do not allow more than one device to be active at a
time. The most common example is a simultaneous read operations on the Flash memory
and the PSRAM which would result in a data bus contention. Therefore it is recommended
to put the other devices in the high impedance state when reading the selected device.
Figure 3.
Functional block diagram
VDDF
VPPF
EF
GF
A23-A24
DPDF
WF
RPF
WPF
512 Mbit
Flash
Memory
A0-A22
DQ0-DQ15
WAIT
L
K
VCCP
EP
GP
VSS V
DDQ
128Mbit
PSRAM
WP
CRP
UBP
LBP
Ai11731
14/23
M36P0R9070E0
Table 2.
Main operating modes(1)
Flash memory
Operation
EF GF WF RPF
DPDF WAIT
(2)
(3)
L
Bus Read
VIL VIL VIH VIH de-a(4)
VIL(5)
Bus Write
(4)
VIL VIH VIL VIH de-a
(5)
Address Latch
VIL X VIH VIH de-a(4)
VIL
Output Disable VIL VIH VIH VIH de-a(4) Hi-Z
Standby
Reset
Deep PowerDown
VIH X
X
X
VIH
A0A17 DQ0- DQ8EP WP GP UBP LBP CRP A19 A18
A20- DQ7 DQ15
A22
Data Output
Data Input
PSRAM must be disabled
VIL
Data Output or
Hi-Z(6)
X
Hi-Z
Hi-Z
de-a(4)
Hi-Z
X
(4)
X
X
VIL de-a
Hi-Z
X
VIH X
X
VIH
a(7)
Hi-Z
X
Any PSRAM mode is allowed
Hi-Z
Hi-Z
Word Read
VIL VIL VIL VIL
Valid
Output Output
Valid Valid
Lower Byte
Read
VIH VIL VIH VIL VIL
Valid
Output
High-Z
Valid
Upper Byte
Read
VIL VIL VIH VIL
Valid
High-Z
Output
Valid
Word Write
X VIL VIL VIL
Valid
Input
Valid
Input
Valid
VIL X VIH VIL VIL
Valid
Input
Invalid
Valid
X VIL VIH VIL
Valid
Lower Byte
Write
PSRAM
Functional description
The Flash memory must
Low- VIL
be disabled
Z
VIL
Upper Byte
Write
Invalid
Input
Valid
Read CR (CR
Controlled
Method)
VIH VIL VIL VIL
Program CR
(CR
Controlled)(9)
VIH X
X
X
No Operation
X X
X
X
VIL
X
X
X
X
VIH X X
X
X
X
X
X
X
High-Z
VIH X X
X
X
VIL
X
X
X
High-Z
Deep PowerDown(10)
VIH
Any Flash memory mode
is allowed
Hi-Z
Standby
X
00(RCR)1
0(BCR)X1
(DIDR)(8)
X
00(RCR) BCR/
10(BCR) RCR
(8)
Data
BCR/RCR/
DIDR Content
High-Z
1. X = Don't care, de-a = de-asserted, a = asserted, CR = Configuration Register.
2. The DPDF signal polarity depends on the value of the ECR14 bit.
3. In the Flash memory the WAIT signal polarity is configured using the Set Configuration Register command.
4. If ECR15 is set to '0', the Flash memory cannot enter the Deep Power-Down mode, even if DPDF is asserted.
5. In the Flash memory L can be tied to VIH if the valid address has been previously latched.
6. Depends on GF.
7. ECR15 has to be set to ‘1’ for the Flash memory to enter Deep Power-Down.
8. A18 and A19 are used to select the BCR, RCR or DIDR registers.
9. BCR and RCR only.
10. Bit 4 of the Refresh Configuration Register must be set to ‘0’, bit 4 (BCR4) of the Bus Configuration Register must be set to
‘0’, and E has to be maintained High, VIH, during Deep Power-Down mode.
15/23
Maximum rating
4
M36P0R9070E0
Maximum rating
Stressing the device above the rating listed in the Absolute Maximum Ratings table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the Numonyx SURE Program
and other relevant quality documents.
Table 3.
Absolute maximum ratings
Value
Symbol
Unit
Min
Max
Ambient Operating Temperature
–30
85
°C
TBIAS
Temperature Under Bias
–30
85
°C
TSTG
Storage Temperature
–55
125
°C
VIO
Input or Output Voltage
–0.2
2.45
V
VDD
Supply Voltage
–0.2
2.45
V
Input/Output Supply Voltage
–0.2
2.45
V
Program Voltage
–1.0
11.5
V
Output Short Circuit Current
100
mA
Time for VPP at VPPH
100
hours
TA
VDDQ
VPP
IO
tVPPH
16/23
Parameter
M36P0R9070E0
5
DC and AC parameters
DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristics Tables that
follow, are derived from tests performed under the Measurement Conditions summarized in
Table 4., Operating and AC measurement conditions. Designers should check that the
operating conditions in their circuit match the operating conditions when relying on the
quoted parameters.
Table 4.
Operating and AC measurement conditions
Flash memory
PSRAM
Parameter
Unit
Min
Max
Min
Max
VCCP Supply Voltage
–
–
1.7
1.95
V
VDDF Supply Voltage
1.7
1.95
–
–
V
VDDQ Supply Voltage
1.7
1.95
1.7
1.95
V
VPPF Supply Voltage (Factory environment)
8.5
9.5
–
–
V
VPPF Supply Voltage (Application environment)
–0.4
VDDQ +0.4
–
–
V
Ambient Operating Temperature
–30
85
–30
85
°C
Load Capacitance (CL)
30
30
pF
Impedance Output (Z0)
50
Ω
Output Circuit Protection Resistance (R)
50
Ω
Input Rise and Fall Times
3
Input Pulse Voltages
Input and Output Timing Ref. Voltages
Figure 4.
2
ns
0 to VDDQ
0 to VDDQ
V
VDDQ/2
VDDQ/2
V
AC measurement I/O waveform
VDDQ
VDDQ/2
0V
AI06161
17/23
DC and AC parameters
Figure 5.
M36P0R9070E0
AC measurement load circuit
VCCQ/2
R
DEVICE
UNDER
TEST
OUT
Z0
CL
AI06162a
Table 5.
Capacitance(1)
Symbol
Parameter
Test Condition
CIN
Input Capacitance
COUT
Output Capacitance
Min
Max
Unit
VIN = 0V
14
pF
VOUT = 0V
14
pF
1. Sampled only, not 100% tested.
Please refer to the M58PRxxxJ and M69KB128AB datasheets for further DC and AC
characteristic values and illustrations.
18/23
M36P0R9070E0
6
Package mechanical
Package mechanical
In order to meet environmental requirements, Numonyx offers these devices in ECOPACK®
packages. These packages have a Lead-free second-level interconnect. The category of
Second-Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97.
The maximum ratings related to soldering conditions are also marked on the inner box label.
Figure 6.
TFBGA107 8 × 11mm - 9 × 12 active ball array, 0.8mm pitch, package
outline
D
D1
FD
e
ddd
SE
E E1
BALL "B1"
FE
A
e
b
A2
A1
BGA-Z85
1. Drawing is not to scale.
19/23
Package mechanical
Table 6.
M36P0R9070E0
Stacked TFBGA107 8 × 11mm - 9 × 12 active ball array, 0.8mm pitch,
package mechanical data
millimeters
inches
Symbol
Typ
Min
A
Typ
Min
1.20
A1
Max
0.047
0.20
0.008
A2
0.85
0.033
b
0.35
0.30
0.40
0.014
0.012
0.016
D
8.00
7.90
8.10
0.315
0.311
0.319
D1
6.40
0.252
ddd
20/23
Max
0.10
10.90
11.10
0.004
E
11.00
0.433
E1
8.80
0.346
e
0.80
0.031
FD
0.80
0.031
FE
1.10
0.043
SE
0.40
0.016
0.429
0.437
M36P0R9070E0
7
Part numbering
Part numbering
Table 7.
Ordering information scheme
M36 P
Example:
Device Type
M36 = Multi-Chip Package (Multiple Flash + PSRAM)
0
R
9
0
7
0
E
0
ZAC
E
Flash 1 Architecture
P = Multi-Level, Multiple Bank, Large Buffer
Flash 2 Architecture
0 = No Die
Operating Voltage
R = VDDF = VCCP = VDDQ = 1.7 to 1.95V
Flash 1 Density
9 = 512 Mbits
Flash 2 Density
0 = No Die
RAM 1 Density
7 = 128 Mbits
RAM 0 Density
0 = No Die
Parameter Blocks Location
E = Even Block Flash Memory Configuration
Product Version
0 = 90nm Flash technology, 96ns speed; PSRAM
Package
ZAC= stacked TFBGA107 C stacked footprint.
Option
Blank = Standard Packing
E = ECOPACK® Package, Standard packing
F = ECOPACK® Package, Tape & Reel packing
Note:
Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of
available options (Speed, Package, etc.) or for further information on any aspect of this
device, please contact the Numonyx Sales Office nearest to you.
21/23
Revision history
8
M36P0R9070E0
Revision history
Table 8.
22/23
Document revision history
Date
Revision
Changes
28-Nov-2005
1
Initial release.
13-Jul-2006
2
Document status promoted from Preliminary data to full Datasheet.
Document updated to latest version of M58PRxxxJ datasheet, DC
characteristics tables removed (for values refer to M58PRxxxJ and
M69KB128AB datasheets). PSRAM part replaced by M69KB128AB.
H9 ball is DU in Figure 2: TFBGA connections (top view through
package). TSTG min and VPP max modified in Table 3: Absolute
maximum ratings. Table 2: Main operating modes modified.
PSRAM value for Input Rise and Fall Times filled in in Table 4:
Operating and AC measurement conditions.
30-Nov-2007
3
Applied Numonyx branding.
M36P0R9070E0
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