LINER LTC1642 Hot swap controller Datasheet

LTC1642
Hot Swap Controller
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FEATURES
DESCRIPTIO
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The LTC®1642 is a 16-pin Hot SwapTM controller that
allows a board to be safely inserted and removed from a
live backplane. Using an external N-Channel pass transistor, the board supply voltage can be ramped up at an
adjustable rate. A high side switch driver controls the
N-Channel gate for supply voltages above 2.97V.
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■
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■
■
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Adjustable Undervoltage and Overvoltage
Protection
Foldback Current Limit
Adjustable Current Limit Time-Out
Protected Against Surges to 33V
Single Channel NFET Driver
Latch Off or Automatic Retry on Current Fault
Driver for SCR Crowbar on Overvoltage
Adjustable Reset Timer
Reference Output with Uncommitted Comparator
16-Pin SSOP Package
The SENSE pin allows foldback limiting of the load current,
with circuit breaker action after an adjustable delay time.
The delay allows the part to power-up in current limit. The
CRWBR output can be used to trigger an SCR for crowbar
protection of the load if the input supply exceeds an
adjustable threshold. The RESET output can generate a
system reset with adjustable delay when the supply
voltage falls below an adjustable threshold. The ON
pin cycles the board power. The LTC1642 is available in
the 16-pin SSOP package.
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APPLICATIO S
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■
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Hot Board Insertion
Electronic Circuit Breaker
InfiniBandTM Systems
, LTC and LT are registered trademarks of Linear Technology Corporation. Hot Swap is
a trademark of Linear Technology Corporation. All other trademarks are the property of
their respective owners.
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TYPICAL APPLICATIO
BACKPLANE
0.010Ω
5%
PLUG-IN CARD
FDS6630A
12V
+
(SHORT PIN)
110k
1%
100Ω
5%
VCC
UV = 10.8V
2.87k
1%
OV = 13.2V
11.3k
1%
SENSE
ON
107k
1%
0.047µF
GATE
LTC1642
POWER-GOOD = 11.4V
RESET
FB
MCR
12DC
CRWBR
COMP–
FAULT
2N2222
COMP+
13k
1%
COMPOUT
OV
GND BRK TMR
0.33µF
GND
CLOAD
330Ω
5%
1N4705
18V
12V
AT 2.5A
RST TMR
0.33µF
REF
0.1µF
0.01µF
1642 TA01
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LTC1642
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ABSOLUTE
AXI U RATI GS
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PACKAGE/ORDER I FOR ATIO
(Note 1)
TOP VIEW
Supply Voltage (VCC) .................................– 0.3V to 33V
SENSE Pin ................................... – 0.3V to (VCC + 0.3V)
ON, FB, OV, COMP +, COMP –
RESET, FAULT, COMPOUT .....................– 0.3V to 18.5V
Operating Temperature Range
LTC1642C ............................................... 0°C to 70°C
LTC1642I ............................................ – 40°C to 85°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
CRWBR 1
16 VCC
BRK TMR 2
15 SENSE
RST TMR 3
14 GATE
ON 4
13 REF
RESET 5
12 COMP –
FAULT 6
11 COMP +
FB 7
10 COMPOUT
GND 8
9
OV
GN PACKAGE
16-LEAD PLASTIC SSOP
TJMAX = 150°C, θJA = 130°C/W
The LTC1642A is Recommended for Applications
Where VCC is Higher Than 12V.
ORDER PART NUMBER
GN PART MARKING
1642
1642I
LTC1642CGN
LTC1642IGN
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
DC ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
VCC = 5V unless otherwise specified.
SYMBOL
VCC
PARAMETER
Operating Voltage Range
CONDITIONS
TYP
MAX
16.5
UNITS
V
ICC
VLKHI
VCC Supply Current
VCC Undervoltage Lockout
ON = VCC
VCC Rising
●
●
2.55
1.25
2.73
3.0
2.95
mA
V
VLKLO
VLKHYST
VCC Undervoltage Lockout
VCC Undervoltage Lockout Hysteresis
VCC Falling
●
2.35
2.50
230
2.95
V
mV
VFB
∆VFB
FB Pin Voltage Threshold
FB Pin Threshold Supply Variation
FB Falling
FB Falling, 2.97V ≤ VCC ≤ 16.5V
●
1.208
●
1.220
5
1.232
15
V
mV
VFBHST
IFB(IN)
FB Pin Voltage Threshold Hysteresis
FB Pin Input Current
VOV = 5V
●
3
0
±1
mV
µA
VOV
∆VOV
OV Pin Voltage Threshold
OV Pin Threshold Supply Variation
OV Rising
OV Rising, 2.97V ≤ VCC ≤ 16.5V
●
●
1.220
5
1.232
15
V
mV
VOVHYST
IOV(IN)
OV Pin Voltage Threshold Hysteresis
OV Pin Input Current
VFB = 5V
●
3
0
±1
mV
µA
VRST
∆VRST
RST TMR Pin Voltage Threshold
RST TMR Pin Threshold Supply Variation
RST TMR Rising
RST TMR Rising, 2.97V ≤ VCC ≤ 16.5V
●
1.200
1.220
5
1.250
15
V
mV
IRST
RST TMR Pin Current
Timer On
Timer Off, VRSTTMR = 1.5V
●
– 1.5
– 2.0
10
– 2.5
µA
mA
VBRK
∆VBRK
BRK TMR Pin Voltage Threshold
BRK TMR Pin Threshold Supply Variation
BRK TMR Rising
BRK TMR Rising, 2.97V ≤ VCC ≤ 16.5V
●
1.200
1.220
5
1.250
15
V
mV
IBRK
BRK TMR Pin Current
Timer On
Timer Off, VBRKTMR = 1.5V
●
– 15
– 20
10
– 30
µA
mA
VCR
∆VCR
CRWBR Pin Voltage Threshold
CRWBR Pin Threshold Supply Variation
CRWBR Rising
2.97V ≤ VCC ≤ 16.5V
●
375
410
4
425
15
mV
mV
●
MIN
2.97
1.208
●
●
●
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LTC1642
DC ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
VCC = 5V unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
ICR
CRWBR Pin Current
●
●
– 30
–1000
Circuit Breaker Trip Voltage
●
●
15
45
– 45
–1500
2.3
25
52.5
– 60
VCB
CRWBR On, VCRWBR = 0V
CRWBR On, VCRWBR = 2.1V
CRWBR Off, VCRWBR = 1.5V
VCB = (VCC – VSENSE), VFB = GND
VCB = (VCC – VSENSE), VFB = 1V
2.97V ≤ VCC ≤ 16.5V,
VCB = (VCC – VSENSE), VFB = GND
VCB = (VCC – VSENSE), VFB = 1V
36
60
µA
µA
mA
mV
mV
●
●
12
42
25
52.5
39
63
mV
mV
VCC = VSENSE = 16.5V
Charge Pump On, VGATE = GND
Charge Pump Off, VGATE = 5V
VGATE – VCC, VCC = 2.97V
VGATE – VCC, VCC = 5V
VGATE – VCC, VCC = 15V
●
0.5
– 30
8.0
14
18
µA
µA
mA
V
V
V
1.38
1.26
V
V
ISENSE
IGATE
SENSE Pin Input Bias Current
GATE Pin Output Current
∆VGATE
External N-Channel Gate Drive
VONHI
VONLO
ON Pin Threshold
ON Pin Threshold
VONHYST
ION(IN)
ON Pin Hysteresis
ON Pin Input Current
VOL
Output Low Voltage
IPU
Logic Output Pull-Up Current
RESET, FAULT, COMPOUT IOL = 1.54mA ●
RESET, FAULT IO = 5mA
RESET, FAULT = GND
VREF
∆VLNR
Reference Output Voltage
Reference Supply Variation
No Load
2.97V ≤ VCC ≤ 16.5V, No Load
●
∆VLDR
IRSC
Reference Load Regulation
Reference Short-Circuit Current
IO = 0mA to –1mA, Sourcing Only
VREF = 0V
●
VCOS
VCHYST
Comparator Offset Voltage
Comparator Hysteresis
VCM = VREF
VCM = VREF
●
ON Rising
ON Falling
●
– 20
●
●
●
4.5
10
4.5
– 25
10
5.9
11.5
8.5
●
1.30
1.20
1.34
1.22
110
0
●
VON = 5V
mV
µA
±1
0.4
2
V
V
µA
1.220
5
1.232
15
V
mV
2.5
4.5
7.5
mV
mA
±10
mV
mV
– 15
1.208
●
3
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired.
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TYPICAL PERFOR A CE CHARACTERISTICS
∆VGATE vs VCC
∆VGATE vs Temperature
16
15
14
12
IGATE vs Temperature
30
TA = 25°C
VCC = 12V
28
12
VCC = 5V
VCC = 3V
VCC = 5V
VCC = 12V
VCC = 15V
29
VCC = 15V
8
6
IGATE (µA)
∆VGATE (V)
∆VGATE (V)
27
10
9
6
VCC = 3V
25
24
23
4
22
3
2
0
–50
26
21
–25
0
25
50
75
TEMPERATURE (°C)
100
125
1642 G03
0
3
6
9
VCC (V)
12
15
1642 G26
20
–50
VGATE = 0V
–25
0
25
50
75
TEMPERATURE (°C)
100
125
1642 G04
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LTC1642
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TYPICAL PERFOR A CE CHARACTERISTICS
GATE Pull-Down Current (Current
Limit Active)
IGATE Pull-Up Current vs VCC
CRWBR-TMR Threshold Voltage
vs Temperature
128
TA = 25°C
405
VCC = 12V
CRWBR–TMR THRESHOLD VOLTAGE (mV)
25
112
96
15
80
IGATE (A)
10
64
VCC = 5V
48
32
5
0
VGATE = 0V
TA = 25°C
16
0
3
6
VCC = 3.3V
9
VCC (V)
12
15
0
4
8
12
16
VGATE (V)
20
1.2
0.8
0.4
9
VCC (V)
12
1.43
1.42
1.41
1.40
1.39
1.38
–50
15
–25
OV THRESHOLD VOLTAGE (V)
1.220
1.216
1.212
1.208
12
15
1642 G27
125
0
25
50
75
TEMPERATURE (°C)
100
125
FB RISING
1.220
FB FALLING
1.218
1.216
1.214
–50
–25
0
25
50
75
TEMPERATURE (°C)
125
OV Threshold Voltage vs VCC
1.232
1.224
TA = 25°C
OV RISING
1.222
1.220
OV FALLING
1.218
1.216
1.214
–50
100
1642 G06
VCC = 5V
FB RISING
FB FALLING
100
1.222
OV Threshold Voltage vs
Temperature
1.228
0
25
50
75
TEMPERATURE (°C)
1.224
1.226
9
VCC (V)
–25
1642 G13
1.232
FB THRESHOLD VOLTAGE (V)
396
VCC = 5V
1.44
FB Threshold Voltage vs VCC
6
397
1.226
1642 G35
3
398
FB Threshold Voltage vs
Temperature
FB THRESHOLD VOLTAGE (V)
CRWBR DRIVER CURRENT (mA)
CRWBR DRIVER CURRENT (mA)
1.6
1.224
399
VCC = 5V
TA = 25°C
TA = 25°C
400
1642 G05
1.45
2.0
6
401
CRWBR Driver Current vs
Temperature
CRWBR Driver Current vs VCC
3
402
1642 G36
1642 G23
0
403
395
–50
24
OV THRESHOLD VOLTAGE (V)
IGATE (µA)
20
VCC = 5V
404
–25
0
25
50
75
TEMPERATURE (°C)
100
125
1642 G07
OV RISING
1.228
1.224
OV FALLING
1.220
1.216
1.212
1.208
3
6
9
VCC (V)
12
15
1642 G28
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LTC1642
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TYPICAL PERFOR A CE CHARACTERISTICS
FAULT and RESET VOL vs
Temperature
FAULT and RESET Pull-Up Current
(IOH) vs VCC
600
160
IOL = 5mA
3.0
500
TA = 25°C
80
60
40
TA = 125°C
6
9
VCC (V)
12
VCC = 3V
VCC = 5V
300
VCC = 12V
200
–25
0
25
50
75
TEMPERATURE (°C)
100
CURRENT LIMIT THRESHOLD VOLTAGE (mV)
CURRENT LIMIT THRESHOLD VOLTAGE (mV)
FB = 0V
VCC = 15V
26.5
VCC = 12V
26.0
VCC = 5V
25.5
VCC = 3V
25.0
0
25
50
75
TEMPERATURE (°C)
100
125
125
VCC = 15V
56.0
55.5
VCC = 12V
55.0
VCC = 5V
54.5
54.0
VCC = 3V
53.5
–50
–25
0
25
50
75
TEMPERATURE (°C)
100
125
1.36
ON RISING
1.32
1.28
1.24
ON FALLING
1.20
–50
∆VREF (mV)
ICC (mA)
VREF (V)
1.224
10
VON = 5V
1.216
1.212
VON = 0V
0
1642 G24
100
0
–2
–4
–6
–8
–10
–12
–14
–16
–18
–20
–22
– 42
0
125
Reference O/P Impedance
TA = 25°C
TA = 25°C
15
0
25
50
75
TEMPERATURE (°C)
1642 G22
1.228
12
–25
1642 G21
20
1.220
125
VCC = 12V
ICC vs VCC
9
VCC (V)
100
1.40
56.5
1.232
6
0
25
50
75
TEMPERATURE (°C)
ON Pin Threshold Voltage vs
Temperature
FB = 1V
VREF vs VCC
3
–25
1642 G17
57.0
1642 G20
1.208
VCC = 15V
0
–50
Current Limit Threshold Voltage
(Nominal) vs Temperature
27.5
–25
VCC = 12V
1642 G16
Current Limit Threshold Voltage
(Full Foldback) vs Temperature
24.5
–50
VCC = 5V
0.5
1642 G14
27.0
VCC = 3V
1.5
VCC = 15V
0
–50
15
2.0
1.0
100
20
3
2.5
400
VOLTAGE (V)
TA = –55°C
100
ON PIN THRESHOLD VOLTAGE (V)
120
VOLTAGE (mV)
PULL-UP CURRENT (µA)
3.5
IOL = 1.54mA
140
0
FAULT and RESET VOL vs
Temperature
25
VCC (V)
50
1642 G25
TA = 25°C
VCC = 5V
VCC = 3.3V
0
2.5
5
VCC = 12V,
15V
7.5 10 12.5 15 17.5 20
IREF (mA)
1642 G37
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LTC1642
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CRWBR (Pin 1): Overvoltage Crowbar Circuit Timer and
Trigger. This pin controls an external overvoltage crowbar
circuit. A capacitor from the pin to ground sets a 9ms/µF
delay after an overvoltage occurs until an external SCR is
triggered. See Applications Information. Ground the
CRWBR pin if unused.
BRK TMR (Pin 2): Circuit Breaker Timer. Connect a
capacitor from BRK TMR to ground to set a 60ms/µF delay
from the time the sense resistor current reaches its limit
until the FET is shut off. FAULT output is then asserted and
the FET remains off until the chip is reset. Ground BRK
TMR to allow the part to remain in current limit indefinitely.
RST TMR (Pin 3): Analog System/Reset Timer. A capacitor from this pin to ground sets a 0.6s/µF delay from the
ON pin going high to the start of the GATE pin’s ramp. It
also sets the delay from output voltage good, as sensed by
the FB pin, to RESET going high.
ON (Pin 4): ON Control Input. When ON is low the GATE
pin is grounded and FAULT goes high. The GATE pin
voltage starts ramping up one RST TMR timing cycle after
ON goes high. Pulsing the ON pin low for at least 2µs resets
the chip if it latches off after a sustained overvoltage or
current limit. The threshold for a low to high transition is
1.34V with 110mV of hysteresis. A 21V zener clamp limits
the voltage at this pin. The pin can be safely tied to VCC >
21V through a series resistor that limits the current below
1mA.
RESET (Pin 5): Open Drain Reset Output. RESET is pulled
low if the voltage at the FB pin is below its trip point. RESET
goes high one RESET timing cycle after the FB voltage
exceeds its trip point plus 3mV of hysteresis. RESET has
a weak pull-up to one diode drop below VCC and an external
resistor can pull the pin above VCC. A 21V zener clamp
limits the voltage at this pin. The pin can be safely tied to
VCC > 21V through a series resistor that limits the current
below 1mA.
FAULT (Pin 6): Open Drain Fault Output. FAULT is pulled
low when the part turns off following a sustained overvoltage or current limit. It goes high 2µs after the ON pin goes
low. FAULT has a weak pull-up to one diode drop below
VCC and an external resistor can pull the pin above VCC. A
21V zener clamp limits the voltage at this pin. The pin can
be safely tied to VCC > 21V through a series resistor that
limits the current below 1mA.
FB (Pin 7): Output Voltage Monitor and Foldback Input.
The FB comparator can be used with an external resistive
divider to monitor the output supply voltage. When the FB
voltage is lower than 1.22V the RESET pin is pulled low.
RESET goes high one system timing cycle after the voltage
at FB exceeds its threshold by 3mV of hysteresis. A low
pass filter at the comparator’s output prevents negative
voltage glitches from triggering a false reset.
GND (Pin 8): Chip Ground.
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LTC1642
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PI FU CTIO S
OV (Pin 9): Overvoltage Input. When the voltage on OV
exceeds its trip point the GATE pin is pulled low immediately and the CRWBR timer starts. If OV remains above its
trip point (minus 3mV of hysteresis) long enough for
CRWBR to reach its trip point, then the part turns off until
reset by pulsing the ON pin low. Otherwise, the GATE pin
begins ramping up one RST TMR timing cycle after OV
goes below its trip point. Ground the OV pin to disable
overvoltage protection.
gate to suppress high frequency oscillations. GATE is
immediately pulled to ground when the overvoltage comparator trips or the input supply is below the undervoltage
lockout trip point. During current limit the GATE voltage is
adjusted to maintain constant load current until the circuit
breaker timer trips. At that point GATE is pulled to ground
until the chip is reset. Clamp the GATE pin with an 18V
zener diode (IN4705) to ground if the supply is 8V
or higher.
COMPOUT (Pin 10): Uncommitted Comparator’s Open
Drain Output.
SENSE (Pin 15): Current Sense Input. To use the current
limit place a sense resistor in the supply path between VCC
and SENSE. When the drop across the resistor exceeds a
threshold voltage, the GATE pin is adjusted to maintain a
constant load current and the circuit breaker timer is
started. A foldback feature reduces the current limit as the
voltage at FB approaches ground. Short SENSE to VCC to
disable the current limiting.
COMP + (Pin 11): Uncommitted Comparator’s Noninverting Input.
COMP – (Pin 12): Uncommitted Comparator’s Inverting
Input.
REF (Pin 13): Reference Voltage Output. The 1.22V ±1%
reference should be bypassed with a 0.1µF compensation
capacitor. For VCC = 5V it can source 1mA.
GATE (Pin 14): Gate Drive for the External N-Channel
MOSFET. An internal charge pump provides at least 4.5V
of gate drive and sources 25µA. The pin requires an
external series RC network to ground to compensate the
current limit loop and to limit the ramp rate. A resistor of
100Ω is also recommended in series with the MOSFET
VCC (Pin 16): Positive Supply Voltage. An internal undervoltage lockout circuit holds the GATE pin at ground until
VCC exceeds 2.73V. If VCC exceeds 16.5V an internal shunt
regulator protects the chip from VCC and SENSE pin
voltages up to 33V. In this case the GATE pin voltage will
usually be low but this is not guaranteed; use the OV pin
to ensure that the pass device is off. The VCC pin also
provides a high side connection to the SENSE resistor.
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LTC1642
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BLOCK DIAGRA
GATE
14
VCC 16
CRWBR
1
VCC
+
21V
21V
–
–
–
21V
1.22V
+
21V
+
+
FB 7
+
13 REF
45µA
1.5mA
25µA
–
SENSE 15
1.22V
CHARGE PUMP
23mV TO 53mV
0.41V
–
VCC
RISING
DELAY
15µs TO
100µs
10µA AT 5V
+
OV 9
21V
1.22V
–
5 RESET
RISING
DELAY
15µs TO
100µs
21V
LOGIC
+
ON 4
21V
1.22V
–
VCC
RISING
DELAY
2µs
10µA AT 5V
+
VCC
2.7V
–
6 FAULT
RISING
DELAY
10µs
21V
20µA
2µA
10 COMPOUT
COMP + 11
+
COMP – 12
–
21V
+
21V
+
–
1.22V
–
1.22V
21V
21V
21V
2
3
BRK TMR
RST TMR
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LTC1642
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APPLICATIO S I FOR ATIO
Hot Circuit Insertion
When a circuit board is inserted into a live backplane its
supply bypass capacitors can draw large currents from the
backplane power bus as they charge. These currents can
permanently damage connector pins and can glitch the
backplane supply, resetting other boards in the system.
The LTC1642 limits the charging currents drawn by a
board’s capacitors, allowing safe insertion into a live
backplane.
In the circuit shown in Figure 1 the LTC1642 and the
external NMOS pass transistor Q1 work together to limit
charging currents. Waveforms at board insertion are
shown in Figure 2. When power is first applied to VCC the
chip holds Q1’s gate at ground. After an adjustable delay
a 25µA current source begins to charge the external
capacitor C2, so choose C2 to limit the inrush current
IINRUSH charging the board’s bypass capacitance CLOAD
according to the equation:
C2 = CLOAD •
IINRUSH
RST TMR
2V/DIV
16
VCC
4
Q1
FDS6630A
+
15
SENSE
ON
GATE
14
R10
30k
C4
0.33µF
BRK TMR
FAULT
RST TMR
GND
C1
0.33µF
3
R3
100Ω
R4
330Ω
C2
0.047µF
LTC1642
2
The second RST TMR cycle indicates that VOUT is within
tolerance; it is discussed in the Undervoltage Monitor
section.
OV
10V/DIV
R2
0.010Ω
R7
24k
tRSTTMR = (615ms/µF) C1.
25µA
An internal charge pump supplies the 25µA gate current,
ensuring sufficient gate drive to Q1. At 3V VCC the minimum
gate drive is 4.5V; at 5V VCC the minimum is 10V; at 15V VCC
the minimum is again 4.5V, due to an internal zener clamp
from the GATE pin to ground. Resistor R3 limits this zener’s
transient current during board insertion and removal and
protects against high frequency oscillations in Q1. D1
provides additional protection against supply spikes.
VIN
12V
2.5A
The delay before the GATE pin voltage begins ramping is
determined by the system timer. It comprises an external
capacitor C1 from the RST TMR pin to ground; an internal
2µA current source feeding RST TMR from VCC; an internal
comparator, with the noninverting input tied to RST TMR
and the inverting input tied to the 1.22V reference; and an
internal NMOS pull-down. In standby, the NMOS holds
RST TMR at ground. When the timer starts the NMOS
turns off and the RST TMR voltage ramps up as the current
source charges the capacitor. When RST TMR reaches
1.22V the timer comparator trips, the GATE voltage begins
ramping up and RST TMR returns to ground. The timer
delay is:
8
VOUT
CLOAD
D1
1N4705
18V
6
ALL RESISTORS ±5% UNLESS NOTED
RESET DELAY = 200ms
SHORT-CIRCUIT DURATION = 10ms
1642 F01
Figure 1. Supply Control Circuitry
GATE
20V/DIV
VOUT
20V/DIV
100ms/DIV
1642 F02
Figure 2. Timing at Board Insertion
Powering-Up in Current Limit
Ramping the GATE pin voltage limits the current to I =
25µA • CLOAD/C2, where C2 is the external capacitor
connected to the GATE and CLOAD is the load capacitance.
If the value of CLOAD is uncertain, then a worst-case design
can often result in needlessly long ramp times, and it may
be better to limit the charging current by powering up in
current limit.
Current Limiting and Solid-State Circuit Breaker
The current can be limited by connecting a sense resistor
between the LTC1642’s VCC and SENSE pins. When the
voltage drop across this resistor reaches a limiting value,
1642fb
9
LTC1642
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APPLICATIO S I FOR ATIO
an internal servo loop adjusts the GATE pin voltage such
that Q1 acts as a constant current source. The voltage limit
across R2 increases as the output charges; this foldback
in the current limit helps to even out Q1’s power dissipation. The output is sensed at the FB pin. When FB is
grounded, the sense voltage is limited to 26mV. When FB
is greater than 0.7V, the limit is 56mV and the full dependence is shown in Figure 3.
When the sense resistor voltage is 3mV below its limit, the
circuit breaker timer starts. Once BRK TMR reaches its
threshold, the circuit breaker opens, the GATE pin is pulled
to ground (cutting off Q1) and FAULT is asserted.
The parameter VCB specified in the DC electrical characteristics refers to the voltage difference between the VCC and
SENSE pins needed to start the circuit breaker timer. The
limiting value maintained by the servo loop is 3mV higher
than VCB.
Should the sense resistor voltage drop below its limit
before the timer trips, the GATE voltage begins ramping
back up immediately and the BRK TMR pin returns to
ground. However, due to the slow gate ramp, Q1 continues
to dissipate substantial power for some time. Connecting
R10 in series with timing capacitor C4 (as shown in
Figure 1) ensures that the circuit breaker trips in the event
of repetitive, but brief, load shorts. The delay before the
circuit breaker opens is:
tBRKTMR = C4 (61kΩ – R10).
pin low for at least 2µs and FAULT will go high. Then take
ON high again and the GATE will ramp up after a system
timing cycle. Or, configure the LTC1642 to restart itself
after the circuit breaker trips by connecting FAULT to the
ON pin, as shown in the next section.
The servo loop controlling Q1 during current limit has a
unity-gain frequency of about 125kHz. In Figure 1, R4 and
C2 provide compensation. To ensure stability the product
1/(2 • π • R4 • C2) should be kept below the unity-gain
frequency, and C2 should be more than Q1’s input capacitance CISS. A good starting point for C2 is 0.047µF and R4
is 330Ω. Keep R4 ≥ 100Ω.
Typical waveforms during a load short to ground are
shown in Figure 4. The load is shorted to ground at time 1.
The GATE voltage drops until the load current equals its
maximum limit, and the circuit breaker timer starts. The
short is cleared at time 2, before the timer trips. The BRK
TMR pin returns to ground, and the GATE voltage begins
ramping up. At time 3 the load is shorted again and at time
4 the timer trips, pulling the GATE to ground and asserting
FAULT. Although the short is cleared at time 5, FAULT
doesn’t go high until the ON pin is pulled low at time 6. At
time 7 ON goes high and the system timer starts. When it
trips at time 8 the GATE voltage begins ramping.
To disable current limit and electronic circuit breaker
protection, tie the SENSE pin to VCC, the BRK TMR pin to
GND and omit compensating resistor R4.
MAXIMUM SENSE RESISTOR VOLTAGE (mV)
Once the circuit breaker trips, GATE and FAULT remain at
ground until the chip is restarted. To restart, hold the ON
t2
t1
t4 t6
t3 t5 t7
t8
ILOAD
5A/DIV
GATE
20V/DIV
VOUT
20V/DIV
70
60
50
40
BRK TMR
30
2V/DIV
FAULT
20V/DIV
20
ON
20V/DIV
10
RST TMR
2V/DIV
40ms/DIV
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
FB PIN VOLTAGE (mV)
1
1642 F04
Figure 4. Current Limit and Circuit Breaker Timing
1642 F03
Figure 3. Foldback Current Limit
1642fb
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Automatic Restart After the Circuit Breaker Opens
The LTC1642 will automatically attempt to restart itself
after the circuit breaker opens if the FAULT output is tied
to the ON pin. The circuit is shown in Figure 5. Diode D1
blocks the weak FAULT pull-up current source from unbalancing the R6-R5 divider.
16
VCC
R6
464k
1%
4
6
D1
1N4148
During a continuous current limit such as a load short,
Q1’s duty cycle is equal to the circuit breaker timer period,
divided by the sum of the circuit breaker and system timer
periods:
Short - Circuit Duty Cycle =
Q1
FDS6630A
R2
0.015Ω
VIN
12V
2.5A
R5
60.4k
1%
R10
30k
2
GATE
3
14
R4
330Ω
GND
C1
0.33µF
8
ALL RESISTORS ±5% UNLESS NOTED
Undervoltage Lockout
VGATE
20V/DIV
An internal undervoltage lockout circuit holds the charge
pump off until VCC exceeds 2.73V. If VCC falls below 2.5V,
it turns off the charge pump and clears overvoltage and
current limit faults.
VOUT
10V/DIV
VBRKTMR
1V/DIV
For higher lockout thresholds tie the ON pin to a resistor
divider driven from VCC, as shown in Figure 7. This
circuit keeps the charge pump off until VCC exceeds
(1+R6/R5) • 1.34V, and also turns it off if VCC falls below
(1+R6/R5) • 1.22V.
VRSTTMR
1V/DIV
40ms/DIV
1642 F06
Figure 6. Automatic Retry Following a Load Short
R2
0.015Ω
16
Q1
FDS6630A
VOUT
+
15
SENSE
VCC
R6
464k
1%
1642 F05
Figure 5. Automatic Restart Circuit
The duty cycle is 9% for the Figure 5 circuit. Waveforms
during a load short are shown in Figure 6.
VIN
12V
2.5A
D2
1N4705
18V
C2
0.047µF
BRK TMR
RST TMR
CLOAD
R3
100Ω
FAULT
LTC1642
C4
0.33µF
C4
C 4 + 10 • C1
15
SENSE
ON
VOUT
+
CLOAD
R3
100Ω
LTC1642
UNDERVOLTAGE
LOCKOUT
THRESHOLD = 10.7V
4
R5
60.4k
1%
GATE
ON
14
D1
1N4705
18V
R4
330Ω
RST TMR
3
C1
0.33µF
GND
8
C2
0.047µF
1642 F07
ALL RESISTORS ±5% UNLESS NOTED
Figure 7. Setting a Higher Undervoltage Lockout
1642fb
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Overvoltage Protection
The LTC1642 can protect a load from overvoltages by
turning off the pass transistor if the supply voltage exceeds an adjustable limit, and by triggering a crowbar SCR
if the overvoltage lasts longer than an adjustable time. The
part can also be configured to automatically restart when
the overvoltage clears.
The overvoltage protection circuitry is shown in Figure 8.
The external components comprise a resistor divider
driving the OV pin, timing capacitor C5, NPN emitter
follower Q2, and crowbar SCR Q3. Because the MCR12DC
is not a sensitive-gate device, the optional resistor shunting the SCR gate to ground is omitted. The internal
components comprise a comparator, 1.22V bandgap reference, two current sources, and a timer at the CRWBR
pin. When VCC exceeds (1+R6/R5) • 1.22V the comparator’s
output goes high and internal logic turns off Q1 and starts
the timer. This timer has a 0.410V threshold and uses the
CRWBR pin; when CRWBR reaches 0.410V the timer
comparator trips, and the current sourced from VCC increases to 1.5mA. Emitter follower Q2 boosts this current
to trigger crowbar SCR Q3. The ramp time ∆t needed to
trip the comparator is:
tCRWBR = 9.1(ms/µF) C5
VIN
12V
2.5A
R2
0.015Ω
R6
127k
1%
9
16
VCC
GATE
6
14
R4
330Ω
C2
0.047µF
LTC1642
Q2
2N2222
ON
CRWBR
FAULT
RST TMR
3
C1
0.33µF
CLOAD
R3
100Ω
1
Figure 9 shows typical waveforms when the divider is
driven from VCC. The OV comparator goes high at time 1,
causing the chip to pull the GATE pin to ground and start
the CRWBR timer. At time 2, before the timer’s comparator trips, OV falls below its threshold; the timer resets and
GATE begins charging one system timing cycle later at
time 3. Another overvoltage begins at time 4, and at time
5 the CRWBR timer trips; FAULT goes low and the CRWBR
pin begins sourcing 1.5mA. Even after OV falls below
1.22V at time 6, GATE and FAULT stay low, and CRWBR
continues to source 1.5mA. FAULT goes high when ON
goes low at time 7, and GATE begins charging at time 8,
one RST TMR cycle after FAULT goes high.
Figure 10 shows typical waveforms when the OV divider is
driven from the N-Channel’s output side. Because the
voltage driving the divider collapses after the OV comparator trips, FAULT stays high and CRWBR stays near ground,
which prevents the pin from triggering an SCR. The GATE
voltage begins ramping up after a RST TMR timing cycle.
To disable overvoltage protection completely, tie the OV
and CRWBR pins to GND. For overvoltage protection at the
GATE pin, but without latch off or a crowbar SCR such as
Q3 in Figure 1, tie CRWBR to GND.
VOUT
+
15
SENSE
OV
R5
12.4k
1%
4
Q1
FDS6630A
Once the CRWBR timer trips the LTC1642 latches off: after
the overvoltage clears GATE and FAULT remain at ground
and CRWBR continues sourcing 1.5mA. To restart the part
after the overvoltage clears, hold the ON pin low for at least
2µs and then bring it high. The GATE voltage will begin
ramping up one system timing cycle later. The part will
restart itself if FAULT and ON are connected.
t1 t2
D1
1N4705
18V
Q3
MCR12DC
t3
t4
t5 t6 t7
t8
IN
20V/DIV
OV
2V/DIV
GATE
50V/DIV
OUT
20V/DIV
GND
8
C5
0.01µF
* ADD 220Ω RESISTOR IF
USING A SENSITIVE-GATE SCR
ALL RESISTORS ±5% UNLESS NOTED
OV COMPARATOR TRIPS AT VIN = 13.85V
RESET TIME = 200ms
CROWBAR DELAY TIME = 90µs
Figure 8. Overvoltage Protection Circuitry
1642 F08
CRWBR
1V/DIV
RST TMR
2V/DIV
ON
20V/DIV
FAULT
20V/DIV
100ms/DIV
1642 F09
Figure 9. Overvoltage Timing (Input Side)
1642fb
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If there is an overvoltage, and the resistor divider feeding
OV is connected to the output of the N-Channel pass
transistor, the LTC1642 will automatically restart even if
FAULT is not tied to ON. If the divider is connected to the
input side, the LTC1642 will restart itself only if FAULT is
tied to ON, and only after the overvoltage clears.
The OV and FB Comparators
The propagation delay through the OV and FB comparators on low to high transitions depends strongly on the
differential input voltage. The relationship is shown in
Figure 11. The minimum propagation delay for large
overdrives is about 20µs. In addition the comparators
have 3mV of hysteresis.
Internal Voltage Clamp Protection
The LTC1642 includes a shunt regulator to protect itself
from VCC and SENSE pin voltages up to 33V. The regulator
turns on when VCC exceeds 16.5V and limits most of the
chip’s circuitry to 15V. When it is on the chip functions
normally with one exception: if the charge pump is on, the
GATE voltage is usually near ground but this is not
guaranteed. Use the OV pin to ensure that GATE is grounded.
IN
20V/DIV
OV
2V/DIV
GATE
20V/DIV
OUT
20V/DIV
CRWBR
2V/DIV
RST TMR
2V/DIV
FAULT
20V/DIV
100ms/DIV
1642 F10
Figure 10. Overvoltage Timing (Output Side)
The pull-up voltage on the RESET and FAULT pins follows
VCC until the shunt regulator turns on. When the regulator
is on the pull-up voltage is 14.4V.
Undervoltage Monitor
The LTC1642 will assert RESET if a monitored voltage falls
below an adjustable minimum. When the monitored voltage has exceeded its minimum for at least one system
timing cycle, RESET goes high. The monitoring circuitry
comprises an internal 1.22V bandgap reference, an internal precision voltage comparator and an external resistive
divider to monitor the output supply voltage.
The circuit is shown in Figure 12, and typical waveforms
in Figure 13. When the voltage at the FB pin rises above its
reset threshold (1.22V), the comparator output goes low
and a timing cycle starts (times 1 and 5). Following the
cycle RESET is pulled high. At time 2 the voltage at FB
drops below the comparator’s threshold and RESET is
pulled low. If the FB pin rises above the reset threshold for
less than a timing cycle the RESET output will remain low
(time 3 to time 4). The 15µA pull-up current source to VCC
on RESET has a series diode so the pin can be pulled above
VCC by an external pull-up resistor without forcing current
back into the supply.
OV COMPARATOR PROPAGATION DELAY (µs)
Automatic Restart
70
60
50
40
30
20
10
0
0
40
80
120
160
OV OVERDRIVE (mV)
200
240
1642 F11
Figure 11. OV Comparator Propagation Delay vs
Overdrive Voltage
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The undervoltage monitor behaves differently if FB is
above its threshold when the GATE begins ramping:
RESET goes high as soon as the GATE ramp begins.
RESET goes low immediately if VCC falls below the chip’s
2.5V internal undervoltage lockout threshold.
To disable the undervoltage monitor, tie FB to REF and
ground RESET.
R2
0.015Ω
VIN
12V
2.5A
16
VCC
4
ON
15
SENSE
CLOAD
R3
100Ω
14
R4
330Ω
C2
0.047µF
FB
RESET
VOUT
+
LTC1642
7
D1
1N4705
18V
R9
95.3k
1%
R8
12.4k
1%
t1
t2 t3
t4
t5
VIN
20V/DIV
VRSTTMR
1V/DIV
5
VRESET
10V/DIV
RST TMR GND
C1
0.33µF
The LTC1642’s internal voltage reference is buffered and
brought out to the REF pin. The buffer amplifier should be
compensated with a capacitor connected between REF
and ground. If no DC current is drawn from REF, 0.1µF
ensures an adequate phase margin, but the minimum
compensation increases if REF sources a substantial DC
current, as shown in Figure 14.
Q1
FDS6630A
GATE
3
Reference
8
1642 F12
ALL RESISTORS ±5% UNLESS NOTED.
FB COMPARATOR TRIPS AT VOUT = 10.7V
250ms/DIV
Figure 12. Undervoltage Monitoring Circuitry
1642 F09
Figure 13. Supply Monitor Waveforms
MINIMUM REF COMPENSATION (µF)
10.0
4.0
2.0
1.0
0.4
0.2
0.1
100µA
1mA
REFERENCE CURRENT
10mA
1642 F14
Figure 14. Minimum REF Compensation vs REF Current
1642fb
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Uncommitted Comparator
Layout Considerations
The uncommitted comparator has an open drain output.
The comparator has 3mV of hysteresis: the output goes
high when the differential input voltage exceeds 1.5mV
and goes low when the differential input is less than
–1.5mV.
One ounce copper exhibits a sheet resistance of 530µΩ
per square. To minimize self-heating, traces should be
at least 0.02" wide per ampere of current and 0.03" is
recommended.
The comparator’s input transistors are MOSFETs so the
input bias and offset currents are very small: typically
picoamps at 25°C, increasing to nanoamps at 90°C. If the
auxiliary comparator is unused, the COMP +, COMP – and
COMPOUT pins may be left floating.
In high current applications, the voltage drop along traces
can be appreciable. Connect the LTC1642’s VCC and
SENSE pins directly across sense resistor R2 to prevent
the power trace’s resistance from adding to R2. It is also
a good practice to keep the resistor divider to the ON pin
close to the chip and the divider’s connections to the VCC
and GND pins short. Figure 15 shows an example layout.
R2
ILOAD
LT1642
ON
R6
GND
VCC
TO SHORT
VCC PIN
SENSE
SENSE
RESISTOR, R2
R5
ILOAD
1642 F15
Figure 15. Recommended Layout for R1, R2 and R5
1642fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
15
LTC1642
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TYPICAL APPLICATIO
12V Hot Swap Circuit for InfiniBand Modules
InfiniBand
BACKPLANE
InfiniBand
MODULE
LONG
R2
Q1
DC/DC
CONVERTER
INPUT
VB_In
R6
127k
1%
D2
1N4705
18V
16
R5
SHORT 10.2k 1%
9
VBxEn_L
11
R4
330Ω
5%
R3
100Ω
R12
84.5k
1%
VCC
15
14
SENSE
GATE
10
COMPOUT
OV
COMP+
6
4
ON
REF
C7
0.01µF
COMP
13
C5
0.01µF
CRWBR RST TMR BRK TMR
12
1
3
C6
0.1µF
GND
2
C1*
0.033µF
TO CONVERTER'S
RUN/SS
7
FB
FAULT
–
UV
5
RESET
LTC1642
R11
12.4k
1%
R9
681k
1%
C2
0.047µF
D1*
1N4148
8
R8
100k
1%
30k
C4
0.033µF
LONG
TO DC/DC RETURN
VB_Ret
10k
LOCAL POWER
ENABLE
*INSTALL D1 FOR AUTOMATIC RESTART
IF USING D1, INCREASE C1
MODULE POWER
R2
Q1
25W
0.015Ω,5%
FDS6612†
0.007Ω,5%
FDS6680†
START-UP DELAY IS 20ms TYPICAL
CIRCUIT-BREAKER DELAY IS 1ms TYPICAL
50W
†FAIRCHILD
1642 TA02
(408) 822-2126
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PACKAGE DESCRIPTIO
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.189 – .196*
(4.801 – 4.978)
.015 ± .004
× 45°
(0.38 ± 0.10)
0° – 8°
TYP
.007 – .0098
(0.178 – 0.249)
.016 – .050
(0.406 – 1.270)
.0532 – .0688
(1.35 – 1.75)
.004 – .0098
(0.102 – 0.249)
.0250
(0.635)
BSC
.008 – .012
(0.203 – 0.305)
TYP
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
.229 – .244
(5.817 – 6.198)
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
.009
(0.229)
REF
16 15 14 13 12 11 10 9
.045 ±.005
.150 – .157**
(3.810 – 3.988)
1
2 3
4
5 6
7
8
.254 MIN
.150 – .165
.0165 ± .0015
.0250 BSC
RECOMMENDED SOLDER PAD LAYOUT
GN16 (SSOP) 0204
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1421
Hot Swap Controller
Two Supplies from 3V to 12V and –12V
LTC4211
Hot Swap Controller with Multifunction Current Control
Single Supply from 2.5V to 16.5V, MSOP Package
LT4250
Negative Voltage Hot Swap Controller in SO-8
– 48V Supplies, Active Current Limit
LTC1643
PCI-Bus Hot Swap Controller
3.3V, 5V, ±12V Supplies for PCI Bus, Active Current Limit
1642fb
16
Linear Technology Corporation
LT/LT 0805 REV B • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 1999