STMicroelectronics M50FW040 4 mbit 512kb x8, uniform block 3v supply firmware hub flash memory Datasheet

M50FW040
4 Mbit (512Kb x8, Uniform Block)
3V Supply Firmware Hub Flash Memory
FEATURES SUMMARY
■
■
■
■
■
■
■
■
■
SUPPLY VOLTAGE
– VCC = 3V to 3.6V for Program, Erase and
Read Operations
– VPP = 12V for Fast Erase (optional)
TWO INTERFACES
– Firmware Hub (FWH) Interface for
embedded operation with PC Chipsets.
– Address/Address Multiplexed (A/A Mux)
Interface for programming equipment
compatibility.
FIRMWARE HUB (FWH) HARDWARE
INTERFACE MODE
– 5 Signal Communication Interface
supporting Read and Write Operations
– Hardware Write Protect Pins for Block
Protection
– Register Based Read and Write
Protection
– 5 Additional General Purpose Inputs for
platform design flexibility
– Synchronized with 33MHz PCI clock
PROGRAMMING TIME: 10µs typical
8 UNIFORM 64 Kbyte MEMORY BLOCKS
PROGRAM/ERASE CONTROLLER
– Embedded Byte Program and Block
Erase algorithms
– Status Register Bits
PROGRAM and ERASE SUSPEND
– Read other Blocks during Program/Erase
Suspend
– Program other Blocks during Erase
Suspend
FOR USE in PC BIOS APPLICATIONS
ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code: 2Ch
November 2004
Figure 1. Packages
PLCC32 (K)
TSOP32 (NB)
8 x 14mm
TSOP40 (N)
10 x 20mm
1/41
M50FW040
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2.
Table 1.
Figure 3.
Table 2.
Figure 4.
Figure 5.
Figure 6.
Logic Diagram (FWH Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Signal Names (FWH Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Logic Diagram (A/A Mux Interface). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Signal Names (A/A Mux Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
PLCC Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
TSOP32 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
TSOP40 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Firmware Hub (FWH) Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Input/Output Communications (FWH0-FWH3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Input Communication Frame (FWH4).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Identification Inputs (ID0-ID3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
General Purpose Inputs (FGPI0-FGPI4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Interface Configuration (IC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Interface Reset (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
CPU Reset (INIT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Clock (CLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Top Block Lock (TBL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Write Protect (WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Reserved for Future Use (RFU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Address/Address Multiplexed (A/A Mux) Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . 10
Address Inputs (A0-A10). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Row/Column Address Select (RC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Ready/Busy Output (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Supply Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
VCC Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
VPP Optional Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
VSS Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 3. Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Firmware Hub (FWH) Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Bus Abort. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2/41
M50FW040
Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Block Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Address/Address Multiplexed (A/A Mux) Bus Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 4. FWH Bus Read Field Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 7. FWH Bus Read Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 5. FWH Bus Write Field Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 8. FWH Bus Write Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Read Memory Array Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Read Status Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Read Electronic Signature Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Clear Status Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Program/Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Program/Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 6. Read Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 7. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Program/Erase Controller Status (Bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Erase Suspend Status (Bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Erase Status (Bit 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Program Status (Bit 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
VPP Status (Bit 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Program Suspend Status (Bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Block Protection Status (Bit 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Reserved (Bit 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 8. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
FIRMWARE HUB (FWH) INTERFACE CONFIGURATION REGISTERS . . . . . . . . . . . . . . . . . . . . . . 19
Lock Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Write Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Read Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Lock Down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Firmware Hub (FWH) General Purpose Input Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Manufacturer Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Device Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Firmware Hub (FWH) General Purpose Input Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Manufacturer Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3/41
M50FW040
Device Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 9. Firmware Hub Register Configuration Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 10. Lock Register Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 11. General Purpose Inputs Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
PROGRAM AND ERASE TIMES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 12. Program and Erase Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 13. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 14. Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 15. FWH Interface AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 16. A/A Mux Interface AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 9. FWH Interface AC Testing Input Output Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 10.A/A Mux Interface AC Testing Input Output Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 17. Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 18. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 11.FWH Interface Clock Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 19. FWH Interface Clock Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 12.FWH Interface AC Signal Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 20. FWH Interface AC Signal Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 13.Reset AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 21. Reset AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 14.A/A Mux Interface Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 22. A/A Mux Interface Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 15.A/A Mux Interface Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 23. A/A Mux Interface Write AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 16.PLCC32 – 32 pin Rectangular Plastic Leaded Chip Carrier, Package Outline . . . . . . . . 31
Table 24. PLCC32 – 32 pin Rectangular Plastic Leaded Chip Carrier, Package Mechanical Data 32
Figure 17.TSOP32 – 32 lead Plastic Thin Small Outline, 8x14 mm, Package Outline . . . . . . . . . . 33
Table 25. TSOP32 – 32 lead Plastic Thin Small Outline, 8x14 mm, Package Mechanical Data. . . 33
Figure 18.TSOP40 – 40 lead Plastic Thin Small Outline, 10x20 mm, Package Outline . . . . . . . . . 34
Table 26. TSOP40 – 40 lead Plastic Thin Small Outline, 10x20 mm, Package Mechanical Data. . 34
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 27. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
FLOWCHARTS AND PSEUDO CODES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 19.Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 20.Program Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . 37
Figure 21.Erase Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4/41
M50FW040
Figure 22.Erase Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . 39
REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 28. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5/41
M50FW040
SUMMARY DESCRIPTION
The M50FW040 is a 4 Mbit (512Kb x8) non-volatile memory that can be read, erased and reprogrammed. These operations can be performed
using a single low voltage (3.0 to 3.6V) supply. For
fast erasing in production lines an optional 12V
power supply can be used to reduce the erasing
time.
The memory is divided into blocks that can be
erased independently so it is possible to preserve
valid data while old data is erased. Blocks can be
protected individually to prevent accidental Program or Erase commands from modifying the
memory. Program and Erase commands are written to the Command Interface of the memory. An
on-chip Program/Erase Controller simplifies the
process of programming or erasing the memory by
taking care of all of the special operations that are
required to update the memory contents. The end
of a program or erase operation can be detected
and any error conditions identified. The command
set required to control the memory is consistent
with JEDEC standards.
Two different bus interfaces are supported by the
memory. The primary interface, the Firmware Hub
(or FWH) Interface, uses Intel’s proprietary FWH
protocol. This has been designed to remove the
need for the ISA bus in current PC Chipsets; the
M50FW040 acts as the PC BIOS on the Low Pin
Count bus for these PC Chipsets.
The secondary interface, the Address/Address
Multiplexed (or A/A Mux) Interface, is designed to
be compatible with current Flash Programmers for
production line programming prior to fitting to a PC
Motherboard.
The memory is offered in TSOP32 (8 x 14mm),
TSOP40 (10 x 20mm) and PLCC32 packages and
it is supplied with all the bits erased (set to ’1’).
Figure 2. Logic Diagram (FWH Interface)
Table 1. Signal Names (FWH Interface)
VCC VPP
4
4
FWH0FWH3
ID0-ID3
5
FGPI0FGPI4
WP
FWH4
TBL
M50FW040
CLK
IC
FWH0-FWH3
Input/Output Communications
FWH4
Input Communication Frame
ID0-ID3
Identification Inputs
FGPI0-FGPI4
General Purpose Inputs
IC
Interface Configuration
RP
Interface Reset
INIT
CPU Reset
CLK
Clock
TBL
Top Block Lock
WP
Write Protect
RFU
Reserved for Future Use. Leave
disconnected
VCC
Supply Voltage
VPP
Optional Supply Voltage for Fast
Erase Operations
VSS
Ground
NC
Not Connected Internally
RP
INIT
VSS
AI03623
6/41
M50FW040
Figure 3. Logic Diagram (A/A Mux Interface)
Table 2. Signal Names (A/A Mux Interface)
VCC VPP
11
8
DQ0-DQ7
A0-A10
RC
IC
M50FW040
RB
G
W
RP
IC
Interface Configuration
A0-A10
Address Inputs
DQ0-DQ7
Data Inputs/Outputs
G
Output Enable
W
Write Enable
RC
Row/Column Address Select
RB
Ready/Busy Output
RP
Interface Reset
VCC
Supply Voltage
VPP
Optional Supply Voltage for Fast
Program and Erase Operations
VSS
Ground
NC
Not Connected Internally
VSS
AI10719
A8
A9
RP
VPP
VCC
RC
A10
Figure 4. PLCC Connections
A/A Mux
FGPI2
FGPI3
RP
VPP
VCC
CLK
FGPI4
A/A Mux
1 32
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
FGPI1
FGPI0
WP
TBL
ID3
ID2
ID1
ID0
FWH0
9
M50FW040
25
IC (VIL)
NC
NC
VSS
VCC
INIT
FWH4
RFU
RFU
IC (VIH)
NC
NC
VSS
VCC
G
W
RB
DQ7
A/A Mux
DQ1
DQ2
VSS
DQ3
DQ4
DQ5
DQ6
FWH1
FWH2
VSS
FWH3
RFU
RFU
RFU
17
A/A Mux
AI03616
Note: Pins 27 and 28 are not internally connected.
7/41
M50FW040
Figure 5. TSOP32 Connections
A10
RC
VCC
VPP
RP
A9
A8
A7
A6
A5
A4
NC
NC
NC
VSS
IC
GPI4
CLK
VCC
VPP
RP
GPI3
GPI2
GPI1
GPI0
WP
TBL
1
8
9
M50FW040
16
32
INIT
FWH4/LFRAME
NC
RFU
RFU
RFU
RFU
G
W
NC
DQ7
DQ6
DQ5
DQ4
25
24
FWH3/LAD3
VSS
FWH2/LAD2
FWH1/LAD1
FWH0/LAD0
ID0
ID1
ID2
ID3/RFU
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3
17
A/A Mux
A/A Mux
NC
NC
NC
NC
IC (VIH)
AI10718
1. the RB pin is not available for the A/A Mux interface in the TSOP32 package.
Figure 6. TSOP40 Connections
A/A Mux
NC
IC (VIL)
NC
NC
NC
NC
FGPI4
NC
CLK
VCC
VPP
RP
NC
NC
FGPI3
FGPI2
FGPI1
FGPI0
WP
TBL
1
10
11
20
40
M50FW040
31
30
21
VSS
VCC
FWH4
INIT
RFU
RFU
RFU
RFU
RFU
VCC
VSS
VSS
FWH3
FWH2
FWH1
FWH0
ID0
ID1
ID2
ID3
VSS
VCC
W
G
RB
DQ7
DQ6
DQ5
DQ4
VCC
VSS
VSS
DQ3
DQ2
DQ1
DQ0
A0
A1
A2
A3
A/A Mux
NC
IC (VIH)
NC
NC
NC
NC
A10
NC
RC
VCC
VPP
RP
NC
NC
A9
A8
A7
A6
A5
A4
AI03617
8/41
M50FW040
SIGNAL DESCRIPTIONS
There are two different bus interfaces available on
this part. The active interface is selected before
power-up or during Reset using the Interface Configuration Pin, IC.
The signals for each interface are discussed in the
Firmware Hub (FWH) Signal Descriptions section
and the Address/Address Multiplexed (A/A Mux)
Signal Descriptions section below. The supply signals are discussed in the Supply Signal Descriptions section below.
Firmware Hub (FWH) Signal Descriptions
For the Firmware Hub (FWH) Interface see Figure
2., Logic Diagram (FWH Interface), and Table
1., Signal Names (FWH Interface).
Input/Output Communications (FWH0-FWH3). All
Input and Output Communication with the memory
take place on these pins. Addresses and Data for
Bus Read and Bus Write operations are encoded
on these pins.
Input Communication Frame (FWH4). The Input Communication Frame (FWH4) signals the
start of a bus operation. When Input Communication Frame is Low, VIL, on the rising edge of the
Clock a new bus operation is initiated. If Input
Communication Frame is Low, VIL, during a bus
operation then the operation is aborted. When Input Communication Frame is High, VIH, the current bus operation is proceeding or the bus is idle.
Identification Inputs (ID0-ID3). The Identification Inputs select the address that the memory responds to. Up to 16 memories can be addressed
on a bus. For an address bit to be ‘0’ the pin can
be left floating or driven Low, VIL; an internal pulldown resistor is included with a value of RIL. For
an address bit to be ‘1’ the pin must be driven
High, VIH; there will be a leakage current of ILI2
through each pin when pulled to VIH; see Table 18.
By convention the boot memory must have address ‘0000’ and all additional memories take sequential addresses starting from ‘0001’.
General Purpose Inputs (FGPI0-FGPI4). The General Purpose Inputs can be used as digital inputs
for the CPU to read. The General Purpose Inputs
Register holds the values on these pins. The pins
must have stable data from before the start of the
cycle that reads the General Purpose Input Register until after the cycle is complete. These pins
must not be left to float, they should be driven Low,
VIL, or High, VIH.
Interface Configuration (IC). The Interface Configuration input selects whether the Firmware Hub
(FWH) or the Address/Address Multiplexed (A/A
Mux) Interface is used. The chosen interface must
be selected before power-up or during a Reset
and, thereafter, cannot be changed. The state of
the Interface Configuration, IC, should not be
changed during operation.
To select the Firmware Hub (FWH) Interface the
Interface Configuration pin should be left to float or
driven Low, VIL; to select the Address/Address
Multiplexed (A/A Mux) Interface the pin should be
driven High, VIH. An internal pull-down resistor is
included with a value of RIL; there will be a leakage
current of ILI2 through each pin when pulled to VIH;
see Table 18.
Interface Reset (RP). The Interface Reset (RP)
input is used to reset the memory. When Interface
Reset (RP) is set Low, VIL, the memory is in Reset
mode: the outputs are put to high impedance and
the current consumption is minimized. When RP is
set High, VIH, the memory is in normal operation.
After exiting Reset mode, the memory enters
Read mode.
CPU Reset (INIT). The CPU Reset, INIT, pin is
used to Reset the memory when the CPU is reset.
It behaves identically to Interface Reset, RP, and
the internal Reset line is the logical OR (electrical
AND) of RP and INIT.
Clock (CLK). The Clock, CLK, input is used to
clock the signals in and out of the Input/Output
Communication Pins, FWH0-FWH3. The Clock
conforms to the PCI specification.
Top Block Lock (TBL). The Top Block Lock input is used to prevent the Top Block (Block 7) from
being changed. When Top Block Lock, TBL, is set
Low, VIL, Program and Erase operations in the
Top Block have no effect, regardless of the state
of the Lock Register. When Top Block Lock, TBL,
is set High, VIH, the protection of the Block is determined by the Lock Register. The state of Top
Block Lock, TBL, does not affect the protection of
the Main Blocks (Blocks 0 to 6).
Top Block Lock, TBL, must be set prior to a Program or Erase operation is initiated and must not
be changed until the operation completes or unpredictable results may occur. Care should be taken to avoid unpredictable behavior by changing
TBL during Program or Erase Suspend.
Write Protect (WP). The Write Protect input is
used to prevent the Main Blocks (Blocks 0 to 6)
from being changed. When Write Protect, WP, is
set Low, VIL, Program and Erase operations in the
Main Blocks have no effect, regardless of the state
of the Lock Register. When Write Protect, WP, is
set High, VIH, the protection of the Block determined by the Lock Register. The state of Write
Protect, WP, does not affect the protection of the
Top Block (Block 7).
Write Protect, WP, must be set prior to a Program
or Erase operation is initiated and must not be
changed until the operation completes or unpre9/41
M50FW040
dictable results may occur. Care should be taken
to avoid unpredictable behavior by changing WP
during Program or Erase Suspend.
Reserved for Future Use (RFU). These pins do
not have assigned functions in this revision of the
part. They must be left disconnected.
Address/Address Multiplexed (A/A Mux)
Signal Descriptions
For the Address/Address Multiplexed (A/A Mux)
Interface see Figure 2., Logic Diagram (FWH Interface), and Table 1., Signal Names (FWH Interface).
Address Inputs (A0-A10). The Address Inputs
are used to set the Row Address bits (A0-A10) and
the Column Address bits (A11-A18). They are
latched during any bus operation by the Row/Column Address Select input, RC.
Data Inputs/Outputs (DQ0-DQ7). The Data Inputs/Outputs hold the data that is written to or read
from the memory. They output the data stored at
the selected address during a Bus Read operation. During Bus Write operations they represent
the commands sent to the Command Interface of
the internal state machine. The Data Inputs/Outputs, DQ0-DQ7, are latched during a Bus Write
operation.
Output Enable (G). The Output Enable, G, controls the Bus Read operation of the memory.
Write Enable (W). The Write Enable, W, controls
the Bus Write operation of the memory’s Command Interface.
Row/Column Address Select (RC). The Row/
Column Address Select input selects whether the
Address Inputs should be latched into the Row Address bits (A0-A10) or the Column Address bits
(A11-A18). The Row Address bits are latched on
the falling edge of RC whereas the Column Address bits are latched on the rising edge.
Ready/Busy Output (RB). The Ready/Busy pin
gives the status of the memory’s Program/Erase
Controller. When Ready/Busy is Low, VOL, the
memory is busy with a Program or Erase operation
and it will not accept any additional Program or
Erase command except the Program/Erase Suspend command. When Ready/Busy is High, VOH,
the memory is ready for any Read, Program or
Erase operation.
Supply Signal Descriptions
The Supply Signals are the same for both interfaces.
10/41
VCC Supply Voltage. The VCC Supply Voltage
supplies the power for all operations (Read, Program, Erase etc.).
The Command Interface is disabled when the VCC
Supply Voltage is less than the Lockout Voltage,
VLKO. This prevents Bus Write operations from accidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the memory contents being altered will be invalid. After VCC
becomes valid the Command Interface is reset to
Read mode.
A 0.1µF capacitor should be connected between
the VCC Supply Voltage pins and the VSS Ground
pin to decouple the current surges from the power
supply. Both VCC Supply Voltage pins must be
connected to the power supply. The PCB track
widths must be sufficient to carry the currents required during program and erase operations.
VPP Optional Supply Voltage. The VPP Optional
Supply Voltage pin is used to select the Fast Erase
option of the memory and to protect the memory.
When VPP < VPPLK Program and Erase operations
cannot be performed and an error is reported in
the Status Register if an attempt to change the
memory contents is made. When VPP = VCC Program and Erase operations take place as normal.
When VPP = VPPH Fast Erase operations are
used. Any other voltage input to VPP will result in
undefined behavior and should not be used.
VPP should not be set to VPPH for more than 80
hours during the life of the memory.
VSS Ground. VSS is the reference for all the voltage measurements.
Table 3. Block Addresses
Size
(Kbytes)
Address Range
Block
Number
Block Type
64
70000h-7FFFFh
7
Top Block
64
60000h-6FFFFh
6
Main Block
64
50000h-5FFFFh
5
Main Block
64
40000h-4FFFFh
4
Main Block
64
30000h-3FFFFh
3
Main Block
64
20000h-2FFFFh
2
Main Block
64
10000h-1FFFFh
1
Main Block
64
00000h-0FFFFh
0
Main Block
M50FW040
BUS OPERATIONS
The two interfaces have similar bus operations but
the signals and timings are completely different.
The Firmware Hub (FWH) Interface is the usual interface and all of the functionality of the part is
available through this interface. Only a subset of
functions are available through the Address/Address Multiplexed (A/A Mux) Interface.
Follow the section Firmware Hub (FWH) Bus Operations below and the section Address/Address
Multiplexed (A/A Mux) Bus Operations below for a
description of the bus operations on each interface.
Firmware Hub (FWH) Bus Operations
The Firmware Hub (FWH) Interface consists of
four data signals (FWH0-FWH3), one control line
(FWH4) and a clock (CLK). In addition protection
against accidental or malicious data corruption
can be achieved using two further signals (TBL
and WP). Finally two reset signals (RP and INIT)
are available to put the memory into a known
state.
The data signals, control signal and clock are designed to be compatible with PCI electrical specifications. The interface operates with clock speeds
up to 33MHz.
The following operations can be performed using
the appropriate bus cycles: Bus Read, Bus Write,
Standby, Reset and Block Protection.
Bus Read. Bus Read operations read from the
memory cells, specific registers in the Command
Interface or Firmware Hub Registers. A valid Bus
Read operation starts when Input Communication
Frame, FWH4, is Low, VIL, as Clock rises and the
correct Start cycle is on FWH0-FWH3. On the following clock cycles the Host will send the Memory
ID Select, Address and other control bits on
FWH0-FWH3. The memory responds by outputting Sync data until the wait-states have elapsed
followed by Data0-Data3 and Data4-Data7.
Refer to Table 4., FWH Bus Read Field Definitions, and Figure 7., FWH Bus Read Waveforms,
for a description of the Field definitions for each
clock cycle of the transfer. See Table 20., FWH Interface AC Signal Timing Characteristics, and Figure 12., FWH Interface AC Signal Timing
Waveforms, for details on the timings of the signals.
Bus Write. Bus Write operations write to the
Command Interface or Firmware Hub Registers. A
valid Bus Write operation starts when Input Communication Frame, FWH4, is Low, VIL, as Clock
rises and the correct Start cycle is on FWH0FWH3. On the following Clock cycles the Host will
send the Memory ID Select, Address, other control
bits, Data0-Data3 and Data4-Data7 on FWH0-
FWH3. The memory outputs Sync data until the
wait-states have elapsed.
Refer to Table 5., FWH Bus Write Field Definitions, and Figure 8., FWH Bus Write Waveforms,
for a description of the Field definitions for each
clock cycle of the transfer. See Table 20., FWH Interface AC Signal Timing Characteristics, and Figure 12., FWH Interface AC Signal Timing
Waveforms, for details on the timings of the signals.
Bus Abort. The Bus Abort operation can be used
to immediately abort the current bus operation. A
Bus Abort occurs when FWH4 is driven Low, VIL,
during the bus operation; the memory will tri-state
the Input/Output Communication pins, FWH0FWH3.
Note that, during a Bus Write operation, the Command Interface starts executing the command as
soon as the data is fully received; a Bus Abort during the final TAR cycles is not guaranteed to abort
the command; the bus, however, will be released
immediately.
Standby. When FWH4 is High, VIH, the memory
is put into Standby mode where FWH0-FWH3 are
put into a high-impedance state and the Supply
Current is reduced to the Standby level, ICC1.
Reset. During Reset mode all internal circuits are
switched off, the memory is deselected and the
outputs are put in high-impedance. The memory is
in Reset mode when Interface Reset, RP, or CPU
Reset, INIT, is Low, VIL. RP or INIT must be held
Low, VIL, for tPLPH. The memory resets to Read
mode upon return from Reset mode and the Lock
Registers return to their default states regardless
of their state before Reset, see Table 10. If RP or
INIT goes Low, VIL, during a Program or Erase operation, the operation is aborted and the memory
cells affected no longer contain valid data; the
memory can take up to tPLRH to abort a Program
or Erase operation.
Block Protection. Block Protection can be
forced using the signals Top Block Lock, TBL, and
Write Protect, WP, regardless of the state of the
Lock Registers.
Address/Address Multiplexed (A/A Mux) Bus
Operations
The Address/Address Multiplexed (A/A Mux) Interface has a more traditional style interface. The signals consist of a multiplexed address signals (A0A10), data signals, (DQ0-DQ7) and three control
signals (RC, G, W). An additional signal, RP, can
be used to reset the memory.
The Address/Address Multiplexed (A/A Mux) Interface is included for use by Flash Programming
equipment for faster factory programming. Only a
11/41
M50FW040
subset of the features available to the Firmware
Hub (FWH) Interface are available; these include
all the Commands but exclude the Security features and other registers.
The following operations can be performed using
the appropriate bus cycles: Bus Read, Bus Write,
Output Disable and Reset.
When the Address/Address Multiplexed (A/A Mux)
Interface is selected all the blocks are unprotected. It is not possible to protect any blocks through
this interface.
Bus Read. Bus Read operations are used to output the contents of the Memory Array, the Electronic Signature and the Status Register. A valid
Bus Read operation begins by latching the Row
Address and Column Address signals into the
memory using the Address Inputs, A0-A10, and
the Row/Column Address Select RC. Then Write
Enable (W) and Interface Reset (RP) must be
High, VIH, and Output Enable, G, Low, VIL, in order
to perform a Bus Read operation. The Data Inputs/
Outputs will output the value, see Figure 14., A/A
Mux Interface Read AC Waveforms, and Table
22., A/A Mux Interface Read AC Characteristics,
for details of when the output becomes valid.
Bus Write. Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by latching the Row Address and Column
Address signals into the memory using the Address Inputs, A0-A10, and the Row/Column Address Select RC. The data should be set up on the
Data Inputs/Outputs; Output Enable, G, and Interface Reset, RP, must be High, VIH and Write Enable, W, must be Low, VIL. The Data Inputs/
Outputs are latched on the rising edge of Write Enable, W. See Figure 15., A/A Mux Interface Write
AC Waveforms, and Table 23., A/A Mux Interface
Write AC Characteristics, for details of the timing
requirements.
Output Disable. The data outputs are high-impedance when the Output Enable, G, is at VIH.
Reset. During Reset mode all internal circuits are
switched off, the memory is deselected and the
outputs are put in high-impedance. The memory is
in Reset mode when RP is Low, VIL. RP must be
held Low, VIL for tPLPH. If RP is goes Low, VIL, during a Program or Erase operation, the operation is
aborted and the memory cells affected no longer
contain valid data; the memory can take up to tPLRH to abort a Program or Erase operation.
Table 4. FWH Bus Read Field Definitions
Clock
Cycle
Number
Clock
Cycle
Count
Field
1
1
START
1101b
I
On the rising edge of CLK with FWH4 Low, the contents of FWH0FWH3 indicate the start of a FWH Read cycle.
2
1
IDSEL
XXXX
I
Indicates which FWH Flash Memory is selected. The value on FWH0FWH3 is compared to the IDSEL strapping on the FWH Flash
Memory pins to select which FWH Flash Memory is being addressed.
3-9
7
ADDR
XXXX
I
A 28-bit address phase is transferred starting with the most significant
nibble first.
10
1
MSIZE
0000b
I
Always 0000b (only single byte transfers are supported).
11
1
TAR
1111b
I
The host drives FWH0-FWH3 to 1111b to indicate a turnaround cycle.
12
1
TAR
1111b
(float)
O
The FWH Flash Memory takes control of FWH0-FWH3 during this
cycle.
13-14
2
WSYNC
0101b
O
The FWH Flash Memory drives FWH0-FWH3 to 0101b (short waitsync) for two clock cycles, indicating that the data is not yet available.
Two wait-states are always included.
15
1
RSYNC
0000b
O
The FWH Flash Memory drives FWH0-FWH3 to 0000b, indicating
that data will be available during the next clock cycle.
16-17
2
DATA
XXXX
O
Data transfer is two CLK cycles, starting with the least significant
nibble.
18
1
TAR
1111b
O
The FWH Flash Memory drives FWH0-FWH3 to 1111b to indicate a
turnaround cycle.
19
1
TAR
1111b
(float)
N/A
The FWH Flash Memory floats its outputs, the host takes control of
FWH0-FWH3.
12/41
FWH0- Memory
FWH3
I/O
Description
M50FW040
Figure 7. FWH Bus Read Waveforms
CLK
FWH4
FWH0-FWH3
START
IDSEL
ADDR
MSIZE
TAR
SYNC
DATA
TAR
1
1
7
1
2
3
2
2
Number of
clock cycles
AI03437
Table 5. FWH Bus Write Field Definitions
Clock
Cycle
Number
Clock
Cycle
Count
Field
FWH0FWH3
Memory
I/O
1
1
START
1110b
I
On the rising edge of CLK with FWH4 Low, the contents of
FWH0-FWH3 indicate the start of a FWH Write Cycle.
Description
2
1
IDSEL
XXXX
I
Indicates which FWH Flash Memory is selected. The value
on FWH0-FWH3 is compared to the IDSEL strapping on the
FWH Flash Memory pins to select which FWH Flash
Memory is being addressed.
3-9
7
ADDR
XXXX
I
A 28-bit address phase is transferred starting with the most
significant nibble first.
10
1
MSIZE
0000b
I
Always 0000b (single byte transfer).
11-12
2
DATA
XXXX
I
Data transfer is two cycles, starting with the least significant
nibble.
13
1
TAR
1111b
I
The host drives FWH0-FWH3 to 1111b to indicate a
turnaround cycle.
14
1
TAR
1111b
(float)
O
The FWH Flash Memory takes control of FWH0-FWH3
during this cycle.
15
1
SYNC
0000b
O
The FWH Flash Memory drives FWH0-FWH3 to 0000b,
indicating it has received data or a command.
16
1
TAR
1111b
O
The FWH Flash Memory drives FWH0-FWH3 to 1111b,
indicating a turnaround cycle.
17
1
TAR
1111b
(float)
N/A
The FWH Flash Memory floats its outputs and the host takes
control of FWH0-FWH3.
Figure 8. FWH Bus Write Waveforms
CLK
FWH4
FWH0-FWH3
Number of
clock cycles
START
IDSEL
ADDR
MSIZE
DATA
TAR
SYNC
TAR
1
1
7
1
2
2
1
2
AI03441
13/41
M50FW040
COMMAND INTERFACE
All Bus Write operations to the memory are interpreted by the Command Interface. Commands
consist of one or more sequential Bus Write operations.
After power-up or a Reset operation the memory
enters Read mode.
The commands are summarized in Table
7., Commands. Refer to Table 7. in conjunction
with the text descriptions below.
Read Memory Array Command. The Read Memory Array command returns the memory to its
Read mode where it behaves like a ROM or
EPROM. One Bus Write cycle is required to issue
the Read Memory Array command and return the
memory to Read mode. Once the command is issued the memory remains in Read mode until another command is issued. From Read mode Bus
Read operations will access the memory array.
While the Program/Erase Controller is executing a
Program or Erase operation the memory will not
accept the Read Memory Array command until the
operation completes.
Read Status Register Command. The Read Status Register command is used to read the Status
Register. One Bus Write cycle is required to issue
the Read Status Register command. Once the
command is issued subsequent Bus Read operations read the Status Register until another command is issued. See the section on the Status
Register for details on the definitions of the Status
Register bits.
Read Electronic Signature Command. The Read
Electronic Signature command is used to read the
Manufacturer Code and the Device Code. One
Bus Write cycle is required to issue the Read Electronic Signature command. Once the command is
issued subsequent Bus Read operations read the
Manufacturer Code or the Device Code until another command is issued.
After the Read Electronic Signature Command is
issued the Manufacturer Code and Device Code
can be read using Bus Read operations using the
addresses in Table 6.
Program Command. The Program command
can be used to program a value to one address in
the memory array at a time. Two Bus Write operations are required to issue the command; the second Bus Write cycle latches the address and data
in the internal state machine and starts the Program/Erase Controller. Once the command is issued subsequent Bus Read operations read the
Status Register. See the section on the Status
Register for details on the definitions of the Status
Register bits.
14/41
If the address falls in a protected block then the
Program operation will abort, the data in the memory array will not be changed and the Status Register will output the error.
During the Program operation the memory will
only accept the Read Status Register command
and the Program/Erase Suspend command. All
other commands will be ignored. Typical Program
times are given in Table 12.
Note that the Program command cannot change a
bit set at ‘0’ back to ‘1’ and attempting to do so will
not cause any modification on its value. The Erase
command must be used to set all of the bits in the
block to ‘1’.
See Figure 19., Program Flowchart and Pseudo
Code, for a suggested flowchart on using the Program command.
Erase Command. The Erase command can be
used to erase a block. Two Bus Write operations
are required to issue the command; the second
Bus Write cycle latches the block address in the internal state machine and starts the Program/Erase
Controller. Once the command is issued subsequent Bus Read operations read the Status Register. See the section on the Status Register for
details on the definitions of the Status Register
bits.
If the block is protected then the Erase operation
will abort, the data in the block will not be changed
and the Status Register will output the error.
During the Erase operation the memory will only
accept the Read Status Register command and
the Program/Erase Suspend command. All other
commands will be ignored. Typical Erase times
are given in Table 12.
The Erase command sets all of the bits in the block
to ‘1’. All previous data in the block is lost.
See Figure 21., Erase Flowchart and Pseudo
Code, for a suggested flowchart on using the
Erase command.
Clear Status Register Command. The Clear Status Register command can be used to reset bits 1,
3, 4 and 5 in the Status Register to ‘0’. One Bus
Write is required to issue the Clear Status Register
command. Once the command is issued the memory returns to its previous mode, subsequent Bus
Read operations continue to output the same data.
The bits in the Status Register are sticky and do
not automatically return to ‘0’ when a new Program
or Erase command is issued. If an error occurs
then it is essential to clear any error bits in the Status Register by issuing the Clear Status Register
command before attempting a new Program or
Erase command.
M50FW040
Program/Erase Suspend Command. The
Program/Erase Suspend command can be used to
pause a Program or Erase operation. One Bus
Write cycle is required to issue the Program/Erase
Suspend command and pause the Program/Erase
Controller. Once the command is issued it is necessary to poll the Program/Erase Controller Status
bit to find out when the Program/Erase Controller
has paused; no other commands will be accepted
until the Program/Erase Controller has paused.
After the Program/Erase Controller has paused,
the memory will continue to output the Status Register until another command is issued.
During the polling period between issuing the Program/Erase Suspend command and the Program/
Erase Controller pausing it is possible for the operation to complete. Once Program/Erase Controller Status bit indicates that the Program/Erase
Controller is no longer active, the Program Suspend Status bit or the Erase Suspend Status bit
can be used to determine if the operation has completed or is suspended. For timing on the delay between issuing the Program/Erase Suspend
command and the Program/Erase Controller
pausing see Table 12.
During Program/Erase Suspend the Read Memory Array, Read Status Register, Read Electronic
Signature and Program/Erase Resume commands will be accepted by the Command Interface. Additionally, if the suspended operation was
Erase then the Program command will also be accepted; only the blocks not being erased may be
read or programmed correctly.
See Figure 20., Program Suspend & Resume
Flowchart and Pseudo Code, and Figure
22., Erase Suspend & Resume Flowchart and
Pseudo Code, for suggested flowcharts on using
the Program/Erase Suspend command.
Program/Erase Resume Command. The
Program/Erase Resume command can be used to restart the Program/Erase Controller after a
Program/Erase Suspend operation has paused it.
One Bus Write cycle is required to issue the Program/Erase Resume command. Once the command is issued subsequent Bus Read operations
read the Status Register.
Table 6. Read Electronic Signature
Code
Address
Data
Manufacturer Code
00000h
20h
Device Code
00001h
2Ch
15/41
M50FW040
Command
Cycles
Table 7. Commands
Bus Write Operations
1st
2nd
Address
Data
Address
Data
Read Memory Array
1
X
FFh
Read Status Register
1
X
70h
1
X
90h
1
X
98h
2
X
40h
PA
PD
2
X
10h
PA
PD
Erase
2
X
20h
BA
D0h
Clear Status Register
1
X
50h
Program/Erase Suspend
1
X
B0h
Program/Erase Resume
1
X
D0h
1
X
00h
1
X
01h
1
X
60h
1
X
2Fh
1
X
C0h
Read Electronic Signature
Program
Invalid/Reserved
Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block.
Read Memory Array. After a Read Memory Array command, read the memory as normal until another command is issued.
Read Status Register. After a Read Status Register command, read the Status Register as normal until another command is issued.
Read Electronic Signature. After a Read Electronic Signature command, read Manufacturer Code, Device Code until another command is issued.
Erase, Program. After these commands read the Status Register until the command completes and another command is issued.
Clear Status Register. After the Clear Status Register command bits 1, 3, 4 and 5 in the Status Register are reset to ‘0’.
Program/Erase Suspend. After the Program/Erase Suspend command has been accepted, issue Read Memory Array, Read Status
Register, Program (during Erase suspend) and Program/Erase resume commands.
Program/Erase Resume. After the Program/Erase Resume command the suspended Program/Erase operation resumes, read the
Status Register until the Program/Erase Controller completes and the memory returns to Read Mode.
Invalid/Reserved. Do not use Invalid or Reserved commands.
16/41
M50FW040
STATUS REGISTER
The Status Register provides information on the
current or previous Program or Erase operation.
Different bits in the Status Register convey different information and errors on the operation.
To read the Status Register the Read Status Register command can be issued. The Status Register
is automatically read after Program, Erase and
Program/Erase Resume commands are issued.
The Status Register can be read from any address.
The Status Register bits are summarized in Status
Register Bits. Refer to Table 8. in conjunction with
the text descriptions below.
Program/Erase Controller Status (Bit 7). The Program/Erase Controller Status bit indicates whether
the Program/Erase Controller is active or inactive.
When the Program/Erase Controller Status bit is
‘0’, the Program/Erase Controller is active; when
the bit is ‘1’, the Program/Erase Controller is inactive.
The Program/Erase Controller Status is ‘0’ immediately after a Program/Erase Suspend command
is issued until the Program/Erase Controller pauses. After the Program/Erase Controller pauses the
bit is ‘1’.
During Program and Erase operation the Program/Erase Controller Status bit can be polled to
find the end of the operation. The other bits in the
Status Register should not be tested until the Program/Erase Controller completes the operation
and the bit is ‘1’.
After the Program/Erase Controller completes its
operation the Erase Status, Program Status, VPP
Status and Block Protection Status bits should be
tested for errors.
Erase Suspend Status (Bit 6). The Erase Suspend Status bit indicates that an Erase operation
has been suspended and is waiting to be resumed. The Erase Suspend Status should only be
considered valid when the Program/Erase Controller Status bit is ‘1’ (Program/Erase Controller
inactive); after a Program/Erase Suspend command is issued the memory may still complete the
operation rather than entering the Suspend mode.
When the Erase Suspend Status bit is ‘0’ the Program/Erase Controller is active or has completed
its operation; when the bit is ‘1’ a Program/Erase
Suspend command has been issued and the
memory is waiting for a Program/Erase Resume
command.
When a Program/Erase Resume command is issued the Erase Suspend Status bit returns to ‘0’.
Erase Status (Bit 5). The Erase Status bit can be
used to identify if the memory has applied the
maximum number of erase pulses to the block and
still failed to verify that the block has erased correctly. The Erase Status bit should be read once
the Program/Erase Controller Status bit is ‘1’ (Program/Erase Controller inactive).
When the Erase Status bit is ‘0’ the memory has
successfully verified that the block has erased correctly; when the Erase Status bit is ‘1’ the Program/Erase Controller has applied the maximum
number of pulses to the block and still failed to verify that the block has erased correctly.
Once the Erase Status bit is set to ‘1’ the it can
only be reset to ‘0’ by a Clear Status Register command or a hardware reset. If it is set to ‘1’ it should
be reset before a new Program or Erase command
is issued, otherwise the new command will appear
to fail.
Program Status (Bit 4). The Program Status bit
can be used to identify if the memory has applied
the maximum number of program pulses to the
byte and still failed to verify that the byte has programmed correctly. The Program Status bit should
be read once the Program/Erase Controller Status
bit is ‘1’ (Program/Erase Controller inactive).
When the Program Status bit is ‘0’ the memory has
successfully verified that the byte has programmed correctly; when the Program Status bit is
‘1’ the Program/Erase Controller has applied the
maximum number of pulses to the byte and still
failed to verify that the byte has programmed correctly.
Once the Program Status bit is set to ‘1’ it can only
be reset to ‘0’ by a Clear Status Register command or a hardware reset. If it is set to ‘1’ it should
be reset before a new Program or Erase command
is issued, otherwise the new command will appear
to fail.
VPP Status (Bit 3). The VPP Status bit can be
used to identify an invalid voltage on the VPP pin
during Program and Erase operations. The VPP
pin is only sampled at the beginning of a Program
or Erase operation. Indeterminate results can occur if VPP becomes invalid during a Program or
Erase operation.
When the VPP Status bit is ‘0’ the voltage on the
VPP pin was sampled at a valid voltage; when the
VPP Status bit is ‘1’ the VPP pin has a voltage that
is below the VPP Lockout Voltage, VPPLK, the
memory is protected; Program and Erase operation cannot be performed.
Once the VPP Status bit set to ‘1’ it can only be reset to ‘0’ by a Clear Status Register command or a
hardware reset. If it is set to ‘1’ it should be reset
before a new Program or Erase command is issued, otherwise the new command will appear to
fail.
17/41
M50FW040
Program Suspend Status (Bit 2). The Program
Suspend Status bit indicates that a Program operation has been suspended and is waiting to be resumed. The Program Suspend Status should only
be considered valid when the Program/Erase
Controller Status bit is ‘1’ (Program/Erase Controller inactive); after a Program/Erase Suspend command is issued the memory may still complete the
operation rather than entering the Suspend mode.
When the Program Suspend Status bit is ‘0’ the
Program/Erase Controller is active or has completed its operation; when the bit is ‘1’ a Program/
Erase Suspend command has been issued and
the memory is waiting for a Program/Erase Resume command.
When a Program/Erase Resume command is issued the Program Suspend Status bit returns to
‘0’.
Block Protection Status (Bit 1). The Block Protection Status bit can be used to identify if the Pro-
gram or Erase operation has tried to modify the
contents of a protected block. When the Block Protection Status bit is to ‘0’ no Program or Erase operations have been attempted to protected blocks
since the last Clear Status Register command or
hardware reset; when the Block Protection Status
bit is ‘1’ a Program or Erase operation has been attempted on a protected block.
Once it is set to ‘1’ the Block Protection Status bit
can only be reset to ‘0’ by a Clear Status Register
command or a hardware reset. If it is set to ‘1’ it
should be reset before a new Program or Erase
command is issued, otherwise the new command
will appear to fail.
Using the A/A Mux Interface the Block Protection
Status bit is always ‘0’.
Reserved (Bit 0). Bit 0 of the Status Register is
reserved. Its value should be masked.
Table 8. Status Register Bits
Operation
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
(1)
‘0’
‘0’
‘0’
‘0’
‘0’
Program active
‘0’
X
Program suspended
‘1
X(1)
‘0’
‘0’
‘0’
‘1’
‘0’
Program completed successfully
‘1’
X(1)
‘0’
‘0’
‘0’
‘0’
‘0’
Program failure due to VPP Error
‘1’
X(1)
‘0’
‘0’
‘1’
‘0’
‘0’
Program failure due to Block Protection (FWH Interface only)
‘1’
X(1)
‘0’
‘0’
‘0’
‘0’
‘1’
Program failure due to cell failure
‘1’
X(1)
‘0’
‘1’
‘0’
‘0’
‘0’
Erase active
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
Erase suspended
‘1’
‘1’
‘0’
‘0’
‘0’
‘0’
‘0’
Erase completed successfully
‘1’
‘0’
‘0’
‘0’
‘0’
‘0’
‘0’
Erase failure due to VPP Error
‘1’
‘0’
‘0’
‘0’
‘1’
‘0’
‘0’
Erase failure due to Block Protection (FWH Interface only)
‘1’
‘0’
‘0’
‘0’
‘0’
‘0’
‘1’
Erase failure due to failed cell(s) in block
‘1’
‘0’
‘1’
‘0’
‘0’
‘0’
‘0’
Note: 1. For Program operations during Erase Suspend Bit 6 is ‘1’, otherwise Bit 6 is ‘0’.
18/41
M50FW040
FIRMWARE HUB (FWH) INTERFACE CONFIGURATION REGISTERS
When the Firmware Hub Interface is selected several additional registers can be accessed. These
registers control the protection status of the
Blocks, read the General Purpose Input pins and
identify the memory using the Electronic Signature
codes. See Table 9. for the memory map of the
Configuration Registers.
Lock Registers
The Lock Registers control the protection status of
the Blocks. Each Block has its own Lock Register.
Three bits within each Lock Register control the
protection of each block, the Write Lock Bit, the
Read Lock Bit and the Lock Down Bit.
The Lock Registers can be read and written,
though care should be taken when writing as, once
the Lock Down Bit is set, ‘1’, further modifications
to the Lock Register cannot be made until cleared,
to ‘0’, by a reset or power-up.
See Table 10. for details on the bit definitions of
the Lock Registers.
Write Lock. The Write Lock Bit determines
whether the contents of the Block can be modified
(using the Program or Erase Command). When
the Write Lock Bit is set, ‘1’, the block is write protected; any operations that attempt to change the
data in the block will fail and the Status Register
will report the error. When the Write Lock Bit is reset, ‘0’, the block is not write protected through the
Lock Register and may be modified unless write
protected through some other means.
When VPP is less than VPPLK all blocks are protected and cannot be modified, regardless of the
state of the Write Lock Bit. If Top Block Lock, TBL,
is Low, VIL, then the Top Block (Block 7) is write
protected and cannot be modified. Similarly, if
Write Protect, WP, is Low, VIL, then the Main
Blocks (Blocks 0 to 6) are write protected and cannot be modified.
After power-up or reset the Write Lock Bit is always set to ‘1’ (write protected).
Read Lock. The Read Lock bit determines
whether the contents of the Block can be read
(from Read mode). When the Read Lock Bit is set,
‘1’, the block is read protected; any operation that
attempts to read the contents of the block will read
00h instead. When the Read Lock Bit is reset, ‘0’,
read operations in the Block return the data programmed into the block as expected.
After power-up or reset the Read Lock Bit is always reset to ‘0’ (not read protected).
Lock Down. The Lock Down Bit provides a
mechanism for protecting software data from sim-
ple hacking and malicious attack. When the Lock
Down Bit is set, ‘1’, further modification to the
Write Lock, Read Lock and Lock Down Bits cannot
be performed. A reset or power-up is required before changes to these bits can be made. When the
Lock Down Bit is reset, ‘0’, the Write Lock, Read
Lock and Lock Down Bits can be changed.
Firmware Hub (FWH) General Purpose Input
Register
The Firmware Hub (FWH) General Purpose Input
Register holds the state of the Firmware Hub Interface General Purpose Input pins, FGPI0-FGPI4.
When this register is read, the state of these pins
is returned. This register is read-only and writing to
it has no effect.
The signals on the Firmware Hub Interface General Purpose Input pins should remain constant
throughout the whole Bus Read cycle in order to
guarantee that the correct data is read.
Manufacturer Code Register
Reading the Manufacturer Code Register returns
the manufacturer code for the memory. The manufacturer code for STMicroelectronics is 20h. This
register is read-only and writing to it has no effect.
Device Code Register
Reading the Device Code Register returns the device code for the memory, 2Ch. This register is
read-only and writing to it has no effect.
Firmware Hub (FWH) General Purpose Input
Register
The Firmware Hub (FWH) General Purpose Input
Register holds the state of the Firmware Hub Interface General Purpose Input pins, FGPI0-FGPI4.
When this register is read, the state of these pins
is returned. This register is read-only and writing to
it has no effect.
The signals on the Firmware Hub Interface General Purpose Input pins should remain constant
throughout the whole Bus Read cycle in order to
guarantee that the correct data is read.
Manufacturer Code Register
Reading the Manufacturer Code Register returns
the manufacturer code for the memory. The manufacturer code for STMicroelectronics is 20h. This
register is read-only and writing to it has no effect.
Device Code Register
Reading the Device Code Register returns the device code for the memory, 2Ch. This register is
read-only and writing to it has no effect.
19/41
M50FW040
Table 9. Firmware Hub Register Configuration Map
Memory
Address
Default
Value
Access
Top Block Lock Register (Block 7)
FBF0002h
01h
R/W
T_MINUS01_LK
Top Block [-1] Lock Register (Block 6)
FBE0002h
01h
R/W
T_MINUS02_LK
Top Block [-2] Lock Register (Block 5)
FBD0002h
01h
R/W
T_MINUS03_LK
Top Block [-3] Lock Register (Block 4)
FBC0002h
01h
R/W
T_MINUS04_LK
Top Block [-4] Lock Register (Block 3)
FBB0002h
01h
R/W
T_MINUS05_LK
Top Block [-5] Lock Register (Block 2)
FBA0002h
01h
R/W
T_MINUS06_LK
Top Block [-6] Lock Register (Block 1)
FB90002h
01h
R/W
T_MINUS07_LK
Top Block [-7] Lock Register (Block 0)
FB80002h
01h
R/W
Firmware Hub (FWH) General Purpose Input Register
FBC0100h
N/A
R
Manufacturer Code Register
FBC0000h
20h
R
Device Code Register
FBC0001h
2Ch
R
Mnemonic
T_BLOCK_LK
FGPI_REG
MANUF_REG
DEV_REG
Register Name
Table 10. Lock Register Bit Definitions
Bit
Bit Name Value
7-3
2
1
0
Function
Reserved
Read-Lock
Lock-Down
Write-Lock
‘1’
Bus Read operations in this Block always return 00h.
‘0’
Bus read operations in this Block return the Memory Array contents. (Default value).
‘1’
Changes to the Read-Lock bit and the Write-Lock bit cannot be performed. Once a ‘1’ is
written to the Lock-Down bit it cannot be cleared to ‘0’; the bit is always reset to ‘0’ following
a Reset (using RP or INIT) or after power-up.
‘0’
Read-Lock and Write-Lock can be changed by writing new values to them. (Default value).
‘1’
Program and Erase operations in this Block will set an error in the Status Register. The
memory contents will not be changed. (Default value).
‘0’
Program and Erase operations in this Block are executed and will modify the Block contents.
Note: 1. Applies to Top Block Lock Register (T_BLOCK_LK) and Top Block [-1] Lock Register (T_MINUS01_LK) to Top Block [-7] Lock Register (T_MINUS07_LK).
Table 11. General Purpose Inputs Register Definition
Bit
Bit Name
Value
7-5
4
3
2
1
0
Function
Reserved
‘1’
Input Pin FGPI4 is at VIH
‘0’
Input Pin FGPI4 is at VIL
‘1’
Input Pin FGPI3 is at VIH
‘0’
Input Pin FGPI3 is at VIL
‘1’
Input Pin FGPI2 is at VIH
‘0’
Input Pin FGPI2 is at VIL
‘1’
Input Pin FGPI1 is at VIH
‘0’
Input Pin FGPI1 is at VIL
‘1’
Input Pin FGPI0 is at VIH
‘0’
Input Pin FGPI0 is at VIL
FGPI4
FGPI3
FGPI2
FGPI1
FGPI0
Note: 1. Applies to the General Purpose Inputs Register (FGPI-REG).
20/41
M50FW040
PROGRAM AND ERASE TIMES
The Program and Erase times are shown in Table
12.
Table 12. Program and Erase Times
Typ (1)
Max
Unit
Byte Program
10
200
µs
Block Program
0.4
5
sec
VPP = 12V ± 5%
0.75
8
sec
VPP = VCC
1
10
sec
Program/Erase Suspend to Program pause(2)
5
µs
Program/Erase Suspend to Block Erase pause(2)
30
µs
Parameter
Test Condition
Min
Block Erase
Note: 1. TA = 25°C, VCC = 3.3V
2. Sampled only, not 100% tested.
21/41
M50FW040
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings table may cause permanent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality documents.
Table 13. Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Unit
–65
150
°C
TSTG
Storage Temperature
TLEAD
Lead Temperature during Soldering
VIO (2)
Input or Output Voltage
–0.6
VCC + 0.6
V
VCC
Supply Voltage
–0.6
4
V
VPP
Program Voltage
–0.6
13
V
See note 1
°C
Note: 1. Compliant with JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST ECOPACK ® 7191395 specification, and
the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU.
2. Minimum Voltage may undershoot to –2V and for less than 20ns during transitions. Maximum Voltage may overshoot to VCC + 2V
and for less than 20ns during transitions.
22/41
M50FW040
DC AND AC PARAMETERS
This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and
AC characteristics Tables that follow, are derived
from tests performed under the Measurement
Conditions summarized in Table 14., Table 15.
and Table 16. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted
parameters.
Table 14. Operating Conditions
Symbol
TA
VCC
Parameter
Min
Max
Unit
Ambient Operating Temperature (Device Grade 1)
0
70
°C
Ambient Operating Temperature (Device Grade 5)
–20
85
°C
3
3.6
V
Supply Voltage
Table 15. FWH Interface AC Measurement Conditions
Parameter
Value
Unit
10
pF
≤ 1.4
ns
0.2 VCC and 0.6 VCC
V
0.4 VCC
V
Value
Unit
30
pF
Input Rise and Fall Times
≤ 10
ns
Input Pulse Voltages
0 to 3
V
1.5
V
Load Capacitance (CL)
Input Rise and Fall Times
Input Pulse Voltages
Input and Output Timing Ref. Voltages
Table 16. A/A Mux Interface AC Measurement Conditions
Parameter
Load Capacitance (CL)
Input and Output Timing Ref. Voltages
Figure 9. FWH Interface AC Testing Input Output Waveforms
0.6 VCC
0.4 VCC
0.2 VCC
Input and Output AC Testing Waveform
IO < ILO
IO > ILO
IO < ILO
Output AC Tri-state Testing Waveform
AI03404
23/41
M50FW040
Figure 10. A/A Mux Interface AC Testing Input Output Waveform
3V
1.5V
0V
AI01417
Table 17. Impedance
Symbol
Parameter
Test Condition
CIN(1)
Input Capacitance
VIN = 0V
CCLK(1)
Clock Capacitance
VIN = 0V
LPIN(2)
Recommended Pin
Inductance
Note: 1. Sampled only, not 100% tested.
2. See PCI Specification.
3. TA = 25 °C, f = 1 MHz).
24/41
Min
3
Max
Unit
13
pF
12
pF
20
nH
M50FW040
Table 18. DC Characteristics
Symbol
VIH
VIL
Parameter
Interface
Test Condition
Min
Max
Unit
FWH
0.5 VCC
VCC + 0.5
V
A/A Mux
0.7 VCC
VCC + 0.3
V
FWH
–0.5
0.3 VCC
V
A/A Mux
-0.5
0.8
V
Input High Voltage
Input Low Voltage
VIH(INIT)
INIT Input High Voltage
FWH
1.35
VCC + 0.5
V
VIL(INIT)
INIT Input Low Voltage
FWH
–0.5
0.2 VCC
V
ILI(2)
Input Leakage Current
0V ≤ VIN ≤ VCC
±10
µA
ILI2
IC, IDx Input Leakage
Current
IC, ID0, ID1, ID2, ID3 = VCC
200
µA
RIL
IC, IDx Input Pull Low
Resistor
100
kΩ
VOH
Output High Voltage
VOL
ILO
20
FWH
IOH = –500µA
0.9 VCC
V
A/A Mux
IOH = –100µA
VCC – 0.4
V
FWH
IOL = 1.5mA
0.1 VCC
V
A/A Mux
IOL = 1.8mA
0.45
V
0V ≤ VOUT ≤ VCC
±10
µA
Output Low Voltage
Output Leakage Current
VPP1
VPP Voltage
3
3.6
V
VPPH
VPP Voltage
(Fast Erase)
11.4
12.6
V
VPPLK(1)
VPP Lockout Voltage
1.5
VLKO(1)
VCC Lockout Voltage
1.8
V
2.3
V
ICC1
Supply Current (Standby)
FWH
FWH4 = 0.9 VCC, VPP = VCC
All other inputs 0.9 VCC to 0.1 VCC
VCC = 3.6V, f(CLK) = 33MHz
100
µA
ICC2
Supply Current (Standby)
FWH
FWH4 = 0.1 VCC, VPP = VCC
All other inputs 0.9 VCC to 0.1 VCC
VCC = 3.6V, f(CLK) = 33MHz
10
mA
ICC3
Supply Current
(Any internal operation
active)
FWH
VCC = VCC max, VPP = VCC
f(CLK) = 33MHz
IOUT = 0mA
60
mA
ICC4
Supply Current (Read)
A/A Mux
G = VIH, f = 6MHz
20
mA
Supply Current
(Program/Erase)
A/A Mux
Program/Erase Controller Active
20
mA
VPP Supply Current
(Read/Standby)
VPP > VCC
400
µA
VPP Supply Current
(Program/Erase active)
VPP = VCC
40
mA
VPP = 12V ± 5%
15
mA
ICC5(1)
IPP
IPP1(1)
Note: 1. Sampled only, not 100% tested.
2. Input leakage currents include High-Z output leakage for all bi-directional buffers with tri-state outputs.
25/41
M50FW040
Figure 11. FWH Interface Clock Waveform
tCYC
tHIGH
tLOW
0.6 VCC
0.5 VCC
0.4 VCC, p-to-p
0.4 VCC
(minimum)
0.3 VCC
0.2 VCC
AI03403
Table 19. FWH Interface Clock Characteristics
Symbol
Parameter
Test Condition
Value
Unit
tCYC
CLK Cycle Time(1)
Min
30
ns
tHIGH
CLK High Time
Min
11
ns
tLOW
CLK Low Time
Min
11
ns
Min
1
V/ns
Max
4
V/ns
CLK Slew Rate
peak to peak
Note: 1. Devices on the PCI Bus must work with any clock frequency between DC and 33MHz. Below 16MHz devices may be guaranteed
by design rather than tested. Refer to PCI Specification.
26/41
M50FW040
Figure 12. FWH Interface AC Signal Timing Waveforms
CLK
tCHQV
tCHQZ
tDVCH
tCHQX
tCHDX
FWH0-FWH3
VALID
VALID OUTPUT DATA
FLOAT OUTPUT DATA
VALID INPUT DATA
AI03405
Table 20. FWH Interface AC Signal Timing Characteristics
Symbol
PCI
Symbol
tCHQV
tval
CLK to Data Out
tCHQX(1)
ton
tCHQZ
Parameter
Test Condition
Value
Unit
Min
2
ns
Max
11
ns
CLK to Active
(Float to Active Delay)
Min
2
ns
toff
CLK to Inactive
(Active to Float Delay)
Max
28
ns
tAVCH
tDVCH
tsu
Input Set-up Time(2)
Min
7
ns
tCHAX
tCHDX
th
Input Hold Time(2)
Min
0
ns
Note: 1. The timing measurements for Active/Float transitions are defined when the current through the pin equals the leakage current specification.
2. Applies to all inputs except CLK.
27/41
M50FW040
Figure 13. Reset AC Waveforms
RP, INIT
tPLPH
W, G, FWH4
tPHWL, tPHGL, tPHFL
tPLRH
RB
AI03420
Table 21. Reset AC Characteristics
Symbol
Parameter
tPLPH
RP or INIT Reset Pulse Width
tPLRH
RP or INIT Low to Reset
RP or INIT Slew Rate(1)
tPHFL
RP or INIT High to FWH4 Low
tPHWL
tPHGL
RP High to Write Enable or Output
Enable Low
Note: 1. See Chapter 4 of the PCI Specification.
28/41
Test Condition
Value
Unit
Min
100
ns
Program/Erase Inactive
Max
100
ns
Program/Erase Active
Max
30
µs
Rising edge only
Min
50
mV/ns
FWH Interface only
Min
30
µs
A/A Mux Interface only
Min
50
µs
M50FW040
Figure 14. A/A Mux Interface Read AC Waveforms
tAVAV
ROW ADDR VALID
A0-A10
NEXT ADDR VALID
COLUMN ADDR VALID
tAVCL
tAVCH
tCLAX
tCHAX
RC
tCHQV
G
tGLQV
tGHQZ
tGLQX
tGHQX
DQ0-DQ7
VALID
W
tPHAV
RP
AI03406
Table 22. A/A Mux Interface Read AC Characteristics
Symbol
Parameter
Test Condition
Value
Unit
tAVAV
Read Cycle Time
Min
250
ns
tAVCL
Row Address Valid to RC Low
Min
50
ns
tCLAX
RC Low to Row Address Transition
Min
50
ns
tAVCH
Column Address Valid to RC high
Min
50
ns
tCHAX
RC High to Column Address Transition
Min
50
ns
tCHQV(1)
RC High to Output Valid
Max
150
ns
tGLQV(1)
Output Enable Low to Output Valid
Max
50
ns
tPHAV
RP High to Row Address Valid
Min
1
µs
tGLQX
Output Enable Low to Output Transition
Min
0
ns
tGHQZ
Output Enable High to Output Hi-Z
Max
50
ns
tGHQX
Output Hold from Output Enable High
Min
0
ns
Note: 1. G may be delayed up to tCHQV – tGLQV after the rising edge of RC without impact on tCHQV.
29/41
M50FW040
Figure 15. A/A Mux Interface Write AC Waveforms
Write erase or
program setup
A0-A10
R1
Write erase confirm or
valid address and data
C1
R2
tCLAX
tAVCH
tAVCL
Automated erase
or program delay
Read Status
Register Data
Ready to write
another command
C2
tCHAX
RC
tWHWL
tWLWH
tCHWH
W
tVPHWH
tWHGL
G
tWHRL
RB
tQVVPL
VPP
tDVWH
DQ0-DQ7
DIN1
tWHDX
DIN2
VALID SRD
AI04185
Table 23. A/A Mux Interface Write AC Characteristics
Symbol
Parameter
Test Condition
Value
Unit
tWLWH
Write Enable Low to Write Enable High
Min
100
ns
tDVWH
Data Valid to Write Enable High
Min
50
ns
tWHDX
Write Enable High to Data Transition
Min
5
ns
tAVCL
Row Address Valid to RC Low
Min
50
ns
tCLAX
RC Low to Row Address Transition
Min
50
ns
tAVCH
Column Address Valid to RC High
Min
50
ns
tCHAX
RC High to Column Address Transition
Min
50
ns
tWHWL
Write Enable High to Write Enable Low
Min
100
ns
tCHWH
RC High to Write Enable High
Min
50
ns
tVPHWH(1)
VPP High to Write Enable High
Min
100
ns
tWHGL
Write Enable High to Output Enable Low
Min
30
ns
tWHRL
Write Enable High to RB Low
Min
0
ns
Output Valid, RB High to VPP Low
Min
0
ns
tQVVPL(1,2)
Note: 1. Sampled only, not 100% tested.
2. Applicable if VPP is seen as a logic input (VPP < 3.6V).
30/41
M50FW040
PACKAGE MECHANICAL
Figure 16. PLCC32 – 32 pin Rectangular Plastic Leaded Chip Carrier, Package Outline
D
D1
A1
A2
1 N
B1
E2
E3
e
E1 E
F
B
0.51 (.020)
E2
1.14 (.045)
A
D3
R
D2
CP
D2
PLCC-A
Note: Drawing is not to scale.
31/41
M50FW040
Table 24. PLCC32 – 32 pin Rectangular Plastic Leaded Chip Carrier, Package Mechanical Data
millimeters
inches
Symbol
Typ
Min
Max
A
3.18
A1
Min
Max
3.56
0.125
0.140
1.53
2.41
0.060
0.095
A2
0.38
–
0.015
–
B
0.33
0.53
0.013
0.021
B1
0.66
0.81
0.026
0.032
CP
0.10
0.004
D
12.32
12.57
0.485
0.495
D1
11.35
11.51
0.447
0.453
D2
4.78
5.66
0.188
0.223
–
–
–
–
E
14.86
15.11
0.585
0.595
E1
13.89
14.05
0.547
0.553
E2
6.05
6.93
0.238
0.273
D3
7.62
0.300
E3
10.16
–
–
0.400
–
–
e
1.27
–
–
0.050
–
–
0.00
0.13
0.000
0.005
–
–
–
–
F
R
N
32/41
Typ
0.89
32
0.035
32
M50FW040
Figure 17. TSOP32 – 32 lead Plastic Thin Small Outline, 8x14 mm, Package Outline
A2
N
1
e
E
B
N/2
A
D1
CP
D
DIE
C
A1
TSOP-a
α
L
Note: Drawing is not to scale.
Table 25. TSOP32 – 32 lead Plastic Thin Small Outline, 8x14 mm, Package Mechanical Data
millimeters
inches
Symbol
Typ
Min
A
Max
Typ
Min
1.200
Max
0.0472
A1
0.050
0.150
0.0020
0.0059
A2
0.950
1.050
0.0374
0.0413
α
0°
5°
0°
5°
B
0.170
0.270
0.0067
0.0106
C
0.100
0.210
0.0039
0.0083
CP
0.100
0.0039
D
13.800
14.200
0.5433
0.5591
D1
12.300
12.500
0.4843
0.4921
–
–
–
–
E
7.900
8.100
0.3110
0.3189
L
0.500
0.700
0.0197
0.0276
N
32
e
0.500
0.0197
32
33/41
M50FW040
Figure 18. TSOP40 – 40 lead Plastic Thin Small Outline, 10x20 mm, Package Outline
A2
N
1
e
E
B
N/2
A
D1
CP
D
DIE
C
A1
TSOP-a
α
L
Note: Drawing is not to scale.
Table 26. TSOP40 – 40 lead Plastic Thin Small Outline, 10x20 mm, Package Mechanical Data
millimeters
inches
Symbol
Typ
Min
A
Typ
Min
1.200
Max
0.0472
A1
0.050
0.150
0.0020
0.0059
A2
0.950
1.050
0.0374
0.0413
B
0.170
0.270
0.0067
0.0106
C
0.100
0.210
0.0039
0.0083
CP
0.100
0.0039
D
19.800
20.200
0.7795
0.7953
D1
18.300
18.500
0.7205
0.7283
–
–
–
–
E
9.900
10.100
0.3898
0.3976
L
0.500
0.700
0.0197
0.0276
α
0°
5°
0°
5°
N
40
e
34/41
Max
0.500
0.0197
40
M50FW040
PART NUMBERING
Table 27. Ordering Information Scheme
Example:
M50FW040
K
1
T
G
Device Type
M50
Architecture
F = Firmware Hub Interface
Operating Voltage
W = 3V to 3.6V
Device Function
040 = 4 Mbit (x8), Uniform Block
Package
K = PLCC32
NB = TSOP32 (8 x 14mm)
N = TSOP40: 10 x 20 mm
Device Grade
5 = Temperature range –20 to 85 °C.
Device tested with standard test flow
1 = Temperature range 0 to 70 °C.
Device tested with standard test flow
Option
blank = Standard Packing
T = Tape & Reel Packing
Plating Technology
blank = Standard SnPb plating
G = Lead-Free, RoHS compliant, Sb2O3-free and TBBA-free
Devices are shipped from the factory with the memory content bits erased to ’1’.
For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device,
please contact the ST Sales Office nearest to you.
35/41
M50FW040
FLOWCHARTS AND PSEUDO CODES
Figure 19. Program Flowchart and Pseudo Code
Start
Program command:
– write 40h or 10h
– write Address & Data
(memory enters read status state after
the Program command)
Write 40h or 10h
Write Address
& Data
do:
–read Status Register if Program/Erase
Suspend command given execute
suspend program loop
NO
Read Status
Register
Suspend
b7 = 1
NO
YES
Suspend
Loop
while b7 = 1
YES
b3 = 0
NO
VPP Invalid
Error (1, 2)
If b3 = 1, VPP invalid error:
– error handler
NO
Program
Error (1, 2)
If b4 = 1, Program error:
– error handler
NO
Program to Protected
Block Error (1, 2)
YES
b4 = 0
YES
FWH
Interface
Only
b1 = 0
If b1 = 1, Program to protected block error:
– error handler
YES
End
AI03407
Note: 1. A Status check of b1 (Protected Block), b3 (VPP invalid) and b4 (Program Error) can be made after each Program operation by
following the correct command sequence.
2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.
36/41
M50FW040
Figure 20. Program Suspend & Resume Flowchart and Pseudo Code
Start
Write B0h
Program/Erase Suspend command:
– write B0h
– write 70h
Write 70h
do:
– read Status Register
Read Status
Register
b7 = 1
NO
while b7 = 1
YES
b2 = 1
NO
Program Complete
If b2 = 0 Program completed
YES
Write a read
Command
Read data from
another address
Write D0h
Write FFh
Program Continues
Read Data
Program/Erase Resume command:
– write D0h to resume the program
– if the Program operation completed
then this is not necessary.
The device returns to Read as
normal (as if the Program/Erase
suspend was not issued).
AI03408
37/41
M50FW040
Figure 21. Erase Flowchart and Pseudo Code
Start
Erase command:
– write 20h
– write Block Address & D0h
(memory enters read Status Register after
the Erase command)
Write 20h
Write Block Address
& D0h
Suspend
b7 = 1
do:
– read Status Register
– if Program/Erase Suspend command
given execute suspend erase loop
NO
Read Status
Register
NO
YES
Suspend
Loop
while b7 = 1
YES
b3 = 0
NO
VPP Invalid
Error (1)
NO
Command
Sequence Error (1)
If b3 = 1, VPP invalid error:
– error handler
YES
b4, b5 = 0
If b4, b5 = 1, Command sequence error:
– error handler
YES
b5 = 0
NO
Erase Error (1)
If b5 = 1, Erase error:
– error handler
YES
FWH
Interface
Only
b1 = 0
NO
Erase to Protected
Block Error (1)
If b1 = 1, Erase to protected block error:
– error handler
YES
End
AI03409
Note: 1. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.
38/41
M50FW040
Figure 22. Erase Suspend & Resume Flowchart and Pseudo Code
Start
Write B0h
Program/Erase Suspend command:
– write B0h
– write 70h
Write 70h
do:
– read Status Register
Read Status
Register
b7 = 1
NO
while b7 = 1
YES
b6 = 1
NO
Erase Complete
If b6 = 0, Erase completed
YES
Read data from
another block
or
Program
Write D0h
Write FFh
Erase Continues
Read Data
Program/Erase Resume command:
– write D0h to resume erase
– if the Erase operation completed
then this is not necessary.
The device returns to Read as
normal (as if the Program/Erase
suspend was not issued).
AI03410
39/41
M50FW040
REVISION HISTORY
Table 28. Document Revision History
Date
Version
September 2000
-01
First Issue
04-Oct-2000
-02
DC Characteristics: ICC4 changed
11-Apr-01
-03
Document type: from Preliminary Data to Data Sheet
Program and Erase functions clarification
Read Electronic Signature table change
FWH Register Configuration Map table change
Input Register Definition table, note clarification
DC Characteristics parameters clarification and new VIH and VIL parameters added
FWH Interface AC Signal Timing Characteristics change
A/A Mux Interface Read AC Characteristics change
A/A Mux Interface Write AC Characteristics change
A/A Mux Interface Write AC Waveforms change
06-Jul-2001
-04
Note 2 changed (Table 13., Absolute Maximum Ratings)
12-Mar-2002
-05
RFU pins must be left disconnected
Specification of PLCC32 package mechanical data revised
09-Jul-2004
6.0
Revision numbering modified.
Document imported in new template (and so reformatted).
Temperature Range ordering information replaced by Device Grade, Standard
packing option added and Plating Technology added to Table 27., Ordering
Information Scheme. TLEAD parameter added to Table 13., Absolute Maximum
Ratings and TBIAS parameter removed.
12-Jul-2004
7.0
Inches values corrected in Table 27., Ordering Information Scheme.
10-Nov-2004
8.0
TSOP32 package added. Figure 3., Logic Diagram (A/A Mux Interface) and Table
2., Signal Names (A/A Mux Interface) added.
40/41
Revision Details
M50FW040
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2004 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
41/41