Digital Controller for Isolated Power Supply with PMBus Interface ADP1051 Preliminary Technical Data FEATURES GENERAL DESCRIPTION Versatile, digital voltage mode controller High speed, input voltage feed-forward control 6 PWM logic outputs with 625ps resolution Switching frequency 50 kHz to 625 kHz Frequency synchronization master & slave Multiple energy saving modes Adaptive dead-time compensation for efficiency optimization Low device power consumption - typical 100 mW Direct Parallel operation • Accurate droop current share • Pre-bias start-up • Reverse current protection • Conditional over-voltage protection Extensive fault detection and protections Ultra compact package design 4*4mm 24-pin LFCSP PMBus Compliant Easy to use programming via Graphic User Interface (GUI) High reliability EEPROM for programming & data storage -40 °C ~ 125 °C operation temperature The ADP1051 is an advanced digital controller with PMBusTM interface targeting high density, high efficiency DCDC power conversion. This controller implements voltage mode control with high speed, input line feed-forward for enhanced transient and improved noise performance. The ADP1051 has 6 programmable PWM outputs capable of controlling most high efficiency power supply topologies with added control of synchronous rectification. The device includes adaptive dead-time compensation to improve the efficiency over the load range and programmable light load mode operation combined with low device power consumption to reduce system standby power losses. The ADP1051 implements several features to enable a robust system of parallel and redundant operation for customers that require high availability or parallel connection. The device includes master/slave synchronization, reverse current protection and prebias start-up, accurate current sharing between power supplies and conditional overvoltage techniques to identify and safely shutdown an erroneous power supply in parallel operation mode. The ADP1051 is based on flexible state machine architecture and is register programmed using an intuitive, graphical-user interface. The easy–to-use interface reduces design cycle time and results in a robust, hardware coded system loaded into the built-in EEPROM. The small size 4*4 mm LFCSP package makes the ADP1051 ideal for ultra-compact, isolated DCDC power module or embedded designs. APPLICATIONS High density, Isolated DC/DC power supplies • Intermediate bus converters • High availability parallel power systems Server, storage, industrial, networking, and communications infrastructure LOAD DC INPUT DRIVER SR1 SR2 VF CS2- CS2+ OVP VS+ VS- CS1 ADP1051 OUTA DRIVER iCoupler SYNI/FLGI OUTB OUTC OUTD RES VDD ADD RTD VCORE PG/ALT# CTRL SDA SCL AGND PMBUS Figure 1. Typical Application Circuit Rev. PrA Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2013 Analog Devices, Inc. All rights reserved. ADP1051 Preliminary Technical Data TABLE OF CONTENTS Features ..................................................................................................... 1 Applications .............................................................................................. 1 General Description ................................................................................ 1 Specifications............................................................................................ 3 Absolute Maximum Ratings .................................................................. 8 Thermal Resistance ............................................................................. 8 Soldering .............................................................................................. 8 ESD Caution.........................................................................................8 Pin Configuration and Function Descriptions ....................................9 Application Configurations ..................................................................11 Typical Performance Characteristics ..................................................13 Theory of Operation .............................................................................14 Outline Dimensions ..............................................................................15 Ordering Guide..................................................................................15 Rev. PrA | Page 2 of 17 Preliminary Technical Data ADP1051 SPECIFICATIONS VDD = 3.0V to 3.6 V, TA = -40°C to +125°C, unless otherwise noted. FSR = Full Scale Range. Table 1. Specifications Parameter SUPPLY Symbol VDD VDD IDD IDD Test Conditions/Comments Min Typ Max Unit 3.0 3.3 3.6 V PWM pins unloaded Normal operation (PSON is high or low) 29 Shut down (VDD below UVLO) 60 During EEPROM programming, 40 ms IDD + 6 mA 100 μA mA POWER-ON RESET Power-ON RESET VDD rising UVLO Threshold VDD falling 2.750 UVLO Hysteresis 2.850 3.0 V 2.975 V 35 OVLO Threshold 3.7 OVLO Debounce 3.9 mV 4.1 V When set to 2 μs 2 μs When set to 500 μs 500 μs VCORE PIN Output Voltage 330 nF capacitor between VCORE to AGND 2.50 2.6 2.70 V Using RES = 10 kΩ (±0.1%) 190 200 210 MHz OSCILLATOR AND PLL PLL Frequency DPWM Resolution 625 OUTA, OUTB, OUTC, OUTD, SR1, SR2 PINS Output Low Voltage Output High Voltage VOL Sinking Current = 10 mA VOH Sourcing Current = 10 mA ps 0.4 VDD−0.4 V V Rise Time CLOAD = 50 pF 3.5 ns Fall Time CLOAD = 50 pF 1.5 ns VS VOLTAGE SENSE PIN Input Voltage Range Differential voltage from VS+ to VS- 0 Input Voltage FSR 1 1.60 1.6 V V VS Accurate ADC Valid Input Voltage Range 1.6 V ADC Clock Frequency 1.56 MHz Register Update Rate 100 Hz 12 Bits Resolution Measurement Accuracy Factory trimmed at 1.0 V From 0% to 100% of Input Voltage Range From 10% to 90% of Input Voltage Range From 900 mV to 1.1 V −10 +10 % FSR -160 +160 mV −2.5 +2.5 % FSR -40 +40 mV −1.0 +1.0 % FSR -16 +16 mV 65 ppm/°C +200 mV Temperature Coeffient Common Mode Voltage Offset -200 VS High Speed ADC Equivalent Sampling fsw Rev. PrA | Page 3 of 17 kHz ADP1051 Parameter Frequency Equivalent Resolution Preliminary Technical Data Symbol Dynamic Range VS UVP Test Conditions/Comments Min Typ Max Unit At 390.6 kHz switching frequency 6 Bits Regulation voltage TBD mV to TBD V ±25 mV Based on VS Accurate ADC UVP accuracy 1 Comparator Update Speed 82 4 % us OVP PIN Usable Voltage Range 0.75 Threshold Accuracy Propagation Delay (Latency) Debounce time not included 1.5 V 1 1.25 % 58 110 ns 1 1.60 V VF VOLTAGE SENSE PIN Input Voltage Range Voltage from VF to AGND 0 Input Voltage FSR 1.6 V General ADC Valid Input Voltage Range 1.6 V ADC Clock Frequency 1.56 MHz Register Update Rate 100 Hz Resolution 12 Bits Measurement Accuracy From 10% to 90% of Input Voltage FSR From 0% to 100% of Input Voltage FSR −3.5 +3.5 % FSR -56 +56 mV −10 +10 % FSR -160 +160 mV 1.6 V Feed Forward ADC Input Voltage Range 0.5 1 Resolution 11 Bits Sampling Period 10 μs CS1 CURRENT SENSE PIN Input Voltage Range Input Voltage FSR VIN Differential voltage from CS1 to AGND 0 1 1.6 1.60 V V 1.6 V CS1 ADC Valid Input Voltage Range ADC Clock Frequency 1.56 MHz Register Update Rate 100 Hz Resolution Measurement Accuracy 12 From 10% to 90% of Input Voltage Range From 0% to 100% of Input Voltage Range Bits −3.5 +3.5 % FSR -56 +56 mV −10 +10 % FSR -160 +160 mV CS1 Fast OCP Threshold Value 1 Threshold Value 2 Propagation Delay (Latency) 1.18 1.2 1.22 V 0.22 0.25 0.28 V 58 110 ns 120 mV Debounce/blanking time not included CS2 CURRENT SENSE PINS Input Voltage Range Differential voltage from CS2+ to CS2− 0 To achieve measurement accuracy 0.9 1.15 1.4 V 1.81 1.9 1.99 mA Input Voltage FSR Common Mode Voltage 120 Current Sink (High Side) Rev. PrA | Page 4 of 17 mV Preliminary Technical Data Parameter Current Source (Low Side) Symbol ADP1051 Test Conditions/Comments 4.99 kΩ, 0.1% differential resistor Min 180 Typ 230 Temperature Coefficient Max 280 Unit μA 70 ppm/°C 120 mV CS2 ADC Valid Input Voltage Range 0 ADC Clock Frequency 1.56 MHz Resolution 12 Bits Measurement Accuracy Low Side Mode with User Trim From 0 mV to 110 mV From 110 mV to 120 mV High Side Mode with User Trim From 0 mV to 110 mV From 110 mV to 120 mV -1 +1 mV −1.85 +2.1 % FSR −2.22 +2.52 mV −6.1 +1.5 % FSR −6.36 +0.84 mV −1.6 +2.3 % FSR −1.92 +2.76 mV −5.3 +0.7 % FSR −6.36 +0.84 mV CS2 Accurate OCP Threshold Accuracy Same as ADC accuracy Speed When set to 7 bits averaging speed 82 us When set to 9 bits averaging speed 328 us CS2 Reverse Current Comparator Threshold Accuracy Threshold Speed −3 mV setting -8.5 −3.00 0 mV −6 mV setting -12.0 −6 0 mV −9 mV setting -15.5 −9 -2.9 mV −12 mV setting -18.5 −12 -5.9 mV −15 mV setting −22.0 −15 −8.0 mV −18 mV setting −25.5 −18 −11.0 mV −21 mV setting −28.5 −21 -14.0 mV −24 mV setting Debounce = 40 ns −32 −24 110 −16.5 150 mV ns Voltage from RTD to AGND 0 1.6 V When set to 46 μA, factory default setting 44.3 46 47.3 μA When set to 40 μA 38.6 40 42 μA When set to 30 μA 28.8 30 31.7 μA When set to 20 μA 18.8 20 21.5 μA When set to 10 μA 9.1 10 11 μA 1.6 V RTD TEMPERATURE SENSE PIN Input Voltage Input Voltage FSR Source Current 1.6 V RTD ADC Valid Input Voltage Range ADC Clock Frequency 1.56 MHz Register Update Rate 100 Hz Resolution 12 Bits Measurement Accuracy From 2% to 20% of valid input voltage Rev. PrA | Page 5 of 17 −0.3 +0.45 % FSR ADP1051 Parameter Preliminary Technical Data Symbol Test Conditions/Comments Min −4.8 From 0% to 100% of valid input voltage T = 85°C with 100 kΩ||16.5 kΩ Typ Max +7.2 Unit mV −2.6 +1.6 % FSR −0.9 +0.25 % FSR −14.4 +4 mV -0.5 +1.1 % FSR +17.6 mV OTP Threshold Accuracy T = 100°C with 100 kΩ||16.5 kΩ -8 Comparator Speed 10 Temperature Readings According to Internal Linearization Scheme ms Factory trimmed to 46 µA (set Register 0xFE2D to 0xE6); NTC R0 = 100 kΩ, 1%; beta = 4250 1%; REXT = 16.5 kΩ 1% T = 25°C to 100°C 7 °C T = 100°C to 125°C 5 °C VOL Sinking Current = 10 mA 0.4 V Input Low Level VIL Sinking Current = 10 mA 0.4 V Input High Level VIH PG/ALT# (OPEN DRAIN) PIN Output Low Level CTRL, SYNI/FLGI PINS SDA/SCL PINS VDD − 0.8 V VDD = 3.3 V Input Voltage Low VIL Input Voltage High VIH Output Voltage Low VOL 0.8 VDD − 1.2 Leakage Current V V −5 0.4 V +5 µA 400 kHz 50 ns SERIAL BUS TIMING Clock Frequency 100 Glitch Immunity tSW Bus Free Time tBUF 4.7 µs Start Setup Time tSU;STA 4.7 µs Start Hold Time tHD;STA 4 µs SCL Low Time tLOW 4.7 µs SCL High Time tHIGH 4 SCL, SDA Rise Time tR SCL, SDA Fall Time tF Data Setup Time tSU;DAT 250 ns Data Hold Time tHD;DAT 300 ns µs 1000 ns 300 ns EEPROM EEPROM Update Time Reliability Endurance1 Data Retention2 Time from the updating command to EEPROM updating finish (TJ = 25°C) 40 ms TJ = 85°C 10,000 Cycles TJ = 125°C 1,000 Cycles TJ = 85°C 20 Years TJ = 125°C 10 Years Endurance is qualified as per JEDEC Standard 22 Method A117 and measured at −40°C, +25°C, +85°C, and +125°C. 2 Retention lifetime equivalent at junction temperature (TJ) = 85°C as per JEDEC Standard 22 Method A117. Retention lifetime derates with junction temperature. 1 Rev. PrA | Page 6 of 17 Preliminary Technical Data ADP1051 tF tR tHD;STA tLOW SCL tHIGH tHD;DAT tSU;STA tSU;DAT tSU;STO SDA tBUF P S S Figure 2. Serial Bus Timing Diagram. Rev. PrA | Page 7 of 17 P 10241-003 tHD;STA ADP1051 Preliminary Technical Data ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 2. Absolute Maximum Rating Parameter Supply Voltage (Continuous) VDD Digital Pins: OUTA, OUTB, OUTC, OUTD, SR1, SR2, PG/ALT#, SDA, SCL VS- to AGND VS, VF, OVP, RTD, ADD, CS1, CS2+, CS2SYNI/FLGI, CTRL Operating Temperature Range Storage Temperature Range Junction Temperature Peak Solder Reflow Temperature Rating 4.2 V −0.3 V to VDD + 0.3 V θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. −0.3 V to +0.3 V −0.3 V to VDD + 0.3 V Package Type 24 Lead LFCSP −0.3 V to VDD + 0.3 V −40°C to +125°C −65°C to +150°C 150 °C SOLDERING SnPb Assemblies (10 to 30 secs) RoHS Compliant Assemblies (20 to 40 secs) ESD Charged Device Model ESD Human Body Model 240 °C 260 °C Table 3. Thermal Resistance θJA 36.26 θJC 1.51 Unit °C/W It is important to follow the correct guidelines when laying out the PCB footprint for the ADP1051, and for soldering the part onto the PCB. For detailed information about these guidelines, see the AN772 Application Note. ESD CAUTION 1.5 kV 5.0 kV Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. PrA | Page 8 of 17 Preliminary Technical Data ADP1051 OVP RTD ADD RES AGND VDD PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 24 23 22 21 20 19 VS- 1 18 VCORE VS+ 2 17 PG/ALT# CS2- 3 16 CTRL CS2+ 4 15 SDA VF 5 14 SCL CS1 6 13 ADP1051 8 9 10 11 12 OUTA OUTB OUTC OUTD SR1 7 SR2 TOP VIEW (Not to Scale) SYNI/FLGI Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 Mnemonic VS- 2 VS+ 3 CS2- 4 CS2+ 5 VF 6 CS1 7 8 9 10 11 SR1 SR2 OUTA OUTB OUTC 12 OUTD 13 14 15 16 SYNI/FLGI SCL SDA CTRL 17 18 PG/ALT# VCORE 19 VDD Description Inverting Voltage Sense Input. This is the connection for the ground line of the power rail. There should be a low ohmic connection to AGND. It is recommended that the resistor divider on this input have a tolerance specification of 0.5% or better to allow for trimming. Noninverting Voltage Sense Input. This signal is referred to VS−. It is recommended that the resistor divider on this input have a tolerance specification of 0.5% or better to allow for trimming. Inverting Differential Current Sense Input. Nominal voltage at this pin should be 1.15 V for best operation. When using high-side current sensing in a 12 V application, place a 5.62 kΩ resistor between the sense resistor and this pin. When using low-side current sensing, place a 5 kΩ resistor between the sense resistor and this pin. When using high-side current sensing, use the formula R = (VCOMMONMODE – 1.15)/1.9mA. A 0.1% resistor must be used to connect this circuit. Noninverting Differential Current Sense Input. Nominal voltage at this pin should be 1.15 V for best operation. When using high-side current sensing in a 12 V application, place a 5.62 kΩ resistor between the sense resistor and this pin. When using low-side current sensing, place a 5 kΩ resistor between the sense resistor and this pin. When using high-side current sensing, use the formula R = (VCOMMONMODE – 1.15)/1.9 mA. A 0.1% resistor must be used to connect this circuit. Three optional functions can be implemented with this pin: feed forward, primary side input voltage sensing and input voltage lost detect. It is connected upstream of the output inductor through a resistor divider network. The nominal voltage at this pin should be 1V. This signal is referred to AGND Primary Side Current Sense Input. This pin is connected to the primary side current sensing ADC and to the fast OCP comparator. This signal is referred to AGND. The resistors on this input must have a tolerance specification of 0.5% or better to allow for trimming. PWM logic output drive. This pin can be disabled when not in use. This signal is referred to AGND. PWM logic output drive. This pin can be disabled when not in use. This signal is referred to AGND. PWM logic output drive. This pin can be disabled when not in use. This signal is referred to AGND. PWM logic output drive. This pin can be disabled when not in use. This signal is referred to AGND. PWM logic output drive. This pin can be disabled when not in use. This signal is referred to AGND. This pin can also be programmed as a synchronization output. PWM logic output drive. This pin can be disabled when not in use. This signal is referred to AGND. This pin can also be programmed as a synchronization output. Synchronization signal input. It also used as an external signal input to generate a flag condition. I2C/PMBus Serial Clock Input and Output (Open Drain). This signal is referred to AGND. I2C/PMBus Serial Data Input and Output (Open Drain). This signal is referred to AGND. PMBus CONTROL signal. It is recommended that a 1 nF capacitor be included from the CTRL pin to AGND for noise debounce and decoupling. This signal is referred to AGND. Power Good Output (Open Drain). This signal is referred to AGND. This pin is also used PMBus ALERT# signal. Output of 2.6 V regulator. Connect a minimum 330 nF decoupling capacitor from this pin to the AGND as close as possible to the IC, minimizing the PCB trace length. It is recommended that the VCORE pin not be used as a reference or to generate other logic levels using resistive dividers. Positive Supply voltage 3.0 V to 3.6 V referred to AGND. Connect a 2.2 μF decoupling capacitor from this pin to the AGND as close as possible to the IC, minimizing the PCB trace length. Rev. PrA | Page 9 of 17 ADP1051 Pin No. 20 Mnemonic AGND 21 RES 22 ADD 23 RTD 24 OVP EP Preliminary Technical Data Description IC Common Analog GND. The internal analog circuitry ground and digital circuitry ground is star connected to this pin through bonding wires. Resistor Input. This pin sets up the internal reference for internal PLL Frequency. Connect a 10 kΩ resistor (±0.1%) from RES to AGND. This signal is referred to AGND. Address Select Input to program I2C/PMBus address. Connect a resistor from ADD to AGND. This signal is referred to AGND. Thermistor Input. Place a thermistor 100 kΩ 1% beta = 4250 1% in parallel with a 16.5 kΩ (1%) resistor. This pin is referenced to AGND. Connect to AGND if not used. Over Voltage Protection. This signal is used as redundant OVP protection. This signal is referred to VS-. Exposed Pad. The ADP1051 has an exposed thermal pad on the underside of the package. For increased reliability of the solder joints and maximum thermal capability, it is recommended that the pad be soldered to the PCB AGND plane. Rev. PrA | Page 10 of 17 Preliminary Technical Data ADP1051 APPLICATION CONFIGURATIONS LOAD DC INPUT ADP3624/ ADP3654 SR1 SR2 CS2- VF CS2+ VS+ OVP VS- CS1 ADP1051 OUTA ADuM3223/ ADuM4223 SYNI/FLGI OUTB OUTC OUTD RES VDD ADD RTD VCORE PG/ALT# CTRL SDA AGND SCL PMBUS Figure 4. Full Bridge Converter LOAD DC INPUT ADP3624/ ADP3654 SR1 SR2 CS2- VF CS2+ OVP VS+ VS- CS1 ADuM3223/ ADuM4223 ADP1051 OUTA SYNI/FLGI OUTB OUTC OUTD RES VDD ADD RTD VCORE PG/ALT# CTRL SDA PMBUS Figure 5. Half Bridge Converter Rev. PrA | Page 11 of 17 SCL AGND ADP1051 Preliminary Technical Data DC INPUT LOAD ADP3624/ ADP3654 SR1 SR2 CS2- VF CS2+ OVP VS+ VS- CS1 ADuM3221 ADP1051 OUTA SYNI/FLGI OUTB OUTC OUTD RES VDD ADD RTD VCORE PG/ALT# CTRL SDA PMBUS Figure 6. Active Clamp Forward Converter Rev. PrA | Page 12 of 17 SCL AGND Preliminary Technical Data ADP1051 TYPICAL PERFORMANCE CHARACTERISTICS Figure 7. VS ADC Accuracy vs. Temperature (from 10% to 90% of FSR) Figure 10. CS2 ADC Accuracy vs. Temperature (from 0 mV to 120 mV) Figure 8. VF ADC Accuracy vs. Temperature (from 10% to 90% of FSR) Figure 11. RTD ADC Accuracy vs. Temperature Figure 9. CS1 ADC Accuracy vs. Temperature (from 10% to 90% of FSR) Figure 12. CS1 Fast OCP Threshold vs. Temperature Rev. PrA | Page 13 of 17 ADP1051 Preliminary Technical Data THEORY OF OPERATION programmable PWM outputs for control of FET drivers and synchronous rectification FET drivers. This programmability allows many traditional and specific switching topologies to be realized. The ADP1051 is designed as a flexible, easy-to-use, digital power supply controller. The ADP1051 integrates the typical functions that are needed to control a power supply such as: Output voltage sense and feedback Voltage feed forward control Digital loop filter compensation PWM generation Current, voltage, and temperature sense Housekeeping and I2C/PMBus interface Calibration and trimming Conventional power supply housekeeping features, such as remote and local voltage sense and primary side current sense, are included. An extensive set of protections are offered, including overvoltage protection (OVP), over current protection (OCP), over temperature protection (OTP), under voltage protection (UVP), SR reverse current protection (RCP). All these features are programmable through the I2C/PMBus interface. This interface is also used for calibrations. Other information, such as input current, output current, and fault flags, is also available through this digital bus interface. The main function of controlling the output voltage is performed using the feedback ADCs, the digital loop filter, and the PWM block. The feedback ADCs use a multipath approach. There is a combination of a high speed, low resolution (fast and coarse) ADC and a low speed, high resolution (slow and accurate) ADC. The ADC outputs combine to form a high speed and high resolution feedback path. Loop compensation is implemented using the digital filter. This PID (proportional, integral, derivative) filter is implemented in the digital domain, allowing easy programming of filter characteristics, which is of great value in customizing and debugging designs. The PWM block generates up to six VF CS1 The internal EEPROM can store all programmed values and allows standalone control without a microcontroller. A free, downloadable ADP1051 GUI is available that provides all the necessary software to program the ADP1051. To obtain the latest GUI software and a user guide, visit http://www.analog.com/digitalpower. The ADP1051 operates from a single 3.3V power supply and is specified from -40°C to 125°C. CS2+ CS2- VS+ VS- 1.2V 0.25V C D A C D A C D A C D A - + + VREF - • • • • • • • OVP OUTA + OUTB DAC OUTC ADC PWM ENGINE RTD DIGITAL CORE ADD OUTD OSC 8kB EEPROM SR1 RES PMBus AGND UVLO SR2 VDD LDO SYNI/FLGI SCL SDA CTRL PG/ALT# Figure 13. Functional Block Diagram Rev. PrA | Page 14 of 17 VCORE Preliminary Technical Data ADP1051 OUTLINE DIMENSIONS Figure 14. 24-Lead 4 x 4 mm Lead frame Chip-Scale Package [LFCSP] Mechanical Package Dimensions ORDERING GUIDE Model 1 ADP1051ACPZ-RL ADP1051ACPZ-R7 ADP1051-240-EVALZ ADP1051DC1-EVALZ ADP-I2C-USB-Z 1 Temperature Range −40°C to +125°C −40°C to +125°C Package Description 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ] ADP1051 240 W Evaluation Board ADP1051 Daughter Card USB to I2C Adapter Z = RoHS Compliant Part. Rev. PrA | Page 15 of 17 Package Option CP-24-7 CP-24-7 ADP1051 Preliminary Technical Data NOTES Rev. PrA | Page 16 of 17 Preliminary Technical Data ADP1051 NOTES ©2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR1433-0-3/13/(PrA) Rev. PrA | Page 17 of 17