NLX1G99 Configurable Multifunction Gate The NLX1G99 MiniGatet is an advanced high−speed CMOS multifunction gate with a 3−state output. With the output enable input (OE) at High, the output is disabled and is kept at high impedance. With the output enable input (OE) at Low, the device can be configured for logic functions such as MUX, AND, OR, NAND, NOR, XOR, XNOR, INVERT and BUFFER, depending on the combination of the 4−bit input. The device has Schmitt−trigger inputs, thereby enhancing noise immunity. The NLX1G99 input and output structures provide protection when voltages up to 7.0 V are applied, regardless of the supply voltage. www.onsemi.com MARKING DIAGRAMS UDFN8 1.45 x 1.0 CASE 517BZ 1 UDFN8 1.6 x 1.0 CASE 517BY 1 XM Features • • • • • • • High Speed: tPD = 6.7 ns (Max) @ VCC = 3.3 V Low Power Dissipation: ICC = 1 mA (Max) at TA = 25°C Power Down Protection Provided on inputs Balanced Propagation Delays Overvoltage Tolerant (OVT) Input and Output Pins Ultra−Small Packages These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant UDFN8 1.95 x 1.0 CASE 517CA XM AF M 1 AA or E = Specific Device Code M = Date Code G = Pb−Free Package PIN ASSIGNMENT 1 OE 2 A 3 B ORDERING INFORMATION 4 GND See detailed ordering and shipping information in the package dimensions section on page 12 of this data sheet. 5 C 6 D 7 Y 8 VCC PIN ASSIGNMENTS OE 1 A 2 8 VCC 7 Y B 3 6 D GND 4 5 C (Top View) © Semiconductor Components Industries, LLC, 2016 June, 2016 − Rev. 6 1 Publication Order Number: NLX1G99/D NLX1G99 FUNCTION DIAGRAM OE A Y B C D Figure 1. Function Diagram FUNCTION TABLE* INPUT OUTPUT OE D C B A Y L L L L L L L L L L H H L L L H L L L L L H H H L L H L L L L L H L H L L L H H L H L L H H H H L H L L L H L H L L H L L H L H L H L H L H H L L H H L L H L H H L H H L H H H L L L H H H H L H H or L H or L H or L H or L Z *To select a logic function, please refer to “Logic Configurations” section. FUNCTION SELECTION LOGIC CONFIGURATION PAGE 3−State Buffers 3 3−State Inverters 3 3−State MUXes 3 3−State AND / OR / NOR 4 3−State NAND / OR 5 3−State XOR/XNOR 6 www.onsemi.com 2 NLX1G99 LOGIC CONFIGURATIONS 3−State Buffer Functions Available OE Input Y Figure 2. Function OE A B C D 3−State Buffer L Input H or L L H H H or L L H or L Input H L H or L L L L H Input Input L H H or L L L L H Input Input Input 3−State Inverter Functions Available OE Input Y Figure 3. Function OE A B C D 3−State Buffer L Input X L H H H or L H H or L Input H L H or L H H L H Input Input L H H or L H H H L Input Input Input 3−State MUX Functions Available OE OE A/B A/B Input 1 Y Input 2 Input 1 Y Input 2 Figure 4. Function OE A B C D 3−State 2−to−1 3−State 2−to−1 3−State 2−to−1, Inverted Out 3−State 2−to−1, Inverted Out L Input 1 Input 2 Input 1 Input 2 Input 2 Input 1 Input 2 Input 1 Input 1 or Input 2 Input 2 or Input 1 Input 1 or Input 2 Input 2 or Input 1 L L H H www.onsemi.com 3 NLX1G99 3−State AND/NOR/OR Function Available OE OE Input 1 Input 1 Y Input 2 Y Input 2 Figure 5. No. of Inputs AND/NAND Function OR/NOR Function OE A B C D 2 2 3−State AND 3−State AND 3−State NOR 3−State NOR L L L Input 1 Input 2 Input 2 Input 1 L L OE OE Input 1 Input 1 Y Input 2 Y Input 2 Figure 6. No. of Inputs AND/NAND Function OR/NOR Function OE A B C D 2 2 3−State AND 3−State AND 3−State NOR 3−State NOR L Input 2 H L Input 1 Input 1 Input 2 L H OE OE Input 1 Input 1 Y Input 2 Y Input 2 Figure 7. No. of Inputs AND/NAND Function OR/NOR Function OE A B C D 2 2 3−State AND 3−State AND 3−State NOR 3−State NOR L Input 1 H L Input 2 Input 2 Input 1 L H OE OE Input 1 Input 1 Y Input 2 Y Input 2 Figure 8. No. of Inputs AND/NAND Function OR/NOR Function OE A B C D 2 2 3−State AND 3−State AND 3−State OR 3−State OR L Input 1 Input 2 H H Input 2 Input 1 L L www.onsemi.com 4 NLX1G99 3−State NAND/OR Function Available OE OE Input 1 Input 1 Y Input 2 Y Input 2 Figure 9. No. of Inputs AND/NAND Function OR/NOR Function OE A B C D 2 2 3−State NAND 3−State NAND 3−State OR 3−State OR L L L Input 1 Input 2 Input 2 Input 1 H H OE OE Input 1 Input 1 Y Input 2 Y Input 2 Figure 10. No. of Inputs AND/NAND Function OR/NOR Function OE A B C D 2 2 3−State NAND 3−State NAND 3−State OR 3−State OR L Input 2 H L Input 1 Input 1 Input 2 H L OE OE Input 1 Input 1 Y Input 2 Y Input 2 Figure 11. No. of Inputs AND/NAND Function OR/NOR Function OE A B C D 2 2 3−State NAND 3−State NAND 3−State OR 3−State OR L Input 1 H L Input 2 Input 2 Input 1 H L OE OE Input 1 Input 1 Y Input 2 Y Input 2 Figure 12. No. of Inputs AND/NAND Function OR/NOR Function OE A B C D 2 2 3−State AND 3−State AND 3−State OR 3−State OR L Input 1 Input 2 H H Input 2 Input 1 L L www.onsemi.com 5 NLX1G99 3−State XOR/XNOR Function Available OE Input 1 Y Input 2 Figure 13. Function OE A B C D 3−State XOR L Input 1 Input 2 H or L H or L L L H or L H or L Input 1 Input 2 H H L L H H Input 1 Input 2 Input 2 Input 1 Input 2 Input 1 Input 2 Input 1 OE Input 1 Y Input 2 Figure 14. Function OE A B C D 3−State XOR L H L Input 1 Input 2 OE Input 1 Y Input 2 Figure 15. Function OE A B C D 3−State XOR L H L Input 1 Input 2 OE Input 1 Y Input 2 Figure 16. Function OE A B C D 3−State XNOR 3−State XNOR L H H L L Input 1 Input 2 Input 2 Input 1 www.onsemi.com 6 NLX1G99 MAXIMUM RATINGS Symbol Value Unit VCC DC Supply Voltage −0.5 to +7.0 V VIN DC Input Voltage −0.5 to +7.0 V −0.5 to VCC + 0.5 −0.5 to +7.0 −0.5 to +7.0 V VIN < GND −50 mA VOUT < GND −50 mA VOUT Parameter DC Output Voltage Active Mode (High or Low State) Tristate Mode (Output at Hi−Z) Power Down Mode (VCC = 0 V) IIK DC Input Diode Current IOK DC Output Diode Current IO DC Output Source/Sink Current ±50 mA ICC DC Supply Current Per Supply Pin ±100 mA IGND DC Ground Current per Ground Pin ±100 mA TSTG Storage Temperature Range −65 to +150 °C TL Lead Temperature, 1 mm from Case for 10 Seconds 260 °C TJ Junction Temperature Under Bias 150 °C MSL FR VESD ILATCHUP Moisture Sensitivity Level 1 Flammability Rating Oxygen Index: 28 to 34 ESD Withstand Voltage UL 94 V−0 @ 0.125 in Human Body Model (Note 2) Machine Model (Note 3) Charged Device Model (Note 4) Latchup Performance Above VCC and Below GND at 125°C (Note 5) > 2000 > 200 N/A V ±500 mA Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2 ounce copper trace no air flow. 2. Tested to EIA / JESD22−A114−A. 3. Tested to EIA / JESD22−A115−A. 4. Tested to JESD22−C101−A. 5. Tested to EIA / JESD78. RECOMMENDED OPERATING CONDITIONS Symbol Parameter VCC Positive DC Supply Voltage VIN Digital Input Voltage VOUT Output Voltage TA Operating Free−Air Temperature Dt /DV Input Transition Rise or Fall Rate Active Mode (High or Low State) Tristate Mode (Output at Hi−Z) Power Down Mode (VCC = 0 V) VCC = 2.5 V $ 0.2 V VCC = 3.3 V $ 0.3 V VCC = 5.0 V $ 0.5 V Min Max Unit 1.65 5.5 V 0 5.5 V 0 0 0 VCC 5.5 5.5 V −55 +125 °C 0 0 0 No Limit No Limit No Limit nS/V Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. www.onsemi.com 7 NLX1G99 DC ELECTRICAL CHARACTERISTICS TA = 255C Symbol Parameter Conditions VCC (V) Min Max TA v +855C TA = −555C to +1255C Min Min VT+ Positive Threshold Voltage 1.65 1.8 2.3 3.0 4.5 5.5 0.79 0.87 1.11 1.5 2.16 2.61 1.16 1.28 1.56 1.87 2.74 3.33 VT− Negative Threshold Voltage 1.65 1.8 2.3 3.0 4.5 5.5 0.35 0.38 0.58 0.84 1.41 1.78 0.62 0.68 0.87 1.19 1.9 2.29 0.35 0.38 0.58 0.84 1.41 1.78 VH Hysteresis Voltage 1.65 1.8 2.3 3.0 4.5 5.5 0.30 0.33 0.40 0.53 0.71 0.8 0.62 0.68 0.8 0.87 1.04 1.2 0.30 0.33 0.40 0.53 0.71 0.8 VOH Minimum High−Level Output Voltage VIN = VT−MIN or VT+MAX IOH = −50 mA IOH = −100 mA VIN = VT−MIN or VT+MAX IOH = −4 mA IOH = −8 mA IOH = −12 mA IOH = −16 mA IOH = −24 mA IOH = −32 mA VOL Maximum Low−Level Output Voltage Max 1.16 1.28 1.56 1.87 2.74 3.33 Max Unit 1.16 1.28 1.56 1.87 2.74 3.33 V 0.35 0.38 0.58 0.84 1.41 1.78 0.62 0.68 0.8 0.87 1.04 1.2 0.30 0.33 0.40 0.53 0.71 0.8 V 0.62 0.68 0.8 0.87 1.04 1.2 V V 1.65−5.5 1.65−5.5 VCC−0.1 VCC−0.1 VCC−0.1 VCC−0.1 VCC−0.1 VCC−0.1 V 1.65 2.3 2.7 3.0 3.0 4.5 1.2 1.9 2.2 2.4 2.3 3.8 1.2 1.9 2.2 2.4 2.3 3.8 1.2 1.9 2.2 2.4 2.3 3.8 V VIN = VT−MIN or VT+MAX IOL = 50 mA IOL = 100 mA 1.65−5.5 1.65−5.5 0.1 0.1 0.1 0.1 0.1 0.1 VIN = VT−MIN or VT+MAX IOL = 4 mA IOL = 8 mA IOL = 12 mA IOL = 16 mA IOL = 24 mA IOL = 32 mA 1.65 2.3 2.7 3.0 3.0 4.5 0.45 0.3 0.4 0.4 0.55 0.55 0.45 0.3 0.4 0.4 0.55 0.55 0.45 0.3 0.4 0.4 0.55 0.55 IIN Input Leakage Current 0 v VIN v 5.5 V 0 − 5.5 $0.1 $1.0 $1.0 mA Ioff Power off Leakage Current VIN or VO = 5.5 V 0 $1.0 $10 $10 mA IOZ Tri−state Output Leakage Current VO = VCC or GND 1.65−5.5 $1.0 $10 $10 mA ICC Quiescent Supply Current VIN = VCC or GND, IO = 0 1.65−5.5 1.0 10 10 mA DICC Increase in ICC Per Input One input at (VCC−0.6) V, other inputs at VCC or GND 2.3 − 5.5 10 100 100 mA Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. www.onsemi.com 8 NLX1G99 AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0 ns) TA = 255C TA v +855C TA = −555C to +1255C Symbol Parameter VCC (V) Test Condition Min Typ Max Min Max Min Max Unit tPLH, tPHL Propagation Delay, Any Input to Output Y (See Test Circuit) 1.65−1.95 2.3 − 2.7 3.0 − 3.6 4.5 − 5.5 Refer to switch positions and loading conditions in Figure 17 to 21. 4.3 2.4 1.7 1.3 12.8 7.1 5.2 4.0 25.1 10.2 6.7 4.5 4.3 2.4 1.7 1.3 25.1 10.2 6.9 4.9 4.3 2.4 1.7 1.3 25.1 10.2 7.0 5.0 ns tEN Output Enable Time, OE to Y 1.65−1.95 2.3 − 2.7 3.0 − 3.6 4.5 − 5.5 Refer to switch positions and loading conditions in Figure 17 to 21. 3.4 2.1 1.3 1.0 24.7 11 7.5 5.7 3.4 2.1 1.3 1.0 24.7 12 8.0 6.2 3.4 2.1 1.3 1.0 24.7 12.2 8.3 6.5 ns tDIS Output Disable Time, OE to Y 1.65−1.95 2.3 − 2.7 3.0 − 3.6 4.5 − 5.5 Refer to switch positions and loading conditions in Figure 17 to 21. 4.0 2.7 3.5 2.0 15.5 7.5 7.0 5.5 4.0 2.7 3.5 2.0 15.5 7.5 7.0 5.5 4.0 2.7 3.5 2.0 15.5 7.5 7.0 5.5 ns tPLH, tPHL Propagation Delay, Any Input to Output Y (See Test Circuit) 1.65−1.95 2.3 − 2.7 3.0 − 3.6 4.5 − 5.5 Refer to switch Positions and loading conditions in Figure 22 to 26. 4.3 2.5 2.3 1.6 25.7 10.7 7.6 5.2 4.3 2.5 2.3 1.6 25.7 10.7 7.6 5.2 4.3 2.5 2.3 1.6 25.7 10.7 7.6 5.2 ns tEN Output Enable Time, OE to Y 1.65−1.95 2.3 − 2.7 3.0 − 3.6 4.5 − 5.5 Refer to switch Positions and loading conditions in Figure 22 to 26. 4.2 2.4 2.0 1.7 25.2 11.3 8.0 6.0 4.2 2.4 2.0 1.7 25.2 12.2 8.5 6.5 4.2 2.4 2.0 1.7 25.2 13 8.7 6.7 ns tDIS Output Disable Time, OE to Y 1.65−1.95 2.3 − 2.7 3.0 − 3.6 4.5 − 5.5 Refer to switch Positions and loading conditions in Figure 22 to 26. 3.7 2.0 2.1 1.0 15 6.5 5.6 4.5 3.7 2.0 2.1 1.0 15 6.7 5.8 4.7 3.7 2.0 2.1 1.0 15 6.9 5.9 4.9 ns CIN Input Capacitance 3.3 3.5 pF CO Output Capacitance 3.3 6.0 pF CPD Power Dissipation Capacitance (Note 6) 3.3 22 pF f = 10 MHz 13.6 7.8 5.6 4.4 6. CPD is defined as the value of the internal equivalent capacitance which is calculated from the dynamic operating current consumption without load. Average operating current can be obtained by the equation ICC(OPR) = CPD • VCC • fin + ICC. CPD is used to determine the no−load dynamic power consumption: PD = CPD • VCC2 • fin + ICC • VCC. www.onsemi.com 9 NLX1G99 TEST CIRCUIT AND VOLTAGE WAVEFORMS From Output Under Test RL VLOAD S1 CL * S1 Test Open GND RL tPLH/tPHL Open tPLZ/tPZL VLOAD tPHZ/tPZH GND *CL includes probes and jig capacitance. Figure 17. Load Circuit Inputs VCC VI tr/tf VM VLOAD CL RL VD 1.8 V $ 0.15 V VCC v 2 ns VCC/2 2 x VCC 15 pF 1 MW 0.15 V 2.5 V $ 0.2 V VCC v 2 ns VCC/2 2 x VCC 15 pF 1 MW 0.15 V 3.3 V $ 0.3 V 3V v 2.5 ns 1.5 V 6V 15 pF 1 MW 0.3 V 5.5 V $ 0.5 V VCC v 2.5 ns VCC/2 2 x VCC 15 pF 1 MW 0.3 V Timing Input tW Input VI VM 0V VI VM VM tsu 0V Data Input th VM VI VM 0V Figure 18. Voltage Waveforms Pulse Duration VI Input VM VM VM tPHL Output Control 0V tPHL tPLH Output Output Figure 19. Voltage Waveforms Setup and Hold Times VM Output Waveform 1 S1 at VLOAD (Note 7) VOH VOL tPLH VM VM VM VM 0V VM tPZH VOH Output Waveform 2 S1 at GND (Note 7) VOL Figure 20. Voltage Waveforms Propagation Delay Times Inverting and Noninverting Outputs VI VM VLOAD/2 VOL + VD VOL tPHZ VOH VOH − VD [0 V Figure 21. Voltage Waveforms Enable and Disable Times Low− and High−Level Enabling 7. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control 8. All input pulses are supplied by generators having the following characteristics: PRR v 10 MHz, ZO = 50 W. 9. The outputs are measured one at a time, with one transition per measurement. 10. All parameters are waveforms are not applicable to all devices. www.onsemi.com 10 NLX1G99 From Output Under Test VLOAD S1 RL Test S1 tPLH/tPHL Open tPLZ/tPZL VLOAD tPHZ/tPZH GND Open GND CL * RL *CL includes probes and jig capacitance. Figure 22. Load Circuit Inputs VCC VI tr/tf VM VLOAD CL RL VD 1.8 V $ 0.15 V VCC v 2 ns VCC/2 2 x VCC 30 pF 1 kW 0.15 V 2.5 V $ 0.2 V VCC v 2 ns VCC/2 2 x VCC 30 pF 500 W 0.15 V 3.3 V $ 0.3 V 3V v 2.5 ns 1.5 V 6V 50 pF 500 W 0.3 V 5.5 V $ 0.5 V VCC v 2.5 ns VCC/2 2 x VCC 50 pF 500 W 0.3 V Timing Input tW Input VI VM 0V VI VM VM tsu 0V Data Input th VM VI VM 0V Figure 23. Voltage Waveforms Pulse Duration VI Input VM VM Output VM tPHL Output Control 0V tPHL tPLH Output Figure 24. Voltage Waveforms Setup and Hold Times VM Output Waveform 1 S1 at VLOAD (Note 11) VOH VOL tPLH VM VM VM VM 0V VM tPZH VOH Output Waveform 2 S1 at GND (Note 11) VOL Figure 25. Voltage Waveforms Propagation Delay Times Inverting and Noninverting Outputs VI VM VLOAD/2 VOL + VD VOL tPHZ VOH VOH − VD [0 V Figure 26. Voltage Waveforms Enable and Disable Times Low− and High−Level Enabling 11. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control 12. All input pulses are supplied by generators having the following characteristics: PRR v 10 MHz, ZO = 50 W. 13. The outputs are measured one at a time, with one transition per measurement. 14. All parameters are waveforms are not applicable to all devices. www.onsemi.com 11 NLX1G99 ORDERING INFORMATION Package Shipping† NLX1G99DMUTCG UDFN8, 1.95 x 1.0, 0.5P (Pb−Free) 3000 / Tape & Reel NLX1G99DMUTWG UDFN8, 1.95 x 1.0, 0.5P (Pb−Free) 3000 / Tape & Reel NLX1G99EMUTCG (In Development) UDFN8, 1.6 x 1.0, 0.4P (Pb−Free) 3000 / Tape & Reel NLX1G99FMUTCG (In Development) UDFN8, 1.45 x 1.0, 0.35P (Pb−Free) 3000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 12 NLX1G99 PACKAGE DIMENSIONS UDFN8 1.6x1.0, 0.4P CASE 517BY ISSUE O PIN ONE REFERENCE 0.10 C 2X 2X ÉÉÉ ÉÉÉ ÉÉÉ 0.10 C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.20 MM FROM TERMINAL TIP. 4. PACKAGE DIMENSIONS EXCLUSIVE OF BURRS AND MOLD FLASH. A B D E DIM A A1 A3 b D E e L L1 TOP VIEW A3 0.05 C A 0.05 C A1 SIDE VIEW C RECOMMENDED SOLDERING FOOTPRINT* SEATING PLANE 7X e/2 0.49 e 1 7X MILLIMETERS MIN MAX 0.45 0.55 0.00 0.05 0.13 REF 0.15 0.25 1.60 BSC 1.00 BSC 0.40 BSC 0.25 0.35 0.30 0.40 L 8X 0.26 4 L1 1.24 8 5 BOTTOM VIEW 8X b 0.10 M C A B 0.05 M C 0.53 1 PKG OUTLINE 0.40 PITCH DIMENSIONS: MILLIMETERS NOTE 3 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. www.onsemi.com 13 NLX1G99 PACKAGE DIMENSIONS UDFN8 1.45x1.0, 0.35P CASE 517BZ ISSUE O PIN ONE REFERENCE 0.10 C 2X 2X 0.10 C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.20 MM FROM TERMINAL TIP. 4. PACKAGE DIMENSIONS EXCLUSIVE OF BURRS AND MOLD FLASH. A B D ÉÉ ÉÉ ÉÉ E DIM A A1 A3 b D E e L L1 TOP VIEW A3 0.05 C A 0.05 C A1 SIDE VIEW C RECOMMENDED SOLDERING FOOTPRINT* SEATING PLANE 7X 0.48 e/2 e 1 7X MILLIMETERS MIN MAX 0.45 0.55 0.00 0.05 0.13 REF 0.15 0.25 1.45 BSC 1.00 BSC 0.35 BSC 0.25 0.35 0.30 0.40 8X 0.22 L 4 L1 1.18 8 5 BOTTOM VIEW 8X 0.53 b 0.10 M C A B 0.05 M C NOTE 3 PKG OUTLINE 0.35 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. www.onsemi.com 14 1 NLX1G99 PACKAGE DIMENSIONS UDFN8 1.95x1.0, 0.5P CASE 517CA ISSUE O PIN ONE REFERENCE 0.10 C 2X 2X ÉÉÉ ÉÉÉ ÉÉÉ 0.10 C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.20 MM FROM TERMINAL TIP. 4. PACKAGE DIMENSIONS EXCLUSIVE OF BURRS AND MOLD FLASH. A B D E DIM A A1 A3 b D E e L L1 TOP VIEW A3 0.05 C A 0.05 C A1 SIDE VIEW C RECOMMENDED SOLDERING FOOTPRINT* SEATING PLANE 7X e/2 0.49 e 7X MILLIMETERS MIN MAX 0.45 0.55 0.00 0.05 0.13 REF 0.15 0.25 1.95 BSC 1.00 BSC 0.50 BSC 0.25 0.35 0.30 0.40 L 8X 0.30 4 1 L1 1.24 8 5 8X BOTTOM VIEW b 0.10 M C A B 0.05 M C 0.54 NOTE 3 1 PKG OUTLINE 0.50 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. MiniGate is a trademark of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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