TI CDC318ADL 1-line to 18-line clock driver with i2c control interface Datasheet

CDC318A
1-LINE TO 18-LINE CLOCK DRIVER
WITH I2C CONTROL INTERFACE
SCAS614 – SEPTEMBER 1998
D
D
D
D
D
D
D
D
D
D
DL PACKAGE
(TOP VIEW)
High-Speed, Low-Skew 1-to-18 Clock Buffer
for Synchronous DRAM (SDRAM) Clock
Buffering Applications
Output Skew, tsk(o), Less Than 250 ps
Pulse Skew, tsk(p), Less Than 500 ps
Supports up to Four Unbuffered SDRAM
Dual Inline Memory Modules (DIMMs)
I2C Serial Interface Provides Individual
Enable Control for Each Output
Operates at 3.3 V
Distributed VCC and Ground Pins Reduce
Switching Noise
100-MHz Operation
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015
Packaged in 48-Pin Shrink Small Outline
(DL) Package
NC
NC
VCC
1Y0
1Y1
GND
VCC
1Y2
1Y3
GND
A
VCC
2Y0
2Y1
GND
VCC
2Y2
2Y3
GND
VCC
5Y0
GND
VCC
SDATA
description
The CDC318A is a high-performance clock buffer
designed to distribute high-speed clocks in PC
applications. This device distributes one input (A)
to 18 outputs (Y) with minimum skew for clock
distribution. The CDC318A operates from a 3.3-V
power supply. It is characterized for operation
from 0°C to 70°C.
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
NC
NC
VCC
4Y3
4Y2
GND
VCC
4Y1
4Y0
GND
OE
VCC
3Y3
3Y2
GND
VCC
3Y1
3Y0
GND
VCC
5Y1
GND
GND
SCLOCK
NC – No internal connection
This device has been designed with consideration
for optimized EMI performance. Depending on the
application layout, damping resistors in series to
the clock outputs (like proposed in the PC100
specification) may not be needed in most cases.
The device provides a standard mode (100K-bits/s) I2C serial interface for device control. The implementation
is as a slave/receiver. The device address is specified in the I2C device address table. Both of the I2C inputs
(SDATA and SCLOCK) are 5-V tolerant and provide integrated pullup resistors (typically 140 kΩ).
Three 8-bit I2C registers provide individual enable control for each of the outputs. All outputs default to enabled
at powerup. Each output can be placed in a disabled mode with a low-level output when a low-level control bit
is written to the control register. The registers are write only and must be accessed in sequential order (i.e.,
random access of the registers is not supported).
The CDC318A provides 3-state outputs for testing and debugging purposes. The outputs can be placed in a
high-impedance state via the output-enable (OE) input. When OE is high, all outputs are in the operational state.
When OE is low, the outputs are placed in a high-impedance state. OE provides an integrated pullup resistor.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Intel is a trademark of Intel Corporation
Copyright  1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
CDC318A
1-LINE TO 18-LINE CLOCK DRIVER
WITH I2C CONTROL INTERFACE
SCAS614 – SEPTEMBER 1998
FUNCTION TABLE
INPUTS
OUTPUTS
OE
A
1Y0–1Y3
2Y0–2Y3
3Y0–3Y3
4Y0–4Y3
5Y0–5Y1
L
X
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
H
L
H
H
L
H†
L
H†
L
H†
L
H†
H†
L
† The function table assumes that all outputs are enabled via the appropriate I2C configuration register bit. If the output is disabled
via the appropriate configuration bit, then the output is driven to a low state, regardless of the state of the A input.
logic diagram (positive logic)
38
OE
24
SDATA
I2C
I2C
Register
Space
18
/
4, 5, 8, 9
25
SCLOCK
1Y0–1Y3
13, 14, 17, 18
2Y0–2Y3
11
A
31, 32, 35, 36
3Y0–3Y3
40, 41, 44, 45
4Y0–4Y3
21, 28
5Y0–5Y1
2
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CDC318A
1-LINE TO 18-LINE CLOCK DRIVER
WITH I2C CONTROL INTERFACE
SCAS614 – SEPTEMBER 1998
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
1Y0–1Y3
4, 5, 8, 9
O
3.3-V SDRAM byte 0 clock outputs
2Y0–2Y3
13, 14, 17, 18
O
3.3-V SDRAM byte 1 clock outputs
3Y0–3Y3
31, 32, 35, 36
O
3.3-V SDRAM byte 2 clock outputs
4Y0–4Y3
40, 41, 44, 45
O
3.3-V SDRAM byte 3 clock outputs
5Y0–5Y1
21, 28
O
3.3-V clock outputs provided for feedback control of external phase-locked loops (PLLs)
A
11
I
Clock input
OE
38
I
Output enable. When asserted, OE puts all outputs in a high-impedance state. A nominal
140-kΩ pullup resistor is internally integrated.
SCLOCK
25
I
I2C serial clock input. A nominal 140-kΩ pullup resistor is internally integrated.
SDATA
24
I/O
GND
6, 10, 15, 19, 22, 26,
27, 30, 34, 39, 43
NC
1, 2, 47, 48
VCC
3, 7, 12, 16, 20, 23,
29, 33, 37, 42, 46
Bidirectional I2C serial data input/output. A nominal 140-kΩ pullup resistor is internally
integrated.
Ground
No internal connection. Reserved for future use.
3.3-V power supply
I2C DEVICE ADDRESS
A7
A6
A5
A4
A3
A2
A1
A0 (R/W)
H
H
L
H
L
L
H
—
I2C BYTE 0-BIT DEFINITION†
BIT
DEFINITION
DEFAULT VALUE
7
2Y3 enable (pin 18)
H
6
2Y2 enable (pin 17)
H
5
2Y1 enable (pin 14)
H
4
2Y0 enable (pin 13)
H
3
1Y3 enable (pin 9)
H
2
1Y2 enable (pin 8)
H
1
1Y1 enable (pin 5)
H
0
1Y0 enable (pin 4)
H
† When the value of the bit is high, the output is enabled.
When the value of the bit is low, the output is forced to a
low state. The default value of all bits is high.
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3
CDC318A
1-LINE TO 18-LINE CLOCK DRIVER
WITH I2C CONTROL INTERFACE
SCAS614 – SEPTEMBER 1998
I2C BYTE 1-BIT DEFINITION†
BIT
DEFINITION
DEFAULT VALUE
7
4Y3 enable (pin 45)
H
6
4Y2 enable (pin 44)
H
5
4Y1 enable (pin 41)
H
4
4Y0 enable (pin 40)
H
3
3Y3 enable (pin 36)
H
2
3Y2 enable (pin 35)
H
1
3Y1 enable (pin 32)
H
0
3Y0 enable (pin 31)
H
† When the value of the bit is high, the output is enabled.
When the value of the bit is low, the output is forced to a
low state. The default value of all bits is high.
I2C BYTE 2-BIT DEFINITION†
BIT
DEFINITION
DEFAULT VALUE
7
5Y1 enable (pin 28)
H
6
5Y0 enable (pin 21)
H
5
Reserved
H
4
Reserved
H
3
Reserved
H
2
Reserved
H
1
Reserved
H
0
Reserved
H
† When the value of the bit is high, the output is enabled.
When the value of the bit is low, the output is forced to a
low state. The default value of all bits is high.
4
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CDC318A
1-LINE TO 18-LINE CLOCK DRIVER
WITH I2C CONTROL INTERFACE
SCAS614 – SEPTEMBER 1998
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Input voltage range, VI (SCLOCK, SDATA) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
Output voltage range, VO (SDATA) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . . . . –0.5 V to VCC +0.5 V
Current into any output in the low state (except SDATA), IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA
Current into SDATA in the low state, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 mA
Input clamp current, IIK (VI < 0) (SCLOCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) (SDATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Package thermal impedance, θJA (see Notes 2 and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260_C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for through-hole packages,
which use a trace length of zero. The absolute maximum power dissipation allowed at TA = 55°C (in still air) is 1.2 W.
3. Thermal impedance (ΘJA) can be considerably lower if the device is soldered on the PCB board with a copper layer underneath the
package. A simulation on a PCB board (3 in. × 3 in.) with two internal copper planes (1 oz. cu, 0.036 mm thick) and 0.071 mm cu
(202) in area underneath the package, resulted in ΘJA = 60°C/W. This would allow 1.2 W total power dissipation at TA = 70°C.
recommended operating conditions (see Note 4)
MAX
UNIT
3.135
MIN
TYP
3.465
V
2
VCC+0.3
V
2.2
5.5
V
–0.3
0.8
V
0
1.04
V
Y outputs
–36
mA
Y outputs
24
mA
VCC
3.3-V core supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
SDATA, SCLOCK
(see Note 3)
IOH
IOL
High-level output current
Low-level output current
ri
Input resistance to VCC
SDATA, SCLOCK
(see Note 3)
f(SCL)
t(BUS)
SCLOCK frequency
Bus free time
4.7
µs
tsu(START)
th(START)
START setup time
4.7
µs
tw(SCLL)
tw(SCLH)
SCLOCK low pulse duration
tr(SDATA)
tf(SDATA)
SDATA input rise time
1000
ns
SDATA input fall time
300
ns
tsu(SDATA)
th(SDATA)
SDATA setup time
250
SDATA hold time
20
ns
tsu(STOP)
TA
STOP setup time
4
µs
Operating free-air temperature
0
A, OE
SDATA, SCLOCK
(see Note 3)
A, OE
140
kΩ
100
kHz
4
µs
4.7
µs
4
µs
START hold time
SCLOCK high pulse duration
ns
70
°C
NOTE 4: The CMOS-level inputs fall within these limits: VIH min = 0.7 × VCC and VIL max = 0.3 × VCC.
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5
CDC318A
1-LINE TO 18-LINE CLOCK DRIVER
WITH I2C CONTROL INTERFACE
SCAS614 – SEPTEMBER 1998
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
Input clamp voltage
VOH
High-level
g
output voltage
g
TEST CONDITIONS
Y outputs
Y outputs
VOL
IOH
IOL
Low level output voltage
Low-level
High level output current
High-level
Low-level output current
TYP
High-level input current
VCC = 3.135 V,
VCC = Min to Max,
IOH = –36 mA
IOL = 1 mA
VCC = 3.135 V,
IOL = 24 mA
IOL = 3 mA
0.4
IOL = 6 mA
VO = VCC MAX
0.6
SDATA
VCC = 3.135 V,
VCC = 3.135 V,
Y outputs
VCC = 3.3 V,
VCC = 3.465 V,
VCC = 3.135 V,
VCC = 3.3 V,
VCC –
0.1 V
0.1
0.4
20
VO = 2 V
VO = 1.65 V
– 54
VO = 3.135 V
VO = 1 V
– 21
VCC = 3.465 V,
VO = 1.65 V
VO = 0.4 V
VCC = 3.465 V,
VI = VCC
V
2.4
49
118
mA
93
24
53
20
20
–5
ICC
Supply current
∆ICC
Change in supply current
OE
VCC = 3.465 V,
VI = GND
VCC = 3.465 V,
VCC = 0,
VO = 3.465 V or 0
VI = 0 V to 5.5 V
SCLOCK, SDATA
SCLOCK, SDATA
VCC = 3.465 V,
IO = 0
VCC = 3.135 V to 3.465 V,
One input at VCC – 0.6 V,
All other inputs at VCC or GND
VCC = 3.465 V,
CL = 20 pF,
–10
– 50
– 10
– 50
±10
0.2
µA
µA
µA
50
µA
0.5
mA
500
µA
230
mA
VCC = 3.3 V
VCC = 3.3 V
4
pF
Output capacitance
VI = VCC or GND,
VO = VCC or GND,
6
pF
SDATA I/O capacitance
VI/O = VCC or GND,
VCC = 3.3 V
7
pF
CI
Input capacitance
CO
CI/O
6
mA
– 46
A
High-impedance-state output current
µA
–126
– 92
SCLOCK, SDATA
IOZ
Ioff
V
5
OE
Low-level input current
Dynamic ICC at 100 MHz
V
IOH = –1 mA
135 V
VCC = 3
3.135
IIL
Off-state current
UNIT
–1.2
VCC = Min to Max,
A
IIH
MAX
II = –18 mA
SDATA
Y outputs
MIN
VCC = 3.135 V,
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CDC318A
1-LINE TO 18-LINE CLOCK DRIVER
WITH I2C CONTROL INTERFACE
SCAS614 – SEPTEMBER 1998
switching characteristics over recommended operating conditions
PARAMETER
tPLH
Low-to-high level propagation delay time
tPLH
Low-to-high level propagation delay time
tPHL
High-to-low level propagation delay time
tPHL
High-to-low level propagation delay time
tPZH
tPZL
Enable time to the high level
tPHZ
tPLZ
Disable time from the high level
tsk(o)
tsk(p)
tsk(pr)
tr
FROM
TO
A
Y
SCLOCK↓
SDATA
valid
SDATA↑
Y
TEST CONDITIONS
MIN
MAX
1.2
4.5
ns
VCC = 3.3 V ±0.165 V,
See Figure 3
2
µs
VCC = 3.3 V ±0.165 V,
See Figure 3
150
ns
A
Y
4.5
ns
SCLOCK↓
SDATA
valid
VCC = 3.3 V ±0.165 V,
See Figure 3
2
µs
SDATA↑
Y
VCC = 3.3 V ±0.165 V,
See Figure 3
150
ns
OE
Y
OE
Y
Skew time
A
Y
250
ps
Skew time
A
Y
500
ps
Skew time
A
Y
1
ns
2.2
ns
Enable time to the low level
Disable time from the low level
Rise time
tr
Rise time (see
(
Note 5 and
Figure 3)
tf
Fall time
tf
Fall time ((see Note 5 and
Figure 3)
1.2
UNIT
Y
1
7
1
7
1
7
6
CL = 400 pF
Y
SDATA
7
0.5
CL = 10 pF
SDATA
1
950
0.5
CL = 10 pF
CL = 400 pF
2.3
20
250
ns
ns
ns
ns
ns
NOTE 5: This parameter has a lower limit than BUS specification. This allows use of series resistors for current spike protection.
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CDC318A
1-LINE TO 18-LINE CLOCK DRIVER
WITH I2C CONTROL INTERFACE
SCAS614 – SEPTEMBER 1998
PARAMETER MEASUREMENT INFORMATION
6V
S1
500 Ω
From Output
Under Test
TEST
tPLH /tPHL
tPLZ /tPZL
tPHZ /tPZH
Open
GND
CL = 30 pF
(see Note A)
500 Ω
S1
Open
6V
GND
tw
LOAD CIRCUIT FOR tpd AND tsk
3V
Input
1.5 V
1.5 V
From Output
Under Test
0V
VOLTAGE WAVEFORMS
CL = 30 pF
(see Note A)
1.5 V
0V
tPHL
2.4 V
0.4 V
tr
1.5 V
0V
tPLZ
1.5 V
tPLH
Output
1.5 V
tPZL
3V
Input
VCC
Output
Enable
(high-level
enabling)
LOAD CIRCUIT FOR tr AND tf
1.5 V
VOH
2.4 V
0.4 V
VOL
tf
≈3V
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
1.5 V
VOL
tPHZ
tPZH
VOLTAGE WAVEFORMS
VOL + 0.3 V
VOH
1.5 V
VOH – 0.3 V
≈0V
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
8
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CDC318A
1-LINE TO 18-LINE CLOCK DRIVER
WITH I2C CONTROL INTERFACE
SCAS614 – SEPTEMBER 1998
PARAMETER MEASUREMENT INFORMATION
A
1Y0
tPHL1
tPLH1
1Y1
tPHL2
tPLH2
1Y2
tPHL3
tPLH3
1Y3
tPHL4
tPLH4
2Y0
tPHL5
tPLH5
2Y1
tPHL6
tPLH6
2Y2
tPHL7
tPLH7
2Y3
tPHL8
tPLH8
3Y0
tPHL9
tPLH9
3Y1
tPHL10
tPLH10
3Y2
tPHL11
tPLH11
3Y3
tPHL12
tPLH12
4Y0
tPHL13
tPLH13
4Y1
tPHL14
tPLH14
4Y2
tPHL15
tPLH15
4Y3
tPHL16
tPLH16
5Y0
tPHL17
tPLH17
5Y1
tPHL18
tPLH18
NOTES: A. Output skew, tsk(o), is calculated as the greater of:
– The difference between the fastest and slowest of tPLHn (n = 1:18)
– The difference between the fastest and slowest of tPHLn (n = 1:18)
B. Pulse skew, tsk(p), is calculated as the greater of |tPLHn – tPHLn| (n = 1:18)
C. Process skew, tsk(pr), is calculated as the greater of:
– The difference between the fastest and slowest of tPLHn (n = 1:18) across multiple devices under identical operating conditions
– The difference between the fastest and slowest of tPHLn (n = 1:18) across multiple devices under identical operating conditions
Figure 2. Waveforms for Calculation of tsk(o), tsk(p), tsk(pr)
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CDC318A
1-LINE TO 18-LINE CLOCK DRIVER
WITH I2C CONTROL INTERFACE
SCAS614 – SEPTEMBER 1998
PARAMETER MEASUREMENT INFORMATION
VO = 3.3 V
RL = 1 kΩ
DUT
CL = 10 pF or
CL = 400 pF
GND
TEST CIRCUIT
4 to 6 Bytes for Complete Device
Programming
Start
Condition
(S)
Bit 7
MSB
tw(SCLL)
Bit 0
LSB
(R/W)
Bit 6
Acknowledge
(A)
Stop
Condition
(P)
tsu(START)
tw(SCLH)
0.7 VCC
0.3 VCC
SCLOCK
tsu(START)
tr
tPHL
tf
t(BUS)
tPLH
0.7 VCC
0.3 VCC
SDATA
tf(SDATA)
th(START)
tr(SDATA)
th(SDATA)
tsu(SDATA)
tsu(STOP)
Repeat Start
Condition
(see Note A)
Start or
Repeat Start
Condition
Stop Condition
VOLTAGE WAVEFORMS
BYTE
DESCRIPTION
1
I2C address
2
Command (dummy value, ignored)
3
Byte count (dummy value, ignored)
I2C data byte 0
4
5
6
I2C data byte 1
I2C data byte 2
NOTES: A. The repeat start condition is not supported.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 100 kHz, ZO = 50 Ω, tr ≥ 10 ns, tf ≥ 10 ns.
Figure 3. Propagation Delay Times, tr and tf
10
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CDC318A
1-LINE TO 18-LINE CLOCK DRIVER
WITH I2C CONTROL INTERFACE
SCAS614 – SEPTEMBER 1998
MECHANICAL INFORMATION
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PIN SHOWN
0.025 (0,635)
0.012 (0,305)
0.008 (0,203)
48
0.005 (0,13) M
25
0.006 (0,15) NOM
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
1
0°– 8°
24
0.040 (1,02)
A
0.020 (0,51)
Seating Plane
0.110 (2,79) MAX
0.004 (0,10)
0.008 (0,20) MIN
PINS **
28
48
56
A MAX
0.380
(9,65)
0.630
(16,00)
0.730
(18,54)
A MIN
0.370
(9,40)
0.620
(15,75)
0.720
(18,29)
DIM
4040048 / C 03/97
NOTES: A.
B.
C.
D.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
Falls within JEDEC MO-118
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