Freescale M68HC05 Microcontroller Datasheet

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Freescale Semiconductor, Inc.
MC68HC05J1A
MC68HCL05J1A
MC68HSC05J1A
Technical Data
M68HC05
Microcontrollers
MC68HC05J1A/D
Rev. 3, 4/2002
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MC68HC05J1A
MC68HCL05J1A
MC68HSC05J1A
Technical Data
To provide the most up-to-date information, the revision of our
documents on the World Wide Web will be the most current. Your printed
copy may be an earlier revision. To verify you have the latest information
available, refer to:
http://www.motorola.com/semiconductors/
The following revision history table summarizes changes contained in
this document. For your convenience, the page number designators
have been linked to the appropriate location.
MC68HC05J1A — Rev. 3.0
Technical Data
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Revision History
Date
July, 2001
Page
Number(s)
Description
10.5 Thermal Characteristics — In table under Thermal
resistance, device numbers corrected
97
Section 12. Ordering Information — Added Table 12-1. MC
Order Numbers for clarity
111
Update World Wide Web address
112
2.0
3.0
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April, 2002
Revision
Level
Technical Data
MC68HC05J1A — Rev. 3.0
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List of Sections
Section 1. General Description . . . . . . . . . . . . . . . . . . . . 17
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Section 2. Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Section 3. Central Processor Unit (CPU) . . . . . . . . . . . . 33
Section 4. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Section 5. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Section 6. Low-Power Modes. . . . . . . . . . . . . . . . . . . . . . 55
Section 7. Parallel Input/Output (I/O). . . . . . . . . . . . . . . . 61
Section 8. Multifunction Timer. . . . . . . . . . . . . . . . . . . . . 71
Section 9. Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . 77
Section 10. Electrical Specifications. . . . . . . . . . . . . . . . 95
Section 11. Mechanical Specifications . . . . . . . . . . . . . 109
Section 12. Ordering Information . . . . . . . . . . . . . . . . . 111
Appendix A. MC68HCL05J1A. . . . . . . . . . . . . . . . . . . . . 117
Appendix B. MC68HSC05J1A . . . . . . . . . . . . . . . . . . . . 123
MC68HC05J1A — Rev. 3.0
Technical Data
List of Sections
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List of Sections
Technical Data
MC68HC05J1A — Rev. 3.0
List of Sections
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Technical Data — MC68HC05J1A
Table of Contents
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Section 1. General Description
1.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.4
Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
1.5
MCU Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.6
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.6.1
VDD and VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.6.2
OSC1 and OSC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
1.6.2.1
Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.6.2.2
Ceramic Resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.6.2.3
RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.6.2.4
External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
1.6.3
RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.6.4
IRQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.6.5
PA7–PA0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.6.6
PB5–PB0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Section 2. Memory
2.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.3
Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.4
Input/Output (I/O) Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
2.5
Random-Access Memory (RAM) . . . . . . . . . . . . . . . . . . . . . . . 28
2.6
Read-Only Memory (ROM). . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
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Section 3. Central Processor Unit (CPU)
3.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
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3.3
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.3.1
Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.3.2
Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.3.3
Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.3.4
Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.3.5
Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.4
Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Section 4. Interrupts
4.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.3
Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.3.1
Software Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.3.2
External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.3.2.1
IRQ Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
4.3.2.2
PA3–PA0 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.3.2.3
IRQ Status and Control Register . . . . . . . . . . . . . . . . . . . 45
4.3.3
Timer Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.3.3.1
Timer Overflow Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.3.3.2
Real-Time Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.4
Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Section 5. Resets
5.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.3
Reset Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
5.3.1
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
5.3.2
External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.3.3
Computer Operating Properly (COP) Reset . . . . . . . . . . . . . 51
5.3.4
Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
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5.4
Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.4.1
CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.4.2
I/O Port Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.4.3
Multifunction Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5.4.4
COP Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
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Section 6. Low-Power Modes
6.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.3
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.4
Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6.5
Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.6
Data-Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Section 7. Parallel Input/Output (I/O)
7.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
7.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
7.3
I/O Port Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
7.4
Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
7.4.1
Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
7.4.2
Data Direction Register A. . . . . . . . . . . . . . . . . . . . . . . . . . . 63
7.4.3
Pulldown Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
7.4.4
Port A External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
7.5
Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
7.5.1
Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
7.5.2
Data Direction Register B. . . . . . . . . . . . . . . . . . . . . . . . . . . 68
7.5.3
Pulldown Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
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Section 8. Multifunction Timer
8.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
8.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
8.3
Timer Status and Control Register . . . . . . . . . . . . . . . . . . . . . . 73
8.4
COP Watchdog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
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Section 9. Instruction Set
9.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
9.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
9.3
Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
9.3.1
Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
9.3.2
Immediate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
9.3.3
Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
9.3.4
Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
9.3.5
Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
9.3.6
Indexed, 8-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
9.3.7
Indexed, 16-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
9.3.8
Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
9.4
Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
9.4.1
Register/Memory Instructions. . . . . . . . . . . . . . . . . . . . . . . .82
9.4.2
Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . . 83
9.4.3
Jump/Branch Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . 84
9.4.4
Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . . .86
9.4.5
Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
9.5
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
9.6
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Section 10. Electrical Specifications
10.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
10.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
10.3
Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
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10.4
Operating Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . 97
10.5
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
10.6
Power Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
10.7
5.0-Volt DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . .99
10.8
3.3-Volt DC Electrical Characteristics. . . . . . . . . . . . . . . . . . .100
10.9
5.0-Volt Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
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10.10 3.3-Volt Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Section 11. Mechanical Specifications
11.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
11.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
11.3
20-Pin Plastic Dual In-Line Package (PDIP). . . . . . . . . . . . . .110
11.4
20-Pin Small Outline Integrated Circuit Package (SOIC) . . . . 110
Section 12. Ordering Information
12.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
12.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
12.3
MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
12.4
MCU Ordering Forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
12.5
Application Program Media. . . . . . . . . . . . . . . . . . . . . . . . . . . 112
12.6
Diskettes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
12.7
EPROMs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
12.8
ROM Program Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
12.9
ROM Verification Units (RVUs). . . . . . . . . . . . . . . . . . . . . . . . 115
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Appendix A. MC68HCL05J1A
A.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
A.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
A.3
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 118
A.4
MC Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
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Appendix B. MC68HSC05J1A
B.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
B.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
B.3
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 124
B.4
Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
B.5
MC Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
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List of Figures
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Figure
Title
Page
1-1
1-2
1-3
MC68HC05J1A Block Diagram . . . . . . . . . . . . . . . . . . . . . . 20
Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Bypassing Layout Recommendation . . . . . . . . . . . . . . . . . . 22
1-4
1-8
1-9
Crystal Connections
with Feedback Resistor Mask Option . . . . . . . . . . . . . . . 23
Crystal Connections
without Feedback Resistor Mask Option. . . . . . . . . . . . . 23
Ceramic Resonator Connections
with Feedback Resistor Mask Option . . . . . . . . . . . . . . . 24
Ceramic Resonator Connections
without Feedback Resistor Mask Option. . . . . . . . . . . . . 24
RC Oscillator Connections . . . . . . . . . . . . . . . . . . . . . . . . . . 25
External Clock Connections . . . . . . . . . . . . . . . . . . . . . . . . . 25
2-1
2-2
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3-1
3-2
3-3
3-4
3-5
3-6
Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Index Register (X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . . 38
4-1
4-2
4-3
External Interrupt Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
IRQ Status and Control Register (ISCR) . . . . . . . . . . . . . . . 45
Stacking Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
1-5
1-6
1-7
MC68HC05J1A — Rev. 3.0
Technical Data
List of Figures
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List of Figures
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Figure
Title
Page
4-4
5-1
5-2
6-1
Interrupt Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
COP Register (COPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Stop/Wait/Halt Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
7-1
7-2
7-3
7-4
7-5
7-6
7-7
7-8
Port A Data Register (PORTA). . . . . . . . . . . . . . . . . . . . . . . 62
Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . . .63
Pulldown Register A (PDRA) . . . . . . . . . . . . . . . . . . . . . . . .64
Port A I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Port B Data Register (PORTB). . . . . . . . . . . . . . . . . . . . . . . 67
Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . .68
Pulldown Register B (PDRB) . . . . . . . . . . . . . . . . . . . . . . . .69
Port B I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
8-1
8-2
8-3
8-4
Multifunction Timer Block Diagram. . . . . . . . . . . . . . . . . . . .72
Timer Status and Control Register (TSCR) . . . . . . . . . . . . . 73
Timer Counter Register (TCNTR) . . . . . . . . . . . . . . . . . . . . 75
COP Register (COPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
10-1
10-2
10-3
10-4
10-5
10-6
10-7
10-8
10-9
10-10
10-11
Typical VOH/IOH (VDD = 5.0 V) . . . . . . . . . . . . . . . . . . . . . . 101
Typical VOH/IOH (VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . 101
Typical VOL/IOL (VDD = 5.0 V) . . . . . . . . . . . . . . . . . . . . . . 102
Typical VOL/IOL (VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . 102
Typical Operating IDD (25°C) . . . . . . . . . . . . . . . . . . . . . . .103
Typical Wait Mode IDD (25°C) . . . . . . . . . . . . . . . . . . . . . . 103
Typical Internal Operating Frequency
for Various VDD at 25°C — RC Option Only . . . . . . . . .104
External Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Stop Mode Recovery Timing . . . . . . . . . . . . . . . . . . . . . . .107
Power-On Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
A-1
A-2
Maximum Run Mode IDD versus Frequency . . . . . . . . . . . 120
Maximum Wait Mode IDD versus Frequency . . . . . . . . . . . 121
Technical Data
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List of Tables
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Table
Title
Page
4-1
Reset/Interrupt Vector Addresses . . . . . . . . . . . . . . . . . . . . . 47
7-1
7-2
Port A Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Port B Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
8-1
Real-Time Interrupt Rate Selection . . . . . . . . . . . . . . . . . . . . 74
9-1
9-2
9-3
9-4
9-5
9-6
9-7
Register/Memory Instructions. . . . . . . . . . . . . . . . . . . . . . . . . 82
Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . . . 83
Jump and Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . .85
Bit Manipulation Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . 86
Control Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
12-1
MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
A-1
A-2
A-3
A-4
A-5
Low-Power Output Voltage (VDD = 1.8–2.4 Vdc) . . . . . . . . .118
Low-Power Output Voltage (VDD = 2.5–3.6 Vdc) . . . . . . . . .118
Low-Power Supply Current. . . . . . . . . . . . . . . . . . . . . . . . . . 119
Low-Power Pulldown Current . . . . . . . . . . . . . . . . . . . . . . . . 120
MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
B-1
B-2
B-3
B-4
High-Speed Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . 124
High-Speed Control Timing (VDD = 5.0 V ± 10%). . . . . . . . .125
High-Speed Control Timing (VDD = 3.3 V ± 10%) . . . . . . . . 125
MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
MC68HC05J1A — Rev. 3.0
Technical Data
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List of Tables
Technical Data
MC68HC05J1A — Rev. 3.0
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Technical Data — MC68HC05J1A
Section 1. General Description
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1.1 Contents
1.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.4
Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
1.5
MCU Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.6
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.6.1
VDD and VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.6.2
OSC1 and OSC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
1.6.2.1
Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.6.2.2
Ceramic Resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.6.2.3
RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.6.2.4
External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
1.6.3
RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.6.4
IRQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.6.5
PA7–PA0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.6.6
PB5–PB0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
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General Description
1.2 Introduction
The MC68HC05J1A is a member of the low-cost, high-performance
M68HC05 Family of 8-bit microcontroller units (MCU). The M68HC05
Family is based on the customer-specified integrated circuit (CSIC)
design strategy. All MCUs in the family use the popular M68HC05
central processor unit (CPU) and are available with a variety of
subsystems, memory sizes and types, and package types.
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On-chip memory of the MC68HC05J1A includes:
•
1240 bytes of user read-only memory (ROM)
•
64 bytes of user random-access memory (RAM)
Information on the MC68HCL05J1A, a low-power version of the
MC68HC05J1A, is introduced in Appendix A. MC68HCL05J1A.
Information on the MC68HSC05J1A, a high-speed version of the
MC68HC05J1A, is introduced in Appendix B. MC68HSC05J1A.
1.3 Features
Features of the MCU include:
•
Popular M68HC05 CPU
•
Memory-mapped input/output (I/O) registers
•
1240 bytes of user ROM including eight user vector locations
•
64 bytes of user RAM
•
14 bidirectional I/O pins with these features:
– Software programmable pulldown devices
– Four I/O pins with 8-mA current sinking capability
– Four I/O pins with maskable external interrupt capability
•
Hardware mask and flag for external interrupts
•
Fully static operation with no minimum clock speed
•
On-chip oscillator with connections for a crystal or ceramic
resonator or for a resistor-capacitor (RC) network
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General Description
Mask Options
•
15-bit multifunction timer
•
Computer operating properly (COP) watchdog
•
Power-saving stop (or halt), wait, and data-retention modes
•
Illegal address reset
•
Internal steering diode between RESET and VDD pins
•
8 × 8 unsigned multiply instruction
•
20-pin plastic dual in-line package (PDIP)
•
20-pin small outline integrated circuit package (SOIC)
1.4 Mask Options
Available MC68HC05J1A mask options are:
•
On-chip oscillator connections: crystal/ceramic resonator
connections or resistor-capacitor (RC) network connections
•
Crystal/ceramic resonator feedback resistor: connected or not
connected (available only with crystal/ceramic oscillator mask
option)
•
STOP instruction: enabled or disabled (converted to WAIT
instruction)
•
External interrupt pins: edge-triggered or edge- and
level-triggered
•
Port A and port B pulldown resistors: connected or not connected
•
COP watchdog timer: enabled or disabled
•
Port A external interrupt capability: enabled or disabled
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General Description
1.5 MCU Structure
USER ROM — 1240 BYTES
ARITHMETIC/LOGIC
UNIT
CPU CONTROL
PA6
* 8-mA sink capability
** External interrupt capability
ACCUMULATOR
RESET
INDEX REGISTER
RESET
STACK POINTER
0 0 0 0 0 0 0 0 1 1
PROGRAM COUNTER
0 0 0 0 0
CONDITION CODE REGISTER
1 1 1 H I N C Z
POWER
VSS
OSC1
OSC2
PB4
PB3
PB2
PB1
PB0
MULTIFUNCTION
TIMER
COP WATCHDOG
AND
ILLEGAL ADDRESS
DETECT
VDD
PB5
PORT B
M68HC05
MCU
DATA DIRECTION REGISTER B
IRQ
CPU CLOCK
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USER RAM — 64 BYTES
*
*
PA5 *
PA4 *
PA3 **
PA2 **
PA1 **
PA0 **
PA7
PORT A
DATA DIRECTION REGISTER A
Figure 1-1 shows the structure of the MC68HC05J1A MCU.
INTERNAL
OSCILLATOR
DIVIDE
BY TWO
INTERNAL CLOCK
Figure 1-1. MC68HC05J1A Block Diagram
Technical Data
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General Description
Pin Assignments
1.6 Pin Assignments
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Figure 1-2 shows the MC68HC05J1A pin assignments.
OSC1
1
20
RESET
OSC2
2
19
IRQ
PB5
3
18
PA0
PB4
4
17
PA1
PB3
5
16
PA2
PB2
6
15
PA3
PB1
7
14
PA4
PB0
8
13
PA5
VDD
9
12
PA6
VSS
10
11
PA7
Figure 1-2. Pin Assignments
1.6.1 VDD and VSS
VDD and VSS are the power supply and ground pins. The MCU operates
from a single 5-V power supply.
Very fast signal transitions occur on the MCU pins, placing high
short-duration current demands on the power supply. To prevent noise
problems, take special care to provide good power supply bypassing at
the MCU. Place bypass capacitors as close to the MCU as possible, as
Figure 1-3 shows. C2 is an optional bulk current bypass capacitor for
use in applications that require the port pins to source high current
levels.
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V+
VDD
VDD
MCU
C1
0.1 µF
C2
+
C1
C2
VSS
VSS
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Figure 1-3. Bypassing Layout Recommendation
1.6.2 OSC1 and OSC2
The OSC1 and OSC2 pins are the control connections for the on-chip
oscillator. Depending on the mask option selected, the oscillator can be
driven by any one of these:
•
Crystal
•
Ceramic resonator
•
Resistor-capacitor (RC) network
•
External clock signal
The frequency of the internal oscillator is fOSC. The MCU divides the
internal oscillator output by two to produce the internal clock with a
frequency of fOP.
An internal feedback resistor between the OSC1 and OSC2 pins is
available as a mask option. The feedback resistor mask option is
available only when the crystal/ceramic resonator mask option is also
selected.
1.6.2.1 Crystal
With the crystal/ceramic resonator mask option, a crystal connected to
the OSC1 and OSC2 pins can drive the on-chip oscillator. Figure 1-4
and Figure 1-5 show a typical crystal oscillator circuit for an AT-cut,
parallel resonant crystal. Follow the crystal supplier’s recommendations,
as the crystal parameters determine the external component values
Technical Data
MC68HC05J1A — Rev. 3.0
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General Description
Pin Assignments
required to provide reliable startup and maximum stability. The load
capacitance values used in the oscillator circuit design should include all
stray layout capacitances. To minimize output distortion, mount the
crystal and capacitors as close as possible to the pins.
NOTE:
Use an AT-cut crystal and not an AT-strip crystal. The MCU may
overdrive an AT-strip crystal.
VSS
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MCU
C3
XTAL
OSC2
OSC1
OSC1
OSC2
C4
XTAL
C3
27 pF
C4
27 pF
VDD
C2
C1
VSS
Figure 1-4. Crystal Connections
with Feedback Resistor Mask Option
VSS
C3
MCU
R
10 MΩ
OSC2
OSC1
OSC1
XTAL
R
OSC2
C4
VDD
XTAL
C3
27 pF
C4
27 pF
C2
C1
VSS
Figure 1-5. Crystal Connections
without Feedback Resistor Mask Option
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1.6.2.2 Ceramic Resonator
To reduce cost, use a ceramic resonator in place of the crystal. Use the
circuit in Figure 1-6 or Figure 1-7 for a ceramic resonator and follow the
resonator manufacturer’s recommendations. The load capacitance
values used in the oscillator circuit design should include all stray layout
capacitances. To minimize output distortion, mount the resonator as
close as possible to the pins.
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VSS
CERAMIC
RESONATOR
C3
27 pF
CERAMIC
RESONATOR
C3
OSC2
OSC1
MCU
OSC1
OSC2
C4
C4
27 pF
VDD
C2
C1
VSS
Figure 1-6. Ceramic Resonator Connections
with Feedback Resistor Mask Option
VSS
C3
CERAMIC
RESONATOR
R
10 MΩ
OSC2
OSC1
MCU
OSC1
R
OSC2
C4
C3
27 pF
CERAMIC
RESONATOR
VDD
C4
27 pF
C2
C1
VSS
Figure 1-7. Ceramic Resonator Connections
without Feedback Resistor Mask Option
Technical Data
MC68HC05J1A — Rev. 3.0
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General Description
Pin Assignments
1.6.2.3 RC Oscillator
OSC1
R
MCU
R
OSC2
OSC2
OSC1
VDD
C2
C1
VSS
Figure 1-8. RC Oscillator Connections
1.6.2.4 External Clock
With the RC oscillator mask option, an external clock from another
CMOS-compatible device can drive the OSC1 input. Leave the OSC2
pin unconnected, as Figure 1-9 shows.
OSC2
MCU
OSC1
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For maximum cost reduction, the RC oscillator mask option allows the
configuration shown in Figure 1-8 to drive the on-chip oscillator. The
OSC2 signal is a square wave, and the signal on OSC1 is a triangular
wave. The optimum frequency for the RC oscillator configuration is
2 MHz. Mount the RC components as close as possible to the pins for
startup stabilization and to minimize output distortion.
EXTERNAL
CMOS CLOCK
Figure 1-9. External Clock Connections
MC68HC05J1A — Rev. 3.0
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1.6.3 RESET
A logic 0 on the RESET pin forces the MCU to a known startup state.
See 5.3.2 External Reset for more information.
1.6.4 IRQ
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The IRQ pin is an asynchronous external interrupt pin.
See 4.3.2.1 IRQ Pin.
1.6.5 PA7–PA0
PA7–PA0 are the pins of port A, a general-purpose, bidirectional I/O
port. See 7.4 Port A.
1.6.6 PB5–PB0
PB5–PB0 are the pins of port B, a general-purpose, bidirectional I/O
port. See 7.5 Port B.
Technical Data
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Technical Data — MC68HC05J1A
Section 2. Memory
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2.1 Contents
2.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.3
Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.4
Input/Output (I/O) Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
2.5
Random-Access Memory (RAM) . . . . . . . . . . . . . . . . . . . . . . . 28
2.6
Read-Only Memory (ROM). . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.2 Introduction
This section describes the organization of the on-chip memory.
2.3 Memory Map
The central processor unit (CPU) can address 2 Kbytes of memory
space as shown in Figure 2-1. The read-only memory (ROM) portion of
memory holds the program instructions, fixed data, user-defined vectors,
and interrupt service routines. The random-access memory (RAM)
portion of memory holds variable data. Input/output (I/O) registers are
memory-mapped so that the CPU can access their locations in the same
way that it accesses all other memory locations.
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Memory
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Memory
2.4 Input/Output (I/O) Section
The first 32 addresses of the memory space, $0001–$001F, are the I/O
section. These are the addresses of the I/O control registers, status
registers, and data registers. See Figure 2-2.
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One I/O register shown in Figure 2-2 is located outside the 32-byte I/O
section: the computer operating properly (COP) register is mapped at
$07F0.
2.5 Random-Access Memory (RAM)
The 64 addresses from $00C0 to $00FF serve as both the user RAM and
the stack RAM. The CPU uses five stack RAM bytes to save all CPU
register contents before processing an interrupt. During a subroutine
call, the CPU uses two bytes to store the return address. The stack
pointer decrements during pushes and increments during pulls.
NOTE:
Be careful when using nested subroutines or multiple interrupt levels.
The CPU may overwrite data in the RAM during a subroutine or during
the interrupt stacking operation.
2.6 Read-Only Memory (ROM)
The ROM is located in two areas of the memory map:
1. Addresses $0300–$07CF contain 1232 bytes of user ROM.
2. Addresses $07F8–$07FF contain 16 bytes of ROM reserved for
user vectors.
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Memory
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Memory
Read-Only Memory (ROM)
$0000
PORT A DATA REGISTER
PORT B DATA REGISTER
UNUSED
UNUSED
PORT A DATA DIRECTION REGISTER
PORT B DATA DIRECTION REGISTER
UNUSED
UNUSED
TIMER STATUS AND CONTROL REGISTER
TIMER COUNTER REGISTER
IRQ STATUS AND CONTROL REGISTER
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
PORT A PULLDOWN REGISTER
PORT B PULLDOWN REGISTER
UNUSED
UNUSED
UNUSED
I/O REGISTERS
32 BYTES
$001F
$0020
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$00BF
$00C0
UNUSED
160 BYTES
USER
RAM
64 BYTES
$00FF
$0100
$02FF
$0300
STACK
RAM
64 BYTES
$07CF
$07D0
TEST ROM
32 BYTES
$07F7
$07F8
$07FF
COP REGISTER *
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
TIMER VECTOR (HIGH BYTE)
TIMER VECTOR (LOW BYTE)
EXTERNAL INTERRUPT VECTOR (HIGH BYTE)
EXTERNAL INTERRUPT VECTOR (LOW BYTE)
SOFTWARE INTERRUPT VECTOR (HIGH BYTE)
SOFTWARE INTERRUPT VECTOR (LOW BYTE)
RESET VECTOR (LOW BYTE)
RESET VECTOR (LOW BYTE)
$07F0
$07F1
$07F2
$07F3
$07F4
$07F5
$07F6
$07F7
$07F8
$07F9
$07FA
$07FB
$07FC
$07FD
$07FE
$07FF
UNUSED
512 BYTES
USER ROM
1232 BYTES
$07EF
$07F0
•
•
•
RESERVED
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
$000C
$000D
$000E
$000F
$0010
$0011
$0012
$0013
$0014
•
•
•
$001F
RESERVED FOR TEST (ROM)
8 BYTES
USER VECTORS (ROM)
8 BYTES
to bit 0 of $07F0 clears the COP
*Writing
watchdog. Reading $07F0 returns ROM
data.
Figure 2-1. Memory Map
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Memory
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Memory
Addr.
Register Name
Read:
Port A Data Register
(PORTA) Write:
See page 62.
Reset:
$0000
Read:
Port B Data Register
(PORTB) Write:
See page 67.
Reset:
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$0001
$0002
Unimplemented
$0003
Unimplemented
$0004
$0005
Bit 7
6
5
4
3
2
1
Bit 0
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
PB2
PB1
PB0
Unaffected by reset
0
PB5
PB4
PB3
Unaffected by reset
Read:
Data Direction Register A
DDRA7
(DDRA) Write:
See page 63.
Reset:
0
Read:
Data Direction Register B
(DDRB) Write:
See page 68.
Reset:
0
0
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
0
0
0
0
0
0
0
DDRB5
DDRB4
DDRB3
DDRB2
DDRB1
DDRB0
0
0
0
0
0
0
0
0
TOIE
RTIE
RT1
RT0
TOFR
RTIFR
0
0
0
RTIF
$0006
Unimplemented
$0007
Unimplemented
TOF
$0008
Read:
Timer Status and Control
Register (TSCR) Write:
See page 73.
Reset:
0
0
0
0
0
0
1
1
Read:
Timer Counter Register
(TCNTR) Write:
See page 75.
Reset:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
0
0
0
0
$0009
$000A
Read:
IRQ Status and Control
Register (ISCR) Write:
See page 45.
Reset:
IRQF
IRQE
0
IRQR
1
0
0
= Unimplemented
0
0
R
= Reserved
0
0
0
U = Unaffected
Figure 2-2. I/O Register Summary (Sheet 1 of 2)
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Memory
Read-Only Memory (ROM)
Addr.
Register Name
$000B
Unimplemented
Bit 7
6
5
4
3
2
1
Bit 0
PDIA6
PDIA5
PDIA4
PDIA3
PDIA2
PDIA1
PDIA0
0
0
0
0
0
0
0
PDIB5
PDIB4
PDIB3
PDIB2
PDIB1
PDIB0
↓
$000F
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$0010
$0011
$0012
Unimplemented
Read:
Pulldown Register A
(PDRA) Write: PDIA7
See page 64.
Reset:
0
Read:
Pulldown Register B
(PDRB) Write:
See page 69.
Reset:
U
U
0
0
0
0
0
0
R
R
R
R
R
R
R
R
Unimplemented
↓
$001E
Unimplemented
Read:
$001F
Reserved
Write:
Reset:
$07F0
COP Register Read:
(COPR)
Write:
See page 51.
Reset:
Unaffected by reset
COPC
U
U
U
U
U
= Unimplemented
R
= Reserved
U
U
0
U = Unaffected
Figure 2-2. I/O Register Summary (Sheet 2 of 2)
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Memory
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Technical Data — MC68HC05J1A
Section 3. Central Processor Unit (CPU)
3.1 Contents
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3.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.3
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.3.1
Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.3.2
Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.3.3
Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.3.4
Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.3.5
Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.4
Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.2 Introduction
This section describes the central processor unit (CPU) registers.
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Central Processor Unit (CPU)
3.3 CPU Registers
Figure 3-1 shows the five CPU registers. CPU registers are not part of
the memory map.
7
6
5
4
3
2
1
0
ACCUMULATOR (A)
7
6
5
4
3
2
1
0
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INDEX
REGISTER (X)
15
14
13
12
11
10
9
8
7
6
0
0
0
0
0
0
0
0
1
1
15
14
13
12
11
10
9
8
7
6
0
0
0
0
0
5
4
3
2
1
0
STACK
POINTER (SP)
SP
5
4
3
2
1
0
PROGRAM
COUNTER (PC)
PCH
PCL
7
6
5
4
3
2
1
0
1
1
1
H
I
N
Z
C
CONDITION CODE
REGISTER (CCR)
HALF-CARRY FLAG
INTERRUPT MASK
NEGATIVE FLAG
ZERO FLAG
CARRY/BORROW FLAG
Figure 3-1. Programming Model
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Central Processor Unit (CPU)
CPU Registers
3.3.1 Accumulator
The accumulator (A) shown in Figure 3-2 is a general-purpose 8-bit
register. The CPU uses the accumulator to hold operands and results of
arithmetic and non-arithmetic operations.
Bit 7
6
5
4
3
2
1
Bit 0
Read:
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Write:
Reset:
Unaffected by reset
Figure 3-2. Accumulator (A)
3.3.2 Index Register
In the indexed addressing modes, the CPU uses the byte in the index
register (X) shown in Figure 3-3 to determine the conditional address of
the operand. See 9.3.5 Indexed, No Offset, 9.3.6 Indexed, 8-Bit
Offset, and 9.3.7 Indexed, 16-Bit Offset for more information on
indexed addressing.
The 8-bit index register also can serve as a temporary data storage
location.
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Unaffected by reset
Figure 3-3. Index Register (X)
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Central Processor Unit (CPU)
3.3.3 Stack Pointer
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The stack pointer (SP) shown in Figure 3-4 is a 16-bit register that
contains the address of the next free location on the stack. During a reset
or after the reset stack pointer (RSP) instruction, the stack pointer
initializes to $00FF. The address in the stack pointer decrements as data
is pushed onto the stack and increments as data is pulled from the stack.
The 10 most significant bits of the stack pointer are fixed permanently at
0000000011, so the stack pointer produces addresses from $00C0 to
$00FF. If subroutines and interrupts use more than 64 stack locations,
the stack pointer wraps around to address $00FF and begins writing
over the previously stored data. A subroutine uses two stack locations.
An interrupt uses five locations.
Read:
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Bit
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Write:
Reset:
= Unimplemented
Figure 3-4. Stack Pointer (SP)
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CPU Registers
3.3.4 Program Counter
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The program counter (PC) shown in Figure 3-5 is a 16-bit register that
contains the address of the next instruction or operand to be fetched.
The five most significant bits of the program counter are ignored
internally and appear as 00000.
Normally, the address in the program counter automatically increments
to the next sequential memory location every time an instruction or
operand is fetched. Jump, branch, and interrupt operations load the
program counter with an address other than that of the next sequential
location.
Read:
Bit
15
14
13
12
11
0
0
0
0
0
0
0
0
0
0
10
9
8
7
6
5
4
3
2
1
Bit
0
Write:
Reset:
Loaded with vector from $07FE and $07FF
Figure 3-5. Program Counter (PC)
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3.3.5 Condition Code Register
The condition code register (CCR) shown in Figure 3-6 is an 8-bit
register whose three most significant bits are permanently fixed at 111.
The condition code register contains the interrupt mask and four flags
that indicate the results of prior instructions.
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Read:
Bit 7
6
5
1
1
1
4
3
2
1
Bit 0
H
I
N
Z
C
U
1
U
U
U
Write:
Reset:
1
1
1
= Unimplemented
U = Unaffected
Figure 3-6. Condition Code Register (CCR)
H — Half-Carry Flag
The CPU sets the half-carry flag when a carry occurs between bits 3
and 4 of the accumulator during an add without carry (ADD) or add
with carry (ADC) operation. The half-carry bit is required for
binary-coded decimal (BCD) arithmetic operations. Reset has no
effect on the half-carry flag.
I — Interrupt Mask Flag
Setting the interrupt mask (I) disables interrupts. If an interrupt
request occurs while the interrupt mask is a logic 0, the CPU saves
the CPU registers on the stack, sets the interrupt mask, and then
fetches the interrupt vector. If an interrupt request occurs while the
interrupt mask is set, the interrupt request is latched. The CPU
processes the latched interrupt as soon as the interrupt mask is
cleared again.
A return-from-interrupt (RTI) instruction pulls the CPU registers from
the stack, restoring the interrupt mask to its cleared state. After a
reset, the interrupt mask is set and can be cleared only by a clear
interrupt mask bit (CLI), STOP, or WAIT instruction.
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Central Processor Unit (CPU)
Arithmetic/Logic Unit (ALU)
N — Negative Flag
The CPU sets the negative flag when an arithmetic operation, logical
operation, or data manipulation produces a negative result (bit 7 in the
results is a logic 1). Reset has no effect on the negative flag.
Z — Zero Flag
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The CPU sets the zero flag when an arithmetic operation, logical
operation, or data manipulation produces a result of $00. Reset has
no effect on the zero flag.
C — Carry/Borrow Flag
The CPU sets the carry/borrow flag when an addition operation
produces a carry out of bit 7 of the accumulator or when a subtraction
operation requires a borrow. Some logical operations and data
manipulation instructions also clear or set the carry/borrow bit. Reset
has no effect on the carry/borrow flag.
3.4 Arithmetic/Logic Unit (ALU)
The arithmetic/logic unit (ALU) performs the arithmetic and logical
operations defined by the instruction set. The binary arithmetic circuits
decode instructions and set up the ALU for the selected operation. Most
binary arithmetic is based on the addition algorithm, carrying out
subtraction as negative addition. Multiplication is not performed as a
discrete operation but as a chain of addition and shift operations within
the ALU. The multiply instruction requires 11 internal clock cycles to
complete this chain of operations.
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Technical Data — MC68HC05J1A
Section 4. Interrupts
4.1 Contents
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4.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.3
Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.3.1
Software Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.3.2
External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.3.2.1
IRQ Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
4.3.2.2
PA3–PA0 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.3.2.3
IRQ Status and Control Register . . . . . . . . . . . . . . . . . . . 45
4.3.3
Timer Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.3.3.1
Timer Overflow Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.3.3.2
Real-Time Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.4
Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
4.2 Introduction
This section describes how interrupts temporarily change the normal
processing sequence.
4.3 Interrupt Sources
These sources can generate interrupt requests:
•
SWI (software interrupt) instruction
•
IRQ pin
•
PA3–PA0 pins (mask option)
•
Multifunction timer
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Interrupts
An interrupt temporarily stops normal program execution to process a
particular event. An interrupt does not stop the execution of the
instruction in progress, but takes effect when the current instruction
completes its execution. Interrupt processing automatically saves the
central processor unit (CPU) registers on the stack and loads the
program counter with a user-defined vector address.
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4.3.1 Software Interrupt
The software interrupt (SWI) instruction causes a non-maskable
interrupt.
4.3.2 External Interrupts
These sources can generate external interrupts:
•
IRQ pin
•
PA3–PA0 pins (mask option)
Setting the I bit in the condition code register or clearing the IRQE bit in
the interrupt status and control register disables external interrupts.
4.3.2.1 IRQ Pin
An interrupt signal on the IRQ pin latches an external interrupt request.
When the CPU completes its current instruction, it tests the IRQ latch. If
the IRQ latch is set, the CPU then tests the I bit in the condition code
register and the IRQE bit in the interrupt status and control register. If the
I bit is clear and the IRQE bit is set, the CPU then begins the interrupt
sequence. The CPU clears the IRQ latch while it fetches the interrupt
vector, so that another external interrupt request can be latched during
the interrupt service routine. As soon as the I bit is cleared during the
return from interrupt, the CPU can recognize the new interrupt request.
Figure 4-1 shows the external interrupt logic.
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Interrupts
Interrupt Sources
TO BIH & BIL
INSTRUCTION
PROCESSING
IRQ
LEVEL-SENSITIVE TRIGGER
PA3
(MASK OPTION)
VDD
PA2
IRQ
LATCH
EXTERNAL
INTERRUPT
REQUEST
R
PORT A
EXTERNAL INTERRUPTS
ENABLED
IRQR
RST
IRQ VECTOR FETCH
IRQF
PA0
IRQE
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PA1
IRQ STATUS AND CONTROL REGISTER
(MASK OPTION)
INTERNAL DATA BUS
Figure 4-1. External Interrupt Logic
External interrupt triggering sensitivity is a mask option. The IRQ pin can
be negative edge-triggered only or negative edge- and low
level-triggered.
With the mask option for an edge- and level-sensitive external interrupt
trigger, a falling edge or a low level on the IRQ pin latches an external
interrupt request. Edge- and level-sensitive triggering allows the use of
multiple wired-OR external interrupt sources. An external interrupt
request is latched as long as any source is holding the IRQ pin low.
With the mask option for an edge-sensitive only external interrupt trigger,
a falling edge on the IRQ pin latches an external interrupt request. A
subsequent external interrupt request can be latched only after the
voltage level on the IRQ pin returns to logic 1 and then falls again to
logic 0.
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4.3.2.2 PA3–PA0 Pins
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The mask option for port A external interrupts enables pins PA3–PA0 to
serve as additional external interrupt sources. An interrupt signal on a
PA3–PA0 pin latches an external interrupt request. After completing the
current instruction, the CPU tests the IRQ latch. If the IRQ latch is set,
the CPU then tests the I bit in the condition code register and the IRQE
bit in the interrupt status and control register. If the I bit is clear and the
IRQE bit is set, the CPU then begins the interrupt sequence. The CPU
clears the IRQ latch while it fetches the interrupt vector, so that another
external interrupt request can be latched during the interrupt service
routine. As soon as the I bit is cleared during the return from interrupt,
the CPU can recognize the new interrupt request.
External interrupt triggering sensitivity is a mask option. The PA3–PA0
pins can be positive edge-triggered only or positive edge- and high
level-triggered.
With the mask option for an edge- and level-sensitive external interrupt
trigger, a rising edge or a high level on a PA3–PA0 pin latches an
external interrupt request. Edge- and level-sensitive triggering allows the
use of multiple wired-OR external interrupt sources. As long as any
source is holding a PA3–PA0 pin high, an external interrupt request is
latched, and the CPU continues to execute the interrupt service routine.
With the mask option for an edge-sensitive only external interrupt trigger,
a rising edge on a PA3–PA0 pin latches an external interrupt request. A
subsequent external interrupt request can be latched only after the
voltage level of the previous interrupt signal returns to logic 0 and then
rises again to logic 1.
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Interrupts
Interrupt Sources
4.3.2.3 IRQ Status and Control Register
The IRQ status and control register (ISCR), shown in Figure 4-2,
contains an external interrupt mask, an external interrupt flag, and a flag
reset bit.
Address:
$000A
Bit 7
Read:
6
5
4
3
2
0
0
0
0
Write:
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Bit 0
IRQF
IRQE
Reset:
1
0
IRQR
1
0
0
0
0
0
0
0
= Unimplemented
Figure 4-2. IRQ Status and Control Register (ISCR)
IRQE — External Interrupt Request Enable Bit
This read/write bit enables external interrupts. Resets set the IRQE
bit.
1 = External interrupt processing enabled
0 = External interrupt processing disabled
IRQF — External Interrupt Request Flag
The IRQ flag is a clearable, read-only bit that is set when an external
interrupt request is pending. Resets clear the IRQF bit.
1 = Interrupt request pending
0 = No interrupt request pending
These conditions set the IRQ flag:
a. An external interrupt signal on the IRQ pin
b. An external interrupt signal on pin PA3, PA2, PA1, or PA0
when PA3–PA0 are enabled to serve as external interrupt
sources
The CPU clears the IRQ flag when fetching the interrupt vector.
Writing to the IRQ flag has no effect. Clear the IRQ flag by writing a
logic 1 to the IRQR bit.
IRQR — Interrupt Request Reset Bit
This write-only bit clears the IRQ flag.
1 = IRQF bit cleared
0 = No effect
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Interrupts
4.3.3 Timer Interrupts
The multifunction timer can generate these interrupts:
•
Timer overflow interrupt
•
Real-time interrupt
Setting the I bit in the condition code register disables timer interrupts.
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4.3.3.1 Timer Overflow Interrupt
A timer overflow interrupt request occurs if the timer overflow flag, TOF,
becomes set while the timer overflow interrupt enable bit, TOIE, is also
set. See 8.3 Timer Status and Control Register.
4.3.3.2 Real-Time Interrupt
A real-time interrupt request occurs if the real-time interrupt flag, RTIF,
becomes set while the real-time interrupt enable bit, RTIE, is also set.
See 8.3 Timer Status and Control Register.
4.4 Interrupt Processing
The CPU takes these actions to begin servicing an interrupt:
•
Stores the CPU registers on the stack in the order shown
in Figure 4-3
•
Sets the I bit in the condition code register to prevent further
interrupts
•
Loads the program counter with the contents of the appropriate
interrupt vector locations:
– $07FC and $07FD (software interrupt vector)
– $07FA and $07FB (external interrupt vector)
– $07F8 and $07F9 (timer interrupt vector)
The return-from-interrupt (RTI) instruction causes the CPU to recover
the CPU registers from the stack as shown in Figure 4-3.
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Interrupts
Interrupt Processing
$00C0 (BOTTOM OF STACK)
$00C1
$00C2
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UNSTACKING
ORDER
•
•
•
•
•
•
5
1
CONDITION CODE REGISTER
4
2
ACCUMULATOR
3
3
INDEX REGISTER
2
4
PROGRAM COUNTER (HIGH BYTE)
1
5
PROGRAM COUNTER (LOW BYTE)
STACKING
ORDER
•
•
•
•
•
•
$00FD
$00FE
$00FF (TOP OF STACK)
Figure 4-3. Stacking Order
Table 4-1 summarizes the reset and interrupt sources and vector
assignments.
Table 4-1. Reset/Interrupt Vector Addresses
Local
Mask
Global
Mask
Priority
(1 = Highest)
Vector Address
Reset
Power-on
RESET pin
COP watchdog(1)
illegal address
None
None
None
None
None
1
1
1
1
$07FE–$07FF
Software
interrupt
(SWI)
User code
None
None
Same priority
as instruction
$07FC–$07FD
External
interrupt
IRQ pin
PA3 pin(2)
PA2 pin(2)
PA1 pin(2)
PA0 pin(2)
IRQE bit
I bit
2
$07FA–$07FB
Timer
interrupts
TOF bit
RTIF bit
TOFE bit
RTIE bit
I bit
3
$07F8–$07F9
Function
Source
1. The COP watchdog is a mask option.
2. Port A external interrupt capability is a mask option.
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Interrupts
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Interrupts
Figure 4-4 shows the sequence of events caused by an interrupt.
FROM
RESET
YES
I BIT SET?
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NO
EXTERNAL
INTERRUPT?
YES
CLEAR IRQ LATCH
NO
TIMER
INTERRUPT?
YES
STACK PCL, PCH, X, A, CCR
SET I BIT
LOAD PC WITH INTERRUPT VECTOR
NO
FETCH NEXT
INSTRUCTION
SWI
INSTRUCTION?
YES
NO
RTI
INSTRUCTION?
YES
UNSTACK CCR, A, X, PCH, PCL
NO
EXECUTE INSTRUCTION
Figure 4-4. Interrupt Flowchart
Technical Data
MC68HC05J1A — Rev. 3.0
Interrupts
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Technical Data — MC68HC05J1A
Section 5. Resets
5.1 Contents
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5.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.3
Reset Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
5.3.1
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
5.3.2
External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.3.3
Computer Operating Properly (COP) Reset . . . . . . . . . . . . . 51
5.3.4
Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.4
Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.4.1
CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.4.2
I/O Port Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.4.3
Multifunction Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5.4.4
COP Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5.2 Introduction
This section describes the four reset sources and how they initialize the
microcontroller unit (MCU).
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Resets
5.3 Reset Types
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A reset immediately stops the operation of the instruction being
executed, initializes certain control bits, and loads the program counter
with a user-defined reset vector address. These conditions produce a
reset:
•
Initial power-up (power-on reset)
•
A logic 0 applied to the RESET pin (external reset)
•
Timeout of the mask-optional computer operating properly (COP)
watchdog (COP reset)
•
An opcode fetch from an address not in the memory map (illegal
address reset)
Figure 5-1 is a block diagram of the reset sources.
COP WATCHDOG
(MASK OPTION)
VDD
POWER-ON RESET
ILLEGAL ADDRESS RESET
INTERNAL ADDRESS BUS
R
RESET
RESET
LATCH
RST
TO CPU
AND
SUBSYSTEMS
INTERNAL CLOCK
Figure 5-1. Reset Sources
5.3.1 Power-On Reset
A positive transition on the VDD pin generates a power-on reset. The
power-on reset is strictly for power-up conditions and cannot be used to
detect drops in power supply voltage.
Technical Data
MC68HC05J1A — Rev. 3.0
Resets
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Resets
Reset Types
A 4064 tCYC (internal clock cycle) delay after the oscillator becomes
active allows the clock generator to stabilize. If the RESET pin is at logic
0 at the end of 4064 tCYC, the MCU remains in the reset condition until
the signal on the RESET pin goes to logic 1.
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5.3.2 External Reset
A logic 0 applied to the RESET pin for one and one-half tCYC generates
an external reset. A Schmitt trigger senses the logic level at the RESET
pin.
5.3.3 Computer Operating Properly (COP) Reset
A timeout of the COP watchdog generates a COP reset. The COP
watchdog is part of a software error detection system and must be
cleared periodically to start a new timeout period. See 8.4 COP
Watchdog.
To clear the COP watchdog and prevent a COP reset, write a logic 0 to
bit 0 (COPC) of the COP register at location $07F0. The COP register,
shown in Figure 5-2, is a write-only register that returns the contents of
a ROM location when read.
The COP watchdog function is a mask option.
Address:
$07F0
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
COPC
U
U
U
= Unimplemented
U
U
U
U
0
U = Unaffected by reset
Figure 5-2. COP Register (COPR)
COPC — COP Clear Bit
COPC is a write-only bit. Periodically writing a logic 0 to COPC
prevents the COP watchdog from resetting the MCU.
MC68HC05J1A — Rev. 3.0
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Resets
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Resets
5.3.4 Illegal Address Reset
An opcode fetch from an address that is not in the ROM (locations
$0300–$07FF) or the RAM (locations $00C0–$00FF) generates an
illegal address reset.
5.4 Reset States
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This subsection describes how resets initialize the MCU.
5.4.1 CPU
A reset has the following effects on the CPU:
•
Loads the stack pointer with $FF
•
Sets the I bit in the condition code register, inhibiting interrupts
•
Sets the IRQE bit in the interrupt status and control register
•
Loads the program counter with the user-defined reset vector from
locations $07FE and $07FF
•
Clears the stop latch, enabling the CPU clock
•
Clears the wait latch, waking the CPU from the wait mode
5.4.2 I/O Port Registers
A reset has these effects on I/O port registers:
•
Clears bits DDRA7–DDRA0 in data direction register A so that port
A pins are inputs
•
Clears bits PDIA7–PDIA0 in pulldown register A so that port A
pulldown devices are enabled
•
Clears bits DDRB5–DDRB0 in data direction register B so that port
B pins are inputs
•
Clears bits PDIB5–PDIB0 in pulldown register B so that port B
pulldown devices are enabled
•
Has no effect on port A or port B data registers
Technical Data
MC68HC05J1A — Rev. 3.0
Resets
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Resets
Reset States
5.4.3 Multifunction Timer
A reset has these effects on the multifunction timer:
•
Clears the timer status and control register
•
Clears the timer counter register
5.4.4 COP Watchdog
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A reset clears the COP watchdog, if the COP watchdog is enabled by
mask option.
MC68HC05J1A — Rev. 3.0
Technical Data
Resets
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Resets
Technical Data
MC68HC05J1A — Rev. 3.0
Resets
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Technical Data — MC68HC05J1A
Section 6. Low-Power Modes
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6.1 Contents
6.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.3
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.4
Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6.5
Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.6
Data-Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6.2 Introduction
This section describes the four low-power modes:
•
Stop mode
•
Wait mode
•
Halt mode (mask option)
•
Data-retention mode
6.3 Stop Mode
The STOP instruction puts the microcontroller unit (MCU) in its lowest
power-consumption mode and has these effects on the MCU:
•
Clears TOF and RTIF, the timer interrupt flags in the timer status
and control register, removing any pending timer interrupts
•
Clears TOIE and RTIE, the timer interrupt enable bits in the timer
status and control register, disabling further timer interrupts
•
Clears the multifunction timer counter
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Low-Power Modes
•
Sets the IRQE bit in the IRQ status and control register to enable
external interrupts
•
Clears the I bit in the condition code register, enabling interrupts
•
Stops the internal oscillator, turning off the central processor unit
(CPU) clock and the timer clock, including the computer operating
properly (COP) watchdog
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The STOP instruction does not affect any other registers or any
input/output (I/O) lines.
These conditions bring the MCU out of stop mode:
•
An external interrupt signal on the IRQ pin — A high-to-low
transition on the IRQ pin loads the program counter with the
contents of locations $07FA and $07FB.
•
An external interrupt signal on a port A external interrupt
pin — If the mask option for the port A external interrupt function
is selected, a low-to-high transition on a PA3–PA0 pin loads the
program counter with the contents of locations $07FA and $07FB.
•
External reset — A logic 0 on the RESET pin resets the MCU and
loads the program counter with the contents of locations $07FE
and $07FF.
When the MCU exits stop mode, processing resumes after a
stabilization delay of 4064 oscillator cycles.
6.4 Wait Mode
The WAIT instruction puts the MCU in an intermediate
power-consumption mode and has these effects on the MCU:
•
Clears the I bit in the condition code register, enabling interrupts
•
Sets the IRQE bit in the IRQ status and control register, enabling
external interrupts
•
Stops the central processor unit (CPU) clock, but allows the
internal oscillator and timer clock to continue to run
The WAIT instruction does not affect any other registers or any I/O lines.
Technical Data
MC68HC05J1A — Rev. 3.0
Low-Power Modes
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Low-Power Modes
Halt Mode
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These conditions restart the CPU clock and bring the MCU out of wait
mode:
•
An external interrupt signal on the IRQ pin — A high-to-low
transition on the IRQ pin loads the program counter with the
contents of locations $07FA and $07FB.
•
An external interrupt signal on a port A external interrupt
pin — If the mask option for the port A external interrupt function
is selected, a low-to-high transition on a PA3–PA0 pin loads the
program counter with the contents of locations $07FA and $07FB.
•
A timer interrupt — A timer overflow or a real-time interrupt request
loads the program counter with the contents of locations $07F8
and $07F9.
•
A COP watchdog reset — A timeout of the mask-optional COP
watchdog resets the MCU and loads the program counter with the
contents of locations $07FE and $07FF. Software can enable
real-time interrupts so that the MCU can periodically exit wait
mode to reset the COP watchdog.
•
External reset — A logic 0 on the RESET pin resets the MCU and
loads the program counter with the contents of locations $07FE
and $07FF.
6.5 Halt Mode
If the mask option to disable the STOP instruction is selected, a STOP
instruction puts the MCU in halt mode. The halt mode is identical to the
wait mode, except that a recovery delay of 1–4064 internal clock cycles
occurs when the MCU exits the halt mode. If the mask option to disable
the STOP instruction is selected, the COP watchdog cannot be
inadvertently turned off by a STOP instruction.
Figure 6-1 shows the sequence of events in stop, wait, and halt modes.
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Low-Power Modes
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Low-Power Modes
STOP
STOP
DISABLED?
YES
HALT
WAIT
CLEAR I BIT IN CCR
SET IRQE BIT IN ISCR
TURN OFF CPU CLOCK
TIMER CLOCK ACTIVE
CLEAR I BIT IN CCR
SET IRQE BIT IN ISCR
TURN OFF CPU CLOCK
TIMER CLOCK ACTIVE
NO
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CLEAR I BIT IN CCR
SET IRQE BIT IN ISCR
CLEAR TOF, RTIF, TOIE, AND RTIE BITS IN TSCR
TURN OFF INTERNAL OSCILLATOR
EXTERNAL
RESET?
YES
YES
EXTERNAL
RESET?
NO
NO
EXTERNAL
INTERRUPT?
YES
YES
YES
EXTERNAL
INTERRUPT?
NO
EXTERNAL
RESET?
NO
YES
NO
EXTERNAL
INTERRUPT?
NO
TURN ON INTERNAL OSCILLATOR
START STABILIZATION DELAY
YES
END OF
STABILIZATION
DELAY?
NO
TIMER
INTERRUPT?
YES
NO
YES
YES
COP
RESET?
NO
TIMER
INTERRUPT?
NO
YES
COP
RESET?
NO
TURN ON CPU CLOCK
1. LOAD PC WITH RESET VECTOR
OR
2. SERVICE INTERRUPT
a. SAVE CPU REGISTERS ON STACK
b. SET I BIT IN CCR
c. LOAD PC WITH INTERRUPT VECTOR
Figure 6-1. Stop/Wait/Halt Flowchart
Technical Data
MC68HC05J1A — Rev. 3.0
Low-Power Modes
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Low-Power Modes
Data-Retention Mode
6.6 Data-Retention Mode
In data-retention mode, the MCU retains random-access memory (RAM)
contents and CPU register contents at VDD voltages as low as 2.0 Vdc.
The data-retention feature allows the MCU to remain in a low
power-consumption state during which it retains data, but the CPU
cannot execute instructions.
To put the MCU in data-retention mode:
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1. Drive the RESET pin to logic 0.
2. Lower the VDD voltage. The RESET pin must remain low
continuously during data-retention mode.
To take the MCU out of data-retention mode:
1. Return VDD to normal operating voltage.
2. Return the RESET pin to logic 1.
MC68HC05J1A — Rev. 3.0
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Low-Power Modes
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Low-Power Modes
Technical Data
MC68HC05J1A — Rev. 3.0
Low-Power Modes
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Technical Data — MC68HC05J1A
Section 7. Parallel Input/Output (I/O)
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7.1 Contents
7.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
7.3
I/O Port Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
7.4
Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
7.4.1
Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
7.4.2
Data Direction Register A. . . . . . . . . . . . . . . . . . . . . . . . . . . 63
7.4.3
Pulldown Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
7.4.4
Port A External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
7.5
Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
7.5.1
Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
7.5.2
Data Direction Register B. . . . . . . . . . . . . . . . . . . . . . . . . . . 68
7.5.3
Pulldown Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
7.2 Introduction
This section describes the two bidirectional input/output (I/O) ports.
7.3 I/O Port Function
The 14 bidirectional I/O pins form two parallel I/O ports. Each I/O pin is
programmable as an input or an output. The contents of the data
direction registers determine the data direction of each I/O pin.
All 14 I/O pins have mask-optional, software-programmable pulldown
devices.
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Parallel Input/Output (I/O)
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Parallel Input/Output (I/O)
7.4 Port A
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Port A is an 8-bit, general-purpose, bidirectional I/O port with these
features:
•
Programmable pulldown devices (mask option)
•
8-mA current sinking capability (pins PA7–PA4)
•
External interrupt capability (mask option: pins PA3–PA0)
7.4.1 Port A Data Register
The port A data register (PORTA) contains a bit for each of the port A
pins. When a port A pin is programmed to be an output, the state of its
data register bit determines the state of the output pin. When a port A pin
is programmed to be an input, reading the port A data register returns
the logic state of the pin.
Address:
$0000
Bit 7
6
5
4
3
2
1
Bit 0
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
Read:
Write:
Reset:
Unaffected by reset
Figure 7-1. Port A Data Register (PORTA)
PA7–PA0 — Port A Data Bits
These read/write bits are software-programmable. Data direction of
each bit is under the control of the corresponding bit in data direction
register A. Resets have no effect on port A data.
Technical Data
MC68HC05J1A — Rev. 3.0
Parallel Input/Output (I/O)
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Parallel Input/Output (I/O)
Port A
7.4.2 Data Direction Register A
The contents of data direction register A (DDRA) determine whether
each port A pin is an input or an output. Writing a logic 1 to a DDRA bit
enables the output buffer for the associated port A pin; a logic 0 disables
the output buffer. A reset initializes all DDRA bits to 0, configuring all port
A pins as inputs.
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Address:
$0004
Bit 7
6
5
4
3
2
1
Bit 0
DDRA7
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Figure 7-2. Data Direction Register A (DDRA)
DDRA7–DDRA0 — Port A Data Direction Bits
These read/write bits control port A data direction.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
NOTE:
Avoid glitches on port A pins by writing to the port A data register before
changing DDRA bits from logic 0 to logic 1.
MC68HC05J1A — Rev. 3.0
Technical Data
Parallel Input/Output (I/O)
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Parallel Input/Output (I/O)
7.4.3 Pulldown Register A
All port A pins have mask-optional, programmable pulldown devices that
typically sink 100 µA. Clearing the PDIA7–PDIA0 bits in pulldown
register A (PDRA) turns on the pulldown devices. See Figure 7-3.
Pulldown register A can turn on a port A pulldown device only when the
port A pin is an input. Reset clears the PDIA7–PDIA0 bits, turning on all
the port A pulldown devices.
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Address:
$0010
Bit 7
6
5
4
3
2
1
Bit 0
Write:
PDIA7
PDIA6
PDIA5
PDIA4
PDIA3
PDIA2
PDIA1
PDIA0
Reset:
0
0
0
0
0
0
0
0
Read:
= Unimplemented
Figure 7-3. Pulldown Register A (PDRA)
PDIA7–PDIA0 — Port A Pulldown Inhibit Bits
Writing logic 0s to these write-only bits turns on the port A pulldown
devices. Reading pulldown register A returns undefined data.
1 = Corresponding port A pin pulldown device turned off
0 = Corresponding port A pin pulldown device turned on
NOTE:
Avoid a floating port A input by clearing its pulldown register bit before
changing its DDRA bit from logic 1 to logic 0.
Do not use read-modify-write instructions on pulldown register A.
Technical Data
MC68HC05J1A — Rev. 3.0
Parallel Input/Output (I/O)
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Parallel Input/Output (I/O)
Port A
7.4.4 Port A External Interrupts
If the port A external interrupt mask option is selected, the PA3–PA0 pins
serve as external interrupt pins in addition to the IRQ pin.
External interrupt triggering sensitivity is a mask option. The PA3–PA0
pins can be positive edge-triggered or positive edge- and high
level-triggered.
When testing for external interrupts, the BIH and BIL instructions test the
voltage on the IRQ pin, not the state of the internal IRQ signal.
Therefore, BIH and BIL cannot test the port A external interrupt pins.
Figure 7-4 shows the port A I/O logic.
READ $0004
WRITE $0004
INTERNAL DATA BUS
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NOTE:
WRITE $0000
EXTERNAL
INTERRUPT
REQUEST
(PINS PA3–PA0)
DATA DIRECTION
REGISTER A
BIT DDRAx
PORT A DATA
REGISTER
BIT PAx
PAx
8-mA SINK
CAPABILITY
(PINS PA7–PA4)
READ $0000
WRITE $0010
PULLDOWN
REGISTER A
BIT PDIAx
100-µA
PULLDOWN
DEVICE
RESET
PULLDOWN DEVICES ENABLED
(MASK OPTION)
Figure 7-4. Port A I/O Circuit
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Parallel Input/Output (I/O)
When a port A pin is programmed as an output, reading the port bit
actually reads the value of the data latch and not the voltage on the pin
itself. When a port A pin is programmed as an input, reading the port bit
reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its DDR bit. Table 7-1 summarizes the
operations of the port A pins.
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Table 7-1. Port A Pin Functions
Pulldown
Mask
Option
Control Bits
Accesses
to PDRA
I/O Pin
Mode
PDIAx
DDRAx
Read
No
X(1)
0
Input,
hi-z
U (2)
No
X
1
Output
Yes
0
0
Yes
0
Yes
Yes
Write
Accesses
to DDRA
Accesses
to PORTA
Read/Write
Read
Write
PDIA7–PDIA0 DDRA7–DDRA0
Pin
PA7–PA0
U
PDIA7–PDIA0 DDRA7–DDRA0
PA7–PA0
PA7–PA0
Input,
pulldown on
U
PDIA7–PDIA0 DDRA7–DDRA0
Pin
PA7–PA0
1
Output,
pulldown on
U
PDIA7–PDIA0 DDRA7–DDRA0 PA7–PA00
PA7–PA0
1
0
Input,
hi-z
U
PDIA7–PDIA0 DDRA7–DDRA0
Pin
PA7–PA0
1
1
Output
U
PDIA7–PDIA0 DDRA7–DDRA0
PA7–PA0
PA7–PA0
1. X = Don’t care
2. U = Undefined
Technical Data
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Parallel Input/Output (I/O)
Port B
7.5 Port B
Port B is a 6-bit, general-purpose, bidirectional I/O port with
programmable pulldown devices.
7.5.1 Port B Data Register
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The port B data register (PORTB) contains a bit for each of the port B
pins. When a port B pin is programmed to be an output, the state of its
data register bit determines the state of the output pin. When a port B pin
is programmed to be an input, reading the port B data register returns
the logic state of the pin.
Address:
Read:
$0001
Bit 7
6
0
0
5
4
3
2
1
Bit 0
PB5
PB4
PB3
PB2
PB1
PB0
Write:
Reset:
Unaffected by reset
= Unimplemented
Figure 7-5. Port B Data Register (PORTB)
PB5–PB0 — Port B Data Bits
These read/write bits are software programmable. Data direction of
each bit is under the control of the corresponding bit in the port B data
direction register.
Bits 7 and 6 — Not used
Bits 7 and 6 always read as logic 0s. Writes to these bits have no
effect.
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7.5.2 Data Direction Register B
The contents of data direction register B (DDRB) determine whether
each port B pin is an input or an output. Writing a logic 1 to a DDRB bit
enables the output buffer for the associated port B pin; a logic 0 disables
the output buffer. A reset initializes all DDRB bits to logic 0, configuring
all port B pins as inputs.
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Address:
Read:
$0005
Bit 7
6
0
0
5
4
3
2
1
Bit 0
DDRB5
DDRB4
DDRB3
DDRB2
DDRB1
DDRB0
0
0
0
0
0
0
Write:
Reset:
0
0
= Unimplemented
Figure 7-6. Data Direction Register B (DDRB)
DDRB5–DDRB0 — Data Direction Bits
These read/write bits control port B data direction.
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
Bit 7 and 6 — Not used
Bits 7 and 6 always read as logic 0s. Writes to these bits have no
effect.
NOTE:
Avoid glitches on port B pins by writing to the port B data register before
changing DDRB bits from logic 0 to logic 1.
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Port B
7.5.3 Pulldown Register B
All port B pins have mask-optional, programmable pulldown devices that
typically sink 100 µA. Clearing any of the PDIB5–PDIB0 bits in pulldown
register B (PDRB) turns on the pulldown devices. See Figure 7-7.
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Pulldown register B can turn on a port B pulldown device only when the
port B pin is an input. Reset clears bits PDIB5–PDIB0, turning on the port
B pulldown devices.
Address:
$0011
Bit 7
6
5
4
3
2
1
Bit 0
Write:
PDIB5
PDIB4
PDIB3
PDIB2
PDIB1
PDIB0
Reset:
0
0
0
0
0
0
Read:
= Unimplemented
Figure 7-7. Pulldown Register B (PDRB)
PDIB5–PDIB0 — Pulldown Inhibit Bits
Writing logic 0s to these write-only bits turns on the port B pulldown
devices. Reading pulldown register B returns undefined data.
1 = Corresponding port B pin pulldown device turned off
0 = Corresponding port B pin pulldown device turned on
Bits 7 and 6 — Not used
NOTE:
Avoid a floating port B input by clearing its pulldown register bit before
changing its DDRB bit from logic 1 to logic 0.
Do not use read-modify-write instructions on pulldown register B.
Figure 7-8 shows the port B I/O logic.
Reading a port B output actually reads the value of the data latch and
not the voltage on the pin itself. When a port B pin is programmed as an
input, reading the port bit reads the voltage level on the pin. The data
latch can always be written, regardless of the state of its DDR bit.
Table 7-2 summarizes the operation of the port B pins.
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READ $0005
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INTERNAL DATA BUS
WRITE $0005
WRITE $0001
DATA DIRECTION
REGISTER B
BIT DDRBx
PORT B DATA
REGISTER
BIT PBx
PBx
READ $0001
WRITE $0011
PULLDOWN
REGISTER B
BIT PDIBx
100-µA
PULLDOWN
DEVICE
RESET
PULLDOWN DEVICES ENABLED
(MASK OPTION)
Figure 7-8. Port B I/O Circuit
Table 7-2. Port B Pin Functions
Pulldown
Mask
Option
Control Bits
Accesses
to PDRB
I/O Pin
Mode
Read
Write
Accesses
to DDRB
Read/Write
Accesses
to PORTB
PDIBx
DDRBx
No
X(1)
0
Input,
hi-z
U (2)
No
X
1
Output
U
PDIB7–PDIB0 DDRB7–DDRB0 PB7–PB0 PB7–PB0
Yes
0
0
Input,
pulldown on
U
PDIB7–PDIB0 DDRB7–DDRB0
Yes
0
1
Output,
pulldown on
U
PDIB7–PDIB0 DDRB7–DDRB0 PB7–PB0 PB7–PB0
Yes
1
0
Input,
hi-z
U
PDIB7–PDIB0 DDRB7–DDRB0
Yes
1
1
Output
U
PDIB7–PDIB0 DDRB7–DDRB0 PB7–PB0 PB7–PB0
PDIB7–PDIB0 DDRB7–DDRB0
Read
Write
Pin
PB7–PB0
Pin
Pin
PB7–PB0
PB7–PB0
1. X = Don’t care
2. U = Undefined
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Section 8. Multifunction Timer
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8.1 Contents
8.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
8.3
Timer Status and Control Register . . . . . . . . . . . . . . . . . . . . . . 73
8.4
COP Watchdog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
8.2 Introduction
This section describes the operation of the multifunction timer and the
computer operating properly (COP) watchdog. Figure 8-1 shows the
organization of the timer subsystem.
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INTERNAL
DATA BUS
OVERFLOW
INTERNAL CLOCK
÷4
TIMER COUNTER REGISTER ($0009)
(XTAL ÷ 2)
RTIFR
TOFR
RTIE
TOIE
RTIF
INTERRUPT
REQUEST
TOF
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INTERNAL DATA BUS
LEAST SIGNIFICANT 8 BITS
OF 15-STAGE RIPPLE COUNTER
RT0
RT1
TIMER STATUS/CONTROL REGISTER ($0008)
RTI RATE SELECT
POWER-ON
RESET (POR)
÷2
÷2
÷2
÷2
÷2
÷2
÷2
MOST SIGNIFICANT 7 BITS OF 15-STAGE RIPPLE COUNTER
÷2
CLEAR COP WATCHDOG
÷2
÷2
S
Q
COP WATCHDOG RESET
R
Figure 8-1. Multifunction Timer Block Diagram
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Timer Status and Control Register
8.3 Timer Status and Control Register
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The read/write timer status and control register (TSCR) contains these
bits:
•
Timer interrupt enable bits
•
Timer interrupt flags
•
Timer interrupt flag reset bits
•
Timer interrupt rate select bits
Address:
Read:
$0008
Bit 7
6
TOF
RTIF
5
4
TOIE
RTIE
Write:
Reset:
0
0
0
0
3
2
0
0
TOFR
RTIFR
0
0
1
Bit 0
RT1
RT0
1
1
= Unimplemented
Figure 8-2. Timer Status and Control Register (TSCR)
TOF — Timer Overflow Flag
This read-only flag becomes set when the first eight stages of the
counter roll over from $FF to $00. TOF generates a timer overflow
interrupt request if TOIE is also set. Clear TOF by writing a logic 1 to
the TOFR bit. Writing to TOF has no effect. Reset clears TOF.
RTIF — Real-Time Interrupt Flag
This read-only flag becomes set when the selected real-time interrupt
(RTI) output becomes active. RTIF generates a real-time interrupt
request if RTIE is also set. Clear RTIF by writing a logic 1 to the RTIFR
bit. Writing to RTIF has no effect. Reset clears RTIF.
TOIE — Timer Overflow Interrupt Enable Bit
This read/write bit enables timer overflow interrupts.
1 = Timer overflow interrupts enabled
0 = Timer overflow interrupts disabled
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RTIE — Real-Time Interrupt Enable Bit
This read/write bit enables real-time interrupts.
1 = Real-time interrupts enabled
0 = Real-time interrupts disabled
TOFR — Timer Overflow Flag Reset Bit
Writing a logic 1 to this write-only bit clears the TOF bit. TOFR always
reads as logic 0. Reset clears TOFR.
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RTIFR — Real-Time Interrupt Flag Reset Bit
Writing a logic 1 to this write-only bit clears the RTIF bit. RTIFR
always reads as logic 0. Reset clears RTIFR.
RT1 and RT0 — Real-Time Interrupt Select Bits 1 and 0
These read/write bits select one of four RTI rates, as shown in
Table 8-1. Because the selected RTI output drives the COP
watchdog, changing the real-time interrupt rate also changes the
counting rate of the COP watchdog. Reset sets RT1 and RT0.
NOTE:
Changing RT1 and RT0 when a COP timeout is imminent or uncertain
may cause a real-time interrupt request to be missed or an additional
real-time interrupt request to be generated. Clear the COP timer just
before changing RT1 and RT0.
Table 8-1. Real-Time Interrupt Rate Selection
RT1:RT0
Number
of Cycles
to RTI
RTI
Period(1)
Number
of Cycles
to COP Reset
COP Timeout
Period(1)
00
214 = 16,384
8.2 ms
217 = 131,072
65.5 ms
01
215 = 32,768
16.4 ms
218 = 262,144
131.1 ms
10
216 = 65,536
32.8 ms
219 = 524,288
262.1 ms
11
217 = 131,072
65.5 ms
220 = 1,048,576
524.3 ms
1. At 2-MHz bus, 4-MHz XTAL, 0.5 µs per cycle
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Multifunction Timer
Timer Status and Control Register
A 15-stage ripple counter is the core of the timer. The value of the first
eight stages is readable at any time from the read-only timer counter
register (TCNTR).
Address:
Read:
$0009
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
Write:
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Reset:
= Unimplemented
Figure 8-3. Timer Counter Register (TCNTR)
Power-on clears the entire counter chain and begins clocking the
counter. After 4064 cycles, the power-on reset circuit is released,
clearing the counter again and allowing the MCU to come out of reset.
A timer overflow function at the eighth counter stage allows a timer
interrupt every 1024 internal clock cycles.
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8.4 COP Watchdog
Four counter stages at the end of the timer make up the mask-optional
computer operating properly (COP) watchdog. (See Figure 8-4.)
The COP watchdog is a software error detection system that
automatically times out and resets the MCU if not cleared periodically by
a program sequence. Writing a logic 0 to bit 0 of the COP register clears
the COP watchdog and prevents a COP reset.
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Address:
$07F0
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
COPC
U
U
U
U
U
U
U
0
= Unimplemented
Figure 8-4. COP Register (COPR)
COPC — COP Clear Bit
This write-only bit resets the COP watchdog. Reading address $07F0
returns the ROM data at that address.
NOTE:
The STOP instruction turns off the COP watchdog. In applications that
depend on the COP watchdog, the STOP instruction can be disabled by
a mask option.
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Technical Data — MC68HC05J1A
Section 9. Instruction Set
9.1 Contents
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9.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
9.3
Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
9.3.1
Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
9.3.2
Immediate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
9.3.3
Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
9.3.4
Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
9.3.5
Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
9.3.6
Indexed, 8-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
9.3.7
Indexed, 16-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
9.3.8
Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
9.4
Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
9.4.1
Register/Memory Instructions. . . . . . . . . . . . . . . . . . . . . . . .82
9.4.2
Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . . 83
9.4.3
Jump/Branch Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . 84
9.4.4
Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . . .86
9.4.5
Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
9.5
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
9.6
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
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Instruction Set
9.2 Introduction
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The microcontroller unit (MCU) instruction set has 62 instructions and
uses eight addressing modes. The instructions include all those of the
M146805 CMOS Family plus one more: the unsigned multiply (MUL)
instruction. The MUL instruction allows unsigned multiplication of the
contents of the accumulator (A) and the index register (X). The
high-order product is stored in the index register, and the low-order
product is stored in the accumulator.
9.3 Addressing Modes
The central processor unit (CPU) uses eight addressing modes for
flexibility in accessing data. The addressing modes provide eight
different ways for the CPU to find the data required to execute an
instruction.
The eight addressing modes are:
•
Inherent
•
Immediate
•
Direct
•
Extended
•
Indexed, no offset
•
Indexed, 8-bit offset
•
Indexed, 16-bit offset
•
Relative
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Instruction Set
Addressing Modes
9.3.1 Inherent
Inherent instructions are those that have no operand, such as return
from interrupt (RTI) and stop (STOP). Some of the inherent instructions
act on data in the CPU registers, such as set carry flag (SEC) and
increment accumulator (INCA). Inherent instructions require no operand
address and are one byte long.
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9.3.2 Immediate
Immediate instructions are those that contain a value to be used in an
operation with the value in the accumulator or index register. Immediate
instructions require no operand address and are two bytes long. The
opcode is the first byte, and the immediate data value is the second byte.
9.3.3 Direct
Direct instructions can access any of the first 256 memory locations with
two bytes. The first byte is the opcode, and the second is the low byte of
the operand address. In direct addressing, the CPU automatically uses
$00 as the high byte of the operand address.
9.3.4 Extended
Extended instructions use three bytes and can access any address in
memory. The first byte is the opcode; the second and third bytes are the
high and low bytes of the operand address.
When using the Motorola assembler, the programmer does not need to
specify whether an instruction is direct or extended. The assembler
automatically selects the shortest form of the instruction.
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9.3.5 Indexed, No Offset
Indexed instructions with no offset are 1-byte instructions that can
access data with variable addresses within the first 256 memory
locations. The index register contains the low byte of the effective
address of the operand. The CPU automatically uses $00 as the high
byte, so these instructions can address locations $0000–$00FF.
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Indexed, no offset instructions are often used to move a pointer through
a table or to hold the address of a frequently used RAM or I/O location.
9.3.6 Indexed, 8-Bit Offset
Indexed, 8-bit offset instructions are 2-byte instructions that can access
data with variable addresses within the first 511 memory locations. The
CPU adds the unsigned byte in the index register to the unsigned byte
following the opcode. The sum is the effective address of the operand.
These instructions can access locations $0000–$01FE.
Indexed 8-bit offset instructions are useful for selecting the kth element
in an n-element table. The table can begin anywhere within the first 256
memory locations and could extend as far as location 510 ($01FE). The
k value is typically in the index register, and the address of the beginning
of the table is in the byte following the opcode.
9.3.7 Indexed, 16-Bit Offset
Indexed, 16-bit offset instructions are 3-byte instructions that can access
data with variable addresses at any location in memory. The CPU adds
the unsigned byte in the index register to the two unsigned bytes
following the opcode. The sum is the effective address of the operand.
The first byte after the opcode is the high byte of the 16-bit offset; the
second byte is the low byte of the offset.
Indexed, 16-bit offset instructions are useful for selecting the kth element
in an n-element table anywhere in memory.
As with direct and extended addressing, the Motorola assembler
determines the shortest form of indexed addressing.
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Instruction Set
Instruction Types
9.3.8 Relative
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Relative addressing is only for branch instructions. If the branch
condition is true, the CPU finds the effective branch destination by
adding the signed byte following the opcode to the contents of the
program counter. If the branch condition is not true, the CPU goes to the
next instruction. The offset is a signed, two’s complement byte that gives
a branching range of –128 to +127 bytes from the address of the next
location after the branch instruction.
When using the Motorola assembler, the programmer does not need to
calculate the offset, because the assembler determines the proper offset
and verifies that it is within the span of the branch.
9.4 Instruction Types
The MCU instructions fall into five categories:
•
Register/memory instructions
•
Read-modify-write instructions
•
Jump/branch instructions
•
Bit manipulation instructions
•
Control instructions
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Instruction Set
9.4.1 Register/Memory Instructions
These instructions operate on CPU registers and memory locations.
Most of them use two operands. One operand is in either the
accumulator or the index register. The CPU finds the other operand in
memory.
Table 9-1. Register/Memory Instructions
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Instruction
Mnemonic
Add memory byte and carry bit to accumulator
ADC
Add memory byte to accumulator
ADD
AND memory byte with accumulator
AND
Bit test accumulator
BIT
Compare accumulator
CMP
Compare index register with memory byte
CPX
Exclusive OR accumulator with memory byte
EOR
Load accumulator with memory byte
LDA
Load Index register with memory byte
LDX
Multiply
MUL
OR accumulator with memory byte
ORA
Subtract memory byte and carry bit from
accumulator
SBC
Store accumulator in memory
STA
Store index register in memory
STX
Subtract memory byte from accumulator
SUB
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Instruction Set
Instruction Types
9.4.2 Read-Modify-Write Instructions
These instructions read a memory location or a register, modify its
contents, and write the modified value back to the memory location or to
the register.
NOTE:
Do not use read-modify-write operations on write-only registers.
Table 9-2. Read-Modify-Write Instructions
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Instruction
Mnemonic
Arithmetic shift left (same as LSL)
ASL
Arithmetic shift right
ASR
Bit clear
BCLR(1)
Bit set
BSET(1)
Clear register
CLR
Complement (one’s complement)
COM
Decrement
DEC
Increment
INC
Logical shift left (same as ASL)
LSL
Logical shift right
LSR
Negate (two’s complement)
NEG
Rotate left through carry bit
ROL
Rotate right through carry bit
ROR
Test for negative or zero
TST(2)
1. Unlike other read-modify-write instructions, BCLR and BSET use
only direct addressing.
2. TST is an exception to the read-modify-write sequence because it
does not write a replacement value.
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9.4.3 Jump/Branch Instructions
Jump instructions allow the CPU to interrupt the normal sequence of the
program counter. The unconditional jump instruction (JMP) and the
jump-to-subroutine instruction (JSR) have no register operand. Branch
instructions allow the CPU to interrupt the normal sequence of the
program counter when a test condition is met. If the test condition is not
met, the branch is not performed.
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The BRCLR and BRSET instructions cause a branch based on the state
of any readable bit in the first 256 memory locations. These 3-byte
instructions use a combination of direct addressing and relative
addressing. The direct address of the byte to be tested is in the byte
following the opcode. The third byte is the signed offset byte. The CPU
finds the effective branch destination by adding the third byte to the
program counter if the specified bit tests true. The bit to be tested and its
condition (set or clear) is part of the opcode. The span of branching is
from –128 to +127 from the address of the next location after the branch
instruction. The CPU also transfers the tested bit to the carry/borrow bit
of the condition code register.
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Instruction Set
Instruction Types
Table 9-3. Jump and Branch Instructions
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Instruction
Mnemonic
Branch if carry bit clear
BCC
Branch if carry bit set
BCS
Branch if equal
BEQ
Branch if half-carry bit clear
BHCC
Branch if half-carry bit set
BHCS
Branch if higher
BHI
Branch if higher or same
BHS
Branch if IRQ pin high
BIH
Branch if IRQ pin low
BIL
Branch if lower
BLO
Branch if lower or same
BLS
Branch if interrupt mask clear
BMC
Branch if minus
BMI
Branch if interrupt mask set
BMS
Branch if not equal
BNE
Branch if plus
BPL
Branch always
BRA
Branch if bit clear
Branch never
Branch if bit set
BRCLR
BRN
BRSET
Branch to subroutine
BSR
Unconditional jump
JMP
Jump to subroutine
JSR
MC68HC05J1A — Rev. 3.0
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Instruction Set
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Instruction Set
9.4.4 Bit Manipulation Instructions
The CPU can set or clear any writable bit in the first 256 bytes of
memory, which includes I/O registers and on-chip RAM locations. The
CPU can also test and branch based on the state of any bit in any of the
first 256 memory locations.
Table 9-4. Bit Manipulation Instructions
Instruction
Freescale Semiconductor, Inc...
Bit clear
Mnemonic
BCLR
Branch if bit clear
BRCLR
Branch if bit set
BRSET
Bit set
Technical Data
BSET
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Instruction Set
Instruction Types
9.4.5 Control Instructions
These instructions act on CPU registers and control CPU operation
during program execution.
Table 9-5. Control Instructions
Freescale Semiconductor, Inc...
Instruction
Mnemonic
Clear carry bit
CLC
Clear interrupt mask
CLI
No operation
NOP
Reset stack pointer
RSP
Return from interrupt
RTI
Return from subroutine
RTS
Set carry bit
SEC
Set interrupt mask
SEI
Stop oscillator and enable IRQ pin
STOP
Software interrupt
SWI
Transfer accumulator to index register
TAX
Transfer index register to accumulator
TXA
Stop CPU clock and enable interrupts
WAIT
MC68HC05J1A — Rev. 3.0
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Instruction Set
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Instruction Set
9.5 Instruction Set Summary
#opr
opr
opr
opr,X
opr,X
,X
ADD
ADD
ADD
ADD
ADD
ADD
#opr
opr
opr
opr,X
opr,X
,X
AND #opr
AND opr
AND opr
AND opr,X
AND opr,X
AND ,X
ASL opr
ASLA
ASLX
ASL opr,X
ASL ,X
— IMM
DIR
EXT
IX2
IX1
IX
ii
A9
2
B9 dd 3
C9 hh ll 4
D9 ee ff 5
E9 ff
4
F9
3
— IMM
DIR
EXT
IX2
IX1
IX
AB ii
2
BB dd 3
CB hh ll 4
DB ee ff 5
EB ff
4
FB
3
— — —
IMM
DIR
EXT
IX2
IX1
IX
ii
A4
2
B4 dd 3
C4 hh ll 4
D4 ee ff 5
E4 ff
4
F4
3
38
48
58
68
78
dd
— — DIR
INH
INH
IX1
IX
DIR
INH
INH
IX1
IX
37
47
57
67
77
dd
REL
24
rr
3
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — —
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
11
13
15
17
19
1B
1D
1F
dd
dd
dd
dd
dd
dd
dd
dd
5
5
5
5
5
5
5
5
Effect
on CCR
Description
H I N Z C
A ← (A) + (M) + (C)
Add with Carry
A ← (A) + (M)
Add without Carry
A ← (A) ∧ (M)
Logical AND
Arithmetic Shift Left (Same as LSL)
C
0
b7
ASR opr
ASRA
ASRX
ASR opr,X
ASR ,X
Arithmetic Shift Right
BCC rel
Branch if Carry Bit Clear
b0
C
b7
— — b0
PC ← (PC) + 2 + rel ? C = 0
Mn ← 0
— — — — —
ff
ff
Cycles
Opcode
ADC
ADC
ADC
ADC
ADC
ADC
Operation
Address
Mode
Freescale Semiconductor, Inc...
Source
Form
Operand
Table 9-6. Instruction Set Summary (Sheet 1 of 6)
5
3
3
6
5
5
3
3
6
5
BCLR n opr
Clear Bit n
BCS rel
Branch if Carry Bit Set (Same as BLO)
PC ← (PC) + 2 + rel ? C = 1
— — — — —
REL
25
rr
3
BEQ rel
Branch if Equal
PC ← (PC) + 2 + rel ? Z = 1
— — — — —
REL
27
rr
3
BHCC rel
Branch if Half-Carry Bit Clear
PC ← (PC) + 2 + rel ? H = 0
— — — — —
REL
28
rr
3
BHCS rel
Branch if Half-Carry Bit Set
PC ← (PC) + 2 + rel ? H = 1
— — — — —
REL
29
rr
3
BHI rel
Branch if Higher
PC ← (PC) + 2 + rel ? C ∨ Z = 0 — — — — —
REL
22
rr
3
BHS rel
Branch if Higher or Same
REL
24
rr
3
PC ← (PC) + 2 + rel ? C = 0
Technical Data
— — — — —
MC68HC05J1A — Rev. 3.0
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Instruction Set
Instruction Set Summary
Address
Mode
Opcode
Operand
Cycles
Table 9-6. Instruction Set Summary (Sheet 2 of 6)
BIH rel
Branch if IRQ Pin High
PC ← (PC) + 2 + rel ? IRQ = 1
— — — — —
REL
2F
rr
3
BIL rel
Branch if IRQ Pin Low
PC ← (PC) + 2 + rel ? IRQ = 0
— — — — —
REL
2E
rr
3
(A) ∧ (M)
— — —
IMM
DIR
EXT
IX2
IX1
IX
ii
A5
2
B5 dd 3
C5 hh ll 4
D5 ee ff 5
E5 ff
4
F5
3
PC ← (PC) + 2 + rel ? C = 1
— — — — —
REL
25
rr
3
PC ← (PC) + 2 + rel ? C ∨ Z = 1 — — — — —
REL
23
rr
3
Freescale Semiconductor, Inc...
Source
Form
Operation
Description
Effect
on CCR
H I N Z C
BIT #opr
BIT opr
BIT opr
BIT opr,X
BIT opr,X
BIT ,X
Bit Test Accumulator with Memory Byte
BLO rel
Branch if Lower (Same as BCS)
BLS rel
Branch if Lower or Same
BMC rel
Branch if Interrupt Mask Clear
PC ← (PC) + 2 + rel ? I = 0
— — — — —
REL
2C
rr
3
BMI rel
Branch if Minus
PC ← (PC) + 2 + rel ? N = 1
— — — — —
REL
2B
rr
3
BMS rel
Branch if Interrupt Mask Set
PC ← (PC) + 2 + rel ? I = 1
— — — — —
REL
2D
rr
3
BNE rel
Branch if Not Equal
PC ← (PC) + 2 + rel ? Z = 0
— — — — —
REL
26
rr
3
BPL rel
Branch if Plus
PC ← (PC) + 2 + rel ? N = 0
— — — — —
REL
2A
rr
3
BRA rel
Branch Always
PC ← (PC) + 2 + rel ? 1 = 1
— — — — —
REL
20
rr
3
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
01
03
05
07
09
0B
0D
0F
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
— — — — —
BRCLR n opr rel Branch if Bit n Clear
BRN rel
Branch Never
BRSET n opr rel Branch if Bit n Set
BSET n opr
Set Bit n
PC ← (PC) + 2 + rel ? Mn = 0
PC ← (PC) + 2 + rel ? 1 = 0
21
rr
3
PC ← (PC) + 2 + rel ? Mn = 1
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
REL
00
02
04
06
08
0A
0C
0E
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
Mn ← 1
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — —
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
10
12
14
16
18
1A
1C
1E
dd
dd
dd
dd
dd
dd
dd
dd
5
5
5
5
5
5
5
5
PC ← (PC) + 2; push (PCL)
SP ← (SP) – 1; push (PCH)
SP ← (SP) – 1
PC ← (PC) + rel
— — — — —
REL
AD
rr
6
BSR rel
Branch to Subroutine
CLC
Clear Carry Bit
C←0
— — — — 0
INH
98
2
CLI
Clear Interrupt Mask
I←0
— 0 — — —
INH
9A
2
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Instruction Set
CMP #opr
CMP opr
CMP opr
CMP opr,X
CMP opr,X
CMP ,X
COM opr
COMA
COMX
COM opr,X
COM ,X
CPX
CPX
CPX
CPX
CPX
CPX
#opr
opr
opr
opr,X
opr,X
,X
DEC opr
DECA
DECX
DEC opr,X
DEC ,X
EOR
EOR
EOR
EOR
EOR
EOR
#opr
opr
opr
opr,X
opr,X
,X
INC opr
INCA
INCX
INC opr,X
INC ,X
JMP opr
JMP opr
JMP opr,X
JMP opr,X
JMP ,X
DIR
INH
INH
IX1
IX
3F
4F
5F
6F
7F
dd
— — IMM
DIR
EXT
IX2
IX1
IX
ii
A1
2
B1 dd 3
C1 hh ll 4
D1 ee ff 5
E1 ff
4
F1
3
— — 1
DIR
INH
INH
IX1
IX
33
43
53
63
73
— — IMM
DIR
EXT
IX2
IX1
IX
ii
A3
2
B3 dd 3
C3 hh ll 4
D3 ee ff 5
E3 ff
4
F3
3
— — —
DIR
INH
INH
IX1
IX
3A
4A
5A
6A
7A
— — —
IMM
DIR
EXT
IX2
IX1
IX
ii
A8
2
B8 dd 3
C8 hh ll 4
D8 ee ff 5
E8 ff
4
F8
3
— — —
DIR
INH
INH
IX1
IX
3C
4C
5C
6C
7C
DIR
EXT
IX2
IX1
IX
BC dd 2
CC hh ll 3
DC ee ff 4
EC ff
3
FC
2
Effect
on CCR
H I N Z C
M ← $00
A ← $00
X ← $00
M ← $00
M ← $00
Clear Byte
Compare Accumulator with Memory Byte
Complement Byte (One’s Complement)
Compare Index Register with Memory Byte
EXCLUSIVE OR Accumulator with Memory
Byte
Unconditional Jump
M ← (M) = $FF – (M)
A ← (A) = $FF – (A)
X ← (X) = $FF – (X)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
(X) – (M)
M ← (M) – 1
A ← (A) – 1
X ← (X) – 1
M ← (M) – 1
M ← (M) – 1
Decrement Byte
Increment Byte
(A) – (M)
A ← (A) ⊕ (M)
M ← (M) + 1
A ← (A) + 1
X ← (X) + 1
M ← (M) + 1
M ← (M) + 1
PC ← Jump Address
Technical Data
— — 0 1 —
— — — — —
ff
dd
ff
dd
ff
dd
ff
Cycles
Description
Operand
Freescale Semiconductor, Inc...
CLR opr
CLRA
CLRX
CLR opr,X
CLR ,X
Operation
Opcode
Source
Form
Address
Mode
Table 9-6. Instruction Set Summary (Sheet 3 of 6)
5
3
3
6
5
5
3
3
6
5
5
3
3
6
5
5
3
3
6
5
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Instruction Set
Instruction Set Summary
LDA #opr
LDA opr
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
LSL opr
LSLA
LSLX
LSL opr,X
LSL ,X
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Effective Address
Jump to Subroutine
X ← (M)
Load Index Register with Memory Byte
Logical Shift Left (Same as ASL)
C
0
b7
MUL
Unsigned Multiply
— — —
IMM
DIR
EXT
IX2
IX1
IX
ii
A6
2
B6 dd 3
C6 hh ll 4
D6 ee ff 5
E6 ff
4
F6
3
— — —
IMM
DIR
EXT
IX2
IX1
IX
AE ii
2
BE dd 3
CE hh ll 4
DE ee ff 5
EE ff
4
FE
3
38
48
58
68
78
dd
— — DIR
INH
INH
IX1
IX
DIR
INH
INH
IX1
IX
34
44
54
64
74
dd
C
b7
0 — — — 0
INH
42
— — DIR
INH
INH
IX1
IX
30
40
50
60
70
X : A ← (X) × (A)
Negate Byte (Two’s Complement)
NOP
No Operation
— — — — —
INH
9D
— — —
IMM
DIR
EXT
IX2
IX1
IX
AA ii
2
BA dd 3
CA hh ll 4
DA ee ff 5
EA ff
4
FA
3
M ← –(M) = $00 – (M)
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
A ← (A) ∨ (M)
Logical OR Accumulator with Memory
— — DIR
INH
INH
IX1
IX
39
49
59
69
79
Rotate Byte Left through Carry Bit
C
b7
— — 0 b0
b0
MC68HC05J1A — Rev. 3.0
ff
ff
Cycles
BD dd 5
CD hh ll 6
DD ee ff 7
ED ff
6
FD
5
b0
0
NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X
ROL opr
ROLA
ROLX
ROL opr,X
ROL ,X
A ← (M)
Load Accumulator with Memory Byte
Logical Shift Right
#opr
opr
opr
opr,X
opr,X
,X
— — — — —
DIR
EXT
IX2
IX1
IX
H I N Z C
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
ORA
ORA
ORA
ORA
ORA
ORA
Description
Opcode
Freescale Semiconductor, Inc...
JSR opr
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
Operation
Effect
on CCR
Address
Mode
Source
Form
Operand
Table 9-6. Instruction Set Summary (Sheet 4 of 6)
5
3
3
6
5
5
3
3
6
5
1
1
dd
ff
5
3
3
6
5
2
dd
ff
5
3
3
6
5
Technical Data
Instruction Set
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Instruction Set
Opcode
Operand
DIR
INH
INH
IX1
IX
36
46
56
66
76
dd
— — — — —
INH
9C
2
Return from Interrupt
SP ← (SP) + 1; Pull (CCR)
SP ← (SP) + 1; Pull (A)
SP ← (SP) + 1; Pull (X)
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
INH
80
9
Return from Subroutine
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
— — — — —
INH
81
6
A ← (A) – (M) – (C)
— — IMM
DIR
EXT
IX2
IX1
IX
ii
A2
2
B2 dd 3
C2 hh ll 4
D2 ee ff 5
E2 ff
4
F2
3
Freescale Semiconductor, Inc...
Source
Form
Operation
Effect
on CCR
Description
H I N Z C
ROR opr
RORA
RORX
ROR opr,X
ROR ,X
Rotate Byte Right through Carry Bit
RSP
Reset Stack Pointer
SP ← $00FF
RTI
RTS
C
b7
— — b0
ff
Cycles
Address
Mode
Table 9-6. Instruction Set Summary (Sheet 5 of 6)
5
3
3
6
5
SBC #opr
SBC opr
SBC opr
SBC opr,X
SBC opr,X
SBC ,X
Subtract Memory Byte and Carry Bit from
Accumulator
SEC
Set Carry Bit
C←1
— — — — 1
INH
99
2
SEI
Set Interrupt Mask
I←1
— 1 — — —
INH
9B
2
— — —
DIR
EXT
IX2
IX1
IX
B7 dd 4
C7 hh ll 5
D7 ee ff 6
E7 ff
5
F7
4
— 0 — — —
INH
8E
— — —
DIR
EXT
IX2
IX1
IX
BF dd 4
CF hh ll 5
DF ee ff 6
EF ff
5
FF
4
— — IMM
DIR
EXT
IX2
IX1
IX
ii
A0
2
B0 dd 3
C0 hh ll 4
D0 ee ff 5
E0 ff
4
F0
3
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
— 1 — — —
SP ← (SP) – 1; Push (CCR)
SP ← (SP) – 1; I ← 1
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
INH
83
1
0
INH
97
2
STA opr
STA opr
STA opr,X
STA opr,X
STA ,X
Store Accumulator in Memory
STOP
Stop Oscillator and Enable IRQ Pin
STX opr
STX opr
STX opr,X
STX opr,X
STX ,X
SUB
SUB
SUB
SUB
SUB
SUB
#opr
opr
opr
opr,X
opr,X
,X
Store Index Register In Memory
Subtract Memory Byte from Accumulator
SWI
Software Interrupt
TAX
Transfer Accumulator to Index Register
M ← (A)
M ← (X)
A ← (A) – (M)
X ← (A)
Technical Data
— — — — —
2
MC68HC05J1A — Rev. 3.0
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Instruction Set
Opcode Map
Freescale Semiconductor, Inc...
Description
3D
4D
5D
6D
7D
dd
Test Memory Byte for Negative or Zero
TXA
Transfer Index Register to Accumulator
— — — — —
INH
9F
2
WAIT
Stop CPU Clock and Enable Interrupts
— 0 — — —
INH
8F
2
Accumulator
Carry/borrow flag
Condition code register
Direct address of operand
Direct address of operand and relative offset of branch instruction
Direct addressing mode
High and low bytes of offset in indexed, 16-bit offset addressing
Extended addressing mode
Offset byte in indexed, 8-bit offset addressing
Half-carry flag
High and low bytes of operand address in extended addressing
Interrupt mask
Immediate operand byte
Immediate addressing mode
Inherent addressing mode
Indexed, no offset addressing mode
Indexed, 8-bit offset addressing mode
Indexed, 16-bit offset addressing mode
Memory location
Negative flag
Any bit
— — —
(M) – $00
A ← (X)
opr
PC
PCH
PCL
REL
rel
rr
SP
X
Z
#
∧
∨
⊕
()
–( )
←
?
:
—
ff
Cycles
DIR
INH
INH
IX1
IX
Effect
on CCR
H I N Z C
TST opr
TSTA
TSTX
TST opr,X
TST ,X
A
C
CCR
dd
dd rr
DIR
ee ff
EXT
ff
H
hh ll
I
ii
IMM
INH
IX
IX1
IX2
M
N
n
Operand
Operation
Opcode
Source
Form
Address
Mode
Table 9-6. Instruction Set Summary (Sheet 6 of 6)
4
3
3
5
4
Operand (one or two bytes)
Program counter
Program counter high byte
Program counter low byte
Relative addressing mode
Relative program counter offset byte
Relative program counter offset byte
Stack pointer
Index register
Zero flag
Immediate value
Logical AND
Logical OR
Logical EXCLUSIVE OR
Contents of
Negation (two’s complement)
Loaded with
If
Concatenated with
Set or cleared
Not affected
9.6 Opcode Map
See Table 9-7.
MC68HC05J1A — Rev. 3.0
Technical Data
Instruction Set
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Technical Data
Instruction Set
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F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
MSB
LSB
1
DIR
INH = Inherent
IMM = Immediate
DIR = Direct
EXT = Extended
5
5
BSET0
BRSET0
DIR
3
DIR 2
5
5
BCLR0
BRCLR0
DIR
3
DIR 2
5
5
BSET1
BRSET1
DIR
3
DIR 2
5
5
BCLR1
BRCLR1
DIR
3
DIR 2
5
5
BSET2
BRSET2
DIR
3
DIR 2
5
5
BCLR2
BRCLR2
DIR
3
DIR 2
5
5
BSET3
BRSET3
DIR
3
DIR 2
5
5
BCLR3
BRCLR3
DIR
3
DIR 2
5
5
BSET4
BRSET4
DIR
3
DIR 2
5
5
BCLR4
BRCLR4
DIR
3
DIR 2
5
5
BSET5
BRSET5
DIR
3
DIR 2
5
5
BCLR5
BRCLR5
DIR
3
DIR 2
5
5
BSET6
BRSET6
DIR
3
DIR 2
5
5
BCLR6
BRCLR6
DIR
3
DIR 2
5
5
BSET7
BRSET7
DIR
3
DIR 2
5
5
BCLR7
BRCLR7
DIR
3
DIR 2
0
DIR
Bit Manipulation
3
DIR
4
5
INH
6
IX1
Read-Modify-Write
INH
7
IX
REL = Relative
IX = Indexed, No Offset
IX1 = Indexed, 8-Bit Offset
IX2 = Indexed, 16-Bit Offset
1
1
1
1
1
1
1
2
TAX
INH
2
CLC
INH
2
SEC
INH
2
CLI
INH
2
SEI
INH
2
RSP
INH
2
NOP
INH
9
2
STOP
INH
2
2
TXA
WAIT
INH
INH 1
10
SWI
INH
9
RTI
INH
6
RTS
INH
8
INH
Control
INH
LSB of Opcode in Hexadecimal
5
6
3
3
5
3
NEG
NEG
NEGX
NEGA
NEG
BRA
IX 1
IX1 1
INH 2
INH 1
DIR 1
REL 2
3
BRN
2
REL
1
3
11
BHI
MUL
2
REL
1
INH
5
6
3
3
5
3
COM
COM
COMX
COMA
COM
BLS
IX 1
IX1 1
INH 2
INH 1
DIR 1
2
REL 2
5
6
3
3
5
3
LSR
LSR
LSRX
LSRA
LSR
BCC
IX
IX1 1
INH 2
INH 1
DIR 1
2
REL 2
3
BCS/BLO
2
REL
5
6
3
3
5
3
ROR
ROR
RORX
RORA
ROR
BNE
IX
IX1 1
INH 2
INH 1
DIR 1
2
REL 2
5
6
3
3
5
3
ASR
ASR
ASRX
ASRA
ASR
BEQ
IX
IX1 1
INH 2
INH 1
DIR 1
2
REL 2
5
6
3
3
5
3
ASL/LSL ASLA/LSLA ASLX/LSLX ASL/LSL ASL/LSL
BHCC
IX
IX1 1
INH 2
INH 1
DIR 1
2
REL 2
5
6
3
3
5
3
ROL
ROL
ROLX
ROLA
ROL
BHCS
IX
IX1 1
INH 2
INH 1
DIR 1
2
REL 2
5
6
3
3
5
3
DEC
DEC
DECX
DECA
DEC
BPL
IX
IX1 1
INH 2
INH 1
DIR 1
2
REL 2
3
BMI
2
REL
5
6
3
3
5
3
INC
INC
INCX
INCA
INC
BMC
IX
IX1 1
INH 2
INH 1
DIR 1
2
REL 2
4
5
3
3
4
3
TST
TST
TSTX
TSTA
TST
BMS
IX
IX1 1
INH 2
INH 1
DIR 1
2
REL 2
3
BIL
2
REL
1
5
6
3
3
5
3
CLR
CLR
CLRX
CLRA
CLR
BIH
IX 1
IX1 1
INH 2
INH 1
DIR 1
2
REL 2
2
2
REL
Branch
Table 9-7. Opcode Map
2
SUB
IMM
2
CMP
IMM
2
SBC
IMM
2
CPX
IMM
2
AND
IMM
2
BIT
IMM
2
LDA
IMM
2
2
2
2
2
2
2
2
2
2
2
2
2
MSB
0
LSB
0
3
SUB
DIR
3
CMP
DIR
3
SBC
DIR
3
CPX
DIR
3
AND
DIR
3
BIT
DIR
3
LDA
DIR
4
STA
DIR
3
EOR
DIR
3
ADC
DIR
3
ORA
DIR
3
ADD
DIR
2
JMP
DIR
5
JSR
DIR
3
LDX
DIR
4
STX
DIR
B
DIR
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
5
SUB
IX2
5
CMP
IX2
5
SBC
IX2
5
CPX
IX2
5
AND
IX2
5
BIT
IX2
5
LDA
IX2
6
STA
IX2
5
EOR
IX2
5
ADC
IX2
5
ORA
IX2
5
ADD
IX2
4
JMP
IX2
7
JSR
IX2
5
LDX
IX2
6
STX
IX2
D
IX2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
4
SUB
IX1 1
4
CMP
IX1 1
4
SBC
IX1 1
4
CPX
IX1 1
4
AND
IX1 1
4
BIT
IX1 1
4
LDA
IX1 1
5
STA
IX1 1
4
EOR
IX1 1
4
ADC
IX1 1
4
ORA
IX1 1
4
ADD
IX1 1
3
JMP
IX1 1
6
JSR
IX1 1
4
LDX
IX1 1
5
STX
IX1 1
E
IX1
MSB of Opcode in Hexadecimal
4
SUB
EXT
4
CMP
EXT
4
SBC
EXT
4
CPX
EXT
4
AND
EXT
4
BIT
EXT
4
LDA
EXT
5
STA
EXT
4
EOR
EXT
4
ADC
EXT
4
ORA
EXT
4
ADD
EXT
3
JMP
EXT
6
JSR
EXT
4
LDX
EXT
5
STX
EXT
C
EXT
Register/Memory
5 Number of Cycles
BRSET0 Opcode Mnemonic
3
DIR Number of Bytes/Addressing Mode
2
6
BSR
2
REL 2
2
LDX
2
IMM 2
2
EOR
IMM
2
ADC
2
IMM
2
ORA
2
IMM
2
ADD
2
IMM
2
2
2
2
2
2
2
2
A
IMM
Freescale Semiconductor, Inc...
STX
LDX
JSR
JMP
ADD
ORA
ADC
EOR
STA
LDA
BIT
AND
CPX
SBC
CMP
SUB
F
IX
3
IX
IX
4
IX
3
IX
5
IX
2
IX
3
IX
3
IX
3
IX
3
IX
4
IX
3
IX
3
IX
3
IX
3
IX
3
IX
3
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
MSB
LSB
Freescale Semiconductor, Inc.
Instruction Set
MC68HC05J1A — Rev. 3.0
Freescale Semiconductor, Inc.
Technical Data — MC68HC05J1A
Section 10. Electrical Specifications
Freescale Semiconductor, Inc...
10.1 Contents
10.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
10.3
Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
10.4
Operating Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . 97
10.5
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
10.6
Power Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
10.7
5.0-Volt DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . .99
10.8
3.3-Volt DC Electrical Characteristics. . . . . . . . . . . . . . . . . . .100
10.9
5.0-Volt Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
10.10 3.3-Volt Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
10.2 Introduction
This section contains electrical and timing specifications.
MC68HC05J1A — Rev. 3.0
Technical Data
Electrical Specifications
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Electrical Specifications
10.3 Maximum Ratings
Maximum ratings are the extreme limits to which the MCU can be
exposed without permanently damaging it.
Freescale Semiconductor, Inc...
The MCU contains circuitry to protect the inputs against damage from
high static voltages; however, do not apply voltages higher than those
shown in the table here. Keep VIn and VOut within the range
VSS ≤ (VIn or VOut) ≤ VDD. Connect unused inputs to the appropriate
voltage level, either VSS or VDD.
Rating(1)
Symbol
Value
Unit
Supply voltage
VDD
–0.3 to +7.0
V
Input voltage
VIn
VSS –0.3
to VDD +0.3
V
I
25
mA
TSTG
–65 to +150
°C
Current drain per pin excluding
VDD and VSS
Storage temperature range
1. Voltages referenced to VSS
NOTE:
This device is not guaranteed to operate properly at the maximum
ratings. Refer to 10.7 5.0-Volt DC Electrical Characteristics and
10.8 3.3-Volt DC Electrical Characteristics for guaranteed operating
conditions.
Technical Data
MC68HC05J1A — Rev. 3.0
Electrical Specifications
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Electrical Specifications
Operating Temperature Range
10.4 Operating Temperature Range
Rating
Symbol
Freescale Semiconductor, Inc...
Operating temperature range
MC68HC05J1AP(1), DW (2)
MC68HC05J1AC(3)P, CDW
MC68HC05J1AV(4)P
MC68HC05J1AVDW
Value
Unit
0 to +70
–40 to +85
–40 to +105
–40 to +105
TA
°C
1. P = Plastic dual in-line package (PDIP)
2. DW = Small outline integrated circuit (SOIC)
3. C = Extended temperature range (–40°C to +85°C)
4. V = Automotive temperature range (–40°C to +105°C)
10.5 Thermal Characteristics
Characteristic
Symbol
Value
Unit
Maximum junction temperature
TJ
150
°C
Thermal resistance
MC68HC05J1AP(1)
MC68HC05J1ADW (2)
θJA
68
85
°C/W
1. P = Plastic dual in-line package (PDIP)
2. DW = Small outline integrated circuit (SOIC)
MC68HC05J1A — Rev. 3.0
Technical Data
Electrical Specifications
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Electrical Specifications
10.6 Power Considerations
The average chip junction temperature, TJ, in °C can be obtained from:
TJ = TA + (PD x θJA)
(1)
Freescale Semiconductor, Inc...
Where:
TA = ambient temperature in °C
θJA = package thermal resistance, junction to ambient in °C/W
PD = PINT + PI/O
PINT = ICC × VCC = chip internal power dissipation
PI/O = power dissipation on input and output pins (user-determined)
For most applications, PI/O < PINT and can be neglected.
Ignoring PI/O, the relationship between PD and TJ is approximately:
K
PD =
(2)
TJ + 273°C
Solving equations (1) and (2) for K gives:
= PD x (TA + 273°C) + θJA x (PD)2
(3)
where K is a constant pertaining to the particular part. K can be
determined from equation (3) by measuring PD (at equilibrium) for a
known TA. Using this value of K, the values of PD and TJ can be obtained
by solving equations (1) and (2) iteratively for any value of TA.
Technical Data
MC68HC05J1A — Rev. 3.0
Electrical Specifications
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Electrical Specifications
5.0-Volt DC Electrical Characteristics
10.7 5.0-Volt DC Electrical Characteristics
Characteristic(1)
Symbol
Min
Typ
Max
Unit
VOL
VOH
—
VDD – 0.1
—
—
0.1
—
V
Output high voltage
PA7–PA0, PB5–PB0 (ILoad = –0.8 mA)
VOH
VDD – 0.8
—
—
V
Output low voltage
PA3–PA0, PB5–PB0 (ILoad = 1.6 mA)
PA7–PA4 (ILoad = 8.0 mA)
VOL
—
—
—
—
0.4
0.4
V
Input high voltage
PA7–PA0, PB5–PB0, IRQ, RESET, OSC1
VIH
0.7 × VDD
—
VDD
V
Input low voltage
PA7–PA0, PB5–PB0, IRQ, RESET, OSC1
VIL
VSS
—
0.2 × VDD
V
—
—
3.0
1.6
4.0
2.5
mA
mA
—
—
0.2
2.0
10
20
µA
µA
Freescale Semiconductor, Inc...
Output voltage
ILoad = 10.0 µA
ILoad = –10.0 µA
Supply current
Run(2)
Wait(3)
Stop(4)
25°C
–40°C to +85°C
IDD
I/O ports hi-z leakage current
PA7–PA0, PB5–PB0 (pulldown device off)
IIL
—
—
±10
µA
Input pulldown current
PA7–PA0, PB5–PB0 (pulldown device on)
IIL
50
100
200
µA
Input current
RESET, IRQ, OSC1
IIn
—
—
±1
µA
Capacitance
PA7–PA0, PB5–PB0 (input or output)
RESET, IRQ, OSC1, OSC2
COut
CIn
—
—
—
—
12
8
pF
Oscillator internal resistor
(Crystal/ceramic resonator mask option)
Rosc
1.0
2.0
3.0
MΩ
1. VDD = 5.0 Vdc ± 10%; VSS = 0 Vdc; TA = –40°C to +85°C; values reflect average measurements at midpoint of voltage
range at 25°C
2. Run (operating) IDD measured using external square wave clock source (fOSC = 4.2 MHz) with all inputs 0.2 V from rail.
No dc loads. Less than 50 pF on all outputs. CL = 20 pF on OSC2.
3. Wait IDD measured using external square wave clock source (fOSC = 4.2 MHz) with all inputs 0.2 V from rail and only
the timer active. No dc loads. Less than 50 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs.
VIL = 0.2 V. VIH = VDD – 0.2 V. OSC2 capacitance linearly affects wait IDD.
4. Stop IDD measured with OSC1 = V SS. All ports configured as inputs. VIL = 0.2 V. V IH = VDD – 0.2 V.
MC68HC05J1A — Rev. 3.0
Technical Data
Electrical Specifications
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Electrical Specifications
10.8 3.3-Volt DC Electrical Characteristics
Characteristic(1)
Symbol
Min
Typ
Max
Unit
VOL
VOH
—
VDD – 0.1
—
—
0.1
—
V
Output high voltage
PA7–PA0, PB5–PB0 (ILoad = –0.2 mA)
VOH
VDD – 0.3
—
—
V
Output low voltage
PA3–PA0 (ILoad = –0.4 mA)
PA7–PA4 (ILoad = 5.0 mA)
VOL
—
—
—
—
0.3
0.3
V
Input high voltage
PA7–PA0, PB5–PB0, IRQ, RESET, OSC1
VIH
0.7 × VDD
—
VDD
V
Input low voltage
PA7–PA0, PB5–PB0, IRQ, RESET, OSC1
VIL
VSS
—
0.2 × VDD
V
—
—
1.0
0.5
2.0
1.0
mA
mA
—
—
0.1
1
5
10
µA
µA
Freescale Semiconductor, Inc...
Output voltage
ILoad ≤ 10.0 µA
ILoad ≤ –10.0 µA
Supply current
Run(2)
Wait(3)
Stop(4)
25°C
–40°C to +85°C
IDD
I/O ports hi-z leakage current
PA7–PA0, PB5–PB0 (pulldown device off)
IIL
—
—
±10
µA
Input pulldown current
PA7–PA0, PB5–PB0 (pulldown device on)
IIL
20
40
100
µA
Input current
RESET, IRQ, OSC1
IIn
—
—
±1
µA
Capacitance
PA7–PA0, PB5–PB0 (input or output)
RESET, IRQ, OSC1, OSC2
COut
CIn
—
—
—
—
12
8
pF
Oscillator internal resistor
(Crystal/ceramic resonator mask option)
Rosc
1.0
2.0
3.0
MΩ
1. VDD = 3.3 Vdc ± 10%; VSS = 0 Vdc; TA = –40°C to +85°C; values reflect average measurements at midpoint of voltage
range at 25°C
2. Run (operating) IDD measured using external square wave clock source (fOSC = 2.0 MHz) with all inputs 0.2 V from rail.
No dc loads. Less than 50 pF on all outputs. CL = 20 pF on OSC2.
3. Wait IDD measured using external square wave clock source (fOSC = 2.0 MHz) with all inputs 0.2 V from rail and only
the timer active. No dc loads. Less than 50 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs.
VIL = 0.2 V. VIH = VDD – 0.2 V. OSC2 capacitance linearly affects wait IDD.
4. Stop IDD measured with OSC1 = V SS. All ports configured as inputs. VIL = 0.2 V. V IH = VDD – 0.2 V.
Technical Data
MC68HC05J1A — Rev. 3.0
Electrical Specifications
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Electrical Specifications
3.3-Volt DC Electrical Characteristics
4.20
4.30
4.40
VOH (V)
4.50
4.60
Freescale Semiconductor, Inc...
4.70
4.80
85°C
25°C
4.90
–40°C
5.00
0.00
–1.00
–2.00
–3.00
–4.00
–5.00
IOH (mA)
Figure 10-1. Typical VOH/IOH (VDD = 5.0 V)
2.55
2.65
2.75
VOH (V)
2.85
2.95
3.05
3.15
85°C
25°C
3.25
–40°C
3.35
0.00
–1.00
–2.00
–3.00
–4.00
–5.00
IOH (mA)
Figure 10-2. Typical VOH/IOH (VDD = 3.3 V)
MC68HC05J1A — Rev. 3.0
Technical Data
Electrical Specifications
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Electrical Specifications
800
700
600
VOL (V)
500
400
Freescale Semiconductor, Inc...
300
85°C
200
25°C
100
–40°C
0
0.00
2.00
4.00
6.00
8.00
10.00
IOL (mA)
Figure 10-3. Typical VOL/IOL (VDD = 5.0 V)
800
700
600
VOL (V)
500
400
300
85°C
200
25°C
100
–40°C
0
0.00
2.00
4.00
6.00
8.00
10.00
IOL (mA)
Figure 10-4. Typical VOL/IOL (VDD = 3.3 V)
Technical Data
MC68HC05J1A — Rev. 3.0
Electrical Specifications
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Electrical Specifications
3.3-Volt DC Electrical Characteristics
4.000
3.500
3.000
IDD (mA)
2.500
2.000
5.5 V
4.5 V
1.000
3.6 V
2.4 V
0.500
0.000
0.00
0.50
1.00
1.50
2.00
2.50
BUS FREQUENCY (MHz)
3.00
3.50
4.00
Figure 10-5. Typical Operating IDD (25°C)
2.500
2.000
1.500
IDD (mA)
Freescale Semiconductor, Inc...
1.500
5.5 V
1.000
4.5 V
3.6 V
2.4 V
0.500
0.000
0.00
1.00
2.00
3.00
BUS FREQUENCY (MHz)
4.00
5.00
Figure 10-6. Typical Wait Mode IDD (25°C)
MC68HC05J1A — Rev. 3.0
Technical Data
Electrical Specifications
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Electrical Specifications
10.0
FREQUENCY (MHz)
Freescale Semiconductor, Inc...
1.0
1.8 V
2.4 V
0.1
3.0 V
3.6 V
4.5 V
5.0 V
5.5 V
0.01
10
100
1000
RESISTANCE (kΩ)
Figure 10-7. Typical Internal Operating Frequency
for Various VDD at 25°C — RC Option Only
Technical Data
MC68HC05J1A — Rev. 3.0
Electrical Specifications
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Electrical Specifications
5.0-Volt Control Timing
10.9 5.0-Volt Control Timing
Characteristic(1)
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Oscillator frequency
Crystal/ceramic resonator mask option(2)
RC oscillator mask option
External clock mask option
Symbol
fOSC
Min
Max
—
dc
—
4.2
4.2
4.2
—
—
dc
—
2.1
2.1
2.1
2.1
Unit
MHz
Internal operating frequency (fOSC ÷ 2)
Crystal oscillator
Ceramic resonator
RC oscillator
External clock
fop
Cycle time (1 ÷ fop)
tcyc
476
—
ns
RESET pulse width low (edge-triggered)
tRL
1.5
—
tcyc
tRESL
4.0
—
tcyc
IRQ interrupt pulse width low (edge-triggered)
tILIH
125
—
ns
IRQ interrupt pulse period
tILIL
(4)
—
tcyc
PA3–PA0 interrupt pulse width high (edge-triggered)
tIHIL
125
—
ns
PA3–PA0 interrupt pulse period
tIHIH
(4)
—
tcyc
tOH, tOL
200
—
ns
Timer resolution(3)
OSC1 pulse width
MHz
1. V DD = 5.0 Vdc ± 10%; V SS = 0 Vdc; TA = TL to TH
2. Use only AT-cut crystals.
3. The 2-bit timer prescaler is the limiting factor in determining timer resolution.
4. The minimum period, tILIL or tIHIH, should not be less than the number of cycles required to execute the interrupt service
routine plus 19 tcyc.
MC68HC05J1A — Rev. 3.0
Technical Data
Electrical Specifications
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Electrical Specifications
10.10 3.3-Volt Control Timing
Characteristic(1)
Freescale Semiconductor, Inc...
Oscillator frequency
Crystal/ceramic resonator mask option(2)
RC oscillator mask option
External clock mask option
Symbol
fOSC
Min
Max
—
dc
—
2.0
2.0
2.0
—
—
dc
—
1.0
1.0
1.0
1.0
Unit
MHz
Internal operating frequency (fOSC ÷ 2)
Crystal oscillator
Ceramic resonator
RC oscillator
External clock
fop
Cycle time (1 ÷ fop)
tcyc
1000
—
ns
RESET pulse width low (edge-triggered)
tRL
1.5
—
tcyc
tRESL
4.0
—
tcyc
IRQ interrupt pulse width low (edge-triggered)
tILIH
250
—
ns
IRQ interrupt pulse period
tILIL
(4)
—
tcyc
PA3–PA0 interrupt pulse width high (edge-triggered)
tIHIL
250
—
ns
PA3–PA0 interrupt pulse period
tIHIH
(4)
—
tcyc
tOH, tOL
400
—
ns
Timer resolution(3)
OSC1 pulse width
MHz
1. V DD = 3.3 Vdc ± 10%; V SS = 0 Vdc; TA = TL to TH
2. Use only AT-cut crystals.
3. The 2-bit timer prescaler is the limiting factor in determining timer resolution.
4. The minimum period, tILIL or tIHIH, should not be less than the number of cycles required to execute the interrupt service
routine plus 19 tcyc.
Technical Data
MC68HC05J1A — Rev. 3.0
Electrical Specifications
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Electrical Specifications
3.3-Volt Control Timing
tILIL
tILIH
IRQ PIN
tILIH
IRQ1
.
.
.
IRQn
Freescale Semiconductor, Inc...
IRQ (INTERNAL)
Figure 10-8. External Interrupt Timing
OSC (NOTE 1)
tRL
RESET
tILIH
IRQ (NOTE 2)
4064 tCYC
IRQ (NOTE 3)
INTERNAL
CLOCK
INTERNAL
ADDRESS BUS
1FFE
(NOTE 4)
1FFE
1FFE
1FFE
1FFE
1FFF
RESET OR INTERRUPT
VECTOR FETCH
Notes:
1. Internal clocking from OSC1 pin
2. Edge-triggered external interrupt mask option
3. Edge- and level-triggered external interrupt mask option
4. Reset vector shown as example
Figure 10-9. Stop Mode Recovery Timing
MC68HC05J1A — Rev. 3.0
Technical Data
Electrical Specifications
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Electrical Specifications
VDD
(NOTE 1)
4064 tCYC
OSC1 PIN
INTERNAL
CLOCK
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INTERNAL
ADDRESS BUS
1FFE
1FFE
1FFE
1FFE
1FFE
1FFE
INTERNAL
DATA BUS
1FFF
NEW
PCH
NEW
PCL
Notes:
1. Power-on reset threshold is typically between 1 V and 2 V.
2. Internal clock, internal address bus, and internal data bus are not available externally.
Figure 10-10. Power-On Reset Timing
INTERNAL
CLOCK
INTERNAL
ADDRESS BUS
1FFE
INTERNAL
DATA BUS
1FFE
1FFE
1FFE
NEW
PCH
1FFF
NEW
PCL
NEW PC
DUMMY
NEW PC
OP
CODE
tRL
Notes:
1. Internal clock, internal address bus, and internal data bus are not available externally.
2. The next rising edge of the internal clock after the rising edge of RESET initiates the reset sequence.
Figure 10-11. External Reset Timing
Technical Data
MC68HC05J1A — Rev. 3.0
Electrical Specifications
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Technical Data — MC68HC05J1A
Section 11. Mechanical Specifications
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11.1 Contents
11.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
11.3
20-Pin Plastic Dual In-Line Package (PDIP). . . . . . . . . . . . . .110
11.4
20-Pin Small Outline Integrated
Circuit Package (SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
11.2 Introduction
Package dimensions for the MC68HC05J1A are provided in this section.
The packages are:
•
20-pin plastic dual in-line package (PDIP)
•
20-pin small outline integrated circuit package (SOIC)
MC68HC05J1A — Rev. 3.0
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Mechanical Specifications
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Mechanical Specifications
11.3 20-Pin Plastic Dual In-Line Package (PDIP)
-A20
11
1
10
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
B
C
Freescale Semiconductor, Inc...
-T-
L
DIM
A
B
C
D
E
F
G
J
K
L
M
N
K
SEATING
PLANE
M
E
G
N
F
J 20 PL
0.25 (0.010)
D 20 PL
0.25 (0.010)
M
T A
M
T B
M
M
INCHES
MIN
MAX
1.010 1.070
0.240 0.260
0.150 0.180
0.015 0.022
0.050 BSC
0.050 0.070
0.100 BSC
0.008 0.015
0.110 0.140
0.300 BSC
0°
15°
0.020 0.040
MILLIMETERS
MIN
MAX
25.66 27.17
6.60
6.10
4.57
3.81
0.55
0.39
1.27 BSC
1.77
1.27
2.54 BSC
0.38
0.21
3.55
2.80
7.62 BSC
15°
0°
1.01
0.51
CASE 738-03
11.4 20-Pin Small Outline Integrated Circuit Package (SOIC)
-A16
9
-B-
8X
P
0.010 (0.25) M
1
B
M
8
J
D 16X
0.010 (0.25) M
T A
S
B S
F
R
C
-T-
G 14X
K
SEATING
PLANE
M
CASE 751
X 45
DIM
A
B
C
D
F
G
J
K
M
P
R
Technical Data
MILLIMETERS
INCHES
MIN
MAX
10.15
10.45
7.40
7.60
2.35
2.65
0.35
0.49
0.50
0.90
1.27 BSC
0.25
0.32
0.10
0.25
0°
7°
10.05
10.55
0.25
0.75
MIN
MAX
0.400
0.411
0.292
0.299
0.093
0.104
0.014
0.019
0.020
0.035
0.050 BSC
0.010
0.012
0.004
0.009
0°
7°
0.395
0.415
0.010
0.029
MC68HC05J1A — Rev. 3.0
Mechanical Specifications
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Technical Data — MC68HC05J1A
Section 12. Ordering Information
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12.1 Contents
12.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
12.3
MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
12.4
MCU Ordering Forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
12.5
Application Program Media. . . . . . . . . . . . . . . . . . . . . . . . . . . 112
12.6
Diskettes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
12.7
EPROMs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
12.8
ROM Program Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
12.9
ROM Verification Units (RVUs). . . . . . . . . . . . . . . . . . . . . . . . 115
12.2 Introduction
This section contains instructions for ordering custom-masked read-only
memory (ROM) microcontroller units (MCU).
12.3 MC Order Numbers
Table 12-1. MC Order Numbers
Package Type
Temperature
Range
0°C to 70°C
20-pin dual in-line package
20-pin small outline integrated
circuit (SOIC)
Order Number
MC68HC05J1AP
–40°C to 85°C
MC68HC05J1ACP
–40°C to 105°C
MC68HC05J1AVP
0°C to 70°C
MC68HC05J1ADW
–40°C to 85°C
MC68HC05J1ACDW
–40°C to 105°C
MC68HC05J1AVDW
MC68HC05J1A — Rev. 3.0
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Ordering Information
12.4 MCU Ordering Forms
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To initiate an order for a ROM-based MCU, first obtain the current
ordering form for the MCU from a Motorola representative. Submit these
items when ordering MCUs:
•
A current MCU ordering form that is completely filled out
(Contact your Motorola sales office for assistance.)
•
A copy of the customer specification if the customer specification
deviates from the Motorola specification for the MCU
•
Customer’s application program on one of the media listed in
12.5 Application Program Media
The current MCU ordering form is also available through the World Wide
Web at http://www.motorola.com/semiconductors/
12.5 Application Program Media
Deliver the application program to Motorola in one of these media:
•
Macintosh®1 3 1/2-inch diskette (double-sided double-density
800 Kbytes or double-sided high-density 1.4 Mbytes)
•
MS-DOS®2 or PC-DOS®3 3 1/2-inch diskette (double-sided
double-density 720 Kbytes or double-sided high-density
1.44 Mbytes)
•
MS-DOS® or PC-DOS® 5 1/4-inch diskette (double-sided
double-density 360 Kbytes or double-sided high-density
1.2 Mbytes)
•
Erasable, programmable read-only memory(s) (EPROM) 2716,
2732, 2764, 27128, 27256, or 27512 (depending on the size of the
memory map of the MCU)
Use positive logic for data and addresses.
1. Macintosh is a registered trademark of Apple Computer, Inc.
2. MS-DOS is a registered trademark of Microsoft, Inc.
3. PC-DOS is a registered trademark of International Business Machines Corporation.
Technical Data
MC68HC05J1A — Rev. 3.0
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Diskettes
12.6 Diskettes
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If submitting the application program on a diskette, clearly label the
diskette with this information:
•
Customer name
•
Customer part number
•
Project or product name
•
Filename of object code
•
Date
•
Name of operating system that formatted diskette
•
Formatted capacity of diskette
On diskettes, the application program must be in Motorola’s S-record
format (S1 and S9 records), a character-based object file format
generated by M6805 cross assemblers and linkers.
NOTE:
Begin the application program at the first user ROM location. Program
addresses must correspond exactly to the available on-chip user ROM
addresses as shown in the memory map. Write $00 in all non-user ROM
locations or leave all non-user ROM locations blank. See the current
MCU ordering form for additional requirements.
If the memory map has two user ROM areas with the same addresses,
then write the two areas in separate files on the diskette. Label the
diskette with both filenames.
In addition to the object code, a file containing the source code can be
included. Motorola keeps this code confidential and uses it only to
expedite ROM pattern generation in case of any difficulty with the object
code. Label the diskette with the filename of the source code.
MC68HC05J1A — Rev. 3.0
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12.7 EPROMs
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If submitting the application program in an EPROM, clearly label the
EPROM with this information:
NOTE:
•
Customer name
•
Customer part number
•
Checksum
•
Project or product name
•
Date
Begin the application program at the first user ROM location. Program
addresses must correspond exactly to the available on-chip user ROM
addresses as shown in the memory map. Write $00 in all non-user ROM
loctions. See the current MCU ordering form for additional requirements.
Submit the application program in one EPROM large enough to contain
the entire memory map. If the memory map has two user ROM areas
with the same addresses, then write the two areas on separate
EPROMs. Label the EPROMs with the addresses they contain.
Pack EPROMs securely in a conductive IC carrier for shipment. Do not
use Styrofoam®1.
12.8 ROM Program Verification
The primary use for the on-chip ROM is to hold the customer’s
application program. The customer develops and debugs the application
program and then submits the MCU order along with the application
program.
Motorola inputs the customer’s application program code into a
computer program that generates a listing verify file. The listing verify file
represents the memory map of the MCU. The listing verify file contains
the user ROM code and may also contain non-user ROM code, such as
self-check code. Motorola sends the customer a computer printout of the
listing verify file along with a listing verify form.
1. Styrofoam is a registered trademark of The Dow Chemical Company.
Technical Data
MC68HC05J1A — Rev. 3.0
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ROM Verification Units (RVUs)
To aid the customer in checking the listing verify file, Motorola will
program the listing verify file into customer-supplied blank EPROMs or
preformatted Macintosh or DOS disks. All original pattern media are filed
for contractual purposes and are not returned.
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Check the listing verify file thoroughly, then complete and sign the listing
verify form and return the listing verify form to Motorola. The signed
listing verify form constitutes the contractual agreement for the creation
of the custom mask.
12.9 ROM Verification Units (RVUs)
After receiving the signed listing verify form, Motorola manufactures a
custom photographic mask. The mask contains the customer’s
application program and is used to process silicon wafers. The
application program cannot be changed after the manufacture of the
mask begins. Motorola then produces ten MCUs, called RVUs, and
sends the RVUs to the customer. RVUs are usually packaged in
unmarked ceramic and tested to 5 Vdc at room temperature. RVUs are
not tested to environmental extremes because their sole purpose is to
demonstrate that the customer’s user ROM pattern was properly
implemented. The ten RVUs are free of charge with the minimum order
quantity but are not production parts. RVUs are not guaranteed by
Motorola Quality Assurance.
MC68HC05J1A — Rev. 3.0
Technical Data
Ordering Information
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Ordering Information
Technical Data
MC68HC05J1A — Rev. 3.0
Ordering Information
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Technical Data — MC68HC05J1A
Appendix A. MC68HCL05J1A
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A.1 Contents
A.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
A.3
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 118
A.4
MC Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
A.2 Introduction
This appendix introduces the MC68HCL05J1A, a low-power version of
the MC68HC05J1A. All of the information in this document applies to the
MC68HCL05J1A with the exceptions given in this appendix.
MC68HC05J1A — Rev. 3.0
Technical Data
MC68HCL05J1A
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MC68HCL05J1A
A.3 DC Electrical Characteristics
The data in 10.7 5.0-Volt DC Electrical Characteristics and
10.8 3.3-Volt DC Electrical Characteristics applies to the
MC68HCL05J1A with the exceptions shown in Table A-1, Table A-2,
Table A-3, and Table A-4.
Table A-1. Low-Power Output Voltage (VDD = 1.8–2.4 Vdc)
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Characteristic
Symbol
Min
Typ
Max
Unit
Output high voltage
PA7–PA0, PB5–PB0 (ILoad = –0.1 mA)
VOH
VDD –0.3
—
—
V
Output low voltage
PA3–PA0 (ILoad = 0.2 mA)
PA7–PA4 (ILoad = 2.0 mA)
VOL
—
—
—
—
0.3
0.3
V
Table A-2. Low-Power Output Voltage (VDD = 2.5–3.6 Vdc)
Characteristic
Symbol
Min
Typ
Max
Unit
Output high voltage
PA7–PA0, PB5–PB0 (ILoad = –0.2 mA)
VOH
VDD –0.3
—
—
V
Output low voltage
PA3–PA0 (ILoad = 0.4 mA)
PA7–PA4 (ILoad = 5.0 mA)
VOL
—
—
—
—
0.3
0.3
V
Technical Data
MC68HC05J1A — Rev. 3.0
MC68HCL05J1A
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MC68HCL05J1A
Table A-3. Low-Power Supply Current
Characteristic
Symbol
Min
Typ(1)
Max
Unit
—
—
3.0
1.6
4.0
2.5
mA
mA
—
—
0.2
2.0
10
20
µA
µA
—
—
1.0
0.5
2.0
1.0
mA
mA
—
—
0.1
1.0
5.0
10.0
µA
µA
—
—
0.5
250
1.0
500
mA
µA
—
—
0.1
1.0
5.0
10.0
µA
µA
—
—
300
150
700
400
µA
µA
—
—
0.1
1.0
2
5
µA
µA
Supply current (VDD = 4.5–5.5 Vdc, fop = 2.1 MHz)
Run(2)
Wait(3)
Stop(4)
25°C
0°C to 70°C (standard)
IDD
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Supply current (VDD = 2.5–3.6 Vdc, fop = 1.0 MHz)
Run(2)
Wait(3)
Stop(4)
25°C
0°C to 70°C (standard)
IDD
Supply current (VDD = 2.5–3.6 Vdc, fop = 500 kHz)
Run(2)
Wait(3)
Stop(4)
25°C
0°C to 70°C (standard)
IDD
Supply current (VDD = 1.8–2.4 Vdc, fop = 500 kHz)
Run(2)
Wait(3)
Stop(4)
25°C
0°C to 70°C (standard)
IDD
1. Typical values reflect average measurements at midpoint of voltage range at 25°C.
2. Run (operating) IDD measured using external square wave clock source with all inputs 0.2 V from rail. No dc loads. Less
than 50 pF on all outputs. CL = 20 pF on OSC2.
3. WAIT IDD measured using external square wave clock source with all inputs 0.2 V from rail. No dc loads. Less than
50 pF on all outputs. C L = 20 pF on OSC2. All ports configured as inputs. VIL = 0.2 V, VIH = V DD –0.2 V. OSC2
capacitance linearly affects WAIT IDD.
4. Stop IDD measured with OSC1 = VDD. All ports configured as inputs. VIL = 0.2 V, VIH = V DD –0.2 V.
MC68HC05J1A — Rev. 3.0
Technical Data
MC68HCL05J1A
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Table A-4. Low-Power Pulldown Current
Symbol
Min
Typ(1)
Max
Unit
Pulldown current (VDD = 4.5–5.5 Vdc, fop = 2.1 MHz)
PA7–PA0, PB5–PB0 (pulldown device on)
IIL
50
100
200
µA
Pulldown current (VDD = 2.5–3.6 Vdc, fop = 1.0 MHz)
PA7–PA0, PB5–PB0 (pulldown device on)
IIL
8
30
100
µA
Pulldown current (VDD = 2.5–3.6 Vdc, fop = 500 kHz)
PA7–PA0, PB5–PB0 (pulldown device on)
IIL
3
10
50
µA
Pulldown current (VDD = 1.8–2.4 Vdc, fop = 500 kHz)
PA7–PA0, PB5–PB0 (pulldown device on)
IIL
3
10
50
µA
1. Typical values reflect average measurements at midpoint of voltage range at 25°C.
2.0
1.8
VDD = 2.5 V to 3.6 V
1.6
VDD = 1.8 V to 2.4 V
1.4
1.2
RUN IDD (mA)
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Characteristic
1.0
0.8
0.6
0.4
0.2
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
INTERNAL CLOCK FREQUENCY (MHz)
Figure A-1. Maximum Run Mode IDD versus Frequency
Technical Data
MC68HC05J1A — Rev. 3.0
MC68HCL05J1A
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1.0
0.9
VDD = 2.5 V to 3.6 V
0.8
VDD = 1.8 V to 2.4 V
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WAIT IDD (mA)
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
INTERNAL CLOCK FREQUENCY (MHz)
Figure A-2. Maximum Wait Mode IDD versus Frequency
A.4 MC Ordering Information
Table A-5 gives order numbers for the available package types.
Table A-5. MC Order Numbers
Package Type
Temperature
Range
Order
Number
20-pin dual in-line package (DIP)
0°C to 70°C
MC68HCL05J1AP
20-pin small outline integrated
circuit (SOIC)
0°C to 70°C
MC68HCL05J1ADW
MC68HC05J1A — Rev. 3.0
Technical Data
MC68HCL05J1A
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MC68HCL05J1A
Technical Data
MC68HC05J1A — Rev. 3.0
MC68HCL05J1A
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Technical Data — MC68HC05J1A
Appendix B. MC68HSC05J1A
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B.1 Contents
B.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
B.3
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 124
B.4
Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
B.5
MC Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
B.2 Introduction
This appendix introduces the MC68HSC05J1A, a high-speed version of
the MC68HC05J1A. All of the information in this document applies to the
MC68HSC05J1A with the exceptions given in this appendix.
MC68HC05J1A — Rev. 3.0
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MC68HSC05J1A
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B.3 DC Electrical Characteristics
The data in 10.7 5.0-Volt DC Electrical Characteristics and 10.8
3.3-Volt DC Electrical Characteristics applies to the MC68HSC05J1A
with the exceptions given in Table B-1.
Table B-1. High-Speed Supply Current
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Characteristic
Symbol
Min
Typ(1)
Max
Unit
—
—
4.5
2.5
6.0
3.25
mA
mA
—
—
0.2
2.0
10
20
µA
µA
—
—
2.0
1.0
4.0
2.0
mA
mA
—
—
0.1
1.0
5.0
10
µA
µA
Supply current (VDD = 4.5–5.5 Vdc, fOP = 4.0 MHz)
Run(2)
Wait(3)
IDD
Stop(4)
25°C
–40°C to +85°C
Supply current (VDD = 3.0–3.6 Vdc, fOP = 2.1 MHz
Run
Wait
Stop
25°C
–40°C to +85°C
IDD
1. Typical values reflect average measurements at midpoint of voltage range at 25°C.
2. Run (operating) IDD measured using external square wave clock source with all inputs 0.2 V from rail. No dc loads. Less
than 50 pF on all outputs. CL = 20 pF on OSC2.
3. Wait IDD measured using external square wave clock source with all inputs 0.2 V from rail. No dc loads. Less than 50 pF
on all outputs. C L = 20 pF on OSC2. All ports configured as inputs. VIL = 0.2 V, VIH = VDD –0.2 V. OSC2 capacitance
linearly affects wait IDD.
4. Stop IDD measured with OSC1 = V DD. All ports configured as inputs. VIL = 0.2 V, VIH = VDD –0.2 V.
Technical Data
MC68HC05J1A — Rev. 3.0
MC68HSC05J1A
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B.4 Control Timing
The data in 10.9 5.0-Volt Control Timing and 10.10 3.3-Volt Control
Timing applies to the MC68HSC05J1A with the exceptions given in
Table B-2 and Table B-3.
Table B-2. High-Speed Control Timing (VDD = 5.0 V ± 10%)
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Characteristic
Oscillator frequency
Crystal oscillator(1)
Ceramic resonator
External clock
Symbol
fosc
Min
Max
—
—
—
8.0
8.0
8.0
—
—
—
4.0
4.0
4.0
Unit
MHz
Internal operating frequency (fOSC ÷ 2)
Crystal oscillator(1)
Ceramic resonator
External clock
fop
MHz
Cycle time (1 ÷ fOP)
tcyc
250
—
ns
IRQ pulse width low (edge-triggered)
tILIL
63
—
ns
PA3–PA0 interrupt pulse width (edge-triggered)
tIHIL
63
—
ns
tOH or tOL
45
—
ns
Min
Max
Unit
—
—
—
4.2
4.2
4.2
—
—
—
2.1
2.1
2.1
OSC1 pulse width
1. Use only AT-cut crystals.
Table B-3. High-Speed Control Timing (VDD = 3.3 V ± 10%)
Characteristic
Oscillator frequency
Crystal oscillator(1)
Ceramic resonator
External clock
Symbol
fosc
MHz
Internal operating frequency (fOSC ÷ 2)
Crystal oscillator(1)
Ceramic resonator
External clock
fop
MHz
Cycle time (1 ÷ fOP)
tcyc
480
IRQ pulse width low (edge-triggered)
tILIL
125
—
ns
PA3–PA0 interrupt pulse width (edge-triggered)
tIHIL
125
—
ns
tOH or tOL
90
—
ns
OSC1 pulse width
ns
1. Use only AT-cut crystals.
MC68HC05J1A — Rev. 3.0
Technical Data
MC68HSC05J1A
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MC68HSC05J1A
B.5 MC Ordering Information
Table B-4 gives order numbers for the available package types.
Table B-4. MC Order Numbers
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Package Type
Temperature
Range
Order
Number
20-pin dual in-line package (DIP)
0°C to 70°C
MC68HSC05J1AP
20-pin small outline integrated
circuit (SOIC)
0°C to 70°C
MC68HSC05J1ADW
Technical Data
MC68HC05J1A — Rev. 3.0
MC68HSC05J1A
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