FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-16503-4E
32-bit Microcontroller
CMOS
FR60 MB91350A Series
MB91F355A/F353A/F356B/F357B/355A/354A/
MB91353A/352A/351A/V350A
■ DESCRIPTION
The FR family* is a series of standard single-chip microcontrollers that feature a variety of built-in I/O resources
and bus control functions, and that employ a high-performance 32-bit RISC CPU for embedded control applications
that demand powerful and fast CPU processing capabilities.
This product is one of the FR60 family based on the FR30/40 family CPU with enhanced bus access. The FR60
family is a line of single-chip oriented microcontrollers that incorporate a wealth of peripheral resources.
The FR60 family is optimized for embedded control applications that require high CPU processing power, such
as DVD players, navigation equipment, high performance fax machines, and printer controllers.
* : FR, the abbreviation of FUJITSU RISC controller, is a line of products of FUJITSU Limited.
■ FEATURES
1. FR CPU
•
•
•
•
32-bit RISC, load/store architecture with a five-stage pipeline
Maximum operating frequency : 50 MHz (using the PLL at an oscillation frequency of 12.5 MHz)
16-bit fixed length instructions (basic instructions), 1 instruction per cycle
Instruction set optimized for embedded applications : Memory-to-memory transfer, bit manipulation, barrel shift
etc.
• Instructions adapted for high-level languages : Function entry/exit instructions, multiple-register load/store
instructions
• Register interlock functions : Facilitate coding in assemblers
(Continued)
Be sure to refer to the “Check Sheet” for the latest cautions on development.
“Check Sheet” is seen at the following support page
URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
“Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system
development.
Copyright©2003-2007 FUJITSU LIMITED All rights reserved
MB91350A Series
• On-chip multiplier supported at the instruction level.
Signed 32-bit multiplication : 5 cycles
Signed 16-bit multiplication : 3 cycles
• Interrupt (PC, PS save) : 6 cycles, 16 priority levels
• Harvard architecture allowing program access and data access to be executed simultaneously
• Instructions compatible with the FR family
2. Bus interface
• Maximum operating frequency : 25 MHz
• 24-bit address full output (16 Mbyte address space) capability
(21-bit address full output (2 Mbyte address space) capability : MB91F353A/353A/352A/351A)
• 8,16-bit data output
• Built-in prefetch buffer
• Unused data and address pins can be used as general I/O ports.
• Able to output chip-select for 4 completely independent areas that can be configured in units of 64 Kbytes
• Support for various memory interfaces :
SRAM, ROM/Flash
page mode Flash ROM, page mode ROM interface
• Basic bus cycle : 2 cycles
• Programmable automatic wait cycle generator capable of inserting wait cycles for each area
• RDY input for external wait cycles
• DMA support of fly-by transfer capable of wait control for independent I/O
(The MB91F353A/353A/352A/351A does not support fly-by transfer.)
3. Built-in memory
D-bus memory
MB91F353A
MB91353A
MB91V350A MB91F355A MB91F356B
MB91355A
MB91F357B
ROM
MB91352A
MB91354A
MB91351A
No
512 Kbytes
256 Kbytes
512 Kbytes
384 Kbytes
384 Kbytes
RAM (Stack)
16 Kbytes
16 Kbytes
16 Kbytes
16 Kbytes
8 Kbytes
16 Kbytes
RAM (Execute instruction)
16 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
4. DMAC (DMA Controller)
• Capable of simultaneous operation of up to 5 channels (external → external : 3 channels)
• 3 transfer sources (external pin, internal peripheral or software) :
Activation sources are software-selectable (transfer can be activated by UART0/1/2).
• Addressing using 32-bit full addressing mode (increment, decrement, fixed)
• Transfer modes (demand transfer, burst transfer, step transfer, block transfer)
• Fly-by transfer support (between external I/O and memory)
• Selectable transfer data size : 8, 16, or 32-bit
• Multi-byte transfer capability (selected by software)
• DMAC descriptor in IO areas (200H to 240H, 1000H to 1024H)
(The MB91F353A/353A/352A/351A does not have an external interface.)
External pin transfer is not supported. Demand transfer and fly-by transfer cannot be used.
5. Bit search module (for REALOS)
• Search a single word starting from the MSB for the position of the first bit changed from 1 to 0.
(Continued)
2
MB91350A Series
6. Various timers
• 4 channels of 16-bit reload timer (including 1 channel for REALOS) :
Internal clock frequency divider selectable from 2/8/32 (division by 64/128 selectable only for ch.3)
• 16-bit free-run timer : 1 channel
Output compare : 8 channels (MB91F353A/353A/352A/351A : 2 channels)
Input capture
: 4 channels
• 16-bit PPG timer : 6 channels (MB91F353A/353A/352A/351A : 3 channels)
7. UART
•
•
•
•
•
•
•
UART full duplex double buffer : 5 channels (MB91F353A/353A/352A/351A : 4 channels)
Selectable parity on/off
Asynchronous (start-stop synchronized) or CLK-synchronous communications selectable
Built-in dedicated baud rate timer
External clock can be used as transfer clock
Assorted error detection functions (for parity, frame, and overrun errors)
Support for 115 kbps
8. SIO
• 8-bit data serial transfer : 3 channels (MB91F353A/353A/352A/351A : 2 channels)
• Shift clock selectable from among three internal and one external
• Shift direction selectable (transfer from LSB or MSB)
9. Interrupt controller
• Total number of external interrupts : 17 (MB91F353A/353A/352A/351A : 9)
(One non-maskable interrupt pin and 16/8 ordinary interrupt pins that can be used for wakeup in stop mode.)
• Interrupts from internal peripherals
• Programmable priorities (16 levels) for all interrupts except the non-maskable interrupt
10. D/A converter
• 8-bit resolution : 3 channels (MB91F353A/353A/352A/351A : 2 channels)
11. A/D converter
•
•
•
•
10-bit resolution : 12 channels (MB91F353A/353A/352A/351A : 8 channels)
Serial/parallel conversion type Conversion time : 1.48 µs
Conversion mode (one shot conversion mode, continuous conversion mode)
Activation source (software, external trigger, peripheral interrupt)
12. Other interval timer/counter
• 8/16-bit up/down counter
The MB91F353A/353A/352A/351A supports only an 8-bit up/down counter.
• 16-bit timer (U-TIMER) : 5 channels (MB91F353A/353A/352A/351A : 4 channels)
• Watch dog timer
13. I2C bus interface* (supports 400 kbps)
• 1 channel master/slave transmission and reception
• Arbitration and clock synchronization functions
14. I/O ports
• 3 V I/O ports
(5 V input is supported for those ports that are also used for external interrupts (16 ports, MB91F353A/353A/
352A/351A : 8 ports).
• Up to 126 ports (MB91F353A/353A/352A/351A : Up to 84 ports)
(Continued)
3
MB91350A Series
(Continued)
15. Other features
• Internal oscillator circuit as clock source, and PLL multiplication can be selected
• INIT pin provided as a reset pin (the oscillation stabilization wait time when the INIT pin is reset is clock
cycle × 2.)
• Watch dog timer reset and software reset are also provided.
• Support for stop and sleep modes for low power consumption, capable of saving power by operating the CPU
at 32 kHz.
• Gear function
• Built-in time base timer
• Package : MB91F355A/F356B/355A/354A/F357B : LQFP-176 (lead pitch 0.50 mm)
MB91F353A/353A/352A/351A : LQFP-120 (lead pitch 0.50 mm)
• CMOS technology(0.35 µm)
• Power supply voltage : 3.3 V ± 0.3 V
2.7 V to 3.6 V (MB91F356B/F357B only)
* : Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use these
components in an I2C system provided that the system conforms to the I2C Standard Specification as defined by
Philips.
4
MB91350A Series
■ PIN ASSIGNMENTS
• MB91F353A/353A/352A/351A
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
VSS
AVSS/AVRL
AVRH
AVCC
DAVC
DAVS
DA0
DA1
PH5/SCK3
PH4/SO3
PH3/SI3
PH2/SCK2
PH1/SO2
PH0/SI2
PO2/OC2
PO0/OC0
VSS
VCC
PI5/SCK1
PI4/SO1
PI3/SI1
PI2/SCK0
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
PI1/SO0
PI0/SI0
PK7/INT7/ATG
PK6/INT6/FRCK
PK5/INT5
PK4/INT4
PK3/INT3
PK2/INT2
PK1/INT1
PK0/INT0
PM5/SCK7
PM4/SO7/TRG4
PM3/SI7/TRG3
VCC
VSS
PM2/SCK6/ZIN0/TRG2
PM1/SO6/BIN0/TRG1
PM0/SI6/AIN0/TRG0
PN4/PPG4
PN2/PPG2
PN0/PPG0
PA3/CS3
PA2/CS2
PA1/CS1
PA0/CS0
P94/AS
P93
P91
P90/SYSCLK
X1A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
P54/A12
P55/A13
P56/A14
P57/A15
P60/A16
P61/A17
P62/A18
P63/A19
P64/A20
VSS
PL1/SCL
PL0/SDA
VSS
VCC
P80/IN0/RDY
P81/IN1/BGRNT
P82/IN2/BRQ
P83/RD
P84/WR0
P85/IN3/WR1
NMI
MD2
MD1
MD0
INIT
VCC
X1
X0
VSS
X0A
P20/D16
P21/D17
P22/D18
P23/D19
P24/D20
P25/D21
P26/D22
P27/D23
P30/D24
P31/D25
P32/D26
P33/D27
P34/D28
P35/D29
P36/D30
P37/D31
P40/A00
VSS
VCC
P41/A01
P42/A02
P43/A03
P44/A04
P45/A05
P46/A06
P47/A07
P50/A08
P51/A09
P52/A10
P53/A11
(FPT-120P-M21)
5
P20/D16
P21/D17
P22/D18
P23/D19
P24/D20
P25/D21
P26/D22
P27/D23
P30/D24
P31/D25
P32/D26
P33/D27
P34/D28
P35/D29
P36/D30
P37/D31
VSS
VCC
P40/A00
P41/A01
P42/A02
P43/A03
P44/A04
P45/A05
P46/A06
P47/A07
P50/A08
P51/A09
P52/A10
P53/A11
P54/A12
P55/A13
P56/A14
P57/A15
VSS
VCC
P60/A16
P61/A17
P62/A18
P63/A19
P64/A20
P65/A21
P66/A22
P67/A23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
PG4/SO5
PG3/SI5
PG2/SCK4
PG1/SO4
PG0/SI4
PH5/SCK3
PH4/SO3
PH3/SI3
PH2/SCK2
PH1/SO2
PH0/SI2
PI5/SCK1
PI4/SO1
PI3/SI1
PI2/SCK0
PI1/SO0
PI0/SI0
VCC
VSS
PJ7/INT15
PJ6/INT14
PJ5/INT13
PJ4/INT12
PJ3/INT11
PJ2/INT10
PJ1/INT9
PJ0/INT8
PK7/INT7/ATG
PK6/INT6/FRCK
PK5/INT5
PK4/INT4
PK3/INT3
PK2/INT2
PK1/INT1
PK0/INT0
VCC
VSS
PL1/SCL
PL0/SDA
VSS
PM5/SCK7/ZIN1/TRG5
PM4/SO7/BIN1/TRG4
PM3/SI7/AIN1/TRG3
PM2/SCK6/ZIN0/TRG2
MB91350A Series
• MB91F355A/F356B/F357B/355A/354A
(TOP VIEW)
PG5/SCK5
NMI
X1A
VSS
X0A
MD2
MD1
MD0
X0
VCC
X1
INIT
VSS
VCC
PC0/DREQ2
PC1/DACK2
PC2/DSTP2/DEOP2
PB0/DREQ0
PB1/DACK0
PB2/DSTP0/DEOP0
PB3/DREQ1
PB4/DACK1
PB5/DSTP1/DEOP1
PB6/IOWR
PB7/IORD
PA0/CS0
PA1/CS1
PA2/CS2
PA3/CS3
VSS
VCC
P80/IN0/RDY
P81/IN1/BGRNT
P82/IN2/BRQ
P83/RD
P84/WR0
P85/IN3/WR1
P90/SYSCLK
P91
P92/MCLK
P93
P94/AS
VSS
VCC
6
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
(FPT-176P-M02)
PM1/SO6/BIN0/TRG1
PM0/SI6/AIN0/TRG0
PN5/PPG5
PN4/PPG4
PN3/PPG3
PN2/PPG2
PN1/PPG1
PN0/PPG0
VCC
VSS
PO7/OC7
PO6/OC6
PO5/OC5
PO4/OC4
PO3/OC3
PO2/OC2
PO1/OC1
PO0/OC0
PP3/TOT3
PP2/TOT2
PP1/TOT1
PP0/TOT0
VCC
VSS
AVSS/AVRL
AVRH
AVCC
AN11
AN10
AN9
AN8
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
DA2
DA1
DA0
DAVC
DAVS
MB91350A Series
■ PIN DESCRIPTION
Pin no.
LQFP*1
1 to 8
9 to 16
19 to 26
27 to 34
37 to 41
42 to 44
LQFP*2
1 to 8
9 to 16
17, 20 to 26
27 to 34
Pin name
D16 to D23
I/O
circuit
type*3
C
Function
Bit 16 to bit 23 of the external data bus.
Valid only in external bus mode.
P20 to P27
Can be used as ports while in external bus 8-bit mode.
D24 to D31
Bit 24 to bit 31 of the external data bus.
Valid only in external bus mode.
C
P30 to P37
Can be used as ports while in single-chip mode.
A00 to A07
Bit 0 to bit 7 of the external address bus.
Valid only in external bus mode.
C
P40 to P47
Can be used as ports while in single-chip mode.
A08 to A15
Bit 8 to bit 15 of the external address bus.
Valid only in external bus mode.
C
P50 to P57
Can be used as ports while in single-chip mode.
A16 to A20
Bit 16 to bit 20 of the external address bus.
Valid only in external bus mode.
35 to 39
C
P60 to P64
Can be used as ports while in single-chip mode or when the
external address bus is not used.
A21 to A23
Bit 21 to bit 23 of the external address bus.
Valid only in external bus mode.
⎯
C
P65 to P67
Can be used as ports while in single-chip mode or when the
external address bus is not used.
47, 48
106,105
DA0, DA1
⎯
D/A converter output pins
49
⎯
DA2
⎯
D/A converter output pin
50 to 57
113 to 120
AN0 to AN7
G
Analog input pins
58 to 61
⎯
AN8 to AN11
G
Analog input pins
Reload timer output ports.
This pin is valid when timer output is enabled.
TOT0 to TOT3
67 to 70
⎯
D
PP0 to PP3
OC0
71
97
PO0
General-purpose I/O ports.
This pin is valid when the timer output function is
disabled.
Output compare output pin
D
General-purpose I/O port.
This pin can be used as a port when the output compare
output is not used.
(Continued)
7
MB91350A Series
Pin no.
LQFP*1
LQFP*2
Pin name
I/O
circuit
type*3
OC1
72
⎯
PO1
Output compare output pin
D
OC2
73
98
PO2
⎯
PO3 to PO7
D
70
PN0
D
⎯
PN1
D
71
PN2
D
⎯
PN3
D
72
PN4
D
⎯
PN5
General-purpose I/O port.
This pin can be used as a port when the PPG timer output is
not used.
PPG timer output pin
D
PPG5
86
General-purpose I/O port.
This pin can be used as a port when the PPG timer output is
not used.
PPG timer output pin
PPG4
85
General-purpose I/O port.
This pin can be used as a port when the PPG timer output is
not used.
PPG timer output pin
PPG3
84
General-purpose I/O port.
This pin can be used as a port when the PPG timer output is
not used.
PPG timer output pin
PPG2
83
General-purpose I/O ports.
These pins can be used as ports when the output compare
outputs are not used.
PPG timer output pin
PPG1
82
General-purpose I/O port.
This pin can be used as a port when the output compare
output is not used.
Output compare output pins
PPG0
81
General-purpose I/O port.
This pin can be used as a port when the output compare
output is not used.
Output compare output pin
OC3 to OC7
74 to 78
Function
General-purpose I/O port.
This pin can be used as a port when the PPG timer output is
not used.
PPG timer output pin
D
General-purpose I/O port.
This pin can be used as a port when the PPG timer output is
not used.
(Continued)
8
MB91350A Series
Pin no.
LQFP*1
LQFP*2
Pin name
I/O
circuit
type*3
Data input for serial I/O6.
Since this input is always used when serial I/O6 input is
operating, output using the port must be stopped beforehand
unless this operation is the intended operation.
SI6
AIN0
87
88
89
73
Function
D
Input for the up/down counter.
Since this input is always used when input is enabled, output
using the port must be stopped beforehand unless this operation
is the intended operation.
TRG0
External trigger input for PPG timer 0.
Since this input is always used when input is enabled, output
using the port must be stopped beforehand unless this operation
is the intended operation.
PM0
General-purpose I/O port.
This pin can be used as a port when serial I/O, up/down counter,
and PPG timer output are not used.
SO6
Data output from serial I/O6.
This function is valid when data output from serial I/O6 is
enabled.
BIN0
Input for the up/down counter.
Since this input is always used when input is enabled, output
using the port must be stopped beforehand unless this operation
is the intended operation.
74
D
TRG1
External trigger input for PPG timer 1.
Since this input is always used when input is enabled, output
using the port must be stopped beforehand unless this operation
is the intended operation.
PM1
General-purpose I/O port.
This pin can be used as a port when serial I/O, up/down counter,
and PPG timer output are not used.
SCK6
Clock I/O for serial I/O 6.
This function is valid when clock output from serial I/O6 is
enabled or when an external shift clock input is used.
ZIN0
Input for the up/down counter.
Since this input is always used when input is enabled, output
using the port must be stopped beforehand unless this operation
is the intended operation.
75
D
TRG2
External trigger input for PPG timer 2.
Since this input is always used when input is enabled, output
using the port must be stopped beforehand unless this operation
is the intended operation.
PM2
General-purpose I/O port.
This pin can be used as a port when serial I/O, up/down counter,
and PPG timer output are not used.
(Continued)
9
MB91350A Series
Pin no.
LQFP*1
LQFP*2
Pin name
I/O
circuit
type*3
Data input for serial I/O7.
Since this input is always used when serial I/O7 input is
operating, output using the port must be stopped beforehand
unless this operation is the intended operation.
SI7
4
AIN1*
90
78
D
TRG3
PM3
General-purpose I/O port.
This pin can be used as a port when serial I/O, up/down counter,
and PPG timer output are not used.
S07
Data output from serial I/O7.
This function is valid when data output from serial I/O7 is
enabled.
79
D
Input for the up/down counter.
Since this input is always used when input is enabled, output
using the port must be stopped beforehand unless this operation
is the intended operation.
TRG4
External trigger input for PPG timer 4.
Since this input is always used when input is enabled, output
using the port must be stopped beforehand unless this operation
is the intended operation.
PM4
General-purpose I/O port.
This pin can be used as a port when serial I/O, up/down counter,
and PPG timer output are not used.
SCK7
Clock I/O for serial I/O7.
This function is valid when clock output from serial I/O7 is
enabled or when an external shift clock input is used.
ZIN1*
92
Input for the up/down counter.
Since this input is always used when input is enabled, output
using the port must be stopped beforehand unless this operation
is the intended operation.
External trigger input for PPG timer 3.
Since this input is always used when input is enabled, output
using the port must be stopped beforehand unless this operation
is the intended operation.
BIN1*4
91
Function
4
80
D
Input for the up/down counter.
Since this input is always used when input is enabled, output
using the port must be stopped beforehand unless this operation
is the intended operation.
TRG5*
External trigger input for PPG timer 5.
Since this input is always used when input is enabled, output
using the port must be stopped beforehand unless this operation
is the intended operation.
PM5
General-purpose I/O port.
This pin can be used as a port when serial I/O, up/down counter,
and PPG timer output are not used.
4
(Continued)
10
MB91350A Series
Pin no.
LQFP*1
LQFP*2
Pin name
I/O
circuit
type*3
SDA
94
95
98 to 103
42
F
General-purpose I/O port.
This pin can be used as a port when I2C operation is disabled
(open drain output).
SCL
Clock I/O pin for the I2C bus.
This pin is valid when standard mode I2C operation is
enabled.
Output using the port must be stopped beforehand unless this
operation is intended (open drain output).
F
PL1
General-purpose I/O port.
This pin can be used as a port when I2C operation is disabled
(open drain output).
INT0 to INT5
External interrupt inputs.
Since these inputs are always used when the corresponding
external interrupts are enabled, output using the ports must
be stopped beforehand unless this operation is the intended
operation.
E
PK0 to PK5
General-purpose I/O ports
External interrupt input.
Since this input is always used when the corresponding
external interrupt is enabled, output using the port must be
stopped beforehand unless this operation is the intended
operation.
INT6
104
87
E
FRCK
105
DATA I/O pin for the I2C bus.
This pin is valid when standard mode I2C operation is
enabled.
Output using the port must be stopped beforehand unless this
operation is intended (open drain output).
PL0
41
81 to 86
Function
External clock input pin for the free-run timer.
Since this input is always used when it is selected as the
external clock input for the free-run timer, output using the port
must be stopped beforehand unless this operation is the
intended operation.
PK6
General-purpose I/O port
INT7
External interrupt input.
Since this input is always used when the corresponding
external interrupt is enabled, output using the port must be
stopped beforehand unless this operation is the intended
operation.
88
E
ATG
External trigger for the A/D converter.
Since this input is always used when it is selected as the A/D
activation source, output using the port must be stopped
beforehand unless this operation is the intended operation.
PK7
General-purpose I/O port
(Continued)
11
MB91350A Series
Pin no.
LQFP*1
106 to 113
LQFP*2
⎯
Pin name
INT8 to INT15
I/O
circuit
type*3
E
PJ0 to PJ7
116
117
89
SI0
D
General-purpose I/O port
SO0
Data output from UART0.
This function is valid when UART0 data output is enabled.
90
D
120
91
92
D
SI1
Data input for UART1.
Since this input is always used when UART1 input is
operating, output using the port must be stopped beforehand
unless this operation is the intended operation.
D
PI3
General-purpose I/O port
SO1
Data output from UART1.
This function is valid when UART1 data output is enabled.
93
D
94
99
Clock I/O for UART0.
This function is valid when UART0 clock output is enabled or
when an external clock input is used.
General-purpose I/O port.
This function is valid when UART0 clock output is disabled or
when an external clock input is not used.
SCK1
122
General-purpose I/O port.
This function is valid when UART0 data output is disabled.
PI2
PI4
121
Data input for UART0.
Since this input is always used when UART0 input is operating, output using the port must be stopped beforehand unless
this operation is the intended operation.
PI0
SCK0
119
External interrupt inputs.
Since these inputs are always used when the corresponding
external interrupts are enabled, output using the ports must
be stopped beforehand unless this operation is the intended
operation.
General-purpose I/O ports
PI1
118
Function
D
General-purpose I/O port.
This function is valid when UART1 data output is disabled.
Clock I/O for UART1.
This function is valid when UART1 clock output is enabled or
when an external clock input is used.
PI5
General-purpose I/O port.
This function is valid when UART1 clock output is disabled or
when an external clock input is not used.
SI2
Data input for UART2.
Since this input is always used when UART2 input is
operating, output using the port must be stopped beforehand
unless this operation is the intended operation.
PH0
D
General-purpose I/O port
(Continued)
12
MB91350A Series
Pin no.
LQFP*1
LQFP*2
Pin name
I/O
circuit
type*3
Data output from UART2.
This function is valid when UART2 data output is enabled.
SO2
123
124
125
126
100
D
PH1
General-purpose I/O port.
This function is valid when UART2 data output is disabled or
when an external shift clock input is used.
SCK2
Clock I/O for UART2.
This function is valid when UART2 clock output is enabled or
when an external clock input is used.
101
102
D
PH2
General-purpose I/O port.
This function is valid when UART2 clock output is disabled or
when an external clock input is not used.
SI3
Data input for UART3.
Since this input is always used when UART3 input is operating, output using the port must be stopped beforehand unless
this operation is the intended operation.
D
PH3
General-purpose I/O port
SO3
Data output from UART3.
This function is valid when UART3 data output is enabled.
103
D
PH4
SCK3
127
128
129
104
⎯
Function
D
General-purpose I/O port.
This function is valid when UART3 data output is disabled.
Clock I/O for UART3.
This function is valid when UART3 clock output is enabled or
when an external clock input is used.
PH5
General-purpose I/O port.
This function is valid when UART3 clock output is disabled or
when an external clock input is not used.
SI4
Data input for UART4.
Since this input is always used when UART4 input is operating, output using the port must be stopped beforehand unless
this operation is the intended operation.
D
PG0
General-purpose I/O port
SO4
Data output from UART4.
This function is valid when serial I/O4 data output is enabled.
⎯
D
PG1
General-purpose I/O port.
This function is valid when serial I/O4 data output is disabled.
(Continued)
13
MB91350A Series
Pin no.
LQFP*1
LQFP*2
Pin name
I/O
circuit
type*3
SCK4
130
131
132
133
⎯
⎯
D
Function
Clock I/O for UART4.
This function is valid when serial I/O4 clock output is enabled or
when an external clock input is used.
PG2
General-purpose I/O port.
This function is valid when serial I/O4 clock output is disabled
or when an external clock input is not used.
SI5
Data input for serial I/O5.
Since this input is always used when serial I/O5 input is
operating, output using the port must be stopped beforehand
unless this operation is the intended operation.
D
PG3
General-purpose I/O port
SO5
Data output from serial I/O5.
This function is valid when serial I/O5 data output is enabled.
⎯
D
PG4
General-purpose I/O port.
This function is valid when serial I/O5 data output is disabled.
SCK5
Clock I/O for serial I/O5.
This function is valid when serial I/O5 clock output is enabled or
when an external shift clock input is used.
⎯
D
PG5
General-purpose I/O port.
This function is valid when serial I/O5 clock output is disabled
or when an external clock input is not used.
134
51
NMI
H
NMI (non-maskable interrupt) input
135
61
X1A
B
Clock (oscillation) output (sub clock)
137
60
X0A
B
Clock (oscillation) input (sub clock)
H
Mode pins 2 to 0.
These pins set the basic operating mode. Connect the pins to
VCC or VSS.
Input circuit type :
The production version (MASK ROM version) is the "H" type.
The Flash ROM version is the "J" type.
138 to 140
52 to 54
MD2 to MD0
141
58
X0
A
Clock (oscillation) input (main clock)
143
57
X1
A
Clock (oscillation) output (main clock)
144
55
INIT
I
External reset input
147
⎯
DREQ2
PC0
J
C
DMA external transfer request input.
Since this input is always used when it is selected as the DMA
activation source, output using the port must be stopped
beforehand unless this operation is the intended operation.
General-purpose I/O port
(Continued)
14
MB91350A Series
Pin no.
LQFP*1
LQFP*2
Pin name
I/O
circuit
type*3
DACK2
148
149
⎯
⎯
C
⎯
General-purpose I/O port.
This function is valid when DMA transfer request acceptance
output is enabled.
DEOP2
DMA external transfer end output.
This function is valid when DMA external transfer end output is
enabled.
DSTP2
C
DREQ0
C
152
⎯
C
⎯
DMA external transfer request acceptance output.
This function is valid when DMA transfer request acceptance
output is enabled.
PB1
General-purpose I/O port.
This function is valid when DMA transfer request acceptance
output is disabled.
DEOP0
DMA external transfer end output.
This function is valid when DMA external transfer end output is
enabled.
DSTP0
C
DREQ1
PB3
DMA external transfer stop input.
This function is valid when DMA external transfer stop input is
enabled.
General-purpose I/O port.
This function is valid when DMA external transfer end output
and external transfer stop input are disabled.
PB2
153
DMA external transfer request input.
Since this input is always used when it is selected as the DMA
activation source, output using the port must be stopped
beforehand unless this operation is the intended operation.
General-purpose I/O port
DACK0
⎯
DMA external transfer stop input.
This function is valid when DMA external transfer stop input is
enabled.
General-purpose I/O port.
This function is valid when DMA external transfer end output
and external transfer stop input are disabled.
PB0
151
DMA external transfer request acceptance output.
This function is valid when DMA transfer request acceptance
output is enabled.
PC1
PC2
150
Function
C
DMA external transfer request input.
Since this input is always used when it is selected as the DMA
activation source, output using the port must be stopped
beforehand unless this operation is the intended operation.
General-purpose I/O port.
(Continued)
15
MB91350A Series
Pin no.
LQFP*1
LQFP*2
Pin name
I/O
circuit
type*3
DACK1
154
⎯
C
PB4
156
157
158
159
160
⎯
DSTP1
DMA external transfer request acceptance output.
This function is valid when DMA transfer request acceptance
output is enabled.
General-purpose I/O port.
This function is valid when DMA external transfer request
acceptance output is disabled.
DMA external transfer end output.
This function is valid when DMA external transfer end output
is enabled.
DEOP1
155
Function
C
DMA external transfer stop input.
This function is valid when DMA external transfer stop input is
enabled.
PB5
General-purpose I/O port.
This function is valid when DMA external transfer end output
and external transfer stop input are disabled.
IOWR
Write strobe output for DMA fly-by transfer.
This function is valid when write strobe output for DMA fly-by
transfer is enabled.
⎯
C
PB6
General-purpose I/O port.
This function is valid when write strobe output for DMA fly-by
transfer is disabled.
IORD
Read strobe output for DMA fly-by transfer.
This function is valid when read strobe output for DMA fly-by
transfer is enabled.
⎯
C
PB7
General-purpose I/O port.
This function is valid when read strobe output for DMA fly-by
transfer is disabled.
CS0
Chip select 0 output.
This function is valid in external bus mode.
66
C
PA0
General-purpose I/O port.
This function is valid in single-chip mode.
CS1
Chip select 1 output.
This function is valid when chip select 1 output is enabled.
67
C
PA1
General-purpose I/O port.
This function is valid when chip select 1 output is disabled.
CS2
Chip select 2 output.
This function is valid when chip select 2 output is enabled.
68
C
PA2
General-purpose I/O port.
This function is valid when chip select 2 output is disabled.
(Continued)
16
MB91350A Series
Pin no.
LQFP*1
LQFP*2
Pin name
I/O
circuit
type*3
CS3
161
164
69
45
C
General-purpose I/O port.
This function is valid when chip select 3 output is disabled.
RDY
External ready input.
This function is valid when external ready input is enabled.
IN0
Input capture input pin.
Since this input is always used when it is selected for input
capture input, output using the port must be stopped
beforehand unless this operation is the intended operation.
D
General-purpose I/O port.
This function is valid when external ready input is disabled.
External bus open acceptance output.
Outputs an “L” level when the external bus is open.
This function is valid when output is enabled.
BGRNT
166
167
46
47
Chip select 3 output.
This function is valid when chip select 3 output is enabled.
PA3
P80
165
Function
IN1
D
Input capture input pin.
Since this input is always used when it is selected for input
capture input, output using the port must be stopped
beforehand unless this operation is the intended operation.
P81
General-purpose I/O port.
This function is valid when external bus open acceptance is
disabled.
BRQ
External bus open request input.
A high level is input to this pin to request for the external bus
to be made open.
This function is valid when input is enabled.
IN2
D
Input capture input pin.
Since this input is always used when it is selected for input
capture input, output using the port must be stopped
beforehand unless this operation is the intended operation.
P82
General-purpose I/O port.
This function is valid when external bus open request is
disabled.
RD
External bus read strobe output.
This function is valid in external bus mode.
D
48
P83
General-purpose I/O port.
This function is valid in single-chip mode.
(Continued)
17
MB91350A Series
(Continued)
Pin no.
LQFP*1
LQFP*2
Pin name
I/O
circuit
type*3
WR0
168
169
170
49
50
D
General-purpose I/O port.
This function is valid in single-chip mode.
WR1
External bus write strobe output.
This function is valid when WR1 output in external bus mode
is enabled.
IN3
Input capture input pin.
Since this input is always used when it is selected for input
capture input, output using the port must be stopped beforehand unless this operation is the intended operation.
D
P85
General-purpose I/O port.
This function is valid when external bus write enable output is
disabled.
SYSCLK
System clock output.
This function is valid when system clock output is enabled. A
clock having the same frequency as the external bus operating frequency is output (stopped in stop mode).
62
63
C
General-purpose I/O port.
This function is valid when system clock output is disabled.
P91
C
General-purpose I/O port
C
Memory clock output.
This function is valid when memory clock output is enabled. A
clock having the same frequency as the external bus operating frequency is output (stopped in sleep mode).
MCLK
172
⎯
General-purpose I/O port.
This function is valid when memory clock output is disabled.
P92
173
64
P93
C
AS
174
External bus write strobe output.
This function is valid in external bus mode.
P84
P90
171
Function
C
65
P94
General-purpose I/O port
Address strobe output.
This function is valid when address strobe output is enabled.
General-purpose I/O port.
This function is valid when address load output is disabled.
*1 : FPT-176P-M02
*2 : FPT-120P-M21
*3 : Refer to “■ I/O CIRCUIT TYPE” for details on the I/O circuit types.
*4 : These functions are not supported on the FPT-120P-M21.
18
MB91350A Series
[Power supply and GND pins]
Pin number
Pin name
LQFP*1
Function
LQFP*2
17, 35, 65, 79, 93, 96,
114, 136, 145, 162, 175
18, 40, 43, 59,
76, 96, 112
VSS
GND pins. Use the same potential for all
pins.
18, 36, 66, 80, 97, 115,
142, 146, 163, 176
19, 44, 56, 77,
95
VCC
3.3 V power supply pins. Use the same
potential for all pins.
45
107
DAVS
D/A converter GND pin
46
108
DAVC
D/A converter power supply pin
62
109
AVCC
A/D converter analog power supply pin
63
110
AVRH
A/D converter reference power supply pin
64
111
AVSS/AVRL
A/D converter analog GND pin
*1 : FPT-176P-M02
*2 : FPT-120P-M21
19
MB91350A Series
■ I/O CIRCUIT TYPE
Type
Circuit type
Remarks
X1
Clock input
A
Oscillation feedback resistance :
approx. 1 MΩ
X0
Standby control
X1A
Clock input
B
Oscillation feedback resistance for low
speed (sub clock oscillation) :
approx. 7 MΩ
X0A
Standby control
Pull-up control
P-ch
• CMOS level output
• CMOS level input
P-ch
Digital output
N-ch
Digital output
C
With standby control
With pull-up control
Digital input
Standby control
Pull-up control
P-ch
• CMOS level output
• CMOS level hysteresis input
P-ch
Digital output
N-ch
Digital output
D
With standby control
With pull-up control
Digital input
Standby control
(Continued)
20
MB91350A Series
Type
Circuit type
P-ch
N-ch
E
Remarks
Digital output
• CMOS level output
• CMOS level hysteresis input
P-ch
Digital output
Withstand voltage of 5 V
Digital input
• N-ch (Open drain input)
• CMOS level hysteresis input
N-ch
Digital output
F
With standby control
Withstand voltage of 5 V
Digital input
Standby control
Analog input
With switch
P-ch
N-ch
G
Analog input
Control
CMOS level hysteresis input
P-ch
N-ch
H
Digital input
P-ch
CMOS level hysteresis input
With pull-up resistor
P-ch
I
Digital input
(Continued)
21
MB91350A Series
(Continued)
Type
Circuit type
• CMOS level input
• MB91F353A/F355A/F356B/F357B
only
N-ch
N-ch
J
N-ch
N-ch
22
Remarks
Control signal
Mode input
Diffused resistor
N-ch
MB91350A Series
■ HANDLING DEVICES
• Preventing Latch-up
Latch-up may occur in a CMOS IC if a voltage greater than VCC or less than VSS is applied to an input or output
pin or if an above-rating voltage is applied between VCC and VSS. A latch-up,if it occurs, significantly increases
the power supply current and may cause thermal destruction of an element. When you use a CMOS IC, don’t
exceed the absolute maximum rating.
• Treatment of Unused Pins
Do not leave unused input pins open, as this may cause a malfunction. Handle by using a pull-up or pull-down
resistor.
• Power Supply Pins
In products with multiple VCC and VSS pins, the pins of the same potential are internally connected in the device
to avoid abnormal operations including latch-up. However, you must connect the pins to the external power
supply and ground lines in order to lower the electro-magnetic emission level, to prevent abnormal operation of
strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Moreover,
connect the current supply source to the VCC and VSS pins of this device at the low impedance.
It is also advisable to connect a ceramic bypass capacitor of approximately 0.1 µF between VCC and VSS pins
near this device.
• Crystal Oscillator Circuit
Noise near the X0, X1, X0A and X1A pins may cause the device to malfunction. Design the printed circuit board
so that X0, X1, X0A, X1A, the crystal oscillator (or ceramic oscillator), and the bypass capacitor to ground are
located close to the device as possible.
It is strongly recommended that the PC board artwork be designed such that the X0, X1, X0A and X1A pins are
surrounded by ground plane, as stable operation can be obtained by using this layout.
Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device.
• Notes on Using an External Clock
When using an external clock, as a general rule you should simultaneously supply the clock signal to X0 and a
clock signal with the reverse phase to X1. However, the stop mode (oscillator stop mode) must not be used
under this configuration (This is because the X1 pin stops at High level output in STOP mode) .
Using an external clock (normal)
X0
X1
MB91350A series
Note : STOP mode (oscillation stop mode) cannot be used.
• Clock Control Block
Hold the signal for the oscillation stabilization wait time when inputting a Low level to the INIT pin.
23
MB91350A Series
• Notes on Using the Sub Clock
When the X0A and X1A pins are not connected to an oscillator, pull down the X0A pin and leave the X1A pin open.
Using an external clock (normal)
X0
OPEN
X1
MB91350A series
• Treatment of NC and OPEN Pins
Pins marked as NC and OPEN must be left open.
• Mode Pins (MD0 to MD2)
These pins should be connected directly to the VCC or VSS pins.
To prevent the device erroneously switching to test mode due to noise, design the printed circuit board such that
the distance between the mode pins and VCC or VSS pins is as short as possible and the connection impedance
is low.
• Operation at Start-up
The INIT pin must be at Low level when the power supply is turned on.
Immediately after the power supply is turned on, the Low level input needs to be held to the INIT pin for the
oscillation stabilization wait time of the oscillator circuit to ensure that the oscillator has time to settle (For INIT
via the INIT pin, the oscillation stabilization wait time setting is initialized to the minimum value).
• Oscillation Input at Power On
When the power is turned on, maintain the clock input until the device is released from the oscillation stabilization
wait state.
• Precautions While Operating in PLL Clock Mode
On this microcontroller, if the crystal oscillator is disconnected or the external reference clock input stops while
PLL clock mode is selected, the microcontroller may continue to operate at the free-run frequency of the selfoscillating circuit within the PLL. However, Fujitsu does not guarantee this operation.
• External Bus Setting
This model guarantees an external bus frequency of 25 MHz.
If the base clock frequency is set to 50 MHz when the DIVR1 (external bus base clock division setting register)
register is still set to the default value, the external bus frequency will be set to 50 MHz. When you change the
base clock frequency, change the base clock frequency after setting the external bus within 25 MHz.
• MCLK and SYSCLK
The difference between MCLK and SYSCLK is that MCLK stops in SLEEP/STOP mode but SYSCLK stops only
in STOP mode. Use the clock that is appropriate for each application.
Upon initialization, MCLK is disabled (PORT) and SYSCLK is enabled. To use MCLK, the port function register
(PFR) needs to be set to enable the use of the clock.
24
MB91350A Series
• Pull-up Control
If a pull-up resistor is provided to a pin that is used as an external bus pin, there is no guarantee that the pin will
conform to the specifications given in “■ ELECTRICAL CHARACTERISTICS 4. AC Characteristics (4) Normal
Bus Access Read/Write Operation, (5) Multiplex Bus Access Read/Write operation and (7) Hold Timing”.
Furthermore, even if a port has been configured to use a pull-up resistance, this setting is invalid during stop
mode with HIZ=1 and during hardware standby mode.
• Sub Clock Select
At least one NOP instruction needs to be executed immediately after switching the clock source from main clock
mode to sub clock mode.
(Idi
(Idi
stb
nop
#0x0b, r0)
#_CLKR, r12)
r0, @r12
// sub-clock mode
// Must insert NOP instruction
• Bit Search Module
The BSD0, BSD1, and BDSC registers can only be accessed in words.
• D-bus Memory
Do not set the code area to memory on the D-bus because instructions cannot be fetched from the D-bus.
Executing an instruction fetch to the D-bus area will cause incorrect data to be interpreted as code, possibly
causing the device to run out of control.
• Low Power Consumption Mode
When entering sleep or stop mode, be sure to read the standby control register (STCR) immediately after writing
to it.
More specifically, use the following sequence.
Furthermore, after recovering from standby mode, set the I flag, ILM, and ICR registers such that the CPU
branches to the interrupt handler for the interrupt that triggered the controller to recover from standby mode.
(Idi
#value_of_standby, r0)
(Idi
#_STCR, r12)
stb
r0, @r12
// set STOP/SLEEP bit
Idub @r12, r0
// Must read STCR
Idub @r12, r0
// after reading, go into standby mode
NOP
// Must insert NOP × 5
NOP
NOP
NOP
NOP
• Switching the Function of Shared Ports
Use the Port Function Register (PFR) to switch between using an external pin as a port or a shared pin. Note,
however, that bus pins are switched depending on the external bus settings.
25
MB91350A Series
• Prefetch
If prefetch is enabled in a area that is configured as little endian, limit access to the corresponding area to
word-length (32-bit) access.
Byte or halfword does not allow a proper access to data.
• I/O Port Access
Ports can only be accessed in bytes.
• Built-in RAM
Immediately after a reset is released, the internal RAM capacity restriction function begins operating, allowing
only 4 Kbytes to be used for both data and program execution irrespective of the on-chip RAM capacity.
Update the setting to clear the restriction function.
At least one NOP instruction is required immediately after updating this setting.
Please refer to the “MB91350A Series HARDWARE MANUAL CHAPTER 19 DATA INTERNAL RAM/INSTRUCTION INTERNAL RAM ACCESS RESTRICTION FUNCTIONS” for the details.
• Flash Memory
In programming mode, Flash memory cannot be used for the interrupt vector table (However, a reset can be
performed) .
• Notes on the PS Register
As the PS register is processed in advance by some instructions, when the debugger is being used, the following
exception handling may result in execution breaking in an interrupt handling routine or the displayed values of
the flags in the PS register being updated.
As the microcontroller is designed to carry out reprocessing correctly upon returning from such an EIT event,
the operation before and after the EIT always proceeds according to specification.
1. The following behavior may occur if any of the following occurs in the instruction immediately after a DIVOU/
DIVOS instruction :
(a) a user interrupt or NMI is accepted; (b) single-step execution is performed; or (c) execution breaks due
to a data event or from the emulator menu.
• The D0 and D1 flags are updated in advance.
• An EIT handling routine (user interrupt, NMI, or emulator) is executed.
• Upon returning from the EIT, the DIVOU/DIVOS instruction is executed and the D0 and D1 flags are
updated to the same values as in (1).
2. The following behavior occurs when an ORCCR, STILM, MOV Ri or PS instruction is executed to enable a
user interrupt or NMI source while that interrupt is in the active state.
• The PS register is updated in advance.
• The EIT handling routine (user interrupt, NMI, or emulator) is executed.
• Upon returning from the EIT, the above instructions are executed and the PS register is updated to the
same value as in (1).
26
MB91350A Series
[Note on Debugger]
• Single-Step Execution of the RETI Command
If single-step execution is used in an environment where an interrupt occurs frequently, the corresponding
interrupt handling routine will be executed repeatedly to the exclusion of other processing. This will prevent the
main routine and the handlers for low priority level interrupts from being executed (For example, if the time-base
timer interrupt is enabled, stepping over the RETI instruction will always break on the first line of the time-base
timer interrupt handler) .
Disable the corresponding interrupt when the corresponding interrupt handling routine no longer needs debugging.
• Break Function
If the range of addresses that cause a hardware break (including event breaks) is set to the address of the
current system stack pointer or to an area that contains the stack pointer, execution will break after each
instruction regardless of whether the user program actually contains data access instructions.
To prevent this, do not set (word) access to the area containing the address of the system stack pointer as the
target of the hardware break (including event breaks).
• Internal ROM area
Do not set DMAC transfer destination to an address in the internal ROM area.
• Simultaneous Occurrence of a Software Break (INTE instruction) and a User Interrupt/NMI
When a software break and a user interrupt/NMI occur simultaneously, the emulator debugger may react as
follows.
• The debugger stops pointing to a location other than a programmed breakpoint.
• The program does not resume execution correctly after breaking.
If this symptom occurs, use a hardware break in place of the software break. When using a monitor debugger,
do not set a break at the relevant location.
• A malfunction may occur if the stack pointer is in an area that is configured for DSU operand break. Do not
set a data event breaks that apply to accesses to an area that contains the address of the system stack pointer.
27
MB91350A Series
■ BLOCK DIAGRAMS
• MB91F353A/353A/352A/351A
FR CPU
32
32
DMAC 5 channels
Bit search
RAM
16 Kbytes(stack)*
A20 to A00
D31 to D16
Bus
Converter
ROM 512 Kbytes*
RAM 8 Kbytes
32
32
External memory
I/F
X0, X1
MD0 to MD2
INIT
X0A, X1A
Clock
control
32↔16
Adapter
Clock timer
Interrupt
Controller
SI0 to SI3
SO0 to SO3
SCK0 to SCK3
3 channels
PPG
8 channels
External interrupt
PORT
TRG0 to TRG4
PPG0, PPG2, PPG4
4 channels
Reload timer
4 channels
UART
Free-run timer
4 channels
U-timer
SI6, SI7
SO6, SO7
SCK6, SCK7
2 channels
SIO
AN0 to AN7
ATG
AVRH, AVCC
AVSS/AVRL
8 channels
A/D converter
DA0, DA1
DAVC, DAVS
2 channels
D/A converter
4 channels
Input capture
2 channels
Output compare
FRCK
IN0 to IN3
OC0, OC2
1 channel
I2C
SDA
SCL
1 channel
8-bit up/down counter
AIN0
BIN0
ZIN0
* : MB91352A : RAM 8 Kbytes (stack) , ROM 384 Kbytes
MB91351A : RAM 16 Kbytes (stack) , ROM 384 Kbytes
28
RDY
BRQ
BGRNT
SYSCLK
16
PORT
INT0 to INT7
NMI
RD
WR1, WR0
MB91350A Series
• MB91F355A/F356B/F357B/355A/354A
FR CPU
32
32
DMAC 5 channels
Bit search
DREQ0 to DREQ2
DACK0 to DACK2
DEOP0/DSTP0 to DEOP2/DSTP2
IOWR
IORD
RAM (stack)
RAM
(Execute instruction)
X0, X1
MD0 to MD2
INIT
X0A, X1A
A23 to A00
D31 to D16
Bus
Converter
ROM/Flash
32
32
External memory
I/F
32 ↔ 16
Adapter
Clock
control
RDY
BRQ
BGRNT
SYSCLK
Clock timer
16
Interrupt
Controller
PORT
6 channels
PPG
INT0 to INT15
NMI
16 channels
External interrupt
SI0 to SI4
SO0 to SO4
SCK0 to SCK4
5 channels
UART
4 channels
reload timer
Free-run timer
5 channels
U-Timer
SI5 to SI7
SO5 to SO7
SCK5 to SCK7
RD
WR1, WR0
3 channels
SIO
4 channels
input capture
PORT
TRG0 to TRG5
PPG0 to PPG5
TOT0 to TOT3
FRCK
IN0 to IN3
8 channels
output compare
OC0 to OC7
AN0 to AN11
ATG
AVRH, AVCC
AVSS/AVRL
12 channels
A/D converter
DA0 to DA2
DAVC, DAVS
3 channels
D/A converter
1 channel
I2C
ROM/Flash
RAM (stack)
RAM (Execute instruction)
MB91F355A/MB91F357B
512 Kbytes (Flash)
16 Kbytes
8 Kbytes
2 channels
8/16-bit up/down
counter
MB91F356B
256 Kbytes (Flash)
16 Kbytes
8 Kbytes
SDA
SCL
AIN0, AIN1
BIN0, BIN1
ZIN0, ZIN1
MB91355A
512 Kbytes
16 Kbytes
8 Kbytes
MB91354A
384 Kbytes
8 Kbytes
8 Kbytes
29
MB91350A Series
■ CPU AND CONTROL UNIT
Internal architecture
The FR family CPU is a high performance core based on a RISC architecture while incorporating advanced
instructions for embedded controller applications.
1. Features
• RISC architecture
Basic instructions : Executed at 1 instruction per cycle
• 32-bit architecture
General-purpose registers : 32-bit × 16 registers
• 4GB linear memory space
• Built-in multiplier
32-bit × 32-bit multiplication : 5 cycles
16-bit × 16-bit multiplication : 3 cycles
• Enhanced interrupt handling
Fast response speed (6 cycles)
Multiple interrupts supported
Level masking (16 levels)
• Enhanced I/O manipulation instructions
Memory-to-memory transfer instructions
Bit manipulation instructions
• High code efficiency
Basic instruction word length : 16-bit
• Low-power consumption
Sleep mode and stop mode
• Gear function
30
MB91350A Series
2. Internal architecture
The FR-family CPU has a Harvard architecture in which the instruction and data buses are separated. A
32-bit ↔ 16-bit bus converter is connected to the 32-bit bus (F-bus), providing an interface between the CPU
and peripheral resources. A Harvard ↔ Princeton bus converter is connected to both the I-bus and D-bus,
providing an interface between the CPU and the bus controller.
FR CPU
D-bus
I-bus
32
I address
32
External address
24
32
External data
16
Harvard
I data
D address
Data
RAM
D data
32
Address
32
Data
32
32-bit
16-bit
bus converter
Princeton
bus
converter
16
R-bus
Peripheral resources
F-bus
Internal I/O
bus controller
31
MB91350A Series
3. Programming model
• Basic programming model
32-bit
[Initial Value]
R0
XXXX XXXXH
R1
GENERAL
PURPOSE
REGISTERS
R12
R13
AC
R14
FP
XXXX XXXXH
R15
SP
0000 0000 H
Program counter
PC
Program status
PS
Table base register
TBR
Return pointer
RP
System stack pointer
SSP
User stack pointer
USP
Multiplication and division MDH
result registers
MDL
32
⎯
ILM
⎯
SCR
CCR
MB91350A Series
4. Registers
• General purpose registers
32-bit
[Initial Value]
R0
XXXX XXXXH
R1
R12
R13
AC
R14
FP
XXXX XXXXH
R15
SP
0000 0000 H
Registers R0 to R15 are general-purpose registers. The registers are used as the accumulator and memory
access pointers for CPU operations.
Of these 16 registers, the registers listed below are intended for special applications. Some instructions have
been enhanced for this purpose.
R13 : Virtual accumulator
R14 : Frame pointer
R15 : Stack pointer
The initial values of R0 to R14 after a reset are indeterminate. R15 is initialized to 00000000H (SSP value).
• PS (Program Status)
This register holds the program status and is divided into the ILM, SCR, and CCR.
The undefined bits in the following illustration are all reserved bits. Reading these bits always returns “0”. Writing
to them has no effect.
bit 31
PS
bit 20
bit 16
⎯
bit 10 bit 8 bit 7
bit 0
⎯
ILM
SCR
CCR
33
MB91350A Series
• CCR (Condition Code Register)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
CCR
S
I
N
Z
V
C
⎯
⎯
S
I
N
Z
V
C
Initial Value
- - 00XXXXB
: Stack flag. Cleared to “0” by a reset.
: Interrupt enable flag. Cleared to “0” by a reset.
: Negative flag. The initial value after a reset is indeterminate.
: Zero flag. The initial value after a reset is indeterminate.
: Overflow flag. The initial value after a reset is indeterminate.
: Carry flag. The initial value after a reset is indeterminate.
• SCR (System Condition Code Register)
bit 10 bit 9 bit 8
SCR
D1
D0
T
Initial Value
XX0B
Flag for stepwise division
Stores intermediate data for stepwise division operations.
Step trace trap flag
A flag specifying whether the step trace trap function is enabled or not.
The step trace trap function is used by the emulator. This function cannot be used by a user program while
using the emulator.
• ILM
bit 20 bit 19 bit 18 bit 17 bit 16
ILM ILM4 ILM3 ILM2 ILM1 ILM0
Initial Value
01111B
This register stores the interrupt level mask value. The value in the ILM register is used as the level mask.
Initialized to “15” (01111B) by a reset.
• PC (Program Counter)
bit 31
bit 0
PC
Initial Value
XXXXXXXXH
The program counter contains the address of the instruction currently being executed.
The initial value after a reset is indeterminate.
• TBR (Table Base Register)
bit 31
TBR
bit 0
Initial Value
0 0 0 FFC0 0 H
The table base register contains the start address of the vector table used for handling EIT events.
The initial value after a reset is 000FFC00H.
34
MB91350A Series
• RP (Return Pointer)
bit 31
bit 0
RP
Initial Value
XXXXXXXXH
The return pointer contains the address to which to return from a subroutine.
When the CALL instruction is executed, the value in the PC is transferred to the RP.
When the RET instruction is executed, the value in the RP is transferred to the PC.
The initial value after a reset is indeterminate.
• SSP (System Stack Pointer)
bit 31
bit 0
SSP
Initial Value
00000000H
The SSP is the system stack pointer and functions as R15 when the S flag is “0”.
The SSP can be specified explicitly.
The SSP is also used as the stack pointer that specifies the stack for saving the PS and PC when an EIT event
occurs.
The initial value after a reset is 00000000H.
• USP (User Stack Pointer)
bit 31
bit 0
USP
Initial Value
XXXXXXXXH
The USP is the user stack pointer and functions as R15 when the S flag is “1”.
The USP can be specified explicitly.
The initial value after a reset is indeterminate.
This pointer cannot be used by the RETI instruction.
• Multiply & Divide Registers
bit 31
bit 0
MDH
MDL
These registers are 32-bit wide registers that store the results of multiplication and division operations.
The initial value after a reset is indeterminate.
35
MB91350A Series
■ MODE SETTINGS
The FR family uses mode pins (MD2 to MD0) and a mode register (MODR) to set the operation mode.
1. Mode Pins
The MD2, MD1, and MD0 pins specify how the mode vector fetch is performed.
Mode Pins
Reset vector access
Mode name
area
MD2 MD1 MD0
0
0
0
internal ROM mode vector
Internal
0
0
1
external ROM mode vector
External
Remarks
The bus width is specified by the
mode register.
Values other than those listed in the table are prohibited.
2. Mode Register (MODR)
The data that is written to the mode register from the address at 000F FFF8H by the mode vector fetch is called
the mode data.
After the mode register (MODR) , has been set, the device operates according to the configured operating mode.
The mode register is set by all of the reset sources. User programs cannot write to the mode register.
Note : No data exists at the address (0000 07FFH) of the mode register in the previous FR family.
[Register description]
MODR
000F FFF8H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
0
0
0
0
0
ROMA
WTH1
WTH0
Initial Value
XXXXXXXXB
Operating mode setting bits
[bit7-bit3] Reserved bit
Always set these bits to “00000B”. Operation is not guaranteed if these bits are set to a value other than “00000B”.
[bit2] ROMA (internal ROM enable bit)
The ROMA bit is used to set whether to enable the internal F-bus RAM and F-bus ROM areas.
ROMA
Function
Remarks
0
External ROM
mode
Internal F-bus RAM is valid; the area (8 0000H to 10 0000H) of internal ROM is used
as an external area.
1
Internal ROM
mode
Internal F-bus RAM and F-bus ROM are valid.
[bit1, bit0] WTH1, WTH0 (Bus width setting bits)
Used to set the bus width to be used in external bus mode.
In external bus mode, the BW1 and BW0 bits of AMD0 (CS0 area) are set to the value of these bits.
WTH1
WTH0
function
Remarks
36
0
0
8-bit bus width
0
1
16-bit bus width
1
0
1
1
external bus mode
⎯
single chip mode
Setting prohibited
single chip mode
MB91350A Series
■ MEMORY SPACE
1. Memory space
The FR family has 4 Gbytes of logical address space (232 addresses) available to the CPU by linear access.
• Direct Addressing Areas
The following address space areas are used as I/O areas.
These areas are called direct addressing areas. The addresses of operands in these areas can be specified
directly within an instruction.
The size of the directly addressable areas depends on the size of the data being accessed as shown below.
→ Byte data access
→ Half word data access
→ Word data access
: 000H to 0FFH
: 000H to 1FFH
: 000H to 3FFH
2. Memory Map
Memory Map of MB91F355A/F353A/F357B/355A/353A
Single chip
mode
Internal ROM
external bus mode
External ROM
external bus mode
I/O
I/O
I/O
I/O
I/O
I/O
Access
disabled
Access
disabled
Access
disabled
Built-in RAM
8 Kbytes
(Execute instruction)
Built-in RAM
8 Kbytes
(Execute instruction)
Built-in RAM
8 Kbytes
(Execute instruction)
Built-in RAM
16 Kbytes (Stack)
Built-in RAM
16 Kbytes (Stack)
Built-in RAM
16 Kbytes (Stack)
Access
disabled
Access
disabled
0000 0000 H
Direct
addressing area
0000 0400 H
0001 0000 H
0003 E000 H
0004 0000 H
0004 4000 H
0005 0000 H
Access
disabled
Refer to
“■ I/O MAP”.
External area
0008 0000 H
Built-in ROM
512 Kbytes
Built-in ROM
512 Kbytes
Access
disabled
External area
External area
0010 0000 H
FFFF FFFFH
• Each mode is set depending on the mode vector fetch after INIT is negated.
• The available area of internal RAM is restricted immediately after a reset is released. At least one NOP
instruction is required immediately after overwriting the setting for the available RAM area.
37
MB91350A Series
Memory Map of MB91354A
Single chip mode
Internal ROM
external bus mode
External ROM
external bus mode
I/O
I/O
I/O
Direct
addressing area
I/O
I/O
I/O
Refer to “■ I/O MAP”.
Access
disabled
Access
disabled
Access
disabled
Built-in RAM
8 Kbytes
(Execute instruction)
Built-in RAM
8 Kbytes
(Execute instruction)
Built-in RAM
8 Kbytes
(Execute instruction)
Built-in RAM
8 Kbytes (Stack)
Built-in RAM
8 Kbytes (Stack)
Built-in RAM
8 Kbytes (Stack)
Access
disabled
Access
disabled
0000 0000 H
0000 0400 H
0001 0000 H
0003 E000 H
0004 0000 H
0004 2000 H
0005 0000 H
0008 0000 H
000A 0000 H
Access
disabled
External area
Access
disabled
Built-in ROM
384 Kbytes
Built-in ROM
384 Kbytes
Access
disabled
External area
External area
0010 0000 H
FFFF FFFFH
• Each mode is set depending on the mode vector fetch after INIT is negated.
• The available area of internal RAM is restricted immediately after a reset is released. At least one NOP
instruction is required immediately after overwriting the setting for the available RAM area.
38
MB91350A Series
Memory Map of MB91352A
Single chip
mode
Internal ROM
external bus mode
External ROM
external bus mode
0000 0000 H
I/O
I/O
I/O
Direct
addressing area
I/O
I/O
I/O
Refer to
“■ I/O MAP”.
0000 0400 H
0001 0000 H
0003 E000 H
0004 0000 H
Access
disabled
Access
disabled
Access
disabled
Built-in RAM
8 Kbytes
(Execute instruction)
Built-in RAM
8 Kbytes
(Execute instruction)
Built-in RAM
8 Kbytes
(Execute instruction)
Built-in RAM
8 Kbytes (Stack)
Built-in RAM
8 Kbytes (Stack)
Built-in RAM
8 Kbytes (Stack)
Access
disabled
Access
disabled
0004 2000 H
0005 0000 H
Access
disabled
External area
000A 0000 H
Built-in ROM
384 Kbytes
Built-in ROM
384 Kbytes
Access
disabled
External area
External area
0010 0000 H
FFFF FFFFH
• Each mode is set depending on the mode vector fetch after INIT is negated.
• The available area of internal RAM is restricted immediately after a reset is released. At least one NOP
instruction is required immediately after overwriting the setting for the available RAM area.
39
MB91350A Series
Memory Map of MB91351A
Single chip
mode
Internal ROM
external bus mode
External ROM
external bus mode
0000 0000 H
I/O
I/O
I/O
Direct
addressing area
I/O
I/O
I/O
Refer to
“■ I/O MAP”.
0000 0400 H
0001 0000 H
0003 E000 H
0004 0000 H
Access
disabled
Access
disabled
Access
disabled
Built-in RAM
8 Kbytes
(Execute instruction)
Built-in RAM
8 Kbytes
(Execute instruction)
Built-in RAM
8 Kbytes
(Execute instruction)
Built-in RAM
16 Kbytes (Stack)
Built-in RAM
16 Kbytes (Stack)
Built-in RAM
16 Kbytes (Stack)
Access
disabled
Access
disabled
0004 4000 H
0005 0000 H
Access
disabled
External area
000A 0000 H
Built-in ROM
384 Kbytes
Built-in ROM
384 Kbytes
Access
disabled
External area
External area
0010 0000 H
FFFF FFFFH
• Each mode is set depending on the mode vector fetch after INIT is negated.
• The available area of internal RAM is restricted immediately after a reset is released. At least one NOP
instruction is required immediately after overwriting the setting for the available RAM area.
40
MB91350A Series
Memory Map of MB91F356B
Single chip mode
Internal ROM
external bus mode
External ROM
external bus mode
I/O
I/O
I/O
Direct
addressing area
I/O
I/O
I/O
Refer to “■ I/O MAP”.
Access
disabled
Access
disabled
Access
disabled
Built-in RAM
8 Kbytes
(Execute instruction)
Built-in RAM
8 Kbytes
(Execute instruction)
Built-in RAM
8 Kbytes
(Execute instruction)
Built-in RAM
16 Kbytes (Stack)
Built-in RAM
16 Kbytes (Stack)
Built-in RAM
16 Kbytes (Stack)
Access
disabled
Access
disabled
0000 0000 H
0000 0400 H
0001 0000 H
0003 E000 H
0004 0000 H
0004 4000 H
0005 0000 H
Access
disabled
0008 0000 H
000C 0000 H
0010 0000 H
External area
Access
disabled
Built-in ROM
256 Kbytes
Built-in ROM
256 Kbytes
Access
disabled
External area
External area
FFFF FFFFH
• Each mode is set depending on the mode vector fetch after INIT is negated.
• The available area of internal RAM is restricted immediately after a reset is released. At least one NOP
instruction is required immediately after overwriting the setting for the available RAM area.
41
MB91350A Series
■ I/O MAP
This shows the locations of each of the registers for the peripheral resources in memory space.
[How to read the table]
Address
000000H
Register
+0
+1
+2
+3
PDR0 [R/W] B PDR1 [R/W] B PDR2 [R/W] B PDR3 [R/W] B
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
Block diagram
T-unit
Port Data Register
Read/write attribute, Access unit
(B : Byte, H : Half Word, W : Word)
Initial value after a reset
Register name (First-column register at address 4n; second-column register at
address 4n + 2)
Location of left-most register (When using word access, the register
in column 1 is the MSB side of the data.)
Note : Initial values of register bits are represented as follows :
“1” : Initial value is “1”.
“0” : Initial value is “0”.
“X” : Initial value is “X”.
“−” : No physical register at this location
42
MB91350A Series
Address
Register
Block
+0
+1
+2
+3
000000H
⎯⎯⎯⎯
⎯⎯⎯⎯
PDR2[R/W]B
XXXXXXXX
PDR3[R/W]B
XXXXXXXX
000004H
PDR4[R/W]B
XXXXXXXX
PDR5[R/W]B
XXXXXXXX
PDR6[R/W]B
XXXXXXXX
⎯⎯⎯⎯
000008H
PDR8[R/W]B
--XXXXXX
PDR9[R/W]B
---XXXXX
PDRA[R/W]B
----XXXX
PDRB[R/W]B*3
XXXXXXXX
00000CH
PDRC[R/W]B*3
-----XXX
000010H
PDRG[R/W]B*3
--XXXXXX
PDRH[R/W]B
--XXXXXX
PDRI[R/W]B
--XXXXXX
PDRJ[R/W]B*3
XXXXXXXX
000014H
PDRK[R/W]B
XXXXXXXX
PDRL[R/W]B
------XX
PDRM[R/W]B
--XXXXXX
PDRN[R/W]B
--XXXXXX
000018H
PDRO[R/W]B
XXXXXXXX
PDRP[R/W]B*3
----XXXX
⎯⎯⎯⎯
⎯⎯⎯⎯
⎯⎯⎯⎯
R-bus port
data
register*3
⎯⎯⎯⎯
00001CH
000020H
T-unit port
data
register*3
⎯⎯⎯⎯
⎯⎯⎯⎯
3
⎯⎯⎯⎯
⎯⎯⎯⎯
3
Reserved
3
000024H
SMCS5[R/W]B,H*
00000010_----00--
SES5[R/W]B*
------00
SDR5[R/W]B*
XXXXXXXX
SIO5*3
000028H
SMCS6[R/W]B,H
00000010_----00--
SES6[R/W]B
------00
SDR6[R/W]B
XXXXXXXX
SIO6
00002CH
SMCS7[R/W]B,H
00000010_----00--
SES7[R/W]B
------00
SDR7[R/W]B
XXXXXXXX
SIO7
000030H
⎯⎯⎯⎯
⎯⎯⎯⎯
CDCR5[R/W]B*3
0---1111
⎯⎯⎯⎯ *1
SIO
prescaler 5*3
000034H
CDCR6[R/W]B
0---1111
⎯⎯⎯⎯ *1
CDCR7[R/W]B
0---1111
⎯⎯⎯⎯ *1
SIO
prescaler 6, 7
000038H
⎯⎯⎯⎯
SRCL5[W]B*3
--------
SRCL6[W]B
--------
SRCL7[W]B
--------
SIO5 to
SIO7*3
00003CH
⎯⎯⎯⎯
⎯⎯⎯⎯
⎯⎯⎯⎯
⎯⎯⎯⎯
Reserved
000040H
EIRR0[R/W]B,H,W
00000000
ENIR0[R/W]B,H,W
00000000
ELVR0[R/W]B,H,W
00000000
External
interrupts
(INT0 to INT7)
000044H
DICR[R/W]B,H,W
-------0
HRCL[R/W]B,H,W
0--11111
⎯⎯⎯⎯
Delay
interrupt
000048H
00004CH
TMRLR[W]H,W
XXXXXXXX_XXXXXXXX
TMR[R]H,W
XXXXXXXX_XXXXXXXX
⎯⎯⎯⎯
TMCSR[R/W]B,H,W
----0000_00000000
Reload
timer 0
(Continued)
43
MB91350A Series
Address
Register
+0
+1
+2
+3
000050H
TMRLR[W]H,W
XXXXXXXX_XXXXXXXX
TMR[R]H,W
XXXXXXXX_XXXXXXXX
000054H
⎯⎯⎯⎯
TMCSR[R/W]B,H,W
----0000_00000000
000058H
TMRLR[W]H,W
XXXXXXXX_XXXXXXXX
TMR[R]H,W
XXXXXXXX_XXXXXXXX
⎯⎯⎯⎯
TMCSR[R/W]B,H,W
----0000_00000000
00005CH
000060H
000064H
000068H
00006CH
000070H
SSR[R/W]B,H,W
00001000
SIDR[R/W]B,H,W
XXXXXXXX
UTIM[R]H(UTIMR[W]H)
00000000_00000000
SSR[R/W]B,H,W
00001000
SIDR/SODR
[R/W]B,H,W
XXXXXXXX
UTIM[R]H(UTIMR[W]H)
00000000_00000000
SSR[R/W]B,H,W
00001000
SIDR[R/W]B,H,W
XXXXXXXX
000074H
UTIM[R]H(UTIMR[W]H)
00000000_00000000
000078H
ADCS2[R/W]B,H,W ADCS1[R/W]B,H,W
X000XX00
000X0000
Block
Reload
timer 1
Reload
timer 2
SCR[R/W]B,H,W
00000100
SMR[R/W]B,H,W
00--0---
UART0
DRCL[W]B
--------
UTIMC[R/W]B
0--00001
U-TIMER/
UART0
SCR[R/W]B,H,W
00000100
SMR[R/W]B,H,W
00--0---
UART1
DRCL[W]B
--------
UTIMC[R/W]B
0--00001
U-TIMER/
UART1
SCR[R/W]B,H,W
00000100
SMR[R/W]B,H,W
00--0---
UART2
DRCL[W]B
--------
UTIMC[R/W]B
0--00001
U-TIMER/
UART2
ADCT[R/W]H,W
XXXXXXXX_XXXXXXXX
00007CH
ADTH0[R]B,H,W
XXXXXXXX
ADTL0[R]B,H,W
000000XX
ADTH1[R]B,H,W
XXXXXXXX
ADTL1[R]B,H,W
000000XX
000080H
ADTH2[R]B,H,W
XXXXXXXX
ADTL2[R]B,H,W
000000XX
ADTH3[R]B,H,W
XXXXXXXX
ADTL3[R]B,H,W
000000XX
000084H
⎯⎯⎯⎯
DACR2
[R/W]B,H,W*3
-------0
DACR1[R/W]B,H,W DACR0[R/W]B,H,W
-------0
-------0
DADR1[R/W]B,H,W DADR0[R/W]B,H,W
XXXXXXXX
XXXXXXXX
A/D
converter
successive
approximations
D/A
converter*3
000088H
⎯⎯⎯⎯
DADR2
[R/W]B,H,W*3
XXXXXXXX
00008CH
⎯⎯⎯⎯
⎯⎯⎯⎯
⎯⎯⎯⎯
⎯⎯⎯⎯
Reserved
000090H
⎯⎯⎯⎯
⎯⎯⎯⎯
⎯⎯⎯⎯
⎯⎯⎯⎯ *1
Reserved
000094H
IBCR[R/W]B,H,W
00000000
IBSR[R]B,H,W
00000000
000098H
00009CH
ITMK[R/W]B,H,W
00----11_11111111
⎯⎯⎯⎯ *2
IDAR[R/W]B,H,W
00000000
ITBA[R/W]B,H,W
------00_00000000
ISMK[R/W]B,H,W
01111111
ISBA[R/W]B,H,W
-0000000
ICCR[R/W]B,H,W
0-011111
IDBL[R/W]B,H,W
-------0
I2C interface
(Continued)
44
MB91350A Series
Address
Register
+0
+1
+2
+3
0000A0H
⎯⎯⎯⎯
⎯⎯⎯⎯*1
⎯⎯⎯⎯
⎯⎯⎯⎯ *1
0000A4H
⎯⎯⎯⎯
⎯⎯⎯⎯ *1
⎯⎯⎯⎯ *1
⎯⎯⎯⎯ *1
0000A8H
TMRLR[W]H,W
XXXXXXXX_XXXXXXXX
TMR[R]H,W
XXXXXXXX_XXXXXXXX
⎯⎯⎯⎯
TMCSR[R/W]B,H,W
----0000_00000000
0000ACH
0000B0H
RCR1[W]B,H,W*3
00000000
RCR0[W]B,H,W
00000000
0000B4H
CCRH0[R/W]B,H,W
00000000
CCRL0[R/W]B,H,W
00001000
0000B8H
CCRH1[R/W]B,H,W*3 CCRL1[R/W]B,H,W*3
00000000
00001000
UDCR1[R]B,H,W*3
00000000
UDCR0[R]B,H,W
00000000
⎯⎯⎯⎯
CSR0[R/W]B,H,W
00000000
⎯⎯⎯⎯
CSR1[R/W]B,H,W*3
00000000
Block
Reserved
Reload
timer 3
8/16-bit
Up/Down
counter
0, 1*3
0000BCH
⎯⎯⎯⎯
⎯⎯⎯⎯
⎯⎯⎯⎯
⎯⎯⎯⎯
Reserved
0000C0H
SSR[R/W]B,H,W
00001000
SIDR[R/W]B,H,W
XXXXXXXX
SCR[R/W]B,H,W
00000100
SMR[R/W]B,H,W
00--0---
UART3
⎯⎯⎯⎯
UTIMC[R/W]B
0--00001
U-TIMER/
UART3
0000C4H
0000C8H
0000CCH
0000D0H
UTIM[R]H(UTIMR[W]H)
00000000_00000000
SSR[R/W]B,H,W*3
00001000
SIDR[R/W]B,H,W*3
XXXXXXXX
UTIM[R]H(UTIMR[W]H)*3
00000000_00000000
EIRR1[R/W]B,H,W*3
00000000
ENIR1[R/W]B,H,W*3
00000000
SCR[R/W]B,H,W*3 SMR[R/W]B,H,W*3
00000100
00--0--⎯⎯⎯⎯
UTIMC[R/W]B*3
0--00001
ELVR1[R/W]B,H,W*3
00000000
0000D4H
TCDT[R/W]H,W
00000000_00000000
0000D8H
IPCP1[R]H,W
XXXXXXXX_XXXXXXXX
IPCP0[R]H,W
XXXXXXXX_XXXXXXXX
0000DCH
IPCP3[R]H,W
XXXXXXXX_XXXXXXXX
IPCP2[R]H,W
XXXXXXXX_XXXXXXXX
0000E0H
⎯⎯⎯⎯
ICS23[R/W]B,H,W
00000000
⎯⎯⎯⎯
⎯⎯⎯⎯
TCCS[R/W]B,H,W
00000000
UART4*3
U-TIMER/
UART4*3
External
interrupts
(INT8 to
INT15)*3
16-bit
free-run
timer
16-bit input
capture
ICS01[R/W]B,H,W
00000000
(Continued)
45
MB91350A Series
Address
Register
+0
+1
+2
+3
0000E4H
OCCP1[R/W]H,W*3
XXXXXXXX_XXXXXXXX
OCCP0[R/W]H,W
XXXXXXXX_XXXXXXXX
0000E8H
OCCP3[R/W]H,W*3
XXXXXXXX_XXXXXXXX
OCCP2[R/W]H,W
XXXXXXXX_XXXXXXXX
0000ECH
OCCP5[R/W]H,W*3
XXXXXXXX_XXXXXXXX
OCCP4[R/W]H,W*3
XXXXXXXX_XXXXXXXX
0000F0H
OCCP7[R/W]H,W*3
XXXXXXXX_XXXXXXXX
OCCP6[R/W]H,W*3
XXXXXXXX_XXXXXXXX
0000F4H
OCS23[R/W]B,H,W
11101100_00001100
OCS01[R/W]B,H,W
11101100_00001100
0000F8H
OCS67[R/W]B,H,W*3
11101100_00001100
OCS45[R/W]B,H,W*3
11101100_00001100
Block
16-bit
output
compare*3
0000FCH
⎯⎯⎯⎯
⎯⎯⎯⎯
⎯⎯⎯⎯
⎯⎯⎯⎯
Reserved
000100H
to
000114H
⎯⎯⎯⎯
⎯⎯⎯⎯
⎯⎯⎯⎯
⎯⎯⎯⎯
Reserved
⎯⎯⎯⎯
GCN20[R/W]B
00000000
PPG control 0
000118H
GCN10[R/W]H
00110010_00010000
00011CH
⎯⎯⎯⎯
⎯⎯⎯⎯
000120H
PTMR0[R]H,W
11111111_11111111
PCSR0[W]H,W
XXXXXXXX_XXXXXXXX
000124H
PDUT0[W]H,W
XXXXXXXX_XXXXXXXX
000128H
PTMR1[R]H,W*3
11111111_11111111
PCSR1[W]H,W*3
XXXXXXXX_XXXXXXXX
00012CH
PDUT1[W]H,W*3
XXXXXXXX_XXXXXXXX
PCNH1[R/W]B,H,W*3 PCNL1[R/W]B,H,W*3
00000000
00000000
000130H
PTMR2[R]H,W
11111111_11111111
PCSR2[W]H,W
XXXXXXXX_XXXXXXXX
000134H
PDUT2[W]H,W
XXXXXXXX_XXXXXXXX
000138H
PTMR3[R]H,W*3
11111111_11111111
PCSR3[W]H,W*3
XXXXXXXX_XXXXXXXX
00013CH
PDUT3[W]H,W*3
XXXXXXXX_XXXXXXXX
PCNH3[R/W]B,H,W*3 PCNL3[R/W]B,H,W*3
00000000
00000000
000140H
PTMR4[R]H,W
11111111_11111111
PCSR4[W]H,W
XXXXXXXX_XXXXXXXX
000144H
PDUT4[W]H,W
XXXXXXXX_XXXXXXXX
PCNH0[R/W]B,H,W
00000000
PCNH2[R/W]B,H,W
00000000
PCNH4[R/W]B,H,W
00000000
PCNL0[R/W]B,H,W
00000000
PCNL2[R/W]B,H,W
00000000
PCNL4[R/W]B,H,W
00000000
Reserved
PPG0
PPG1*3
PPG2
PPG3*3
PPG4
(Continued)
46
MB91350A Series
Address
Register
+0
+1
000148H
PTMR5[R]H,W*3
11111111_11111111
00014CH
PDUT5[W]H,W*3
XXXXXXXX_XXXXXXXX
+2
+3
Block
PCSR5[W]H,W*3
XXXXXXXX_XXXXXXXX
PCNH5[R/
W]B,H,W*3
00000000
PCNL5[R/
W]B,H,W*3
00000000
PPG5*3
000150H
to
0001FCH
⎯⎯⎯⎯
000200H
DMACA0[R/W]B,H,W *4
00000000_0000XXXX_XXXXXXXX_XXXXXXXX
000204H
DMACB0[R/W]B,H,W
00000000_00000000_XXXXXXXX_XXXXXXXX
000208H
DMACA1[R/W]B,H,W *4
00000000_0000XXXX_XXXXXXXX_XXXXXXXX
00020CH
DMACB1[R/W]B,H,W
00000000_00000000_XXXXXXXX_XXXXXXXX
000210H
DMACA2[R/W]B,H,W *4
00000000_0000XXXX_XXXXXXXX_XXXXXXXX
000214H
DMACB2[R/W]B,H,W
00000000_00000000_XXXXXXXX_XXXXXXXX
000218H
DMACA3[R/W]B,H,W *4
00000000_0000XXXX_XXXXXXXX_XXXXXXXX
00021CH
DMACB3[R/W]B,H,W
00000000_00000000_XXXXXXXX_XXXXXXXX
000220H
DMACA4[R/W]B,H,W *4
00000000_0000XXXX_XXXXXXXX_XXXXXXXX
000224H
DMACB4[R/W]B,H,W
00000000_00000000_XXXXXXXX_XXXXXXXX
000228H
⎯⎯⎯⎯
00022CH
to
00023CH
⎯⎯⎯⎯
Reserved
000240H
DMACR[R/W]B
0XX00000_XXXXXXXX_XXXXXXXX_XXXXXXXX
DMAC
000244H
to
00027CH
⎯⎯⎯⎯
Reserved
000280H
FRLR[R/W]B,H,W*2
------01
⎯⎯⎯⎯
Reserved
⎯⎯⎯⎯
DMAC
⎯⎯⎯⎯
Limit on
F-bus RAM
capacity
(Continued)
47
MB91350A Series
Address
Register
+0
+1
000284H
to
00038CH
000390H
+2
+3
⎯⎯⎯⎯
DRLR[R/W]B,H,W*2
------01
⎯⎯⎯⎯
Reserved
⎯⎯⎯⎯
⎯⎯⎯⎯
000394H
to
0003ECH
⎯⎯⎯⎯
0003F0H
BSD0[W]
XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX
0003F4H
BSD1[R/W]
XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX
0003F8H
BSDC[W]
XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX
0003FCH
BSRR[R]
XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX
Limit on D-bus
RAM capacity
Reserved
Bit search
module
000400H
DDRG[R/W]B*3
--000000
DDRH[R/W]B
--000000
DDRI[R/W]B
--000000
DDRJ[R/W]B*3
00000000
000404H
DDRK[R/W]B
00000000
DDRL[R/W]B
------00
DDRM[R/W]B
--000000
DDRN[R/W]B
--000000
000408H
DDRO[R/W]B
00000000
DDRP[R/W]B*3
----0000
⎯⎯⎯⎯
R-bus data
direction
register*3
⎯⎯⎯⎯
00040CH
000410H
PFRG[R/W]B*
--00-00-
000414H
000418H
3
PFRH[R/W]B
--00-00-
PFRI[R/W]B
--00-00-
⎯⎯⎯⎯
⎯⎯⎯⎯
PFRL[R/W]B
------00
PFRM[R/W]B
--00-00-
PFRN[R/W]B
--000000
PFRO[R/W]B
00000000
PFRP[R/W]B*3
----0000
3
R-bus port
function
register*3
⎯⎯⎯⎯
⎯⎯⎯⎯
00041CH
Reserved
000420H
PCRG[R/W]B*
--000000
PCRH[R/W]B
--000000
PCRI[R/W]B
--000000
⎯⎯⎯⎯
000424H
⎯⎯⎯⎯
⎯⎯⎯⎯
PCRM[R/W]B
--000000
PCRN[R/W]B
--000000
000428H
PCRO[R/W]B
00000000
PCRP[R/W]B*3
----0000
⎯⎯⎯⎯
⎯⎯⎯⎯
00042CH
to
00043CH
Block
⎯⎯⎯⎯
R-bus pull-up
control
register*3
Reserved
(Continued)
48
MB91350A Series
Address
Register
+0
+1
+2
+3
000440H
ICR00[R/W]B,H,W
---11111
ICR01[R/W]B,H,W
---11111
ICR02[R/W]B,H,W
---11111
ICR03[R/W]B,H,W
---11111
000444H
ICR04[R/W]B,H,W
---11111
ICR05[R/W]B,H,W
---11111
ICR06[R/W]B,H,W
---11111
ICR07[R/W]B,H,W
---11111
000448H
ICR08[R/W]B,H,W
---11111
ICR09[R/W]B,H,W
---11111
ICR10[R/W]B,H,W
---11111
ICR11[R/W]B,H,W
---11111
00044CH
ICR12[R/W]B,H,W
---11111
ICR13[R/W]B,H,W
---11111
ICR14[R/W]B,H,W
---11111
ICR15[R/W]B,H,W
---11111
000450H
ICR16[R/W]B,H,W
---11111
ICR17[R/W]B,H,W
---11111
ICR18[R/W]B,H,W
---11111
ICR19[R/W]B,H,W
---11111
000454H
ICR20[R/W]B,H,W
---11111
ICR21[R/W]B,H,W
---11111
ICR22[R/W]B,H,W
---11111
ICR23[R/W]B,H,W
---11111
000458H
ICR24[R/W]B,H,W
---11111
ICR25[R/W]B,H,W
---11111
ICR26[R/W]B,H,W
---11111
ICR27[R/W]B,H,W
---11111
00045CH
ICR28[R/W]B,H,W
---11111
ICR29[R/W]B,H,W
---11111
ICR30[R/W]B,H,W
---11111
ICR31[R/W]B,H,W
---11111
000460H
ICR32[R/W]B,H,W
---11111
ICR33[R/W]B,H,W
---11111
ICR34[R/W]B,H,W
---11111
ICR35[R/W]B,H,W
---11111
000464H
ICR36[R/W]B,H,W
---11111
ICR37[R/W]B,H,W
---11111
ICR38[R/W]B,H,W
---11111
ICR39[R/W]B,H,W
---11111
000468H
ICR40[R/W]B,H,W
---11111
ICR41[R/W]B,H,W
---11111
ICR42[R/W]B,H,W
---11111
ICR43[R/W]B,H,W
---11111
00046CH
ICR44[R/W]B,H,W
---11111
ICR45[R/W]B,H,W
---11111
ICR46[R/W]B,H,W
---11111
ICR47[R/W]B,H,W
---11111
000470H
to
00047CH
Block
Interrupt
controller unit
⎯⎯⎯⎯
000480H
RSRR[R/W]B,H,W
10000000
STCR[R/W]B,H,W
00110011
TBCR[R/W]B,H,W
00XXXX00
CTBR[W]B,H,W
XXXXXXXX
000484H
CLKR[R/W]B,H,W
00000000
WPR[W]B,H,W
XXXXXXXX
DIVR0[R/W]B,H,W
00000011
DIVR1[R/W]B,H,W
00000000
OSCCR[R/W]B
XXXXXXX0
⎯⎯⎯⎯
⎯⎯⎯⎯
⎯⎯⎯⎯
Clock timer
000488H
⎯⎯⎯⎯
Clock control
unit
00048CH
WPCR[R/W]B
00---000
000490H
OSCR[R/W]B
00---000
⎯⎯⎯⎯
⎯⎯⎯⎯
⎯⎯⎯⎯
Main clock
oscillation
stabilization
wait timer
000494H
RSTOP0[W]B
00000000
RSTOP1[W]B
00000000
RSTOP2[W]B
00000000
RSTOP3[W]B
-----000
Peripheral
stop control
⎯⎯⎯⎯
(Continued)
49
MB91350A Series
Address
000498H
Register
+0
+1
+2
+3
⎯⎯⎯⎯
⎯⎯⎯⎯
⎯⎯⎯⎯
⎯⎯⎯⎯
00049CH
to
0005FCH
⎯⎯⎯⎯
Reserved
Reserved
000600H
⎯⎯⎯⎯
⎯⎯⎯⎯
DDR2[R/W]B
00000000
DDR3[R/W]B
00000000
000604H
DDR4[R/W]B
00000000
DDR5[R/W]B
00000000
DDR6[R/W]B
00000000
⎯⎯⎯⎯
000608H
DDR8[R/W]B
--000000
DDR9[R/W]B
---00000
DDRA[R/W]B
----0000
DDRB[R/W]B*3
00000000
00060CH
DDRC[R/W]B*3
-----000
000610H
⎯⎯⎯⎯
⎯⎯⎯⎯
⎯⎯⎯⎯
⎯⎯⎯⎯
000614H
⎯⎯⎯⎯
⎯⎯⎯⎯
PFR6[R/W]B
11111111
⎯⎯⎯⎯
000618H
PFR8[R/W]B
--1--0--
PFR9[R/W]B
---010-1
PFRA[R/W]B
----1111
PFRB1[R/W]B*3
00000000
00061CH
PFRB2[R/W]B*3
00----00
PFRC[R/W]B*3
---00000
⎯⎯⎯⎯
⎯⎯⎯⎯
000620H
⎯⎯⎯⎯
⎯⎯⎯⎯
PCR2[R/W]B
00000000
PCR3[R/W]B
00000000
000624H
PCR4[R/W]B
00000000
PCR5[R/W]B
00000000
PCR6[R/W]B
00000000
⎯⎯⎯⎯
000628H
PCR8[R/W]B
--000000
PCR9[R/W]B
00000000
PCRA[R/W]B
00000000
PCRB[R/W]B*3
00000000
00062CH
PCRC[R/W]B*3
-----000
⎯⎯⎯⎯
⎯⎯⎯⎯
⎯⎯⎯⎯
000630H
to
00063CH
Block
T-unit data
direction
register*3
⎯⎯⎯⎯
________
T-unit port
function
register*3
T-unit pull-up
control
register*3
Reserved
(Continued)
50
MB91350A Series
Address
Register
+0
+1
+2
+3
000640H
ASR0[R/W]H,W
00000000_00000000
ACR0[R/W]B,H,W
1111XX00_00000000
000644H
ASR1[R/W]H,W
00000000_00000000
ACR1[R/W]B,H,W
XXXXXXXX_XXXXXXXX
000648H
ASR2[R/W]H,W
00000000_00000000
ACR2[R/W]B,H,W
XXXXXXXX_XXXXXXXX
00064CH
ASR3[R/W]H,W
00000000_00000000
ACR3[R/W]B,H,W
XXXXXXXX_XXXXXXXX
000650H
ASR4[R/W]H,W
00000000_00000000
ACR4[R/W]B,H,W
XXXXXXXX_XXXXXXXX
000654H
ASR5[R/W]H,W
00000000_00000000
ACR5[R/W]B,H,W
XXXXXXXX_XXXXXXXX
000658H
ASR6[R/W]H,W
00000000_00000000
ACR6[R/W]B,H,W
XXXXXXXX_XXXXXXXX
00065CH
ASR7[R/W]H,W
00000000_00000000
ACR7[R/W]B,H,W
XXXXXXXX_XXXXXXXX
000660H
AWR0[R/W]B,H,W
01111111_11111111
AWR1[R/W]B,H,W
XXXXXXXX_XXXXXXXX
000664H
AWR2[R/W]B,H,W
XXXXXXXX_XXXXXXXX
AWR3[R/W]B,H,W
XXXXXXXX_XXXXXXXX
000668H
AWR4[R/W]B,H,W
XXXXXXXX_XXXXXXXX
AWR5[R/W]B,H,W
XXXXXXXX_XXXXXXXX
00066CH
AWR6[R/W]B,H,W
XXXXXXXX_XXXXXXXX
AWR7[R/W]B,H,W
XXXXXXXX_XXXXXXXX
000670H
⎯⎯⎯⎯
000674H
⎯⎯⎯⎯
000678H
IOWR0[R/W]B,H,W IOWR1[R/W]B,H,W IOWR2[R/W]B,H,W
XXXXXXXX
XXXXXXXX
XXXXXXXX
CSER[R/W]B,H,W
00000001
000684H
to
0007F8H
0007FCH
000800H
to
000AFCH
T-unit
⎯⎯⎯⎯
⎯⎯⎯⎯
00067CH
000680H
Block
⎯⎯⎯⎯
⎯⎯⎯⎯
TCR[W]B,H,W
0000XXXX
⎯⎯⎯⎯
⎯⎯⎯⎯
MODR[W] *5
XXXXXXXX
⎯⎯⎯⎯
Reserved
⎯⎯⎯⎯
⎯⎯⎯⎯
Mode register
Reserved
(Continued)
51
MB91350A Series
Address
Register
+0
+1
+2
+3
000B00H
ESTS0[R/W]
X0000000
ESTS1[R/W]
XXXXXXXX
ESTS2[R]
1XXXXXXX
⎯⎯⎯⎯
000B04H
ECTL0[R/W]
0X000000
ECTL1[R/W]
00000000
ECTL2[W]
000X0000
ECTL3[R/W]
00X00X11
000B08H
ECNT0[W]
XXXXXXXX
ECNT1[W]
XXXXXXXX
EUSA[W]
XXX00000
EDTC[W]
0000XXXX
000B0CH
EWPT[R]
00000000_00000000
⎯⎯⎯⎯
000B10H
EDTR0[W]
XXXXXXXX_XXXXXXXX
EDTR1[W]
XXXXXXXX_XXXXXXXX
000B14H
to
000B1CH
⎯⎯⎯⎯
000B20H
EIA0[W]
XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX
000B24H
EIA1[W]
XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX
000B28H
EIA2[W]
XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX
000B2CH
EIA3[W]
XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX
000B30H
EIA4[W]
XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX
000B34H
EIA5[W]
XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX
000B38H
EIA6[W]
XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX
000B3CH
EIA7[W]
XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX
000B40H
EDTA[R/W]
XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX
000B44H
EDTM[R/W]
XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX
000B48H
EOA0[W]
XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX
000B4CH
EOA1[W]
XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX
000B50H
EPCR[R/W]
XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX
Block
DSU
(EVA chip
only)
(Continued)
52
MB91350A Series
Address
Register
+0
+1
+2
+3
Block
000B54H
EPSR[R/W]
XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX
000B58H
EIAM0[W]
XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX
000B5CH
EIAM1[W]
XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX
000B60H
EOAM0/EODM0[W]
XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX
000B64H
EOAM1/EODM1[W]
XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX
000B68H
EOD0[W]
XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX
000B6CH
EOD1[W]
XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX
000B70H
to
000BFCH
⎯⎯⎯⎯
Reserved
000C00H
Test register (access is not allowed.)
Interrupt
controller unit
000C04H
to
000C14H
Test register (access is not allowed.)
R-bus test
000C18H
to
000FFCH
⎯⎯⎯⎯
Reserved
001000H
DMASA0[R/W]W
XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX
001004H
DMADA0[R/W]W
XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX
001008H
DMASA1[R/W]W
XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX
00100CH
DMADA1[R/W]W
XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX
001010H
DMASA2[R/W]W
XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX
001014H
DMADA2[R/W]W
XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX
001018H
DMASA3[R/W]W
XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX
00101CH
DMADA3[R/W]W
XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX
DSU
(EVA chip
only)
DMAC
(Continued)
53
MB91350A Series
(Continued)
Address
Register
+0
+1
+2
001020H
DMASA4[R/W]W
XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX
001024H
DMADA4[R/W]W
XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX
001028H
to
001FFCH
⎯⎯⎯⎯
+3
DMAC
Reserved
007000H
FLCR[R/W]
0110X000
⎯⎯⎯⎯
⎯⎯⎯⎯
⎯⎯⎯⎯
007004H
FLWC[R/W]
00010011
⎯⎯⎯⎯
⎯⎯⎯⎯
⎯⎯⎯⎯
007008H
⎯⎯⎯⎯
⎯⎯⎯⎯
⎯⎯⎯⎯
⎯⎯⎯⎯
00700CH
⎯⎯⎯⎯
⎯⎯⎯⎯
⎯⎯⎯⎯
⎯⎯⎯⎯
007010H
⎯⎯⎯⎯
⎯⎯⎯⎯
⎯⎯⎯⎯
⎯⎯⎯⎯
007014H
to
0070FFH
Block
⎯⎯⎯⎯
Flash
memory
Reserved
*1 : This is a test register. Access is disabled.
*2 : The available area of internal RAM is restricted immediately after a reset is released. This setting therefore
needs to be changed before using the internal RAM.
In addition, at least one NOP instruction is required immediately after overwriting the setting for the available
RAM area.
*3 : This register does not exist on the MB91F353A/353A/352A/351A. Access is disabled.
*4 : The 16 low-order bits (DTC [15 : 0]) of DMACA0 to DMACA4 cannot be byte-accessed.
*5 : This register is accessed by the mode vector fetch. It cannot be accessed during normal operation.
54
MB91350A Series
3. Vector table
Interrupt number
Offset
TBR default
address
Resource
number
10
16
Interrupt
level
Reset
0
00
⎯
3FCH
000FFFFCH
⎯
Mode vector
1
01
⎯
3F8H
000FFFF8H
⎯
System reserved
2
02
⎯
3F4H
000FFFF4H
⎯
System reserved
3
03
⎯
3F0H
000FFFF0H
⎯
System reserved
4
04
⎯
3ECH
000FFFECH
⎯
System reserved
5
05
⎯
3E8H
000FFFE8H
⎯
System reserved
6
06
⎯
3E4H
000FFFE4H
⎯
Coprocessor absent trap
7
07
⎯
3E0H
000FFFE0H
⎯
Coprocessor error trap
8
08
⎯
3DCH
000FFFDCH
⎯
INTE instruction
9
09
⎯
3D8H
000FFFD8H
⎯
System reserved
10
0A
⎯
3D4H
000FFFD4H
⎯
System reserved
11
0B
⎯
3D0H
000FFFD0H
⎯
Step trace trap
12
0C
⎯
3CCH
000FFFCCH
⎯
NMI request (tool)
13
0D
⎯
3C8H
000FFFC8H
⎯
Undefined instruction exception
14
0E
⎯
3C4H
000FFFC4H
⎯
NMI request
15
0F
15 (FH) fixed
3C0H
000FFFC0H
⎯
External interrupt 0
16
10
ICR00
3BCH
000FFFBCH
6
External interrupt 1
17
11
ICR01
3B8H
000FFFB8H
7
External interrupt 2
18
12
ICR02
3B4H
000FFFB4H
11
External interrupt 3
19
13
ICR03
3B0H
000FFFB0H
⎯
External interrupt 4
20
14
ICR04
3ACH
000FFFACH
⎯
External interrupt 5
21
15
ICR05
3A8H
000FFFA8H
⎯
External interrupt 6
22
16
ICR06
3A4H
000FFFA4H
⎯
External interrupt 7
23
17
ICR07
3A0H
000FFFA0H
⎯
Reload timer 0
24
18
ICR08
39CH
000FFF9CH
8
Reload timer 1
25
19
ICR09
398H
000FFF98H
9
Reload timer 2
26
1A
ICR10
394H
000FFF94H
10
UART0 (Reception completed)
27
1B
ICR11
390H
000FFF90H
0
UART1 (Reception completed)
28
1C
ICR12
38CH
000FFF8CH
1
UART2 (Reception completed)
29
1D
ICR13
388H
000FFF88H
2
UART0 (Transmission completed)
30
1E
ICR14
384H
000FFF84H
3
UART1 (Transmission completed)
31
1F
ICR15
380H
000FFF80H
4
UART2 (Transmission completed)
32
20
ICR16
37CH
000FFF7CH
5
DMAC0 (end, error)
33
21
ICR17
378H
000FFF78H
⎯
DMAC1 (end, error)
34
22
ICR18
374H
000FFF74H
⎯
Interrupt source
(Continued)
55
MB91350A Series
Interrupt number
TBR default Resource
address
number
10
16
Interrupt
level
Offset
DMAC2 (end, error)
35
23
ICR19
370H
000FFF70H
⎯
DMAC3 (end, error)
36
24
ICR20
36CH
000FFF6CH
⎯
DMAC4 (end, error)
37
25
ICR21
368H
000FFF68H
⎯
A/D
38
26
ICR22
364H
000FFF64H
15
IC
39
27
ICR23
360H
000FFF60H
⎯
System reserved
40
28
ICR24
35CH
000FFF5CH
⎯
System reserved
41
29
ICR25
358H
000FFF58H
12
SIO 6
42
2A
ICR26
354H
000FFF54H
13
SIO 7
43
2B
ICR27
350H
000FFF50H
14
UART3 (Reception completed)
44
2C
ICR28
34CH
000FFF4CH
⎯
UART3 (Transmission completed)
45
2D
ICR29
348H
000FFF48H
⎯
Reload timer 3/main oscillation
stabilization wait timer
46
2E
ICR30
344H
000FFF44H
⎯
Timebase timer overflow
47
2F
ICR31
340H
000FFF40H
⎯
System reserved
48
30
ICR32
33CH
000FFF3CH
⎯
Clock counter
49
31
ICR33
338H
000FFF38H
⎯
U/D Counter 0
50
32
ICR34
334H
000FFF34H
⎯
System reserved
51
33
ICR35
330H
000FFF30H
⎯
PPG 0
52
34
ICR36
32CH
000FFF2CH
⎯
PPG 2
53
35
ICR37
328H
000FFF28H
⎯
PPG 4
54
36
ICR38
324H
000FFF24H
⎯
16-bit free-run timer
55
37
ICR39
320H
000FFF20H
⎯
ICU 0 (capture)
56
38
ICR40
31CH
000FFF1CH
⎯
ICU 1 (capture)
57
39
ICR41
318H
000FFF18H
⎯
ICU 2/3 (capture)
58
3A
ICR42
314H
000FFF14H
⎯
OCU 0 (match)
59
3B
ICR43
310H
000FFF10H
⎯
OCU 2 (match)
60
3C
ICR44
30CH
000FFF0CH
⎯
System reserved
61
3D
ICR45
308H
000FFF08H
⎯
System reserved
62
3E
ICR46
304H
000FFF04H
⎯
Interrupt delay source bit
63
3F
ICR47
300H
000FFF00H
⎯
System reserved (Used by REALOS)
64
40
⎯
2FCH
000FFEFCH
⎯
System reserved (Used by REALOS)
65
41
⎯
2F8H
000FFEF8H
⎯
System reserved
66
42
⎯
2F4H
000FFEF4H
⎯
System reserved
67
43
⎯
2F0H
000FFEF0H
⎯
System reserved
68
44
⎯
2ECH
000FFEECH
⎯
Interrupt source
2
(Continued)
56
MB91350A Series
(Continued)
Interrupt number
TBR default Resource
address
number
10
16
Interrupt
level
Offset
System reserved
69
45
⎯
2E8H
000FFEE8H
⎯
System reserved
70
46
⎯
2E4H
000FFEE4H
⎯
System reserved
71
47
⎯
2E0H
000FFEE0H
⎯
System reserved
72
48
⎯
2DCH
000FFEDCH
⎯
System reserved
73
49
⎯
2D8H
000FFED8H
⎯
System reserved
74
4A
⎯
2D4H
000FFED4H
⎯
System reserved
75
4B
⎯
2D0H
000FFED0H
⎯
System reserved
76
4C
⎯
2CCH
000FFECCH
⎯
System reserved
77
4D
⎯
2C8H
000FFEC8H
⎯
System reserved
78
4E
⎯
2C4H
000FFEC4H
⎯
System reserved
79
4F
⎯
2C0H
000FFEC0H
⎯
Used by INT instruction
80
to
255
50
to
FF
⎯
2BCH
to
000H
000FFEBCH
to
000FFC00H
⎯
Interrupt source
57
MB91350A Series
■ PERIPHERAL RESOURCES
1. Interrupt Controller
(1) Description
The interrupt controller manages interrupt reception and arbitration.
Hardware configuration
This module consists of the following components :
• ICR register
• Interrupt priority determination circuit
• Interrupt level and interrupt number (vector) generator
• HOLD request removal request generator
• Main functions
This module has the following major functions :
• Detect NMI and interrupt requests
• Prioritize interrupts (according to level and number)
• Notify interrupt level of selected interrupt request (to CPU)
• Notify interrupt number of selected interrupt request (to CPU)
• Request (to the CPU) to return from stop mode in response to an NMI or interrupt request with interrupt level
other than "11111B"
• Issue requests to the bus master to cancel HOLD requests
58
MB91350A Series
(2) Register list
Interrupt Control Register (ICR)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
ICR00
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR01
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR02
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR03
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR04
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR05
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR06
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR07
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR08
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR09
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR10
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR11
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR12
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR13
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR14
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR15
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR16
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR17
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR18
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR19
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR20
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR21
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR22
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR23
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR24
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR25
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR26
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR27
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR28
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR29
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR30
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR31
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
(Continued)
59
MB91350A Series
(Continued)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
ICR32
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR33
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR34
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR35
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR36
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR37
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR38
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR39
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR40
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR41
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR42
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR43
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR44
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR45
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR46
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
ICR47
⎯
⎯
⎯
ICR4
ICR3
ICR2
ICR1
ICR0
⎯
LVL4
LVL3
LVL2
LVL1
LVL0
Hold request cancel request register (HRCL)
HRCL
60
MHALTI
⎯
MB91350A Series
(3) Block diagram
UNMI
WAKEUP
("1" when LEVEL ≠ 11111B)
Determine order of priority
LEVEL4 to LEVEL0
5
NMI
LEVEL determination
RI00
ICR00
VECTOR
determination
6
LEVEL,
VECTOR
Generation
HLDREQ
Cancel
NMI
request
MHALTI
VCT5 to VCT0
R-bus
61
MB91350A Series
2. External Interrupt/NMI Control
(1) Description
The external interrupt control unit is the block that controls external interrupt requests input to NMI and INT0 to
INT15. The level that is detected as a request can be selected from “H”, “L”, rising edge, or falling edge (except
for NMI).
Note : The MB91F353A/353A/352A/351A does not have INT8 to INT15.
(2) Register list
External interrupt enable register (ENIR)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
EN7
EN6
EN5
EN4
EN3
EN2
EN1
EN0
External interrupt request register (EIRR)
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
ER7
ER6
ER5
ER4
ER3
ER2
ER1
ER0
Request level setting register (ELVR)
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
LB7
LA7
LB6
LA6
LB5
LA5
LB4
LA4
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
LB3
LA3
LB2
LA2
LB1
LA1
LB0
LA0
The above registers (for 8 channels) are available in 2 sets; there are a total of 16 channels.
(3) Block diagram
R-bus
8
Interrupt
request
17
8
16
62
Interrupt enable register
Gate
Request F/F
Edge detection circuit
Interrupt source register
Interrupt level setting register
17
INT0 to INT15
NMI
MB91350A Series
3. REALOS-related Hardware
REALOS-related hardware is used by the real-time OS. Therefore, it cannot be used by user programs when
REALOS is used.
• Delay interrupt module
(1) Description
The delayed interrupt module generates a task switching interrupt.
This module enables software to issue or cancel an interrupt request to the CPU.
(2) Register list
Delayed Interrupt Control Register (DICR)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
⎯
⎯
⎯
⎯
⎯
⎯
⎯
DLYI
(3) Block diagram
R-bus
DLYI
Interrupt
request
63
MB91350A Series
• Bit Search Module
(1) Description
The bit search module searches data written to an input register for “0”, “1”, or a change point and returns the
detected bit position.
(2) Register list
bit 31
bit 0
0 detection data register (BSD0)
1 detection data register (BSD1)
Data register for transition detection (BSDC)
Detection result register (BSRR)
(3) Block diagram
D-bus
Input latch
Address decoder
Input detection
mode
Creating 1 detection data
Input bit search circuit
Search results
64
MB91350A Series
4. 8/16-bit Up/Down Counter
(1) Description
This block is the up/down counter/timer consisting of six event input pins, two 8-bit up/down counter, two 8-bit
reload/compare registers, and their control circuit.
The MB91F355A/F356B/F357B/355A/354A/V350A contains 2 channels of 8-bit up/down counter in this block.
The MB91F353A/353A/352A/351A contains 1 channel of 8-bit up/down counter in this block. It is not possible
to use in 16-bit mode.
This module has the following features.
• 8-bit count register enabling counting from (0)d to (255)d
(enabling counting from (0)d to (65535)d in 16 bits × 1 operation mode)
• Four different count modes available with selectable count clocks
Count mode
Timer mode
Up/down count mode
Phase difference count mode (2 Multiplication)
Phase difference count mode (4 Multiplication)
• In timer mode, the ability to select the count clock input to use from among two internal clock circuits
Count clock
80 ns (12.5 MHz : Frequency division by 2)
(When operating at
320 ns (3.125 MHz : Frequency division by 8)
25 MHz)
• In up/down count mode, the ability to select the edge detection of the external pin input signals
Detection edge
Falling edge detection
Rising edge detection
Detection at rising edge, falling edge, or both edges
Edge detection disabled
• The phase difference count mode is suitable for counting encoders such as motor encoders, and facilitates to
count the angle of revolution and number of revolutions to a high precision by inputting the A phase, B phase,
and Z phase outputs from the encoder
• ZIN pin has two selectable functions (valid in all modes)
ZIN pin
Counter clear function
Gate function
• Compare and reload functions that can be used separately or in combination. When both functions are used
in combination, up/down counting can be performed at an arbitrary width.
Compare/reload
Compare function (output interrupt request on compare match)
function
Compare function (output interrupt request and clear counter on compare
match)
Reload function (output interrupt request and reload on underflow)
Compare/reload function
(output interrupt request and clear counter on compare match; output interrupt
request and reload on underflow)
Compare/reload disabled
• Count direction flag used to identify the preceding count direction
• Capable of independently controlling the generation of interrupts for compare match, reload (underflow),
overflow, or on count direction change
65
MB91350A Series
(2) Register list
• Up/down count register (UDCR)
Up/down count register ch.0 (UDCR0)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
D07
D06
D05
D04
D03
D02
D01
D00
Up/down count register ch.1 (UDCR1)*
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
D15
D14
D13
D12
D11
D10
D09
D08
• Reload compare register (RCR)
Reload compare register ch.0 (RCR0)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
D07
D06
D05
D04
D03
D02
D01
D00
Reload compare register ch.1 (RCR1)*
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
D15
D14
D13
D12
D11
D10
D09
D08
• Counter status register (CSR)
Counter status register ch.0, ch.1 (CSR0, CSR1*)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
CSTR
CITE
UDIE
CMPF
OVFF
UDFF
UDF1
UDF0
• Counter control register (CCRL)
Counter control register ch.0, ch.1 (CCRL0, CCRL1*)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Reserved
CTUT
UCRE
RLDE
UDCC
CGSC
CGE1
CGE0
• Counter control register (CCRH)
Counter control register ch.0 (CCRH0)
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
M16E
CDCF
CFIE
CLKS
CMS1
CMS0
CES1
CES0
• Counter control register ch.1 (CCRH1)*
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Reserved
CDCF
CFIE
CLKS
CMS1
CMS0
CES1
CES0
* : Access to the UDCR1, RCR1, CSR1, CCRL1, CCRH1 registers is prohibited on the MB91F353A/353A/
352A/351A.
66
MB91350A Series
(3) Block diagram
• 8/16-bit up/down counter (ch.0)
Data bus
CGE1
ZIN0
CGE0 CGSC
RCR0 (Reload
compare register ch.0)
CTUT
Reload
control
UCRE
RLDE
Edge/level detection
UDCC
CES1
CES0
M16E
Carry
Counter clear
UDCR0 (up/down UDCR0
counter register ch.0)
CMS1 CMS0
CMPF
UDFF
AIN0
BIN0
Up/down
count
clock
select
Count
Clock
To ch.1
UDIE
CSTR
UDF1
OVFF
UDF0
CDCF
Prescaler
CITE
CLKS
CFIE
Interrupt output
67
MB91350A Series
•8/16-bit up/down counter (ch.1)
Data bus
8 bits
CGE1
ZIN0, ZIN1
CGE0 CGSC
RCR1 (Reload
compare register ch.1)
CTUT
Reload
control
UCRE
RLDE
Edge/level detection
UDCC
Counter clear
8 bits
CES1
UDCR1 (up/down
counter register ch.1)
CES0
CMS1 CMS0
CMPF
UDFF
AIN1
BIN1
Up/down
count
clock
select
Count
Clock
UDIE
CSTR
UDF1
UDF0
CDCF
Prescaler
CITE
CLKS
CFIE
Interrupt output
68
OVFF
MB91350A Series
5. 16-bit Reload Timer
(1) Description
The 16-bit timer consists of a 16-bit down counter, 16-bit reload register, internal clock, clock generation prescaler,
and control register.
The clock source can be selected from among three internal clocks (prepared by frequency dividing the machine
clock by 2/8/32, and also by 64/128 only for ch.3) and an external event.
The interrupt can be used to initiate a DMA transfer.
The MB91F353A/353A/352A/351A does not have timer outputs (TOT0 to TOT3).
This timer has 4 built-in channels.
(2) Register list
Control status register (TMCSR)
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
⎯
⎯
Reserved
CSL2
CSL1
CSL0 Reserved Reserved
(ch.3 only)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Reserved
⎯
OUTL
RELD
INTE
UF
CNTE
TRG
16-bit timer register (TMR)
bit 15
bit 0
16-bit reload register (TMRLR)
bit 15
bit 0
69
MB91350A Series
(3) Block diagram
16-bit reload register (TMRLR)
16
7
Reload
16
16-bit timer register (TMR) UF
RELD
OUTL
Count enable
OUT
CTL.
INTE
UF
R-bus
CSL2
Clock selector
Re-trigger
CNTE
CSL1
TRG
CSL0
3
External timer output
(TOT0 to TOT3)
IN CTL.
TOE0 to TOE3
EXCK
φ
φ
φ
21 23 25
φ
φ
26 27
Prescaler
clear
(ch.3 only)
Machine clock input
Note : The MB91F353A/353A/352A/351A does not have external timer outputs (TOT0 to TOT3).
70
IRQ
MB91350A Series
6. PPG (Programmable Pulse Generator)
The PPG can efficiently output highly precise PWM wave forms.
The MB91F353A/353A/352A/351A contains 3 channels of PPG timer.
The MB91F355A/F356B/F357B/355A/354A/V350A contains 6 channels of PPG timer.
(1) Description
Each channel consists of a 16-bit down counter, 16-bit data register with cycle setting buffer, 16-bit compare
register with duty ratio setting buffer, and pin control unit.
The count clocks for the 16-bit down counter can be selected from the following 4 types : (peripheral clock φ,
φ/4, φ/16, φ/64)
The counter is initialized to "FFFFH" at a reset or counter borrow.
PPG outputs (PPG0 to PPG5) are provided for each channel.
Note : The MB91F353A/353A/352A/351A contains 3 channels of PPG outputs PPG (0, 2, 4). There is no
PPG (1, 3, 5).
(2) Register list
bit 15
bit 0
General control register 10 (GCN10)
General control register 20 (GCN20)
Timer register (PTMR0 to PTMR5)
Cycle setting register (PCSR0 to PCSR5)
Duty setting register (PDUT0)
71
MB91350A Series
(3) Block diagram (overall configuration for 1 channel)
16-bit reload timer ch.0
16-bit reload timer ch.1
General control
register 10
(resource select)
TRG input
PPG timer ch.0
PPG0
TRG input
PPG timer ch.1
PPG1
TRG input
PPG timer ch.2
PPG2
TRG input
PPG timer ch.3
PPG3
External TRG4
TRG input
PPG timer ch.4
PPG4
External TRG5
TRG input
PPG timer ch.5
PPG5
General control
register 20
4
External TRG0 to
TRG3
Note : The MB91F353A/353A/352A/351A does not have PPG1, PPG3, PPG5 and external TRG5.
72
MB91350A Series
7. U-TIMER (16-bit timer for UART baud rate generation)
(1) Description
The U-TIMER is a 16-bit timer for generating the baud rate for the UART. An arbitrary baud rate can be set
depending on the combination of the chip operating frequency and U-TIMER reload value.
The MB91F353A/353A/352A/351A contains 4 channels of this timer.
The MB91F355A/F356B/F357B/355A/354A/V350A contains 5 channels of this timer.
(2) Register list
bit 8 bit 7
bit 15
bit 0
U-TIMER register (UTIM)
Reload register (UTIMR)
U-TIMER control register (UTIMC)
(3) Block diagram
bit 15
bit 0
UTIMR (reload register)
load
bit 15
bit 0
UTIM (U-TIMER)
clock
φ
(Peripheral clock)
underflow
control
f.f.
to UART
73
MB91350A Series
8. UART
(1) Description
The UART is a serial I/O port for asynchronous (start-stop) or CLK synchronous communication. This module
has the features listed below.
The MB91F353A/353A/352A/351A contains 4 channels of UART.
The MB91F355A/F356B/F357B/355A/354A/V350A contains 5 channels of UART.
•
•
•
•
•
•
•
•
•
Full duplex double buffer
Asynchronous (start-stop synchronized) or CLK synchronized transmission
Supports multi-processor mode
Completely programmable baud rate.
Arbitrary baud rate set by built-in timer (Refer to the section for "U-timer".)
Variable baud rate can be input from an external clock.
Error detection functions(parity, framing, overrun)
Transmission signal format is NRZ
UART (ch.0 to ch.2) can start DMA transfers using interrupts (ch.3 and ch.4 cannot start DMA transfers).
Capable of clearing DMAC interrupt source by writing to DRCL register
(2) Register list
Serial input register/serial output register (SIDR/SODR)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
D7
D6
D5
D4
D3
D2
D1
D0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PE
ORE
FRE
RDRF
TDRE
BDS
RIE
TIE
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
MD1
MD0
⎯
⎯
CS0
⎯
⎯
⎯
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PEN
P
SBL
CL
A/D
REC
RXE
TXE
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Serial status register (SSR)
Serial mode register (SMR)
Serial control register (SCR)
DRCL register (DRCL)
74
MB91350A Series
(3) Block diagram
Control
signal
RX interrupt
(to CPU)
From U-TIMER
Clock
selection
circuit
External clock
SCK
SCK (clock)
Transmission clock
SI (Receive data)
Reception
clock
TX interrupt
(to CPU)
Reception control
circuit
Transmission
control circuit
Start bit
detection circuit
Transmission
start
Received bit
Counter
Transmission bit
Counter
Received parity
Counter
Transmission
parity Counter
SO (Send data)
Receive status
decision circuit
RX shifter
TX shifter
RX
complete
Start transmission
SIDR
SODR
For DMA
received error generating
signal (to DMAC)
R - bus
MD1
MD0
SMR
Register
CS0
SCR
Register
PEN
P
SBL
CL
A/D
REC
RXE
TXE
SSR
Register
PE
ORE
FRE
RDRF
TDRE
BDS
RIE
TIE
Control signal
75
MB91350A Series
9. Extended I/O serial interface (SIO)
(1) Description
This block is an 8-bit × 1 channel serial I/O interface that allows data transfer using clock synchronization.
LSB-first or MSB-first transfer mode can be selected for data transfer.
The MB91F353A/353A/352A/351A contains 2 channels of this SIO.
The MB91F355A/F356B/F357B/355A/354A/V350A contains 3 channels of this SIO.
The serial I/O interface operates in 2 modes :
• Internal shift clock mode : Data is transferred synchronized with the internal clock.
• External shift clock mode : Data is transferred synchronized with a clock supplied via the external pin (SCK).
In this mode, data can also be transferred using CPU instructions by operating the
general-purpose port that shares the external pin (SCK) .
(2) Register list
Serial mode control status register (SMCS)
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
SMD2
SMD1
SMD0
SIE
SIR
BUSY
STOP
STRT
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
⎯
⎯
⎯
⎯
MODE
BDS
⎯
⎯
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
⎯
⎯
⎯
⎯
⎯
⎯
TST1
TST0
SIO test register (SES)
SDR (Serial Data Register) (SDR)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
D7
D6
D5
D4
D3
D2
D1
D0
SIO prescaler control register (CDCR)
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
MD
⎯
⎯
⎯
DIV3
DIV2
DIV1
DIV0
DMAC interrupt source clear register (SRCL)
76
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
MB91350A Series
(3) Block diagram
Initial Value
Internal data bus
(MSB first) D0 to D7
(LSB first) D0 to D7
Select transmitting direction
SI6, SI7
Read
Write
SDR (Serial Data Register)
SO6, SO7
SCK6, SCK7
Control circuit
Shift clock counter
Internal clock
2
1
0
SMD2 SMD1 SMD0
SIE
SIR
BUSY STOP STRT MODE BDS
Interrupt
request
SCE
PFR
Register
Internal data bus
77
MB91350A Series
10. 16-bit free-run timer
(1) Description
The 16-bit free-run timer consists of a 16-bit up counter, control register, and status register. The count values
of this timer are used as the base timer for the output compare and input capture modules.
• Four count clock frequencies are available.
• An interrupt can be generated on counter overflow.
• The counter can be initialized upon a match with compare register 0 of the output compare unit, depending
on the mode.
(2) Register list
Timer data register (upper) (TCDT)
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
T15
T14
T13
T12
T11
T10
T9
T8
Timer data register (lower) (TCDT)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
T07
T06
T05
T04
T03
T02
T01
T00
Timer control status register (lower) (TCCS)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
ECLK
IVF
IVFE
STOP
MODE
CLR
CLK1
CLK0
(3) Block diagram
Interrupt
ECLK
IVF
IVFE
STOP
MODE
CLR
CLK1
CLK0
Divider
φ
FRCK
R-bus
Clock
select
Timer data register
(TCDT)
Clock
To internal circuit (T15 to T00)
Comparator
78
MB91350A Series
11. Input Capture
(1) Description
This module detects the rising or falling edge or both edges of an external input signal and then, stores the value
of the 16-bit free-run timer in a register. In addition, the module can generate an interrupt upon detection of an
edge.
The input capture module consists of input capture data registers and a control register.
Each input capture unit has a corresponding external input pin.
• The detection edge of the external input can be selected from among 3 types.
Rising edge
Falling edge
Both edges
• An interrupt can be generated upon detection of a valid edge in the external input.
(2) Register list
Input capture data register (upper) (IPCP)
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
CP15
CP14
CP13
CP12
CP11
CP10
CP09
CP08
Input capture data register (lower) (IPCP)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
CP07
CP06
CP05
CP04
CP03
CP02
CP01
CP00
Input capture control register (ICS23)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
ICP3
ICP2
ICE3
ICE2
EG31
EG30
EG21
EG20
Input capture control register (ICS01)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
ICP1
ICP0
ICE1
ICE0
EG11
EG10
EG01
EG00
79
MB91350A Series
(3) Block diagram
16-bit timer counter value
(T15 to T00)
R-bus
Input capture data register
ch.0, ch.2
16-bit timer counter value
(T15 to T00)
Input capture data register
ch.1, ch.3
IN0, IN2
Input pin
Edge
detection
EG11
EG10
EG01
EG00
EG31
EG30
EG21
EG20
IN1, IN3
Input pin
Edge
detection
ICP1
ICP0
ICE1
ICE0
ICP3
ICP2
ICE3
ICE2
Interrupt
Interrupt
80
MB91350A Series
12. Output Compare
(1) Description
The output compare module consists of a 16-bit compare register, compare output latch, and control register.
When the 16-bit free-run timer value matches the compare register value, the output level is inverted and an
interrupt is issued.
The MB91F353A/353A/352A/351A contains 2 channels of this block.
The MB91F355A/F356B/F357B/355A/354A/V350A contains 8 channels of this block.
This module has the following features.
• The output compare is able to operate independent of each of 8 compare register. There are output pins and
interrupt flags corresponding to each of the compare registers.
• A pair of compare registers can be used to control the output terminal.
The output terminal is reversed by using two compare registers.
• Capable of setting the initial value for each output pin.
• Interrupts can be generated upon a compare match.
• The ch.0 compare register is used as the compare clear register for the 16-bit free-run timer.
(2) Register list
Compare register (OCCP)
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
C15
C14
C13
C12
C11
C10
C09
C08
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
C07
C06
C05
C04
C03
C02
C01
C00
Compare register (OCCP)
Output control register (OCS01)
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
⎯
⎯
⎯
CMOD
⎯
⎯
OTD1
OTD0
Output control register (OCS23)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
ICP1
ICP0
ICE1
ICE0
⎯
⎯
CST1
CST0
81
MB91350A Series
(3) Block diagram
(Only ch.0 is used as a free-run timer
clear register.)
OTD1
OTD0
Output compare
register
Compare
output latch
R-bus
Compare circuit
Output compare
register
OTE0 and OTE7 exist in PFR0.
Compare
output latch
OTE1, OTE3,
OTE5, OTE7
Output
(ch.1, ch.3, ch.5, ch.7)
CST0
ICP1
16-bit free-run timer
Output
(ch.0, ch.2, ch.4, ch.6)
CMOD
Compare circuit
CST1
OTE0, OTE2,
OTE4, OTE6
ICP0
ICE1
ICE0
Interrupt output
Interrupt output
82
MB91350A Series
13. I2C Interface
(1) Description
The I2C interface is a serial I/O port supporting the Inter-IC bus, operating as a master/slave device on the I2C
bus. It has the following features :
• Master/slave transmission and reception
• Arbitration function
• Clock sync function
• Slave address and general call address detection function
• Transmission direction detection function
• Repeated start condition generation and detection function
• Bus error detection function
• 10-bit/7-bit slave address
• Slave address receive acknowledge control when in master mode
• Support for composite slave addresses
• Capable of interrupt when a transmission or bus error occurs
• Standard mode (Max 100 kbps)/High speed mode (Max 400 kbps) supported
83
MB91350A Series
(2) Register list
Bus control register (IBCR)
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
BER
BEIE
SCC
MSS
ACK
GCAA
INTE
INT
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
BB
RSC
AL
LRB
TRX
AAS
GCA
ADT
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
⎯
⎯
⎯
⎯
⎯
⎯
TA9
TA8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
TA7
TA6
TA5
TA4
TA3
TA2
TA1
TA0
Bus status register (IBSR)
10-bit slave address resister (ITBA)
10-bit slave address mask resister (ITMK)
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
ENTB
RAL
⎯
⎯
⎯
⎯
TM9
TM8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
TM7
TM6
TM5
TM4
TM3
TM2
TM1
TM0
7-bit slave address resister (ISBA)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
⎯
SA6
SA5
SA4
SA3
SA2
SA1
SA0
7-bit slave address mask resister (ISMK)
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
ENSB
SM6
SM5
SM4
SM3
SM2
SM1
SM0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
D7
D6
D5
D4
D3
D2
D1
D0
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
TEST
⎯
EN
CS4
CS3
CS2
CS1
CS0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
⎯
⎯
⎯
⎯
⎯
⎯
⎯
DBL
D/A data register (IDAR)
Clock control register (ICCR)
Clock disable register (IDBL)
84
MB91350A Series
(3) Block diagram
ICCR
I2C operation enable
EN
IDBL
Clock enable
DBL
CLKP
ICCR
Clock divide 2
CS4
CS3
2 3 4 5
Sync
32
CS2
CS1
Clock selector 2 (1/12)
CS0
Shift clock edge
changing timing
IBSR
BB
RSC
LRB
TRX
Bus busy
Start
Last Bit
Start stop condition
detection
Error
Sending/
receiving
First byte
ADT
AL
R- bus
Shift clock generation
Arbitration lost detection
IBCR
SCL
BER
BEIE
Interrupt request
SDA
IRQ
INTE
INT
IBCR
SCC
MSS
ACK
GCAA
End
Start
Master
ACK enable
Start stop condition
generation
GC-ACK enable
IDAR
IBSR
AAS
Slave
Global call
Slave address
compare
GCA
ISMK
ENSB
ITMK
ENTB
RAL
ITBA
ITMK
ISBA
ISMK
85
MB91350A Series
14. A/D converter
(1) Description
The A/D converter converts the analog input voltage into a digital value. It has the following features :
• Conversion time : 1.48 µs minimum per channel
• Employing serial / parallel conversion type for sample and hold circuit.
• 10-bit resolution (switchable between 8 and 10 bits)
• Programmatic selection of the analog input from among 12 channels
(The MB91F353A/353A/352A/351A are input 8 channels.)
• Conversion mode
Single conversion mode : Converts 1 selected channel a single time.
Scan conversion mode : Scanning conversion of up to 4 channels.
• Converted data is stored in a data buffer (a total of 4 data buffers) .
• An interrupt request to the CPU can be generated upon completion of A/D conversion. The interrupt can be
used to start a DMA transfer.
• The startup source can be selected from among software, external trigger (falling edge), and reload timer ch.2
(rising edge).
(2) Register list
bit 8 bit 7
bit 15
Control status register (ADCS2/ADCS1)
bit 0
ADCS2
ADCS1
Converted data register 0 (ADTH0/ADTL0)
ADTH0
ADTL0
Converted data register 1 (ADTH1/ADTL1)
ADTH1
ADTL1
Converted data register 2 (ADTH2/ADTL2)
ADTH2
ADTL2
Converted data register 3 (ADTH3/ADTL3)
ADTH3
ADTL3
Conversion time setting register (ADCT)
86
MB91350A Series
(3) Block diagram
Analog input
AVCC, AVRH, AVSS/AVRL
M
P
X
ADT0
S/H
10-bit
A/D
Convertor
M
P
X
ADT1
R-bus
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
AN10
AN11
ADT2
ADT3
Control logic
Interrupt
16-bit reload timer ch.2
External input
Note : The MB91F353A/353A/352A/351A does not have inputs AN8 to AN11.
87
MB91350A Series
15. 8-bit D/A converter
(1) Description
This block contains 3 channels of 8-bit D/A converters and D/A converter registers that can be used to control
the independent output of each channel. The block has the following features.
• Power saving function
• 3.3 V interface
Note : The MB91F353A/353A/352A/351A contains 2 channels of D/A converter.
(2) Register list
D/A data register 0 to 2 (DADR0 to DADR2)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
D/A control register 0 to 2 (DACR0 to DACR2)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
⎯
⎯
⎯
⎯
⎯
⎯
⎯
DAE
Note : The MB91F353A/353A/352A/351A does not have DADR2, DACR2.
(3) Block diagram
R-bus
D/A control
D/A
DAE0
D/A
DAE1
PD
STOP
88
D/A
DAE2
PD
STOP
PD
STOP
D/A
converter
D/A
converter
D/A
converter
D/A output 0
D/A output 1
D/A output 2
MB91350A Series
16. DMAC (DMA Controller)
(1) Description
This module provides direct memory access (DMA) transfers in the FR family devices.
The DMAC enables high speed transfers for various data without CPU intervention, thereby improving system
performance.
• Hardware configuration
The main components of this module are as follows :
• Independent DMA channels × 5 channels
• 5 channels independent access control circuits
• 32-bit address registers (Supports reloading : 2 per channel)
• 16-bit transfer count registers (Supports reloading : 1 per channel)
• 4-bit block count registers (1 per channel)
• External transfer request input pins : DREQ0, DREQ1, and DREQ2. For ch.0 to ch.2 only
Note : The MB91F353A/353A/352A/351A do not have an external interface.
• External transfer request acceptance output pins : DACK0, DACK1, and DACK2. For ch.0 to ch.2 only
Note : The MB91F353A/353A/352A/351A do not have an external interface.
• DMA end output pins : DEOP0, DEOP1, and DEOP2. For ch.0 to ch.2 only
Note : The MB91F353A/353A/352A/351A do not have an external interface.
• Fly-by transfer (memory to I/O and I/O to memory). For ch.0 to ch.2 only
Note : The MB91F353A/353A/352A/351A do not support fly-by transfer.
• 2-cycle transfer
• Main functions
This module has the following major functions for data transfer :
• Supports data transfer over multiple independent channels (5 channels)
(1) Priority order (ch.0 > ch.1 > ch.2 > ch.3 > ch.4)
(2) Order can be reversed for ch.0 and ch.1
(3) DMAC activation triggers
• External dedicated pin input (edge detection/level detection for ch.0 to ch.2 only)
Note : The MB91F353A/353A/352A/351A do not have an external interface.
• Internal peripheral request (Interrupt request sharing, including external interrupts)
• Software request (register write)
(4)Transmission mode
• Demand transfer, burst transfer, step transfer, or block transfer
• Addressing mode : 32-bit full addressing (increment, decrement, or fixed)
(address increment can be in the range - 255 to + 255)
• Data length : Byte, halfword, or word
• Single-shot or reload operation selectable
89
MB91350A Series
(2) Register Description
bit 31
ch.0 Control/status
ch.1 Control/status
ch.2 Control/status
ch.3 Control/status
Register A
(DMACA0)
Register B
(DMACB0)
Register A
(DMACA1)
Register B
(DMACB1)
Register A
(DMACA2)
Register B
(DMACB2)
Register A
Register B
ch.4 Control/status
Register A
Register B
Overall control register
ch.0 Transfer source address register
(DMACA3)
(DMACB3)
(DMACA4)
(DMACB4)
(DMACR)
(DMASA0)
(DMADA0)
ch.1 Transfer source address register
(DMASA1)
(DMADA1)
ch.2 Transfer source address register
(DMASA2)
(DMADA2)
ch.3 Transfer source address register
(DMASA3)
(DMADA3)
ch.4 Transfer source address register
(DMASA4)
(DMADA4)
90
bit 0
MB91350A Series
(3) Block diagram
Counter
DMA transfer request
to bus controller
Selector
Write
back
Buffer
DTC two-stage register DTCR
DMA start
source select
circuit &
request
acceptance
control
Peripheral start request/
Stop input
External pin start request/
Stop input
Counter
DSS [3:0]
Selector
Counter buffer
BLK register
To interrupt controller
IRQ [4:0]
ERIR, EDIR
State
transition
circuit
Clear peripheral interrupt
DDNO register
DSAD two-stage register
MCLREQ
TYPE, MOD, WS
DMA control
SADM, SASZ [7:0] SADR
Write back
Selector
address
Counter buffer
Access
Selector
Bus control block
Selector
Read/write
control
DDNO
Address counter
To bus
controller
Bus control block
Read
Write
Priority circuit
X-bus
Buffer
DDAD two-stage register
DADM, DASZ [7:0] DADR
Write back
5-channel DMAC block diagram
91
MB91350A Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Rating
Parameter
Symbol
Rating
Unit
Remarks
Min
Max
VCC
VSS − 0.5
VSS + 4.0
V
*2
DAVC
VSS − 0.5
VSS + 4.0
V
*3
Analog power supply voltage*1
AVCC
VSS − 0.5
VSS + 4.0
V
*3
Analog reference voltage*1
AVRH
VSS − 0.5
VSS + 4.0
V
*3
VI
VSS − 0.5
VCC + 0.5
V
*8
VIND
VSS − 0.5
VSS + 5.5
V
VIA
VSS − 0.5
AVCC + 0.5
V
VO
VSS − 0.5
VCC + 0.5
V
ICLAMP
− 2.0
+ 2.0
mA
*7
Σ|ICLAMP|
⎯
20
mA
*7
“L” level maximum output current
IOL
⎯
10
mA
*4
“L” level maximum output current
(N-ch open-drain)
IOLND
⎯
20
mA
“L” level average output current
IOLAV
⎯
8
mA
“L” level average output current
(N-ch open-drain)
IOLAVND
⎯
15
mA
ΣIOL
⎯
100
mA
ΣIOLAV
⎯
50
mA
*6
IOH
⎯
− 10
mA
*4
“H” level average output current
IOHAV
⎯
−4
mA
*5
“H” level total maximum output current
ΣIOH
⎯
− 50
mA
“H” level total average output current
ΣIOHAV
⎯
− 20
mA
Power consumption
PD
⎯
850
mW
Operating temperature
Ta
− 40
+ 85
°C
TSTG
⎯
+ 125
°C
Power supply voltage*1
Analog power supply voltage*
1
Input voltage*1
1
Input voltage (N-ch open-drain) *
Analog pin input voltage*
Output voltage*
1
1
Maximum clamp current
Total maximum clamp current
“L” level total maximum output current
“L” level total average output current
“H” level maximum output current
Storage temperature
*8
*5
*6
*1 : The parameter is based on VSS = DAVS = AVSS = 0 V.
*2 : VCC must not be lower than VSS − 0.3 V.
*3 : Be careful not to exceed "VCC + 0.3 V" , for example, when the power is turned on.
*4 : The maximum output current is the peak value for a single pin.
*5 : The average output current is the average current for a single pin over a period of 100 ms.
*6 : The total average output current is the average current for all pins over a period of 100 ms.
(Continued)
92
MB91350A Series
(Continued)
*7 : • Relevant pins : Ports 2, 3, 4, 5, 6, 8, 9, A, H, I, K, M, N, O and AN (A/D input) : MB91F353A/353A/352A/351A
Ports 2, 3, 4, 5, 6, 8, 9, A, B, C, G, H, I, J, K, M, N, O, P and AN (A/D input) :
MB91F355A/F356B/F357B/355A/354A
• Use within recommended operating conditions.
• Use at DC voltage (current).
• + B signals are input signals that exceed the VCC voltage.
• A limiting resistance should always be applied to +B signals by connecting the resistance between the +B
signal and the microcontroller.
• The value of the limiting resistance should be set so that when the + B signal is applied the input current to
the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the microcontroller drive current is low, such as in low power consumption mode, the + B
input potential can increase the potential at the VCC pin via a protective diode, possibly affecting other
devices.
• Note that if a + B input is applied when the microcontroller is off (not fixed at 0 V), power is supplied
through the pin, possibly causing the microcontroller to partially operate.
• Note that if a + B input is applied when the power supply is turned on, power is supplied through the pin,
possibly resulting in a power-supply voltage at which power-on reset does not work.
• Ensure that a + B input pin does not form an open circuit.
• Note that analog I/O pins other than the A/D input pins (such as the LCD drive and comparator input pins)
cannot input + B.
• Sample recommended circuits :
• Input/output equivalent circuits
Protective diode
Vcc
P-ch
Limiting
resistance
+ B input (0 V to 16 V)
N-ch
R
*8 : VI must not exceed the rated voltage. However, If the maximum current to/from an input is limited by some
means using external components, the ICLAMP rating supersedes the VI rating.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
93
MB91350A Series
2. Recommended Operating Conditions
( Other than MB91F356B/F357B)
(VSS = DAVS = AVSS = 0 V)
Parameter
Power supply voltage
Analog power supply voltage
Analog reference voltage
Operating temperature
Symbol
Value
Unit
Remarks
3.6
V
During normal operation
3.0
3.6
V
Hold RAM status at stop
DAVC
VSS − 0.3
VSS + 3.6
AVCC
VSS − 0.3
VSS + 3.6
AVRH
AVSS
AVCC
V
Ta
− 40
+ 85
°C
Min
Max
VCC
3.0
VCC
V
(MB91F356B/F357B only)
(VSS = DAVS = AVSS = 0 V)
Parameter
Power supply voltage
Analog power supply voltage
Analog reference voltage
Operating temperature
Symbol
Value
Unit
Remarks
3.6
V
During normal operation
2.7
3.6
V
Hold RAM status at stop
VCC
3.0
3.6
V
When writing or erasing
Flash memory
DAVC
VSS − 0.3
VSS + 3.6
AVCC
VSS − 0.3
VSS + 3.6
AVRH
AVSS
AVCC
V
− 40
+ 85
°C
0
+70
°C
Min
Max
VCC
2.7
VCC
Ta
V
When writing or erasing
Flash memory*
* : Including the F355A/F353A
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
94
MB91350A Series
3. DC Characteristics
(VCC = 3.0 V to 3.6 V, VCC = 2.7 V to 3.6 V (MB91F356B/F357B only) , VSS = DAVS = AVSS = 0 V, Ta = − 40 °C to + 85 °C)
Parameter
Symbol
VIH
VIHS
“H” level
input voltage
Pin name
Conditions
Port 2, 3, 4, 5, 6,
9, A
Value
Min
Typ
Unit
MB91F355A/F356B/
F357B/355A/354A
Port 8, H, I, M,
N, O, MD0,
MD1, MD2,
INIT, NMI
Hysteresis input
MB91F353A/353A/
352A/351A
VCC + 0.3
⎯
⎯
V
VCC × 0.8
5.25
VIHST
Hysteresis input withstand voltage of 5 V
MB91F355A/F356B/
F357B/355A/354A
Port J, K, L
VILS
“L” level
input voltage
Port 2, 3, 4, 5, 6,
9, A
MB91F353A/353A/
352A/351A
VCC × 0.25
Port 2, 3, 4, 5, 6,
9, A, B, C
MB91F355A/F356B/
F357B/355A/354A
Port 8, H, I, M,
N, O, MD0,
MD1, MD2,
INIT, NMI
Port 8, G, H, I,
M, N, O, P,
MD0, MD1,
MD2, INIT, NMI
Hysteresis input
MB91F355A/F356B/
F357B/355A/354A
Hysteresis input withstand voltage of 5 V
MB91F353A/353A/
352A/351A
Port K, L
VIL
Remarks
MB91F353A/353A/
352A/351A
VCC ×
0.65
Port 2, 3, 4, 5, 6,
9, A, B, C
Port 8, G, H, I,
M, N, O, P,
MD0, MD1,
MD2, INIT, NMI
Max
Hysteresis input
MB91F353A/353A/
352A/351A
⎯
VSS
⎯
V
VCC × 0.2
Hysteresis input
MB91F355A/F356B/
F357B/355A/354A
Port K, L
Hysteresis input withstand voltage of 5 V
MB91F353A/353A/
352A/351A
Port J, K, L
Hysteresis input withstand voltage of 5 V
MB91F355A/F356B/
F357B/355A/354A
VILST
(Continued)
95
MB91350A Series
(VCC = 3.0 V to 3.6 V, VCC = 2.7 V to 3.6 V (MB91F356B/F357B only) , VSS = DAVS = AVSS = 0 V, Ta = − 40 °C to + 85 °C)
Parameter
“H” level
output
voltage
Symbol
Pin name
Conditions
Value
Min
Typ
Max
Unit
Port 2, 3, 4,
5, 6, 8, 9, A,
H, I, J, K, M,
N, O
VOH
MB91F353A/
353A/352A/351A
VCC = 3.0 V,
Port 2, 3, 4, IOH = −4.0 mA
5, 6, 8, 9, A,
B, C, G, H,
I, J, K, M, N,
O, P
VCC − 0.5
⎯
VCC
V
MB91F355A/
F356B/F357B/
355A/354A
Port 2, 3, 4,
5, 6, 8, 9, A,
H, I, K, M,
N, O
“L” level
output
voltage
VOL1
Port L
Input leak
current
(High-Z
Output
Leakage
Current)
ILI
All input pin
Pull-up
resistance
RUP
Power
supply
current
ICC
MB91F353A/
353A/352A/351A
VCC = 3.0 V,
Port 2, 3, 4, IOL = 4.0 mA
5, 6, 8, 9, A,
B, C, G, H,
I, J, K, M, N,
O, P
VOL2
VSS
⎯
0.4
V
VCC = 3.0 V,
IOL = 15.0 mA
−5
⎯
+5
µA
Setting pin
VCC = 3.6 V,
INIT,
VI = 0.45 V
Pull Up
25
50
200
kΩ
fC =
12.5 MHz,
VCC =
3.3 V
MB91F355A/
F356B/F357B/
355A/354A
N-ch
open-drain
VCC = 3.6 V,
0<VI <VCC
VCC
Remarks
Flash
160
220
MASK
125
150
⎯
mA
Flash
85
100
MASK
75
90
MB91F353A/
353A/352A/351A
Multiply by 4RUN
When operating
at
CLKB : 50 MHz
CLKT : 25 MHz
CLKP : 25 MHz
MB91F353A/
353A/352A/351A
Multiply by 2RUN
When operating
at
CLKB : 25 MHz
CLKT : 25 MHz
CLKP : 12.5 MHz
(Continued)
96
MB91350A Series
(Continued)
(VCC = 3.0 V to 3.6 V, VCC = 2.7 V to 3.6 V (MB91F356B/F357B only) , VSS = DAVS = AVSS = 0 V, Ta = − 40 °C to + 85 °C)
Parameter Symbol
Pin name
Conditions
Value
Min
Typ
Power
supply
current
100
140
MB91F353A/
353A/352A/351A
mA Multiply by 4RUN
When operating at
CLKB : 50 MHz
CLKT : 25 MHz
CLKP : 25 MHz
MB91F355A/
F356B/F357B/
355A/354A
Sleep
CLKP : When operating at 25 MHz
1
100
µA
0.3
3.0
Sub RUN
When operating at
CLKB : 32.768 kHz
CLKT : 32.768 kHz
mA CLKP : 32.768 kHz
0.2
2.0
Sub-sleep
When operating at
CLKP : 32.768 kHz
5
120
µA
5
15
pF
⎯
VCC
Ta = + 25 °C,
VCC = 3.3 V
ICCH
ICCL
Ta = + 25 °C,
fC = 32.768 kHz,
VCC = 3.3 V
ICCLS
ICCT
Input
capacitance
CIH
Other than
VCC, VSS,
AVCC, AVSS,
DAVC,
DAVS
⎯
⎯
Remarks
220
fC = 12.5 MHz,
VCC = 3.3 V
ICCS
Unit
MB91F355A/
F356B/F357B/
355A/354A
Multiply by 4RUN
When operating at
CLKB : 50 MHz
CLKT : 25 MHz
CLKP : 25 MHz
160
ICC
Max
At stop
When operating in
watch mode
(Main Off, STOP)
97
MB91350A Series
4. AC Characteristics
(1) Clock Timing
(VCC = 3.0 V to 3.6 V, VCC = 2.7 V to 3.6 V (MB91F356B/F357B only) ,
VSS = DAVS = AVSS = 0 V, Ta = − 40 °C to + 85 °C)
Parameter
Symbol
Clock
frequency
fC
Clock cycle time
tC
Clock
frequency
fC
Pin
name
X0,
X1
⎯
tCP
Internal operating
clock cycle time
When a minimum
value of 12.5 MHz is
input as the X0 clock
frequency and x4
multiplication is set
for the PLL of the
oscillator circuit
fCPP
fCPT
⎯
tCPP
tCPT
Clock
frequency
fC
Clock cycle time
tC
Input clock pulse
width
⎯
Internal operating
clock frequency
fCP,
fCPP,
fCPT
Internal operating
clock cycle time
tCP,
tCPP,
tCPT
Value
Min
Typ
X0A,
X1A
⎯
X0,
X1
PWH/tC
PWL/tC
Unit
12.5
MHz
80
100
ns
10
25
MHz
2.94*
50
25
Remarks
MAIN PLL
(When operating at max
internal frequency
(50 MHz) = 12.5 MHz
self-oscillation with ×
4 PLL)
MAIN self-oscillation
(frequency-halved input)
CPU
MHz Peripheral
External bus
20
CPU
340*
40
ns
Peripheral
External bus
30
32.768
35
kHz
28.6
30.51
33.3
µs
60
%
40
2*
When a standard
value of 32.768 kHz is
input as the X0A
clock frequency
30.51
⎯
Max
10
⎯
fCP
Internal operating
clock frequency
Conditions
⎯
SUB self-oscillation
32.768 kHz
500*
µs
* : The values assume a gear cycle of 1/16.
• Conditions for measuring the clock timing ratings
tC
0.8 VCC
0.2 VCC
PWH
98
PWL
Output pin
C = 50 pF
MB91350A Series
• Operation Guaranteed Range (Other than MB91F356B/F357B)
VCC (V)
Power supply
Operation Guaranteed Range (Ta = − 40 °C to + 85 °C)
fCPP is represented by the shaded area.
3.6
3.0
0 2.94
25
50
fCP, fCPP
(MHz)
Internal clock
• External/internal clock setting range
Oscillation input clock fC = 12.5 MHz
(MHz)
50
Internal clock
fCP
CPU (CLKB) :
Peripheral (CLKP)
External bus (CLKT) :
fCPP,
fCPT
25
12.5
4:4
2:2
1:2
CPU : Peripheral division
ratios
CPU : Peripheral division ratio
Notes : • When the PLL is used, the external clock input must fall between 10.0 MHz and 12.5 MHz.
• Set the PLL oscillation stabilization wait time longer than 454.5 µs.
• The internal clock gear setting should not exceed the relevant value in the table in “(1) Clock timing ratings”.
99
MB91350A Series
• Operation Guaranteed Range (MB91F356B/F357B only)
For Flash memory wait of 2 (FLWC register : WTC[2 : 0] = 010)
VCC (V)
Operation Guaranteed Range (Ta = − 40 °C to + 85 °C)
fCPP is represented by the shaded area.
Power supply
3.6
3.0
2.8
2.7
0 2.94
25
33
40
50
fCP, fCPP
(MHz)
Internal clock
For Flash memory wait of 3 (FLWC register : WTC[2 : 0] = 011)
VCC (V)
Operation Guaranteed Range (Ta = − 40 °C to + 85 °C)
fCPP is represented by the shaded area.
Power supply
3.6
2.7
0 2.94
25
Internal clock
100
50
fCP, fCPP
(MHz)
MB91350A Series
(2) Clock Output Timing
(VCC = 3.0 V to 3.6 V, VCC = 2.7 V to 3.6 V (MB91F356B/F357B only) ,
VSS = DAVS = AVSS = 0 V, Ta = − 40 °C + 85 °C)
Parameter
Symbol
Pin name
Cycle time
tCYC
MCLK*4
SYSCLK
SYSCLK ↑ → SYSCLK ↓
tCHCL
MCLK*4
SYSCLK
SYSCLK ↓ → SYSCLK ↑
tCLCH
MCLK*4
SYSCLK
Conditions
⎯
Value
Unit
Remarks
Min
Max
tCPT
⎯
ns
*1
tCYC − 5
tCYC + 5
ns
*2
tCYC − 5
tCYC + 5
ns
*3
*1 : tCYC is the frequency of one clock cycle after gearing.
*2 : This value is the rating when the gear ratio is set to × 1. For the ratings when the gear ratio is set to 1/2, 1/4
or 1/8, substitute 1/2, 1/4 or 1/8 for n in the following equation.
(1 / 2 × 1 / n) × tCYC − 10
*3 : This value is the rating when the gear ratio is set to × 1.
*4 : The MB91F353A/353A/352A/351A does not have MCLK pin.
In the following AC characteristics, MCLK is equal to SYSCLK.
Note : tCPT represents the internal operating clock cycle time. Refer to “(1) Clock Timing”.
tCYC
tCHCL
MCLK
SYSCLK
tCLCH
VOH
VOH
VOL
101
MB91350A Series
(3) Reset Ratings
(VCC = 3.0 V to 3.6 V, VCC = 2.7 V to 3.6 V (MB91F356B/F357B only) ,
VSS = DAVS = AVSS = 0 V, Ta = − 40 °C to + 85 °C)
Parameter
INIT input time
(at power-on)
INIT input time
(other than at power-on)
Symbol
Pin name
Conditions
Value
Min
tC × 10
tINTL
INIT
⎯
Unit
ns
⎯
tC × 10
Note : tC represents the clock cycle time. Refer to “(1) Clock Timing”.
tINTL
INIT
0.2 VCC
102
Max
ns
MB91350A Series
(4) Normal Bus Access Read/Write Operation
• MB91F353A/353A/352A/351A
(VCC = 3.0 V to 3.6 V, VSS = DAVS = AVSS = 0 V, Ta = − 40 °C to + 85 °C)
Parameter
CS0 to CS3 setup
CS0 to CS3 hold
Symbol
tCSLCH
tCSDLCH
tCHCSH
Pin name
Value
Conditions
Min
AWRxL : W02 = 0
SYSCLK,
AWR0L : W02 = 1
CS0 to CS3
3
−3
tASCH
tASWL
WR0, WR1,
A20 to A00*4
tASRL
RD,
A20 to A00*4
tCHAX
SYSCLK,
A20 to A00*4
tWHAX
WR0, WR1,
A20 to A00*4
tRHAX
RD,
A20 to A00*4
Valid address →
Valid data input time
tAVDV
A20 to A00*4,
D31 to D16
WR0, WR1 delay time
tCHWL
WR0, WR1 delay time
tCHWH
SYSCLK,
WR0, WR1
WR0, WR1 minimum
pulse width
tWLWH
WR0, WR1
tCYC − 5
Data setup → WRx ↑
tDSWH
WR0, WR1,
D31 to D16
tCYC
Address hold
WRx ↑ → Data hold time
tWHDX
RD delay time
tCHRL
RD delay time
tCHRH
RD ↓ → Valid data input
time
tRLDV
Unit
⎯
Remarks
*3
tCYC / 2 + 6
SYSCLK,
A20 to A00*4
Address setup
Max
⎯
3
tCYC / 2 + 6
⎯
3 / 2 × tCYC − 15
⎯
⎯
ns
*1
*2
6
⎯
3
SYSCLK,
RD
6
⎯
tCYC − 10
RD,
D31 to D16
Data setup → RD ↑ Time
tDSRH
RD ↑ → Data hold time
tRHDX
RD minimum pulse width
tRLRH
RD
tCYC − 5
AS setup
tASLCH
AS hold
tCHASH
SYSCLK,
AS
3
*1
10
0
⎯
tCYC / 2 + 6
*1 : When the bus timing is delayed by automatic wait insertion or RDY input, add the time (tCYC × the number of
cycles added for the delay) to this rating.
*2 : This value is the rating when the gear ratio is set to × 1. For the ratings when the gear ratio is set to between 1/2 to
1/16, substitute 1/2 to 1/16 for n in the following equation.
Calculation expression : 3/(2n) × tCYC − 15
*3 : AWRxL : Area Wait Register
*4 : The MB91F353A/353A/352A/351A does not have A23 to A21.
Note : tCYC represents the cycle time. Refer to “(2) Clock Output Timing”.
103
MB91350A Series
tCYC
BA1
SYSCLK
VOH
VOH
VOH
tASLCH
VOH
tCHASH
VOH
AS
VOL
tCSLCH
CS0 to CS3
tCHCSH
VOH
VOL
tASCH
A20 to A00
tCHAX
VOH
VOL
VOH
VOL
tCHRH
tCHRL
tRLRH
RD
VOH
VOL
tASRL
tRHAX
tRHDX
tRLDV
tDSRH
tAVDV
D31 to D16
VOH
VOL
tCHWL
VOH
VOL
tCHWH
tWLWH
VOH
WR0, WR1
tASWL
VOL
tWHAX
tDSWH
D31 to D16
104
VOH
VOL
write
tWHDX
VOH
VOL
MB91350A Series
• MB91F355A/F356B/F357B/355A/354A
Parameter
CS0 to CS3 setup
CS0 to CS3 hold
Symbol
tCSLCH
tCSDLCH
tCHCSH
tASCH
Address setup
tASWL
tASRL
tCHAX
Address hold
tWHAX
tRHAX
Valid address →
Valid data input time
WR0, WR1 delay time
WR0, WR1 delay time
WR0, WR1 minimum
pulse width
Data setup → WRx ↑
WRx ↑ → Data hold time
RD delay time
RD delay time
RD ↓ →
Valid data input time
tAVDV
(VCC = 3.0 V to 3.6 V, VCC = 2.7 V to 3.6 V (MB91F356B/F357B only) ,
VSS = DAVS = AVSS = 0 V, Ta = − 40°C to + 85°C)
Pin name
Conditions
AWRxL*3 : W02 = 0
MCLK,
AWR0L : W02 = 1
CS0 to CS3
MCLK,
A23 to A00*4
WR0, WR1,
A23 to A00*4
RD,
A23 to A00*4
MCLK,
A23 to A00*4
WR0, WR1,
A23 to A00*4
RD,
A23 to A00*4
A23 to A00*4,
D31 to D16
⎯
Value
Unit
Min
Max
3
⎯
ns
−3
⎯
ns
3
tCYC/2 + 6 ns
3
⎯
ns
3
⎯
ns
3
⎯
ns
3
tCYC/2 + 6
ns
3
⎯
ns
3
⎯
ns
⎯
⎯
3/2×
tCYC − 15
6
6
ns
ns
⎯
ns
tCHWL
tCHWH
MCLK,
WR0, WR1
tWLWH
WR0, WR1
tCYC − 5
⎯
ns
tDSWH
tWHDX
tCHRL
tCHRH
WR0, WR1,
D31 to D16
tCYC
3
⎯
⎯
⎯
⎯
6
6
ns
ns
ns
ns
⎯
tCYC − 10
ns
10
⎯
ns
15
⎯
ns
⎯
MCLK,
RD
tRLDV
Data setup → RD ↑ time
tDSRH
RD ↓ → Data hold time
RD minimum pulse width
AS setup
AS hold
tRHDX
tRLRH
tASLCH
tCHASH
3.0 V ≤ VCC ≤ 3.6 V
RD,
D31 to D16
2.7 V ≤ VCC < 3.0 V
RD
MCLK,
AS
⎯
0
⎯
tCYC − 5
⎯
3
⎯
3
tCYC/2 + 6
Remarks
*1
*2
*1
MB91F356B/
F357B only
ns
ns
ns
ns
*1 : When the bus timing is delayed by automatic wait insertion or RDY input, add the time (tCYC × the number of
cycles added for the delay) to this rating.
*2 : This value is the rating when the gear ratio is set to × 1. For the ratings when the gear ratio is set to between 1/2 to
1/16, substitute 1/2 to 1/16 for n in the following equation.
Calculation expression : 3/(2n) × tCYC − 15
*3 : AWRxL : Area Wait Register
*4 : The MB91F353A/353A/352A/351A does not have A23 to A21.
Note : tCYC represents the cycle time. Refer to “(2) Clock output timing”.
105
MB91350A Series
tCYC
BA1
MCLK
VOH
VOH
VOH
tASLCH
VOH
tCHASH
VOH
AS
VOL
tCSLCH
CS0 to CS3
tCHCSH
VOH
VOL
tASCH
A23 to A00
tCHAX
VOH
VOL
VOH
VOL
tCHRH
tCHRL
tRLRH
RD
VOH
VOL
tASRL
tRHAX
tRHDX
tRLDV
tDSRH
tAVDV
D31 to D16
VOH
VOL
tCHWL
VOH
VOL
tCHWH
tWLWH
VOH
WR0, WR1
tASWL
VOL
tWHAX
tDSWH
D31 to D16
106
VOH
VOL
write
tWHDX
VOH
VOL
MB91350A Series
(5) Multiplex Bus Access Read/Write Operation
(VCC = 3.0 V to 3.6 V, VCC = 2.7 V to 3.6 V (MB91F356B/F357B only) ,
VSS = DAVS = AVSS = 0 V, Ta = − 40 °C to + 85 °C)
Parameter
Symbol
A15 to A00 Address
AUDI setup time
→ SYSCLK ↑
tASCH
SYSCLK ↑ →
A15 to A00 Address
AUDI hold time
tCHAX
Pin name
Conditions
Value
Unit
Min
Max
3
⎯
ns
3
tCYC/2 + 6
ns
12
⎯
ns
tCYC − 3
tCYC + 3
ns
SYSCLK,
D31 to D16
⎯
A15 to A00 Address
AUDI setup time
→ AS ↑
tASASH
AS ↑ →
A15 to A0
0 Address
AUDI hold time
tASHAX
SYSCLK,
D31 to D16
Notes : •This rating is not guaranteed when the CS → RD/WR Setup Delay setting by AWR : bit1 is “0”.
• Beside this rating, normal bus interface ratings are applicable.
• tCYC represents the cycle time. Refer to “(2) Clock Output Timing”.
tCYC
BA1
SYSCLK
VOH
VOH
VOH
VOH
VOH
AS
VOL
tASASH
tASCH
D31 to D16
VOH
VOL
tASHAX
tCHAH
VOH
VOL
107
MB91350A Series
(6) Ready Input Timings
(VCC = 3.0 V to 3.6 V, VCC = 2.7 V to 3.6 V (MB91F356B/F357B only) ,
VSS = DAVS = AVSS = 0 V, Ta = − 40 °C to + 85 °C)
Parameter
Symbol
Pin name
Conditions
RDY setup time →
SYSCLK
tRDYS
SYSCLK,
RDY
SYSCLK ↑ →
RDY hold time
tRDYH
SYSCLK,
RDY
Value
Max
⎯
15
⎯
ns
⎯
0
⎯
ns
tCYC
VOH
SYSCLK
VOH
VOL
VOL
tRDYS tRDYH
tRDYS tRDYH
RDY
When WAIT is used.
VOH
VOL
VOH
VOL
RDY
When WAIT is not used.
108
VOH
VOH
VOL
Unit
Min
VOL
MB91350A Series
(7) Hold Timing
(VCC = 3.0 V to 3.6 V, VCC = 2.7 V to 3.6 V (MB91F356B/F357B only) ,
VSS = DAVS = AVSS = 0 V, Ta = − 40 °C to + 85 °C)
Parameter
Symbol
BRQ setup time →
SYSCLK ↑
tBRQS
SYSCLK ↑ →
BRQ hold time
tBRQH
BGRNT delay time
tCHBGL
BGRNT delay time
tCHBGH
Pin floating → BGRNT fall
time
tXZBGL
BGRNT ↑ →
Pin valid time
tBGHXV
Pin name
Value
Conditions
SYSCLK,
BRQ
Unit
Min
Max
15
⎯
ns
0
⎯
ns
tCYC / 2 − 6
tCYC / 2 + 6
ns
tCYC / 2 − 6
tCYC / 2 + 6
ns
tCYC − 10
tCYC + 10
ns
tCYC − 10
tCYC + 10
ns
⎯
SYSCLK,
BGRNT
⎯
BGRNT,
D31 to D16,
A23 to A00,
CS3 to CS0*
* : These only apply in the case where the SREN bit of the area select register (ACR) is set to “1”.
Notes : • It takes 1 cycle or more from when BRQ is captured until GBRNT changes.
• tCYC represents the cycle time. Refer to “(2) Clock Output Timing”.
tCYC
VOH
SYSCLK
VOH
VOH
VOH
tBRQS
tBRQH
VOL
BRQ
VOH
tCHBGH
tCHBGL
BGRNT
VOH
VOL
tXZBGL
D31 to D16,
A23 to A00,
CS3 to CS0*
tBGHXV
High-Z
* : These only apply in the case where the SREN bit of the area select register (ACR) is set to “1”.
109
MB91350A Series
(8) UART, SIO Timing
Parameter
Serial clock
Cycle time
Symbol
tSCYC
(VCC = 3.0 V to 3.6 V, VCC = 2.7 V to 3.6 V (MB91F356B/F357B only) ,
VSS = DAVS = AVSS = 0 V, Ta = − 40 °C to + 85 °C)
Value
Pin name
Conditions
Unit
Remarks
Min
Max
SCK0 to SCK3,
MB91F353A/353A/
352A/351A
SCK6, SCK7
8 tCPP
⎯
MB91F355A/F356B/
SCK0 to SCK7
F357B/355A/354A
SCK ↓ → SO
delay time
Valid SI → SCK
↑
SCK ↑ →
valid SIN hold
time
serial clock
“H” pulse width
serial clock
“L” pulse width
SCK ↓ → SO
delay time
Valid SI → SCK
↑
SCK ↑ →
valid SIN hold
time
tSLOV
tIVSH
tSHIX
tSHSL
SCK0 to SCK3,
SCK6, SCK7,
SO0 to SO3, SO6, SO7
SCK0 to SCK7,
SO0 to SO7
SCK0 to SCK3,
SCK6, SCK7,
SI0 to SI3, SI6, SI7
SCK0 to SCK7,
SI0 to SI7
SCK0 to SCK3,
SCK6, SCK7,
SI0 to SI3, SI6, SI7
SCK0 to SCK7,
SI4, SI5
SCK0 to SCK3,
SCK6, SCK7
− 80
+ 80
MB91F355A/F356B/
F357B/355A/354A
Internal
shift lock
mode
MB91F353A/353A/
352A/351A
100
MB91F355A/F356B/
F357B/355A/354A
MB91F353A/353A/
352A/351A
60
ns
4 tCPP
SCK0 to SCK3,
SCK6, SCK7
tSLOV
tIVSH
tSHIX
MB91F355A/F356B/
F357B/355A/354A
MB91F355A/F356B/
F357B/355A/354A
⎯
150
MB91F353A/353A/
352A/351A
MB91F355A/F356B/
F357B/355A/354A
External
shift clock
mode
MB91F353A/353A/
352A/351A
60
⎯
Notes : • Above rating is for CLK synchronous mode.
• tCPP represents the peripheral clock cycle time. Refer to “(1) Clock Timing”.
110
MB91F353A/353A/
352A/351A
MB91F353A/353A/
352A/351A
SCK0 to SCK7
SCK0 to SCK3,
SCK6, SCK7,
SO0 to SO3, SO6, SO7
SCK0 to SCK7,
SO0 to SO7
SCK0 to SCK3,
SCK6, SCK7,
SI0 to SI3, SI6, SI7
SCK0 to SCK7,
SI0 to SI7
SCK0 to SCK3,
SCK6, SCK7,
SI0 to SI3, SI6, SI7
SCK0 to SCK7,
SI0 to SI7
MB91F355A/F356B/
F357B/355A/354A
⎯
SCK0 to SCK7
tSLSH
MB91F353A/353A/
352A/351A
MB91F355A/F356B/
F357B/355A/354A
MB91F353A/353A/
352A/351A
MB91F355A/F356B/
F357B/355A/354A
MB91350A Series
• Internal shift clock mode
tSCYC
SCK0 to SCK7
VOH
VOL
VOL
tSLOV
VOH
VOL
SO0 to SO7
tIVSH
tSHIX
VOH
VOL
VOH
VOL
SI0 to SI7
• External shift clock mode
tSLSH
tSHSL
VOH
SCK0 to SCK7
VOL
VOL
VOL
tSLOV
SO0 to SO7
VOH
VOL
tIVSH
SI0 to SI7
VOH
VOL
tSHIX
VOH
VOL
111
MB91350A Series
(9) Free-run timer Clock, PPG Timer Input Timing
(VCC = 3.0 V to 3.6 V, VCC = 2.7 V to 3.6 V (MB91F356B/F357B only) ,
VSS = DAVS = AVSS = 0 V, Ta = − 40 °C to + 85 °C)
Parameter
Symbol
Input pulse width
tTIWH
tTIWL
Pin name
Conditions
Value
Min
Max
FRCK,
TRG0 to TRG4,
AIN0, BIN0,
ZIN0
FRCK,
TRG0 to TRG5,
AIN0, AIN1,
BIN0, BIN1,
ZIN0, ZIN1
Remarks
MB91F353A/353A/
352A/351A
⎯
2 tCPP
⎯
ns
MB91F355A/F356B/
F357B/355A/354A
Note : tCPP represents the peripheral clock cycle time. Refer to “(1) Clock Timing”.
FRCK, TRGX, AINX,
BINX, ZINX
tTIWH
112
Unit
tTIWL
MB91350A Series
(10) Trigger Input Timing
(VCC = 3.0 V to 3.6 V, VCC = 2.7 V to 3.6 V (MB91F356B/F357B only) ,
VSS = DAVS = AVSS = 0 V, Ta = − 40 °C to + 85 °C)
Parameter
A/D activation trigger input time
Input capture
input trigger
Symbol
Pin name
Conditions
tATGX
ATG
tINP
IN0 to IN3
Value
Unit
Min
Max
⎯
5 tCPP
⎯
ns
⎯
5 tCPP
⎯
ns
Note : tCPP represents the peripheral clock cycle time. Refer to “(1) Clock Timing”.
tATGX, tINP
ATG,
IN0 to IN3
113
MB91350A Series
(11)DMA controller timing*1
• For edge detection (block/step transfer mode, burst transfer mode)
(VCC = 3.0 V to 3.6 V, VCC = 2.7 V to 3.6 V (MB91F356B/F357B only) ,
VSS = DAVS = AVSS = 0 V, Ta = − 40°C to + 85°C)
Parameter
Symbol
Pin name
Conditions
tDRWL
DREQ0 to DREQ2
⎯
DREQ Input pulse width
DREQ Input pulse width
tDSWH
DSTP0 to DSTP2
Value
Unit
Min
Max
2 tCYC*2
⎯
ns
CYC*2
⎯
ns
2t
*1 : The MB91F353A/353A/352A/351A does not have this standard.
*2 : tCYC becomes tCP when fCPT is greater than fCP.
• For level detection (demand transfer mode)
(VCC = 3.0 V to 3.6 V, VCC = 2.7 V to 3.6 V (MB91F356B/F357B only) ,
VSS = DAVS = AVSS = 0 V, Ta = − 40°C to + 85°C)
Parameter
114
Symbol
Pin name
DREQ setup time
tDRS
MCLK, DREQ0 to DREQ2
DREQ hold time
tDRH
MCLK, DREQ0 to DREQ2
DSTP setup time
tDSTPS
MCLK, DSTP0 to DSTP2
DSTP hold time
tDSTPH
MCLK, DSTP0 to DSTP2
Conditions
⎯
Value
Unit
Min
Max
15
⎯
ns
0.0
⎯
ns
15
⎯
ns
0.0
⎯
ns
MB91350A Series
• Common operation mode
(VCC = 3.0 V to 3.6 V, VCC = 2.7 V to 3.6 V (MB91F356B/F357B only) ,
VSS = DAVS = AVSS = 0 V, Ta = − 40°C to + 85°C)
Parameter
Symbol Pin name
AWRxL* :
W02 = 0
tDALCH
DACK delay time
DEOP delay time
tDADLCH
MCLK,
DACK0 to
DACK2
AWR0L :
W02 = 1
tCHDAH
⎯
tDELCH
AWR0L :
W02 = 0
tDEDLCH
MCLK,
DEOP0 to
DEOP2
tCHIRL
tCHIRH
tCHIWL
AWRxL* :
W02 = 1
⎯
tCHDEH
IORD delay time
Conditions
MCLK,
IORD
Value
Unit
Max
3
⎯
ns
CS timing
⎯
6
ns
FR30 compatible
−3
⎯
ns
CS timing
⎯
6
ns
FR30 compatible
⎯
tCYC/2 + 6
ns
CS timing
⎯
6
ns
FR30 compatible
3
⎯
ns
CS timing
⎯
6
ns
FR30 compatible
−3
⎯
ns
CS timing
⎯
6
ns
FR30 compatible
⎯
tCYC/2 + 6
ns
CS timing
⎯
6
ns
FR30 compatible
⎯
6
ns
⎯
6
ns
⎯
6
ns
tCHIWH
MCLK,
IOWR
⎯
6
ns
IORD minimum pulse width
tIRLIRH
IORD
12
⎯
ns
IOWR minimum pulse width
tIWLIWH
IOWR
12
⎯
ns
IOWR delay time
⎯
Remarks
Min
* : AWRxL : Area Wait Register.
Note : tCYC represents the cycle time. Refer to “(2) Clock output timing”.
115
MB91350A Series
tCYC
VOH
MCLK
VOH
VOL
VOL
VOL
tDRWL
tDRS
tDRH
VOH
DREQ0 to DREQ2
VOL
tDSWH
tDSTPS
tDSTPH
VOH
DSTP0 to DSTP2
VOL
tCHIRL
tCHIRH
tIRLIRH
VOH
IORD
VOL
tCHIWL
tCHIWH
tIWLIWH
VOH
IOWR
VOL
RD,
WRn
VOL
Chip select
timing
DACK0 to DACK2
VOH
tDALCH
tDADLCH
tCHDAH
VOH
VOL
tDELCH
tDEDLCH
DEOP0 to DEOP2
FR30 compatible
timing
tCHDEH
VOH
VOL
tDALCH
tDADLCH
tCHDAH
VOH
DACK0 to DACK2
VOL
tDELCH
tDEDLCH
tCHDEH
VOH
DEOP0 to DEOP2
116
VOL
MB91350A Series
(12) I2C Timing
(VCC = 3.0 V to 3.6 V, VCC = 2.7 V to 3.6 V (MB91F356B/F357B only) ,
VSS = DAVS = AVSS = 0 V, Ta = − 40 °C to + 85 °C)
Parameter
Symbol
Condition
Standard-mode
Fast-mode*4
Unit
Min
Max
Min
Max
fSCL
0
100
0
400
kHz
tHDSTA
4.0
⎯
0.6
⎯
µs
“L” width of the SCL clock
tLOW
4.7
⎯
1.3
⎯
µs
“H” width of the SCL clock
tHIGH
4.0
⎯
0.6
⎯
µs
Set-up time for a repeated START condition
SCL↑→SDA↓
tSUSTA
4.7
⎯
0.6
⎯
µs
Data hold time
SCL↓→SDA↓↑
tHDDAT
0
3.45*2
0
0.9*3
µs
Data set-up time
SDA↓↑→SCL↑
tSUDAT
250
⎯
100
⎯
ns
Set-up time for STOP condition
SCL↑→SDA↑
tSUSTO
4.0
⎯
0.6
⎯
µs
tBUS
4.7
⎯
1.3
⎯
µs
SCL clock frequency
Hold time (repeated) START condition
SDA↓→SCL↓
Bus free time between a STOP and START
condition
R = 1.0 kΩ,
C = 50 pF*1
*1 : R,C : Pull-up resistance and load capacitance of the SCL and SDA lines.
*2 : The maximum tHDDAT only has to be met if the device does not extend the “L” width (tLOW) of the SCL signal.
*3 : A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement
tSUDAT ≥ 250 ns must then be met.
*4 : For use at over 100 kHz, set the machine clock to at least 6 MHz.
SDA
tHDSTA
tSUDAT
tLOW
tBUS
SCL
tHIGH
tHDSTA
tHDDAT
tSUSTA
tSUSTO
117
MB91350A Series
5. Electrical Characteristics for the A/D Converter
• MB91F353A/353A/352A/351A
(VCC = AVCC = 3.0 V to 3.6 V, AVRH = 3.0 V to 3.6 V, VSS = DAVS = AVSS = 0 V, Ta = − 40 °C to + 85 °C)
Parameter
Symbol
Pin
name
Min
Typ
⎯
Resolution
Total error *
Value
1
⎯
Nonlinear error *1
Differential linear error *1
AN7
to
AN0
Full-transition voltage *1
⎯
Conversion time
Analog power supply
current (analog + digital)
Reference power supply
current
(between AVRH and AVRL)
IA
IAH
IR
Interchannel disparity
⎯
⎯
AVRH
AN7
to
AN0
Unit
Remarks
bit
+ 5.0
+ 3.5
+ 2.5
LSB
AVRL − 2.0 AVRL + 1.0 AVRL + 6.0
At AVCC = 3.3 V,
AVRH = 3.3 V
AVRH − 5.5 AVRH + 1.5 AVRH + 3.0
1.48*2
AVCC
IRH
Analog input capacitance
− 3.5
10
− 2.5
⎯
Zero transition voltage *1
− 5.0
Max
⎯
⎯
300
µs
7
⎯
mA
⎯
5
470
⎯
⎯
10
40
⎯
pF
⎯
4
LSB
At STOP
µA
At AVRH = 3.0 V,
AVRL = 0.0 V
At STOP
*1 : Measured in the CPU sleep state
*2 : When the peripheral resource clock frequency is 25.0 MHz, set the Conversion Time Setting Register (ADCT)
to a value equal to or greater than 5334H.
Set each bit as follows :
Sampling time
: SAMP3 to SAMP0 ≥ 5H
Conversion time a : CV03 to CV0 ≥ 3H
Conversion time b : CV13 to CV0 ≥ 3H
Conversion time c : CV23 to CV0 ≥ 4H
118
MB91350A Series
• MB91F355A/F356B/F357B/355A/354A/V350A
(VCC = AVCC = 3.0 V to 3.6 V, AVRH = 3.0 V to 3.6 V, VSS = DAVS = AVSS = 0 V, Ta = − 40°C to + 85°C)
Parameter
Symbol
Pin
name
Min
Typ
⎯
Resolution
Total error*
Value
1
⎯
Nonlinear error*1
Differential linear error*1
⎯
1
Reference power supply
current
(between AVRH and AVRL)
Analog input capacitance
Interchannel disparity
IA
IAH
IR
1.48*2
AVCC
AVRH
IRH
⎯
10
⎯
− 2.5
⎯
Conversion time
Analog power supply current
(analog + digital)
− 3.5
AN11 AVRL − 2.0
to AN0 AVRH − 5.5
Zero transition voltage*1
Full-transition voltage*
− 5.0
AN11
to AN0
⎯
Max
Unit
Remarks
bit
+ 5.0
+ 3.5
+ 2.5
LSB
AVRL + 1.0
AVRL + 6.0
AVRH + 1.5
AVRH + 3.0
⎯
300
µs
8
⎯
mA
⎯
5
470
⎯
⎯
10
40
⎯
pF
⎯
4
LSB
AVCC = 3.3 V,
AVRH = 3.3 V
At stop
µA
AVRH = 3.0 V,
AVRL = 0.0 V
At stop
*1 : Measured in the CPU sleep state
*2 : When the peripheral resource clock frequency is 25.0 MHz, set the Conversion Time Setting Register (ADCT)
to a value equal to or greater than 5334H.
Set each bit as follows :
Sampling time
: SAMP3 to SAMP0 ≥ 5H
Conversion time a : CV03 to CV0 ≥ 3H
Conversion time b : CV13 to CV0 ≥ 3H
Conversion time c : CV23 to CV0 ≥ 4H
119
MB91350A Series
• About the external impedance and sampling time of the analog input
• A/D converter with sample and hold circuit. If the external impedance is too high to ensure sufficient sampling
time, the analog voltage of the internal sample and hold capacitor will not be sufficiently charged, adversely
affecting the A/D conversion precision. Therefore, to satisfy the A/D conversion precision standard, consider
the relationship between the external impedance and minimum sampling time and either adjust the resistor
value and operating frequency or decrease the external impedance so that the sampling time is longer than
the minimum value. Moreover, if sufficient sampling time cannot be ensured, connect a capacitor of about 0.1
µF to the analog input pin.
• Analog input circuit schematic
R
Analog input
Comparator
C
During sampling : ON
R
MB91355A/354A/353A/352A/351A 0.18 kΩ (Max)
MB91F355A/F353A/F356B/F357B 0.18 kΩ (Max)
C
63.0 pF (Max)
39.0 pF (Max)
Note : The values are reference values.
• The relationship between the external impedance and minimum sampling time
(External impedance = 0 kΩ to 20 kΩ)
MB91F355A/F356B/F357B/F353A
100
90
80
70
60
50
40
30
20
10
0
MB91355A/
354A/353A/
352A/351A
0
5
10
15
20
25
30
35
MB91F355A/F356B/F357B/F353A
20
External impedance [kΩ]
External impedance [kΩ]
(External impedance = 0 kΩ to 100 kΩ)
18
16
14
12
10
8
6
4
2
0
MB91355A/
354A/353A/
352A/351A
0
1
Minimum sampling time [µs]
• About errors
The smaller the value of | AVRH−AVSS | , the greater the relative error.
120
2
3
4
5
6
7
Minimum sampling time [µs]
8
MB91350A Series
Definition of A/D Converter Terms
• Resolution
Analog variation that is recognized by an A/D converter.
• Linearity error
The difference between the line connecting the zero transition point ( "00 0000 0000"←→"00 0000 0001" ) and
the full-scale transition point ( "11 1111 1110" ←→ "11 1111 1111" ) and the actual conversion characteristics.
• Differential linear error
Deviation from the ideal value of the input voltage that is required to change the output code by 1 LSB.
Linearity error
3FFH
Differential linear error
Actual conversion
characteristic
Actual conversion
characteristic
(N + 1)H
3FEH
{1 LSB' (N − 1) + VOT}
VFST
(measurement value)
VNT
004H
(measurement value)
003H
Digital output
Digital output
3FDH
Ideal characteristics
NH
V(N+1)T
(N − 1)H
Actual conversion
characteristic
002H
VNT
Ideal characteristics
(measurement value)
(N − 2)H
001H
Actual conversion
characteristic
VOT (measurement value)
AVSS
AVRH
AVSS
AVRH
Analog input
Linear error in digital output N =
Analog input
VNT − {1 LSB’ × (N − 1) + VOT}
1 LSB’
Differential linear error in digital output N =
1 LSB =
N
VFST − VOT
1022
(measurement
value)
V (N + 1) T − VNT
1 LSB’
[LSB]
− 1 [LSB]
[V]
: A/D converter digital output value
VOT : The voltage at which the digital output transitions from (000)H to (001)H
VFST : The voltage at which the digital output transitions from (3FE)H to (3FF)H
VNT : The voltage at which the digital output transitions from (N − 1)H to NH
121
MB91350A Series
• Total error
This error indicates the difference between the actual and ideal values, including the zero transition error/fullscale transition error/linearity error.
Total error
3FFH
Actual conversion
characteristic
3FEH
1.5 LSB'
Digital output
3FDH
{1 LSB' (N − 1) + 0.5 LSB'}
004H
VNT
003H
(measurement value)
Actual conversion
characteristic
002H
Ideal
characteristics
001H
0.5 LSB'
AVSS
AVRH
Analog input
1LSB’ (Ideal value) =
AVRH − AVSS
1024
Total error of digital output N =
N
[V]
VNT − {1 LSB’ × (N − 1) + 0.5 LSB’}
1 LSB’
: A/D converter digital output value
VNT : The voltage at which the digital output transitions from (N + 1)H to NH
VOT ’ (Ideal value) = AVSS + 0.5 LSB’ [V]
VFST ’ (Ideal value) = AVRH − 1.5 LSB’ [V]
122
MB91350A Series
6. Electrical Characteristics for the D/A Converter
(VCC = DAVC = 3.0 V to 3.6 V, VSS = DAVS = AVSS = 0 V, Ta = − 40 °C to + 85 °C)
Parameter
Symbol
Pin
name
Resolution
Nonlinear error
Differential linear error
⎯
Value
Min
Typ
Max
⎯
⎯
8
− 2.0
⎯
+ 2.0
− 1.0
⎯
+ 1.0
Unit
bit
LSB
0.6
Conversion speed
⎯
⎯
⎯
µs
3.0
DA0,
DA1
Output high impedance
DA0 to
DA2
2.0
⎯
Analog current
IADA
IADAH
DAVC
⎯
2.9
3.8
40
⎯
⎯
460*
0.1
⎯
Remarks
kΩ
When the output is unloaded
When the output is unloaded
When load capacitance
(CL) = 20 pF
When load capacitance
(CL) = 100 pF
MB91F353A/353A/352A/
351A
MB91F355A/F356B/F357B/
355A/354A
10 µs conversion when the
output is unloaded
µA
Input digital code, when fixed
at 7AH or 85H
At power-down
* : This D/A converter varies in current consumption depending on each input digital code.
This rating indicates the current consumption when the digital code that maximizes current consumption is input.
123
MB91350A Series
■ FLASH MEMORY ERASE and PROGRAM PERFORMANCE
Parameter
Condition
Sector erase time
Chip erase time
Ta = +25 °C
VCC = 3.3 V
Half word (16-bit width)
programming time
Value
Unit
Remarks
Min
Typ
Max
⎯
1
15
s
Excludes 00H programming
prior erasure
⎯
8
⎯
s
Excludes 00H programming
prior erasure
⎯
16
3600
µs
Excludes system-level overhead
Erase/program cycle
⎯
10000
⎯
⎯
cycle
Flash data retention
time
Average
Ta = +85 °C
20
⎯
⎯
year
*
* : This value comes from the technology qualification (using Arrhenius equation to translate high temperature
measurements into normalized value at +85 °C).
124
MB91350A Series
■ EXAMPLE CHARACTERISTICS
• MB91F353A
“H” level output voltage
“L” level output voltage
VOH vs. VCC
Ta = + 25 °C
VOL1 vs. VCC
Ta = + 25 °C
500
V OL1 [mV]
V OH [V]
4
3
2
1
0
2.7
3
3.3
3.6
400
300
200
100
0
2.7
3.9
3
3.3
“L”level output voltage (N-ch open-drain)
Input leak current
VOL2 vs. VCC
Ta = + 25 °C
ILI vs. VCC
Ta = + 25 °C
400
I LI [µA]
V OL2 [mV]
500
300
200
100
0
2.7
3
3.3
3.6
3.9
3.6
3.9
V CC [V]
V CC [V]
3.6
3.9
6
4
2
0
−2
−4
−6
2.7
3
3.3
V CC [V]
V CC [V]
Pull-up resistance
RUP vs. VCC
Ta = + 25 °C
R UP [k Ω]
200
160
120
80
40
0
2.7
3
3.3
3.6
3.9
V CC [V]
(Continued)
125
MB91350A Series
Power supply current
Power supply current
ICC vs. VCC
300
250
200
150
100
50
0
2.7
ICC vs. fC
Ta = + 25 °C, VCC = 3.3 V, fCP = 4 × fc (multiplied by4)
300
250
200
150
100
50
0
I CC [mA]
I CC [mA]
Ta = + 25 °C, fCP = 50 MHz, fCPP = 25 MHz
3
3.3
3.6
1
3.9
10
Power supply current at sleep
Power supply current at sleep
ICCS vs. VCC
ICCS vs. fC
Ta = + 25 °C, VCC = 3.3 V, fCP = 4 × fc (multiplied by 4)
I CCS [mA]
I CCS [mA]
Ta = + 25 °C, fCP = 50 MHz, fCPP = 25 MHz
300
250
200
150
100
50
0
2.7
3
3.3
3.6
300
250
200
150
100
50
0
3.9
1
V CC [V]
Power supply current at stop
ICCH vs. VCC
ICCL vs. VCC
400
I CCL [ µA]
I CCH [ µA]
500
3
3.3
3.6
300
200
100
0
2.7
3.9
Sub sleep power supply current
3
3.3
V CC [V]
3.6
3.9
Watch mode power supply current
ICCLS vs. VCC
Ta = + 25 °C, fCP = 32 kHz, fCPP = fCPT = 32 kHz
500
400
ICCT vs. VCC
Ta = + 25 °C, fCP = 32 kHz, fCPP = fCPT = 32 kHz
100
80
60
40
20
0
−20
2.7
I CCT [ µA]
I CCLS [ µA]
100
Ta = + 25 °C, fCP = 32 kHz, fCPP = 25 MHz
V CC [V]
300
200
100
0
2.7
10
f C [MHz]
Sub-RUN power supply current
Ta = + 25 °C
100
80
60
40
20
0
−20
2.7
100
f C [MHz]
V CC [V]
3
3.3
V CC [V]
3.6
3.9
3
3.3
3.6
3.9
V CC [V]
(Continued)
126
MB91350A Series
(Continued)
A/D converter power supply current
A/D converter reference power supply current
IA vs. VCC
Ta = + 25 °C
IR vs. VCC
Ta = + 25 °C
800
I R [ µA]
1000
8
I A [mA]
10
6
4
600
400
200
2
0
2.7
3
3.3
3.6
0
2.7
3.9
3
3.3
3.6
3.9
V CC [V]
V CC [V]
A/D converter power supply current at stop
A/D converter reference power supply current
at stop
IAH vs. VCC
Ta = + 25 °C
IRH vs. VCC
Ta = + 25 °C
20
I RH [ µA]
I AH [ µA]
20
10
0
−10
2.7
3
3.3
3.6
10
0
−10
2.7
3.9
3
3.6
D/A converter power supply current
<per 1 channel>
D/A converter power supply current
at power down
IADA vs. VCC
Ta = + 25 °C
IADAH vs. VCC
Ta = + 25 °C
500
300
200
100
0
2.7
3.9
20
400
I ADAH [ µA]
I ADA [ µA]
3.3
V CC [V]
V CC [V]
3
3.3
V CC [V]
3.6
3.9
10
0
−10
2.7
3
3.3
3.6
3.9
V CC [V]
127
MB91350A Series
• MB91355A
“H” level output voltage
VOH vs. VCC
VOL1 vs. VCC
Ta = +25 °C
500
VOL1 [mV]
VOH [V]
4
“L” level output voltage
3
2
1
2.7
3.0
3.3
3.6
400
300
200
100
0
2.7
0
3.9
3.0
“L” level output voltage (N-ch open-drain)
ILI vs. VCC
Ta = +25 °C
400
300
200
100
0
2.7
3.0
3.3
3.6
3.9
Input leak current
ILI [µA]
VOL2 [mV]
500
3.3
VCC [V]
VCC [V]
VOL2 vs. VCC
Ta = +25 °C
3.6
3.9
VCC [V]
6
4
2
0
−2
−4
−6
2.7
3.0
3.3
Ta = +25 °C
3.6
3.9
VCC [V]
Pull-up resistance
RUP vs. VCC
RUP [kΩ]
200
Ta = +25 °C
160
120
80
40
0
2.7
3.0
3.3
3.6
3.9
VCC [V]
(Continued)
128
MB91350A Series
Power supply current
Power supply current
ICC vs. fC
Ta = +25 °C, fCP = 50 MHz,
fCPP = fCPT = 25 MHz
300
250
200
150
100
Ta = +25 °C, VCC = 3.3 V,
fCP = 4 × fC (multiplied by 4)
300
ICC [mA]
ICC [mA]
ICC vs. VCC
250
200
150
100
50
0
50
0
2.7
3.0
3.3
3.6
1
3.9
10
Power supply current at sleep
Power supply current at sleep
ICCS vs. fC
Ta = +25 °C, fCP = 50 MHz,
fCPP = fCPT = 25 MHz
ICCS [mA]
ICCS [mA]
ICCS vs. VCC
300
250
200
150
100
Ta = +25 °C, VCC = 3.3 V,
fCP = 4 × fC (multiplied by 4)
300
250
200
150
100
50
0
50
0
2.7
3.0
3.3
3.6
3.9
1
10
VCC [V]
Sub RUN power supply current
ICCL vs. VCC
ICCH vs. VCC
500
400
ICCL [µA]
20
0
−20
2.7
Ta = +25 °C, fCP = 32 kHz,
fCPP = fCPT = 32 kHz
Ta = +25 °C
100
80
60
40
100
fC [MHz]
Power supply current at stop
ICCH [µA]
100
fC [MHz]
VCC [V]
3.0
3.3
VCC [V]
3.6
3.9
300
200
100
0
2.7
3.0
3.3
3.6
3.9
VCC [V]
(Continued)
129
MB91350A Series
Sub sleep power supply current
Watch mode power supply current
ICCLS vs. VCC
ICCT vs. VCC
Ta = +25 °C, fCP = 32 kHz,
fCPP = fCPT = 32 kHz
500
ICCT [µA]
ICCLS [µA]
400
300
200
100
0
2.7
3.0
3.3
3.6
3.9
VCC [V]
IA vs. VCC
6
600
IR [µA]
IA [mA]
1000
800
4
2
3.0
3.3
3.6
0
2.7
3.0
3.3
3.6
3.9
A/D converter reference power supply current at stop
IRH vs. VCC
Ta = +25 °C
20
IRH [µA]
IAH [µA]
Ta = +25 °C
VCC [V]
10
0
−10
2.7
3.9
200
3.9
A/D converter power supply current at stop
20
3.6
400
VCC [V]
IAH vs. VCC
3.3
IR vs. VCC
Ta = +25 °C
8
0
2.7
3.0
VCC [V]
A/D converter reference power supply voltage
A/D converter power supply current
10
100
80
60
40
20
0
−20
2.7
Ta = +25 °C, fCP = 32 kHz,
fCPP = fCPT = 32 kHz
Ta = +25 °C
10
0
−10
3.0
3.3
VCC [V]
3.6
3.9
2.7
3.0
3.3
3.6
3.9
VCC [V]
(Continued)
130
MB91350A Series
(Continued)
D/A converter power supply current
< per 1 channel >
IADA vs. VCC
500
D/A converter power supply current at power down
20
IADAH [µA]
400
IADA [µA]
IADAH vs. VCC
Ta = +25 °C
300
200
100
Ta = +25 °C
10
0
−10
0
2.7
3.0
3.3
VCC [V]
3.6
3.9
2.7
3.0
3.3
3.6
3.9
VCC [V]
131
MB91350A Series
“H” level output voltage
“L” level output voltage
VOH vs. VCC
Ta = + 25 °C
VOL1 vs. VCC
Ta = + 25 °C
4
500
3
400
V OL1 [mV]
V OH [V]
• MB91353A/352A/351A
2
1
0
2.7
3
3.3
3.6
300
200
100
0
2.7
3.9
3
V CC [V]
3.3
“L”level output voltage (N-ch open-drain)
Input leak current
VOL2 vs. VCC
Ta = + 25 °C
ILI vs. VCC
Ta = + 25 °C
400
I LI [ µA]
V OL2 [mV]
500
300
200
100
0
2.7
3
3.3
3.6
3.9
3.6
3.9
V CC [V]
3.6
3.9
6
4
2
0
−2
−4
−6
2.7
3
3.3
V CC [V]
V CC [V]
Pull-up resistance
RUP vs. VCC
Ta = + 25 °C
R UP [k Ω]
200
160
120
80
40
0
2.7
3
3.3
3.6
3.9
V CC [V]
(Continued)
132
MB91350A Series
Power supply current
Power supply current
ICC vs. VCC
300
250
200
150
100
50
0
2.7
ICC vs. fC
Ta = + 25 °C, VCC = 3.3 V, fCP = 4 × fc (multiplied by4)
300
250
200
150
100
50
0
I CC [mA]
I CC [mA]
Ta = + 25 °C, fCP = 50 MHz, fCPP = 25 MHz
3
3.3
3.6
3.9
1
V CC [V]
Power supply current at sleep
ICCS vs. VCC
I CCS [mA]
ICCS vs. fC
Ta = + 25 °C, VCC = 3.3 V, fCP = 4 × fc (multiplied by 4)
I CCS [mA]
3
3.3
3.6
300
250
200
150
100
50
0
1
3.9
10
Power supply current at stop
Sub-RUN power supply current
ICCH vs. VCC
Ta = + 25 °C
ICCL vs. VCC
Ta = + 25 °C, fCP = 32 kHz, fCPP = 25 MHz
100
80
60
40
20
0
−20
2.7
500
400
I CCL [ µA]
I CCH [ µA]
100
f C [MHz]
V CC [V]
3
3.3
3.6
300
200
100
0
2.7
3.9
3
Sub sleep power supply current
3.6
3.9
Watch mode power supply current
ICCLS vs. VCC
Ta = + 25 °C, fCP = 32 kHz, fCPP = fCPT = 32 kHz
500
ICCT vs. VCC
Ta = + 25 °C, fCP = 32 kHz, fCPP = fCPT = 32 kHz
100
80
60
40
20
0
−20
2.7
I CCT [ µA]
400
300
200
100
0
2.7
3.3
V CC [V]
V CC [V]
I CCLS [ µA]
100
Power supply current at sleep
Ta = + 25 °C, fCP = 50 MHz, fCPP = 25 MHz
300
250
200
150
100
50
0
2.7
10
f C [MHz]
3
3.3
V CC [V]
3.6
3.9
3
3.3
3.6
3.9
V CC [V]
(Continued)
133
MB91350A Series
A/D converter power supply current
A/D converter reference power supply current
IA vs. VCC
Ta = + 25 °C
IR vs. VCC
Ta = + 25 °C
10
1000
8
800
I R [ µA]
I A [mA]
(Continued)
6
4
600
400
200
2
0
2.7
3
3.3
3.6
0
2.7
3.9
3
3.6
3.9
A/D converter power supply current at stop
A/D converter reference power supply current
at stop
IAH vs. VCC
Ta = + 25 °C
IRH vs. VCC
Ta = + 25 °C
20
I RH [ µA]
I AH [ µA]
20
10
0
−10
2.7
3
3.3
3.6
10
0
−10
2.7
3.9
3
3.6
D/A converter power supply current
<per 1 channel>
D/A converter power supply current
at power down
IADA vs. VCC
Ta = + 25 °C
IADAH vs. VCC
Ta = + 25 °C
I ADAH [ µA]
400
300
200
100
0
2.7
3.9
20
500
I ADA [ µA]
3.3
V CC [V]
V CC [V]
3
3.3
V CC [V]
134
3.3
V CC [V]
V CC [V]
3.6
3.9
10
0
−10
2.7
3
3.3
V CC [V]
3.6
3.9
MB91350A Series
■ ORDERING INFORMATION
Part number
Package
Remarks
MB91F355APMT-002
176-pin plastic LQFP
(FPT-176P-M02)
Lead-free Package
MB91F356BPMT
176-pin plastic LQFP
(FPT-176P-M02)
Lead-free Package
MB91F357BPMT
176-pin plastic LQFP
(FPT-176P-M02)
Lead-free Package
MB91355APMT
176-pin plastic LQFP
(FPT-176P-M02)
Lead-free Package
MB91354APMT
176-pin plastic LQFP
(FPT-176P-M02)
Lead-free Package
MB91F353APMT
120-pin plastic LQFP
(FPT-120P-M21)
Lead-free Package
MB91351APMT
120-pin plastic LQFP
(FPT-120P-M21)
Lead-free Package
MB91352APMT
120-pin plastic LQFP
(FPT-120P-M21)
Lead-free Package
MB91353APMT
120-pin plastic LQFP
(FPT-120P-M21)
Lead-free Package
135
MB91350A Series
■ PACKAGE DIMENSION
120-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
16.0 × 16.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
M ounting height
1.70 mm MAX
Weight
0.88 g
Code
(Reference)
P-LFQFP120-16×16-0.50
(FPT-120P-M21)
120-pin plastic LQFP
(FPT-120P-M21)
Note 1) * : These dimensions do not include resin protrusion.
Resin protrusion is +0.25(.010) MAX(each side).
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
18.00±0.20(.709±.008)SQ
+0.40
* 16.00 –0.10 .630 +.016
–.004 SQ
90
61
91
60
0.08(.003)
Details of "A" part
+0.20
1.50 –0.10
+.008
(Mounting height)
.059 –.004
INDEX
0~8˚
120
LEAD No.
1
30
0.50(.020)
C
"A"
31
0.22±0.05
(.009±.002)
0.08(.003)
M
2002 FUJITSU LIMITED F120033S-c-4-4
0.145
.006
+0.05
–0.03
+.002
–.001
0.60±0.15
(.024±.006)
0.10±0.05
(.004±.002)
(Stand off)
0.25(.010)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html
(Continued)
136
MB91350A Series
(Continued)
176-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
24.0 × 24.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
1.86g
Code
(Reference)
P-LFQFP176-24×24-0.50
(FPT-176P-M02)
176-pin plastic LQFP
(FPT-176P-M02)
Note 1) * : Values do not include resin protrusion.
Resin protrusion is +0.25(.010)Max(each side).
Note 2) Pins width and pins thickness include plating thickness
Note 3) Pins width do not include tie bar cutting remainder.
26.00±0.20(1.024±.008)SQ
* 24.00±0.10(.945±.004)SQ
0.145±0.055
(.006±.002)
132
89
133
88
0.08(.003)
Details of "A" part
+0.20
1.50 –0.10
+.008
.059 –.004
0˚~8˚
(Mounting height)
0.10±0.10
(.004±.004)
(Stand off)
INDEX
176
45
"A"
LEAD No.
1
44
0.50(.020)
C
0.22±0.05
(.009±.002)
0.08(.003)
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.25(.010)
M
2003 FUJITSU LIMITED F176006S-c-4-6
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html
137
MB91350A Series
■ MAIN CHANGES IN THIS EDITION
Page
Section
⎯
⎯
4
■ FEATURES
15. Other features
94
■ ELECTRICAL CHARACTERISTICS
2. Recommended Operating Conditions
95 to 98,
■ ELECTRICAL CHARACTERISTICS
101,102, 105, Characteristic values
107 to 110,
112 to 115,
117
Change Results
Added the part number; MB91F357B
Changed the description;
• Provided with INIT as a reset pin (The CPU
operates without oscillation stabilization wait
interval when the INIT pin is reset.)
↓
• INIT pin provided as a reset pin (the oscillation stabilization wait time when the INIT pin is
reset is clock cycle × 2.)
Added the table “MB91F356B/F357B only”
Added the description VCC = 2.7 V to 3.6 V
(MB91F356B/F357B only)
100
4. AC Characteristics
(1) Clock Timing
Added the “(MB91F356B/F357B only)” for the
“• Operation Guaranteed Range”.
105
4. AC Characteristics
(4) Normal Bus Access Read/Write Operation
Changed the conditions and values for the
“Data setup → RD ↑ time”
⎯ → 3.0 V ≤ VCC ≤ 3.6 V, 2.7 V ≤ VCC < 3.0 V
10 →10, 15
118
■ ELECTRICAL CHARACTERISTICS
5. Electrical Characteristics for the
A/D Converter
Changed the table title;
• MB91F353A → • MB91F353A/352A/351A
■ ORDERING INFORMATION
Added the part number; MB91F357BPMT
119
135
Changed the table title;
• MB91F355A → • MB91F355A/F356B/F357B/
355A/354A/V350A
The vertical lines marked in the left side of the page show the changes.
138
MB91350A Series
The information for microcontroller supports is shown in the following homepage.
http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
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circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of
Fujitsu semiconductor device; Fujitsu does not warrant proper
operation of the device with respect to use based on such
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device based on such information, you must assume any
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Please note that Fujitsu will not be liable against you and/or any
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Any semiconductor devices have an inherent chance of failure. You
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