MC14024B 7-Stage Ripple Counter The MC14024B is a 7−stage ripple counter with short propagation delays and high maximum clock rates. The Reset input has standard noise immunity, however the Clock input has increased noise immunity due to Hysteresis. The output of each counter stage is buffered. http://onsemi.com Features • • • • • • • Diode Protection on All Inputs Output Transitions Occur on the Falling Edge of the Clock Pulse Supply Voltage Range = 3.0 Vdc to 18 Vdc Capable of Driving Two Low−power TTL Loads or One Low−power Schottky TTL Load Over the Rated Temperature Range Pin−for−Pin Replacement for CD4024B NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable This Device is Pb−Free and is RoHS Compliant MAXIMUM RATINGS (Voltages Referenced to VSS) PIN ASSIGNMENT CLOCK 1 14 VDD RESET 2 13 NC Q7 3 12 Q1 Q6 4 11 Q2 Q5 5 10 NC Q4 6 9 Q3 VSS 7 8 NC Value Unit −0.5 to +18.0 V −0.5 to VDD + 0.5 V Input or Output Current (DC or Transient) per Pin ±10 mA VDD = PIN 14 VSS = PIN 7 NC = NO CONNECTION PD Power Dissipation, per Package (Note 1) 500 mW MARKING DIAGRAM TA Ambient Temperature Range −55 to +125 °C Tstg Storage Temperature Range −65 to +150 °C TL Lead Temperature (8−Second Soldering) 260 °C Symbol VDD Vin, Vout Iin, Iout Parameter SOIC−14 D SUFFIX CASE 751A DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. August, 2014 − Rev. 10 14024BG AWLYWW 1 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Temperature Derating: “D/DW” Packages: –7.0 mW/_C From 65_C To 125_C © Semiconductor Components Industries, LLC, 2014 14 1 A WL, L YY, Y WW, W G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. Publication Order Number: MC14024B/D MC14024B TRUTH TABLE Clock Reset State 0 0 No Change 0 1 All Outputs Low 1 0 No Change 1 1 All Outputs Low 0 No Change 1 All Outputs Low 0 Advance One Count 1 All Outputs Low LOGIC DIAGRAM 1 CLOCK C Q C Q C Q C Q R Q R Q R Q R Q 2 RESET 12 Q1 11 Q2 4 Q6 3 Q7 Q3 = PIN 9 Q4 = PIN 6 Q5 = PIN 5 ORDERING INFORMATION Package Shipping† MC14024BDG SOIC−14 (Pb−Free) 55 Units / Rail NLV14024BDG* SOIC−14 (Pb−Free) 55 Units / Rail MC14024BDR2G SOIC−14 (Pb−Free) 2500 / Tape & Reel NLV14024BDR2G* SOIC−14 (Pb−Free) 2500 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable. http://onsemi.com 2 MC14024B ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) −55_C Characteristic Symbol 25_C VDD Vdc Min Max Min Typ (Note 2) 125_C Max Min Max Unit Output Voltage Vin = VDD or 0 “0” Level VOL 5.0 10 15 − − − 0.05 0.05 0.05 − − − 0 0 0 0.05 0.05 0.05 − − − 0.05 0.05 0.05 Vdc Vin = 0 or VDD “1” Level VOH 5.0 10 15 4.95 9.95 14.95 − − − 4.95 9.95 14.95 5.0 10 15 − − − 4.95 9.95 14.95 − − − Vdc Input Voltage (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) “0” Level VIL 5.0 10 15 − − − 1.5 3.0 4.0 − − − 2.25 4.50 6.75 1.5 3.0 4.0 − − − 1.5 3.0 4.0 (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) “1” Level 5.0 10 15 3.5 7.0 11 − − − 3.5 7.0 11 2.75 5.50 8.25 − − − 3.5 7.0 11 − − − 5.0 5.0 10 15 –3.0 –0.64 –1.6 –4.2 − − − − –2.4 –0.51 −1.3 −3.4 –4.2 –0.88 –2.25 −8.8 − − − − –1.7 −0.36 –0.9 −2.4 − − − − IOL 5.0 10 15 0.64 1.6 4.2 − − − 0.51 1.3 3.4 0.88 2.25 8.8 − − − 0.36 0.9 2.4 − − − mAdc Input Current Iin 15 − ±0.1 − ±0.00001 ±0.1 − ±1.0 mAdc Input Capacitance (Vin = 0) Cin − − − − 5.0 7.5 − − pF Quiescent Current (Per Package) IDD 5.0 10 15 − − − 5.0 10 20 − − − 0.005 0.010 0.015 5.0 10 20 − − − 150 300 600 mAdc IT 5.0 10 15 Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) VIH Vdc IOH Source Sink Total Supply Current (Notes 3 & 4) (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) Vdc mAdc IT = (0.31 mA/kHz) f + IDD IT = (0.60 mA/kHz) f + IDD IT = (1.89 mA/kHz) f + IDD mAdc Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. 3. The formulas given are for the typical characteristics only at 25_C. 4. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL − 50) Vfk where: IT is in mA (per package), CL in pF, V = (VDD − VSS) in volts, f in kHz is input frequency, and k = 0.001. http://onsemi.com 3 MC14024B SWITCHING CHARACTERISTICS (Note 5) (CL = 50 pF, TA = 25_C) Characteristic Symbol Output Rise and Fall Time tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns tTLH, tTHL Propagation Delay Time Clock to Q1 tPLH, tPHL = (1.7 ns/pF) CL + 295 ns tPLH, tPHL = (0.66 ns/pF) CL + 117 ns tPLH, tPHL = (0.5 ns/pF) CL + 85 ns Clock to Q7 tPLH, tPHL = (1.7 ns/pF) CL + 915 ns tPLH, tPHL = (0.66 ns/pF) CL + 367 ns tPLH, tPHL = (0.5 ns/pF) CL + 275 ns Reset to Qn tPLH, tPHL = (1.7 ns/pF) CL + 415 ns tPLH, tPHL = (0.66 ns/pF) CL + 217 ns tPLH, tPHL = (0.5 ns/pF) CL + 155 ns tPLH, tPHL Clock Pulse Width VDD Min Typ (Note 6) Max 5.0 10 15 − − − 100 50 40 200 100 80 Unit ns ns 5.0 10 15 − − − 380 150 110 600 230 175 5.0 10 15 − − − 1000 400 300 2000 750 565 5.0 10 15 − − − 500 250 180 800 400 300 tWH 5.0 10 15 500 165 125 200 60 40 − − − ns Reset Pulse Width tWH 5.0 10 15 600 350 260 375 200 150 − − − ns Reset Removal Time trem 5.0 10 15 625 190 145 250 75 50 − − − ns tTLH, tTHL 5.0 10 15 − − − − − − 1.0 8.0 200 s ms ms fcl 5.0 10 15 − − − 2.5 8.0 12 1.0 3.0 4.0 MHz Clock Input Rise and Fall Time Input Pulse Frequency 5. The formulas given are for the typical characteristics only at 25_C. 6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. http://onsemi.com 4 MC14024B VDD VOL = Vout VDD C Qn IOH R EXTERNAL POWER SUPPLY VSS COUNT Qn TO A LOGIC “1" LEVEL. Figure 1. Typical Output Source Characteristics Test Circuit VOH = Vout VDD C Qn IOL R EXTERNAL POWER SUPPLY VSS Figure 2. Typical Output Sink Characteristics Test Circuit VDD 500 mF PULSE GENERATOR 0.01 mF CERAMIC ID f C Q1 Q2 Q3 Q4 Q5 Q6 R Q7 VSS CL CL CL CL CL CL CL Figure 3. Power Dissipation Test Circuit http://onsemi.com 5 6 Figure 4. Functional Waveforms http://onsemi.com Q7 (3) Q6 (4) Q5 (5) Q4 (6) Q3 (9) Q2 (11) Q1 (12) RESET (2) CLOCK (1) t rem 1 t WH t TLH t PLH1 t WL 2 t PLH3 t TLH 10% 90% 50% t PHL1 4 8 t TLH t PLH4 50% t PHL2 Input t TLH and t THL = 20 ns t PLH2 t TLH 10% 90% 50% t PLH5 t TLH 50% t PHL3 16 t TLH t PLH6 50% t PHL4 32 t PHL6 t TLH t PLH7 50% t PHL5 64 t THL t PHL7 50% t THL t THL t THL t THL t THL 128 t THL 10% 90% 255 t R7 t R6 t R5 t R4 t R3 t R2 t R1 50% VOL VOH VOL VOH VOL VOH VOL VOH VOL VOH VOL VOH VOL VOH VSS VDD VSS VDD MC14024B MC14024B PACKAGE DIMENSIONS D SOIC−14 NB CASE 751A−03 ISSUE K A B 14 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF AT MAXIMUM MATERIAL CONDITION. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSIONS. 5. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 8 A3 E H L 1 0.25 M DETAIL A 7 B 13X M b 0.25 M C A S B S e DETAIL A h A X 45 _ M A1 C SEATING PLANE DIM A A1 A3 b D E e H h L M MILLIMETERS MIN MAX 1.35 1.75 0.10 0.25 0.19 0.25 0.35 0.49 8.55 8.75 3.80 4.00 1.27 BSC 5.80 6.20 0.25 0.50 0.40 1.25 0_ 7_ INCHES MIN MAX 0.054 0.068 0.004 0.010 0.008 0.010 0.014 0.019 0.337 0.344 0.150 0.157 0.050 BSC 0.228 0.244 0.010 0.019 0.016 0.049 0_ 7_ SOLDERING FOOTPRINT* 6.50 14X 1.18 1 1.27 PITCH 14X 0.58 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. 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