IRFR3710ZPbF IRFU3710ZPbF IRFU3710Z-701PbF HEXFET® Power MOSFET Features Advanced Process Technology Ultra Low On-Resistance 175°C Operating Temperature Fast Switching Repetitive Avalanche Allowed up to Tjmax Multiple Package Options Lead-Free IRFU3710ZPbF I-Pak IRFR3710ZPbF D-Pak Absolute Maximum Ratings Symbol RDS(on) 18m ID 42A D S G G I-Pak Lead form 701 IRFU3710Z-701PbF Refer to page 11 for package outline D Drain Standard Pack Form Quantity Tube 75 IRFU3710ZPbF Tube 75 IRFR3710ZPbF Tape and Reel Left 3000 IRFR3710ZTRLPbF Parameter Max. Continuous Drain Current, VGS @ 10V (Silicon Limited) 56 ID @ TC = 100°C ID @ TC = 25°C IDM PD @TC = 25°C Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V (Package Limited) Pulsed Drain Current Maximum Power Dissipation 39 42 220 140 VGS EAS (Thermally limited) EAS (Tested ) IAR EAR TJ TSTG Linear Derating Factor Gate-to-Source Voltage Single Pulse Avalanche Energy Single Pulse Avalanche Energy Tested Value Avalanche Current Repetitive Avalanche Energy Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds (1.6mm from case) 1 S Source Orderable Part Number ID @ TC = 25°C Thermal Resistance Symbol RJC RJA RJA S D I- Pak IRFU3710ZPbF D- Pak IRFR3710ZPbF G Gate Package Type 100V D Description This HEXFET® Power MOSFET utilizes the latest processing techniques to achieve extremely low on-resistance per silicon area. Additional features of this design are a 175°C junction operating temperature, fast switching speed and improved repetitive avalanche rating . These features combine to make this design an extremely efficient and reliable device for use in a wide variety of applications. Base part number VDSS Parameter Junction-to-Case Junction-to-Ambient ( PCB Mount) Junction-to-Ambient Units A W 0.95 ± 20 150 200 See Fig.12a, 12b, 15, 16 W/°C V mJ A mJ -55 to + 175 °C 300 Typ. ––– ––– ––– Max. 1.05 50 110 Units °C/W 2016-5-31 IRFR/U3710ZPbF & IRFU3710Z-701PbF Electrical Characteristics @ TJ = 25°C (unless otherwise specified) V(BR)DSS V(BR)DSS/TJ RDS(on) VGS(th) Parameter Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage gfs Forward Trans conductance IDSS Drain-to-Source Leakage Current Min. Typ. Max. Units Conditions 100 ––– ––– V VGS = 0V, ID = 250µA ––– 0.088 ––– V/°C Reference to 25°C, ID = 1mA ––– 15 18 m VGS = 10V, ID = 33A 2.0 ––– 4.0 V VDS = VGS, ID = 250µA ––– ––– ––– ––– ––– Qg Qgs Qgd td(on) tr td(off) tf Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Total Gate Charge Gate-to-Source Charge Gate-to-Drain (‘Miller’) Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– 69 15 25 14 43 53 42 20 250 200 -200 100 ––– ––– ––– ––– ––– ––– LD Internal Drain Inductance ––– 4.5 ––– LS Internal Source Inductance ––– 7.5 ––– Ciss Coss Crss Coss Input Capacitance Output Capacitance Reverse Transfer Capacitance Output Capacitance ––– ––– ––– ––– 2930 290 180 1200 ––– ––– ––– ––– VDS = 100V, VGS = 0V VDS = 100V,VGS = 0V,TJ =125°C VGS = 20V nA VGS = -20V ID = 33A nC VDS = 80V VGS = 10V VDD = 50V ID = 33A ns RG = 6.8 VGS = 10V Between lead, 6mm (0.25in.) nH from package and center of die contact VGS = 0V pF VDS = 25V ƒ = 1.0MHz VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz Coss Output Capacitance ––– 180 ––– VGS = 0V, VDS = 80V, ƒ = 1.0MHz Coss eff. Effective Output Capacitance ––– 430 ––– VGS = 0V, VDS = 0V to 80V Min. Typ. Max. Units ––– ––– 56 ––– ––– 220 ––– ––– ––– ––– 35 41 1.3 53 62 Conditions MOSFET symbol showing the integral reverse p-n junction diode. TJ = 25°C,IS = 33A,VGS = 0V TJ = 25°C ,IF = 33A, VDS = 50V di/dt = 100A/µs IGSS Source-Drain Ratings and Characteristics Parameter Continuous Source Current IS (Body Diode) Pulsed Source Current ISM (Body Diode) VSD Diode Forward Voltage trr Reverse Recovery Time Qrr Reverse Recovery Charge ton Forward Turn-On Time S VDS = 25V, ID = 33A 39 µA A V ns nC Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD) Notes: Repetitive rating; pulse width limited by max. junction temperature. (See fig. 11). starting TJ = 25°C, L = 0.28mH, RG = 25, IAS = 33A,VGS =10V. Part not recommended for use above this value. Pulse width 1.0ms; duty cycle 2%. Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical repetitive avalanche performance. This value determined from sample failure population. 100% tested to this value in production. When mounted on 1" square PCB (FR-4 or G-10 Material). For recommended footprint and soldering techniques refer to application note #AN-994. Refer to D-Pak package for Part Marking, Tape and Reel information 2 2016-5-31 IRFR/U3710ZPbF & IRFU3710Z-701PbF 1000 1000 100 BOTTOM TOP ID, Drain-to-Source Current (A) ID, Drain-to-Source Current (A) TOP VGS 15V 10V 6.0V 5.0V 4.8V 4.5V 4.3V 4.0V 100 10 4.0V 60µs PULSE WIDTH Tj = 25°C 1 0.1 1 10 BOTTOM 4.0V 10 1 60µs PULSE WIDTH Tj = 175°C 0.1 0.1 100 10 100 Fig. 2 Typical Output Characteristics Fig. 1 Typical Output Characteristics 100 T J = 175°C 100 10 1.0 T J = 25°C VDS = 25V 60µs PULSE WIDTH 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VGS, Gate-to-Source Voltage (V) Fig. 3 Typical Transfer Characteristics Gfs, Forward Transconductance (S) 1000 ID , Drain-to-Source Current ) 1 V DS, Drain-to-Source Voltage (V) V DS, Drain-to-Source Voltage (V) 3 VGS 15V 10V 6.0V 5.0V 4.8V 4.5V 4.3V 4.0V T J = 25°C 80 60 T J = 175°C 40 20 V DS = 10V 0 0 10 20 30 40 50 60 70 80 ID,Drain-to-Source Current (A) Fig. 4 Typical Forward Transconductance vs. Drain Current 2016-5-31 IRFR/U3710ZPbF & IRFU3710Z-701PbF 100000 VGS, Gate-to-Source Voltage (V) ID= 33A Coss = Cds + Cgd 10000 C, Capacitance(pF) 12.0 VGS = 0V, f = 1 MHZ Ciss = C gs + Cgd, C ds SHORTED Crss = C gd Ciss 1000 Coss Crss 100 10.0 VDS = 80V VDS = 50V VDS = 20V 8.0 6.0 4.0 2.0 0.0 10 1 10 100 0 10 Fig 5. Typical Capacitance vs. Drain-to-Source Voltage ID, Drain-to-Source Current (A) ISD, Reverse Drain Current (A) 1000 10.00 T J = 25°C VGS = 0V 0.10 0.4 0.6 0.8 1.0 1.2 1.4 1.6 VSD , Source-to-Drain Voltage (V) Fig. 7 Typical Source-to-Drain Diode Forward Voltage 4 50 60 70 80 OPERATION IN THIS AREA LIMITED BY R DS (on) 100 T J = 175°C 0.2 40 Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage 1000.00 1.00 30 QG Total Gate Charge (nC) VDS , Drain-to-Source Voltage (V) 100.00 20 1.8 100µsec 10 1msec 1 Tc = 25°C Tj = 175°C Single Pulse 10msec 0.1 1 10 100 1000 VDS , Drain-to-Source Voltage (V) Fig 8. Maximum Safe Operating Area 2016-5-31 IRFR/U3710ZPbF & IRFU3710Z-701PbF 60 Limited By Package 50 ID, Drain Current (A) RDS(on) , Drain-to-Source On Resistance (Normalized) 3.0 40 30 20 10 0 ID = 56A VGS = 10V 2.5 2.0 1.5 1.0 0.5 25 50 75 100 125 150 175 -60 -40 -20 0 TC , Case Temperature (°C) 20 40 60 80 100 120 140 160 180 T J , Junction Temperature (°C) Fig 9. Maximum Drain Current vs. Case Temperature Fig 10. Normalized On-Resistance vs. Temperature Thermal Response ( Z thJC ) 10 1 D = 0.50 0.1 0.01 0.001 0.20 0.10 0.05 0.02 0.01 J R1 R1 J 1 R2 R2 R3 R3 C 1 2 2 3 3 Ci= iRi Ci= iRi SINGLE PULSE ( THERMAL RESPONSE ) C Ri (°C/W) i (sec) 0.576 0.000540 0.249 0.001424 0.224 0.007998 Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc 0.0001 1E-006 1E-005 0.0001 0.001 0.01 0.1 t1 , Rectangular Pulse Duration (sec) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case 5 2016-5-31 IRFR/U3710ZPbF & IRFU3710Z-701PbF 15V L VDS D.U.T RG IAS 20V DRIVER + V - DD A 0.01 tp Fig 12a. Unclamped Inductive Test Circuit V(BR)DSS EAS , Single Pulse Avalanche Energy (mJ) 700 ID 3.4A 4.8A BOTTOM 33A TOP 600 500 400 300 200 100 tp 0 25 50 75 100 125 150 175 Starting T J , Junction Temperature (°C) Fig 12c. Maximum Avalanche Energy vs. Drain Current I AS Fig 12b. Unclamped Inductive Waveforms Fig 13a. Gate Charge Waveform VGS(th) Gate threshold Voltage (V) 4.0 3.0 ID = 250µA 2.0 1.0 -75 -50 -25 0 25 50 75 100 125 150 175 200 T J , Temperature ( °C ) Fig 14. Threshold Voltage vs. Temperature Fig 13b. Gate Charge Test Circuit 6 2016-5-31 IRFR/U3710ZPbF & IRFU3710Z-701PbF 1000 Avalanche Current (A) Duty Cycle = Single Pulse 100 Allowed avalanche Current vs avalanche pulsewidth, tav assuming Tj = 25°C due to avalanche losses 0.01 10 0.05 0.10 1 0.1 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 tav (sec) Fig 15. Typical Avalanche Current vs. Pulse width EAR , Avalanche Energy (mJ) 200 TOP Single Pulse BOTTOM 1% Duty Cycle ID = 33A 150 100 50 0 25 50 75 100 125 150 Starting T J , Junction Temperature (°C) Fig 16. Maximum Avalanche Energy vs. Temperature 7 175 Notes on Repetitive Avalanche Curves , Figures 15, 16: (For further info, see AN-1005 at www.infineon.com) 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of Tjmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long as Tjmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 12a, 12b. 4. PD (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. Iav = Allowable avalanche current. 7. T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as 25°C in Figure 15, 16). tav = Average time in avalanche. D = Duty cycle in avalanche = tav ·f ZthJC(D, tav) = Transient thermal resistance, see figure 11) PD (ave) = 1/2 ( 1.3·BV·Iav) = T/ ZthJC Iav = 2T/ [1.3·BV·Zth] EAS (AR) = PD (ave)·tav 2016-5-31 IRFR/U3710ZPbF & IRFU3710Z-701PbF Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs Fig 18a. Switching Time Test Circuit Fig 18b. Switching Time Waveforms 8 2016-5-31 IRFR/U3710ZPbF & IRFU3710Z-701PbF D-Pak (TO-252AA) Package Outline (Dimensions are shown in millimeters (inches)) D-Pak (TO-252AA) Part Marking Information EXAMPLE: THIS IS AN IRFR120 WITH ASSEMBLY LOT CODE 1234 ASSEMBLED ON WW 16, 2001 IN THE ASSEMBLY LINE "A" PART NUMBER INTERNATIONAL RECTIFIER LOGO Note: "P" in assembly line position indicates "Lead-Free" IRFR120 12 116A 34 ASSEMBLY LOT CODE DATE CODE YEAR 1 = 2001 WEEK 16 LINE A "P" in assembly line position indicates "Lead-Free" qualification to the consumer-level OR INTERNATIONAL RECTIFIER LOGO PART NUMBER IRFR120 12 ASSEMBLY LOT CODE 34 DATE CODE P = DESIGNATES LEAD-FREE PRODUCT (OPTIONAL) P = DESIGNATES LEAD-FREE PRODUCT QUALIFIED TO THE CONSUMER LEVEL (OPTIONAL) YEAR 1 = 2001 WEEK 16 A = ASSEMBLY SITE CODE Notes: 1. 2. For an Automotive Qualified version of this part please seehttp://www.infineon.com/product-info/datasheets/data/auirfr3710z.pdf For the most current drawing please refer to Infineon website at http://www.infineon.com/package/ 9 2016-5-31 IRFR/U3710ZPbF & IRFU3710Z-701PbF I-Pak (TO-251AA) Package Outline Dimensions are shown in millimeters (inches) I-Pak (TO-251AA) Part Marking Information EXAMPLE: THIS IS AN IRFU120 WITH ASSEMBLY LOT CODE 5678 ASSEMBLED ON WW 19, 2001 IN THE ASSEMBLY LINE "A" INTERNATIONAL RECTIFIER LOGO PART NUMBER IRFU120 119A 56 78 ASSEMBLY LOT CODE Note: "P" in assembly line position indicates Lead-Free" DATE CODE YEAR 1 = 2001 WEEK 19 LINE A OR INTERNATIONAL RECTIFIER LOGO PART NUMBER IRFU120 56 ASSEMBLY LOT CODE 78 DATE CODE P = DESIGNATES LEAD-FREE PRODUCT (OPTIONAL) YEAR 1 = 2001 WEEK 19 A = ASSEMBLY SITE CODE Notes: 1. For an Automotive Qualified version of this part please seehttp://www.infineon.com/product-info/auto/ 2. For the most current drawing please refer to Infineon website at http://www.infineon.com/package/ 10 2016-5-31 IRFR/U3710ZPbF & IRFU3710Z-701PbF I-Pak Leadform Option 701 Package Outline Dimensions are shown in millimeters (inches) 11 2016-5-31 IRFR/U3710ZPbF & IRFU3710Z-701PbF D-Pak (TO-252AA) Tape & Reel Information Dimensions are shown in millimeters (inches) TR TRR 16.3 ( .641 ) 15.7 ( .619 ) 12.1 ( .476 ) 11.9 ( .469 ) FEED DIRECTION TRL 16.3 ( .641 ) 15.7 ( .619 ) 8.1 ( .318 ) 7.9 ( .312 ) FEED DIRECTION NOTES : 1. CONTROLLING DIMENSION : MILLIMETER. 2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ). 3. OUTLINE CONFORMS TO EIA-481 & EIA-541. 13 INCH 16 mm NOTES : 1. OUTLINE CONFORMS TO EIA-481. Note: For the most current drawing please refer to Infineon’s web site www.infineon.com 12 2016-5-31 IRFR/U3710ZPbF & IRFU3710Z-701PbF Qualification Information† Industrial (per JEDEC JESD47F) †† Qualification Level Moisture Sensitivity Level D-Pak MSL1 I-Pak (per JEDEC J-STD-020D) †† Yes RoHS Compliant † Qualification standards can be found at Infineon’s web site www.infineon.com †† Applicable version of JEDEC standard at the time of product release. Revision History Date 5/31/2016 Comments Updated datasheet with corporate template. Added disclaimer on last page. Trademarks of Infineon Technologies AG µHVIC™, µIPM™, µPFC™, AU‐ConvertIR™, AURIX™, C166™, CanPAK™, CIPOS™, CIPURSE™, CoolDP™, CoolGaN™, COOLiR™, CoolMOS™, CoolSET™, CoolSiC™, DAVE™, DI‐POL™, DirectFET™, DrBlade™, EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPACK™, EconoPIM™, EiceDRIVER™, eupec™, FCOS™, GaNpowIR™, HEXFET™, HITFET™, HybridPACK™, iMOTION™, IRAM™, ISOFACE™, IsoPACK™, LEDrivIR™, LITIX™, MIPAQ™, ModSTACK™, my‐d™, NovalithIC™, OPTIGA™, Op MOS™, ORIGA™, PowIRaudio™, PowIRStage™, PrimePACK™, PrimeSTACK™, PROFET™, PRO‐SIL™, RASIC™, REAL3™, SmartLEWIS™, SOLID FLASH™, SPOC™, StrongIRFET™, SupIRBuck™, TEMPFET™, TRENCHSTOP™, TriCore™, UHVIC™, XHP™, XMC™ Trademarks updated November 2015 Other Trademarks All referenced product or service names and trademarks are the property of their respec ve owners. Edi on 2016‐04‐19 Published by Infineon Technologies AG 81726 Munich, Germany © 2016 Infineon Technologies AG. All Rights Reserved. Do you have a ques on about this document? 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