HFA3925 Data Sheet July 1998 File Number 4132.4 2.4GHz - 2.5GHz 250mW Power Amplifier Features The Intersil 2.4GHz PRISM™ chip set is a highly integrated five-chip solution for RF modems employing Direct Sequence Spread Spectrum (DSSS) signaling. The HFA3925 2.4GHz2.5GHz, 250mW power amplifier is one of the five chips in the PRISM™ chip set (see the Typical Application Diagram). • Highly Integrated Power Amplifier with T/R Switch ™ The Intersil HFA3925 is an integrated power amplifier with transmit/receive switch in a low cost SSOP 28 plastic package. The power amplifier delivers +27dB of gain with high efficiency and can be operated with voltages as low as 2.7V. The power amplifier switch is fully monolithic and can be controlled with CMOS logic levels. • Operates Over 2.7V to 6V Supply Voltage • High Linear Output Power (P1dB: +24dBm) • Individual Gate Control for Each Amplifier Stage • Low Cost SSOP-28 Plastic Package Applications • Systems Targeting IEEE 802.11 Standard • TDD Quadrature-Modulated Communication Systems • Wireless Local Area Networks • PCMCIA Wireless Transceivers The HFA3925 is ideally suited for QPSK, BPSK or other linearly modulated systems in the 2.4GHz Industrial, Scientific, and Medical (ISM) frequency band. It can also be used in GFSK systems where levels of +25dBm are required. Typical applications include Wireless Local Area Network (WLAN) and wireless portable data collection. REMEMBER: Always apply Negative power to the VG pins before applying the Positive VDD bias. Failure to do so may result in the destruction of the HFA3925 Power Amplifier. Pinout • ISM Systems • TDMA Packet Protocol Radios • PCS/Wireless PBX Ordering Information PART NUMBER TEMP. RANGE (oC) PACKAGE HFA3925IA -40 to 85 28 Ld SSOP HFA3925IA96 -40 to 85 Tape and Reel PKG. NO. M28.15 Functional Block Diagram HFA3925 (SSOP) TOP VIEW T/R CNTRL VDDX(+) GND 1 28 GND GND 2 27 VDD TR GND 3 26 T/R CNTRL GND 4 25 RF OUT GND 5 24 GND GND 6 23 VDD3 GND 7 22 GND RX OUT 8 21 GND VG2 9 20 GND GND 10 19 GND VDD1 11 18 VDD2 GND 12 17 VG3 GND 13 16 GND VG1 14 15 RF IN 2-179 VGX(-) STAGE BIAS CONTROL RX OUT RF IN STAGE 1 STAGE 2 STAGE 3 RF_OUT TO ANTENNA CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 PRISM® is a registered trademark of Intersil Corporation. PRISM logo is a trademark of Intersil Corporation. HFA3925 Typical Application Diagram HSP3824 HFA3724 (FILE# 4064) TUNE/SELECT HFA3424 (NOTE) RXI (FILE# 4131) A/D DESPREAD RXQ I ÷2 (FILE# 4066) 0o/90o M M U U X X RSSI A/D A/D CCA TXI SPREAD RFPA VCO HFA3925 VCO TXQ Q 802.11 MAC-PHY INTERFACE CTRL HFA3624 UP/DOWN CONVERTER DPSK DEMOD DATA TO MAC (FILE# 4067) DPSK MOD. (FILE# 4132) QUAD IF MODULATOR DSSS BASEBAND PROCESSOR DUAL SYNTHESIZER HFA3524 (FILE# 4062) PRISM™ CHIP SET FILE #4063 TYPICAL TRANSCEIVER APPLICATION USING THE HFA3925 NOTE: Required for systems targeting 802.11 specifications. For additional information on the PRISM™ chip set, call (407) 724-7800 to access Intersil AnswerFAX system. When prompted, key in the four-digit document number (File #) of the datasheets you wish to receive. 2-180 The four-digit file numbers are shown in the Typical Application Diagram, and correspond to the appropriate circuit HFA3925 Absolute Maximum Ratings Thermal Information Maximum Input Power (Note 2) . . . . . . . . . . . . . . . . . . . . . . +23dBm Operating Voltages (Notes 2, 3). . . . . . . . . . . . VDD = 8V, VGG = -8V Thermal Resistance (Typical, Note 1) θJA (oC/W) SSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications TA = 25oC, Z0 = 50Ω, VDD = +5V, PIN = -30dBm, f = 2.45GHz, Unless Otherwise Specified PARAMETER MIN TYP MAX UNITS 27 28 32 dB VSWR In/Out - 1.75:1 - Input Return Loss - -11.3 - dB Output Return Loss - -11.3 - dB 22.5 24.5 - dBm Second Harmonic at P1dB - -20 0 dBc Third Harmonic at P1dB - -30 -10 dBc IDD at P1dB (VDD1 + VDD2 + VDD3) - 270 375 mA POWER AMPLIFIER Linear Gain Output Power at P1dB NOTES: 2. Ambient temperature (TA) = 25oC. 3. |VDD | + |VGG | not to exceed 12V. Pin Description PINS SYMBOL 1 GND DC and RF Ground. 2 GND DC and RF Ground. 3 GND DC and RF Ground. 4 GND DC and RF Ground. 5 GND DC and RF Ground. 6 GND DC and RF Ground. 7 GND DC and RF Ground. 8 RX OUT 9 VG2 Negative bias control for the second PA stage, adjusted to set VDD2 quiescent bias current, which is typically 53mA. Typical voltage at pin = -0.75V. Input impedance: > 1MΩ. 10 GND DC and RF Ground. 11 VDD1 Positive bias for the first stage of the PA, 2.7V to 6V. 12 GND DC and RF Ground. 13 GND DC and RF Ground. 14 VG1 Negative bias control for the first PA stage, adjusted to set VDD1 quiescent bias current, which is typically 20mA. Typical voltage at pin = -0.75V. Input impedance: > 1MΩ. 15 RF IN RF Input of the Power Amplifier. 16 GND DC and RF Ground. 2-181 DESCRIPTION Output of T/R Switch for receive mode. HFA3925 Pin Description (Continued) PINS SYMBOL DESCRIPTION 17 VG3 Negative bias control for the third PA stage, adjusted to set VDD3 quiescent bias current, which is typically 90mA. Typical voltage at pin = -0.95V. Input impedance: > 1MΩ. 18 VDD2 Positive bias for the second stage of the PA. 2.7V to 6V. 19-22 GND DC and RF Ground. 23 VDD3 Positive bias for the third stage of the PA. 2.7V to 6V. 24 GND DC and RF Ground. 25 RF OUT 26 T/R CTRL 27 VDD TR VDD for T/R switch. 28 GND DC and RF Ground. RF output of T/R switch and power amplifier for transmit mode. 0V for transmit mode, +5V for receive mode. Low < = 0.2V, high > = VDD -0.2V. NOTE: Process variation will effect VG3 voltage requirement to develop 90mA stage 3 quiescent current, maximum range = -0.69V to -1.04V. Typical Performance Curves Power Amplifier Small Signal Performance NOTE: All data measured at TA = 25oC and VG1, VG2 and VG3 adjusted for first stage quiescent current of 20mA, second stage current of 53mA and third stage current of 90mA, respectively 35 6V -5 VDD1 = VDD2 = VDD3 4V 30 -10 RETURN LOSS (dB) 5V 20 15 -15 5V -20 6V 4V -25 3V 10 2.0 2.2 2.4 2.6 FREQUENCY (GHz) 2.8 -30 2.0 3.0 2.2 FIGURE 1. LINEAR GAIN 2.4 2.6 FREQUENCY (GHz) FIGURE 2. INPUT MATCH 0 RETURN LOSS (dB) GAIN (dB) 3V 25 -5 -10 5V 6V 3V -15 4V -20 2.0 2.2 2.4 2.6 FREQUENCY (GHz) FIGURE 3. OUTPUT MATCH 2-182 2.8 3.0 2.8 3.0 HFA3925 Typical Performance Curves (Continued) Power Amplifier CW Performance at Various Supply Voltages NOTE: All data measured at TA = 25oC and VG1, VG2 and VG3 adjusted for first stage quiescent current of 20mA, second stage current of 53mA and third stage current of 90mA, respectively. 30 50 2.45GHz, VDD1 = VDD2 = VDD3 2.45GHz, VDD1 = VDD2 = VDD3 5V 5V 6V 25 40 6V EFFICIENCY (%) POWER (dBm) 4V 3V 20 15 4V 30 3V 20 10 10 5 -19 -14 -9 POWER INPUT (dBm) -4 0 -19 1 FIGURE 4. POWER OUTPUT -14 -9 INPUT POWER (dBm) -4 1 FIGURE 5. POWER ADDED EFFICIENCY 0 6V COMPRESSION (dBm) -1 5V -2 4V -3 3V -4 -5 -6 -7 -19 2.45GHz, VDD1 = VDD2 = VDD3 -14 -9 -4 1 INPUT POWER (dBm) FIGURE 6. GAIN COMPRESSION Power Amplifier Temperature Performance NOTE: All data measured at TA = 25oC and VG1, VG2 and VG3 adjusted for first stage quiescent current of 20mA, second stage current of 53mA and third stage current of 90mA, respectively. 35 30 2.45GHz, VDD1 = VDD2 = VDD3 = +5V 25 30 POWER (dBm) 25oC GAIN (dB) -20oC -20oC 25 70oC 20 20 25oC 70oC 15 10 15 5 10 2.0 VDD1 = VDD2 = VDD3 = +5V 2.2 2.4 2.6 FREQUENCY (GHz) FIGURE 7. LINEAR GAIN 2-183 2.8 3.0 0 -19 -14 -9 INPUT POWER (dBm) FIGURE 8. POWER OUTPUT -4 1 HFA3925 Typical Performance Curves (Continued) 0 COMPRESSION (dB) -1 -20oC 70oC -2 25oC -3 -4 2.45GHz, VDD1 = VDD2 = VDD3 = +5V -5 -20 -10 -5 -15 0 5 INPUT POWER (dBm) FIGURE 9. GAIN COMPRESSION Power Amplifier Spurious Response at Various Supply Voltages NOTE: All data measured at TA = 25oC and VG1, VG2 and VG3 adjusted for first stage quiescent current of 20mA, second stage current of 53mA and third stage current of 90mA, respectively. 50 70 2.45GHz, TONE SPACING 600kHz 2.45GHz, VDD1 = VDD2 = VDD3 65 3V 40 5V 6V dBc 30 55 5V 6V 50 4V 45 20 3V 4V 40 10 9 13 17 21 FUNDAMENTAL POUT OF TONES (dBm) 25 35 15 17 FIGURE 10. THIRD ORDER INTERMODULATION RATIO 19 21 FUNDAMENTAL POUT (dBm) 60 55 6V 50 5V 45 4V 40 3V 35 15 2.45GHz, VDD1 = VDD2 = VDD3 17 19 21 FUNDAMENTAL POUT (dBm) 23 FIGURE 12. THIRD HARMONIC RATIO 2-184 23 FIGURE 11. SECOND HARMONIC RATIO dBc IMR (dBc) 60 25 25 HFA3925 Typical Performance Curves (Continued) -5 -1 -10 -2 -15 -3 -20 0 RETURN LOSS (dB) 0 ISOLATION (dB) INSERTION LOSS (dB) Transmit/Receive Switch Performance NOTE: All data measured with VDD TR = +5V, TA = 25oC. -5 -10 INPUT -15 -4 -25 -5 2.0 2.2 2.4 2.6 FREQUENCY (GHz) OUTPUT -30 3.0 2.8 -20 2.0 FIGURE 13. RECEIVE MODE T/R INSERTION LOSS/ISOLATION 2.2 2.4 2.6 FREQUENCY (GHz) 2.8 FIGURE 14. RECEIVE MODE T/R SWITCH MATCH Typical Application Example VDD (T/R ANT) C25 RX OUT (50Ω TRANSMISSION LINE) VG2 (-) R3 VDD1 (+) C22 R6 C12 C11 C5 VG1 (-) R2 R5 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 C8 C21 C7 C20 T/R CNTRL RF OUT (50Ω TRANSMISSION LINE) C24 VDD3 (+) C4 C16 C19 C3 C15 C18 VDD2 (+) C14 R4 C13 C23 EXTERNAL CIRCUITRY PARTS LIST LABEL VALUE C3-C5, C7, C8 22pF Bypass (GHz) C23-C24 22pF DC Block C11-C16 1000pF Bypass (MHz) C18-C22 0.01µF Bypass (kHz) R1, R6 1.5kΩ FET Gate Divider Network R3, R5 5kΩ R2 12kΩ R4 1kΩ PURPOSE NOTE: All off-chip components are low cost surface mount components obtainable from multiple sources. (0.020in x 0.040in or 0.030in x 0.050in.) 2-185 R1 VG3 (-) RF IN (50Ω TRANSMISSION LINE) 3.0 HFA3925 Typical Application Diagram 330 PAPE STEP 0 TO +3.5V PAPE 4.7K Positive Supply, Single Stage 3 Adjustment Circuit VCC1 MMBT2222ALT1 MOTOROLA SOT 23 5K VCC2 G2 S2 G1 S1 1 2 3 4 1000pF 1 GND 5pF GND 28 HFA3925 RF1K49093 8 7 6 5 D2 D2 D1 RX OUT 715 35 0.1µF T/R CTRL 26 4 GND 25 5 GND GND 24 6 GND VDD3 23 7 GND GND 22 8 GND 21 9 VG2 GND 20 3.01K 10 GND GND 19 11 VDD1 VDD2 18 12 GND VG3 17 13 GND GND 16 1 2 3 GND RF OUT 22pF 0.1µF 3 VDD T/R 27 D1 L8 BEAD 4 2 GND HFA3424 LNA 0.1µF 8 7 6 5 715 14 VG1 500pF 0.1µF RF IN RF IN 15 22pF 3.01K RF OUT 15nH 820Ω VCC2 10K - +IN POWER UP TIMING TRANSMIT ENABLED +3.5V PAPE MOTOROLA RECEIVE ENABLED 0V VCC2 +3.5V - 4.7µF TANTL 0V VCC2 = +3.5V TRUTH TABLE PAPE 2-186 1K MMBT 2222 ALT1 4 3 2 + VCC1 = +5V 4.7µF + TANTL -OUT + TO -V CONVERTER 1 ICL7660SIBA SUPER VOLTAGE CONVERTER 5 6 7 8 0.1µF TR/CTRL MODE Low (0) High (1) Receive High (1) Low (0) Transmit VCC1 +5V 0V 25ms MIN HFA3925 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. 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