Intersil ISL75052SEHFE/PROTO 1.5a, rad hard, positive, high voltage ldo Datasheet

1.5A, Rad Hard, Positive, High Voltage LDO
ISL75052SEH
Features
The ISL75052SEH is a radiation hardened, single output LDO
specified for an output current of 1.5A. The device operates from
an input voltage range of 4.0V to 13.2V and provides for output
voltages of 0.6V to 12.7V. The output is adjustable based on a
resistor divider setting. Dropout voltages as low as 75mV (at
0.5A) typical can be realized using the device. This allows the
user to improve the system efficiency by lowering VIN to nearly
VOUT.
• DLA SMD 5962-13220
The ENABLE feature allows the part to be placed into a low
shutdown current mode of 165µA (typ). When enabled the device
operates with a low ground current of 11mA (typ), which provides
for operation with Low Quiescent Power consumption.
The device has superior transient response and is designed
keeping Single Event Effects in mind. This results in reduction of
the magnitude of SET seen on the output. There is no need for
additional protection diodes and filters.
COMP pin is provided to enable the use of external
compensation. This is achieved by connecting a resistor and
capacitor from COMP to ground. The device is stable with
Tantalum capacitors as low as 47µF (KEMET T525 series) and
provides excellent regulation all the way from no Load to full
Load. The programmable soft-start allows one to program the
inrush current by means of the decoupling capacitor used on the
BYP pin. The OCP pin allows the short circuit output current limit
threshold to be programmed by means of a resistor from OCP pin
to GND. The OCP setting range is from a 0.16A min to 3.2A max.
The resistor sets the constant current threshold for the output
under fault conditions. The thermal shutdown disables the output
if the device temperature exceeds the specified value, it will
subsequently enter a ON/OFF cycle till the fault is removed.
Applications
• Input supply range 4.0V to 13.2V.
• Output Current up to 1.5A at a TJ = +150°C
• Best in class Accuracy ±1.5%
- Over line, load and temperature
• Ultra Low Dropout:
- 75mV Dropout (typ) @ 0.5A
- 225mV Dropout (typ) @ 1.5A
• Noise of 100µVRMS (typ) between 300Hz to 300kHz
• SET mitigation with no added filtering/diodes
• Shutdown Current of 165µA (typ)
• Externally adjustable Output Voltage
• PSRR 65dB (typ) @ 1kHz
• ENable and PGood Feature
• Programmable Soft-Start/In-rush Current Limiting
• Adjustable Overcurrent Protection
• Over-Temperature Shutdown
• Stable with 47µF Min Tantalum Capacitor
• Package 16 Ld Flat Pack
• Radiation Environment
- High Dose Rate (50-300rad(Si)/s) . . . . . . . . . 100krad(Si)
- Low Dose Rate (0.01rad(Si)/s). . . . . . . . . . . . 100krad(Si)*
- SET/SEL/SEB . . . . . . . . . . . . . . . . . . . . . . . . ..86 MeV.cm2/mg
*Product capability established by initial characterization. The
"EH" version is acceptance tested on a wafer-by-wafer basis to
50krad(Si) at low dose rate.
Related Literature
• LDO regulator for Space Power Systems
• DSP, FPGA and µP Core Power Supplies
See AN1850, "ISL75052SEH Evaluation Board User's Guide"
• Post Regulation of SMPS and Down Hole Drilling
See AN1851, "SEE Testing of the ISL75052SEH"
See AN1852, "Radiation Report of the ISL75052SEH"
0.30
EN
0.25
3,4,5
16
200µF
0.1µF
VOUT
1,2
BYP
ADJ
ISL75052SEH
VIN
15
8
OCP
EN
14
9
VCCX
GND
13
COMP
12
VOUT
2.5V
2.2k
10
0.1µF
0.1µF
PG
0.1µF
200µF
15.8k
2.2n
300Ω
DROPOUT (V)
VIN
+150°C
+125°C
0.20
25°C
0.15
0.10
22k
VIN
1nF
0.05
4.87k
22k
PG
FIGURE 1. TYPICAL APPLICATION
May 29, 2013
FN8456.0
1
0.00 0
0.5
1.0
ILOAD (A)
1.5
2.0
FIGURE 2. DROPOUT vs IOUT
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2013. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners
ISL75052SEH
Block Diagram
COMP
3.8V
LDO
VIN
OCP
VCCX
CURRENT
LIMIT
BYP
600mV
REFERENCE
BIAS
VOUT
POWER
PDMOS
THERMAL
SHUTDOWN
UVLO
EN
ADJ
PG
DELAY
540mV
GND
Typical Applications
1
VOUT
BYP
16
2
VOUT
ADJ
15
3
VIN
EN
14
4
VIN
GND
13
5
ISL75052SEH
COMP
VIN
12
6
NC
GND
11
7
NC
PG
10
8
OCP
VCCX
9
0.1µF
EN
VIN
100µF
100µF
VCCX
22k
0.1µF
10k
1nF
PG
300Ω
VOUT = 2.5V
15.8k
NC = No connect pin can be connected
to either VIN or GND
2.2k
0.1µF
100µF
100µF
2.2nF
4.87k
0.1µF
FIGURE 3.
2
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ISL75052SEH
Pin Configuration
ISL75052SEH
(16 Ld CDFP)
TOP VIEW
VOUT
1
16
BYP
VOUT
2
15
ADJ
VIN
3
14
EN
VIN
4
13
GND
VIN
5
12
NC
6
11
COMP
TMODE
NC
7
10
PG
OCP
8
9
VCCX
DOTTED LINE SHOWS METAL BOTTOM
Pin Descriptions
PIN NUMBER
PIN NAME
DESCRIPTION
3, 4, 5
VIN
Input supply pins.
10
PG
This pin is logic high when VOUT is in regulation signal. A logic low defines when VOUT Circuit 2
is not in regulation.
13
GND
GND pin. Pin 13 is also connected to the metal lid of the package.
9
VCCX
The 3.8V internal bus is pinned out to accept a decoupling capacitor. Connect a 0.1µF Circuit 2
ceramic capacitor from VCCX pin to GND.
1, 2
VOUT
Output voltage pins.
Circuit 1
12
COMP
Add compensation capacitor & resistor between COMP and GND.
Circuit 2
15
ADJ
ADJ pin allows VOUT to be programmed with an external resistor divider.
Circuit 2
6, 7
NC
No connect. May be grounded if needed.
Circuit 2
16
BYP
Connect a 0.1µF capacitor from BYP pin to GND, to filter the internal VREF.
Circuit 2
8
OCP
OCP pin allows the Current limit to be programmed with an external resistor.
Circuit 2
14
EN
VIN independent chip enable. TTL and CMOS compatible.
Circuit 2
11
TMODE
Test Mode pin, must be connected to GND.
Circuit 2
The metal surface on the bottom surface of the package is floating. For mounting
instructions see “Bottom Metal Mounting Guidelines” on page 8.
Circuit 2
Bottom
Metallization
PAD
Circuit 1
Circuit 2
PAD
ESD_CL_12V
GND
ESD_RC_7V
GND
ESD CIRCUIT 1
3
ESD CIRCUIT
ESD CIRCUIT 2
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ISL75052SEH
Ordering Information
ORDERING
NUMBER
INTERNAL
MKT. NUMBER
5962R1322001VXC
ISL75052SEHVFE
5962R1322001V9A
PART
MARKING
Q 5962R13 22001VXC
TEMP
RANGE (°C)
PACKAGE
(RoHS Compliant)
-55 to +125
16 Ld CDFP
ISL75052SEHVX
-55 to +125
Die
ISL75052SEHF/SAMPLE
ISL75052SEHX/SAMPLE
-55 to +125
Die Sample
ISL75052SEHFE/PROTO
ISL75052SEHFE/PROTO
-55 to +125
16 Ld CDFP
ISL75052SEHEV1ZB
Evaluation Board
ISL75052 SEHFE /PROTO
PKG DWG. #
K16.E
K16.E
NOTE:
1. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations.
4
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Absolute Maximum Ratings
Thermal Information
VIN Relative to GND without ion beam (Note 2) . . . . . . . . . . -0.3 to +16.0V
VIN Relative to GND under ion beam (Note 2) . . . . . . . . . . . -0.3 to +14.7V
VOUT Relative to GND (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +14.7V
PG,EN,OCP/ADJ,COMP,REFIN,REFOUT relative to GND (Note 2) . . . -0.3 to
+6.5VDC
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
16 Ld CDFP Package (Notes 5, 6) . . . . . . .
26
4.5
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions (Notes 3)
Ambient Temperature Range (TA) . . . . . . . . . . . . . . . . . . .-55°C to +125°C
Junction Temperature (TJ) (Note 2). . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
VIN Relative to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.0V to 13.2V
VOUT Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.5V to 12.7V
PG, EN, OCP/ADJ relative to GND . . . . . . . . . . . . . . . . . . . . . . . .0V to +5.5V
Radiation Information
Maximum Total Dose
High Dose(Dose Rate = 50 - 300radSi/s) . . . . . . . . . . . .100 krads (Si)
Low Dose(Dose Rate = 10milliradSi/s) (Note 4) . . . . . . 100 krads (Si)
SET (VOUT within ±5% During Events . . . . . . . . . . . . . . . .86MeV/mg/cm2
SEL/B (No Latchup/Burnout . . . . . . . . . . . . . . . . . . . . . . . . 86MeV/mg/cm2
The output capacitance used for SEE testing is 2x100µF for CIN and COUT,
100nF for BYPASS
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
2. Extended operation at these conditions may compromise reliability. Exceeding these limits will result in damage. Recommended operating conditions
define limits where specifications are guaranteed.
3. Refer to “Bottom Metal Mounting Guidelines” on page 8.
4. Product capability established by initial characterization. The "EH" version is acceptance tested on a wafer by wafer basis to 50 krad(Si) at low dose
rate.
5. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
TechBrief TB379
6. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
7. Electromigration specification defined as lifetime average junction temperature of +150°C where max rated DC current = lifetime average current.
Electrical Specifications Unless otherwise noted, all parameters are guaranteed over the following specified conditions:
VIN = VOUT + 0.5V, VOUT = 4.0V, CIN = COUT = 2x100µF 60mΩ, KEMET type T541X107N025AH or equivalent, TJ = +25°C, IL = 0A. Applications must follow
thermal guidelines of the package to determine worst case junction temperature. Please refer to “Applications Information” on page 7 of the data sheet
and Tech Brief TB379. Boldface limits apply over the operating temperature range, -55°C to +125°C. Pulse load techniques used by ATE to ensure TJ = TA
defines guaranteed limits.
PARAMETER
SYMBOL
MIN
(Note 8)
TYP
MAX
(Note 8)
UNITS
VOUT = 2.5V, 4.0V < VIN < 5.0V; 0A < ILOAD < 1.5A,
TJ = -55°C to +125°C
-1.5
0.2
1.5
%
VOUT = 2.5V, 4.0V < VIN < 5.0V; 0A < ILOAD < 1.5A,
TJ = +25°C, Post Rad.
-2.0
0.2
2.0
%
VOUT = 5.0V, 5.5V < VIN < 6.9V; 0A < ILOAD < 1.5A,
TJ = -55°C to +125°C
-1.5
0.2
1.5
%
VOUT = 5.0V, 5.5V < VIN < 6.9V, 0A < ILOAD < 1.5A,
TJ = +25°C, Post Rad.
-2.0
0.2
2.0
%
VOUT = 10.0V, 10.5V < VIN < 13.2V, ILOAD = 0A,
TJ =-55°C to +125°C
-1.5
0.2
1.5
%
VOUT = 10.0V, 10.5V < VIN < 13.2V, ILOAD = 0A,
TJ = +25°C, Post Rad.
-2.0
0.2
2.0
%
VOUT = 10.0V, VIN = 10.5V, ILOAD = 1.5A, VIN =13.2V,
ILOAD = 1.0A, TJ = -55°C to +125°C
-1.5
0.2
1.5
%
VOUT = 10.0V, VIN = 10.5V; ILOAD =1.5A, VIN =13.2V,
ILOAD = 1.0A, TJ = +25°C, Post Rad.
-2.0
0.2
2.0
%
TEST CONDITIONS
DC CHARACTERISTICS
DC Output Voltage Accuracy
VOUT
VOUT Resistor adjust to: 2.5V and 5.0V
VOUT Resistor adjust to: 10.0V
5
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ISL75052SEH
Electrical Specifications Unless otherwise noted, all parameters are guaranteed over the following specified conditions:
VIN = VOUT + 0.5V, VOUT = 4.0V, CIN = COUT = 2x100µF 60mΩ, KEMET type T541X107N025AH or equivalent, TJ = +25°C, IL = 0A. Applications must follow
thermal guidelines of the package to determine worst case junction temperature. Please refer to “Applications Information” on page 7 of the data sheet
and Tech Brief TB379. Boldface limits apply over the operating temperature range, -55°C to +125°C. Pulse load techniques used by ATE to ensure TJ = TA
defines guaranteed limits. (Continued)
PARAMETER
SYMBOL
VCCX Pin
VVCCX
TEST CONDITIONS
TJ = -55°C to +125°C; 4V < VIN < 13.2V; ILOAD = 0A;
MIN
(Note 8)
TYP
MAX
(Note 8)
UNITS
3.7
3.9
4.1
V
ADJ Pin
VADJ
TJ = -55°C to +125°C
591
600
609
mV
ADJ Pin
VADJ
TJ = 25°C, Post Rad
588
600
612
mV
BYP Pin
VBYP
4.0V < VIN < 13.2V; ILOAD=0A,
TJ = -55°C to +125°C
588
600
612
mV
DC Input Line Regulation
4.0V < VIN < 13.2V, VOUT = 2.5V
1
8
mV
DC Input Line Regulation
5.5V < VIN < 13.2V, VOUT = 5.0V
1
20
mV
DC Input Line Regulation
10.5V < VIN < 13.2V, VOUT = 10.0V
1
10
mV
DC Output Load Regulation
VOUT = 2.5V; 0A < ILOAD < 1.5A, VIN = 4.0V
0.3
9
mV
DC Output Load Regulation
VOUT = 5.0V; 0A < ILOAD < 1.5A, VIN = 5.5V
1.3
18
mV
DC Output Load Regulation
VOUT = 10.0V; 0A < ILOAD < 1.5A, VIN = 10.5V
0.1
36
mV
1
µA
6
10
mA
VADJ = 0.6V
ADJ Input Current
IQ
VOUT = 2.5V; ILOAD = 0A, 4.0V < VIN < 13.2V
Ground Pin Current
IQ
VOUT = 2.5V; ILOAD = 1.5A, 4.0V < VIN < 13.2V
8
12
mA
Ground Pin Current
IQ
VOUT = 10.0V, ILOAD = 0A, 11.0V < VIN < 13.2V
15
20
mA
IQ
Ground Pin Current
VOUT = 10.0V, ILOAD = 1.5A, 11.0V < VIN < 13.2V
20
25
mA
Ground Pin Current in Shutdown
ISHDNL
ENABLE Pin = 0V, VIN = 4.0V
70
120
µA
Ground Pin Current in Shutdown
ISHDNH
Ground Pin Current
ENABLE Pin = 0V, VIN = 13.2V
165
300
µA
Dropout Voltage (Note 10)
VDO
ILOAD = 0.5A, VOUT = 3.6V and 12.7V
75
160
mV
Dropout Voltage (Note 10)
VDO
ILOAD = 1.0A, VOUT = 3.6V and 12.7V
150
300
mV
Dropout Voltage (Note 10)
VDO
ILOAD = 1.5A, VOUT = 3.6V and 12.7V
225
400
mV
Output Short Circuit Current for 16
Ld FP
ISCL
VOUT SET = 4.0V, VOUT + 0.5V < VIN < 13.2V,
RSET = 3k, Note 12)
0.16
0.24
0.32
A
Output Short Circuit Current for 16
Ld FP
ISCH
VOUT SET = 4.0V, VOUT + 0.5V < VIN < 13.2V,
RSET = 300Ω, Note 12)
1.6
2.4
3.2
A
Thermal Shutdown Temperature
(Note 9)
TSD
VOUT + 0.5V < VIN < 13.2V
154
175
196
°C
Thermal Shutdown Hysteresis
(Rising Threshold) (Note 9)
TSDn
VOUT + 0.5V < VIN < 13.2V
25
°C
Input Supply Ripple Rejection
(Note 9)
PSRR
VP-P = 300mV, f = 1kHz, ILOAD = 1.5A;
VIN = 4.9V, VOUT = 4.0V
55
65
dB
Input Supply Ripple Rejection
(Note 9)
PSRR
VP-P = 300mV, f = 120Hz, ILOAD = 5mA;
VIN = 4.9V, VOUT = 2.5V
60
70
dB
Input Supply Ripple Rejection
(Note 9)
PSRR
VP-P = 300mV, f = 100kHz, ILOAD = 1.5A;
VIN = 4.9V, VOUT = 4.0V
40
50
dB
AC CHARACTERISTICS
Phase Margin, (Note 9)
PM
VOUT = 2.5V, 4.0V and 10V, COUT = 2x100µF,
RCOMP=22k, CCOMP = 1nF
50
°
Gain Margin, (Note 9)
GM
VOUT = 2.5V, 4.0V and 10V COUT = 2x100µF,
RCOMP = 22k, CCOMP = 1nF
10
dB
ILOAD = 10mA, BW = 300Hz < f < 300kHz, BYPASS to
GND capacitor = 0.2µF
Output Noise Voltage, (Note 9)
6
100
µVRMS
FN8456.0
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ISL75052SEH
Electrical Specifications Unless otherwise noted, all parameters are guaranteed over the following specified conditions:
VIN = VOUT + 0.5V, VOUT = 4.0V, CIN = COUT = 2x100µF 60mΩ, KEMET type T541X107N025AH or equivalent, TJ = +25°C, IL = 0A. Applications must follow
thermal guidelines of the package to determine worst case junction temperature. Please refer to “Applications Information” on page 7 of the data sheet
and Tech Brief TB379. Boldface limits apply over the operating temperature range, -55°C to +125°C. Pulse load techniques used by ATE to ensure TJ = TA
defines guaranteed limits. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 8)
TYP
MAX
(Note 8)
UNITS
0.5
0.8
1.2
V
1
µA
DEVICE START-UP CHARACTERISTICS
Enable Pin Characteristics
Turn-on Threshold
4.0V < VIN < 13.2V
Enable Pin Leakage Current
VIN = 13.2V, EN = 5.5V
Enable Pin Propagation Delay (EN
step 1.2V to VOUT = 100mV)
VIN = 4.5V, VOUT = 4.0V, ILOAD = 1.5A,
COUT = 22µF, CBYP = 0.2µF
0.5
1.0
ms
Enable Pin Turn-on Delay
(EN step 1.2V to PGOOD)
VIN = 4.5V, VOUT = 4.0V, ILOAD = 1.5A,
COUT = 2x100µF, CBYP = 0.2µF
1.4
3.0
ms
Enable Pin Turn-on Delay
(EN step 1.2V to PGOOD)
VIN = 4.5V, VOUT = 4.0V, ILOAD = 1.5A,
COUT = 22µF, CBYP = 0.2µF
1.1
2.5
ms
Hysteresis (Falling Threshold)
4.0V < VIN < 13.2V
75
170
mV
VOUT Error Flag Rising Threshold
83
88
94
%VOUT
VOUT Error Flag Falling Threshold
80
86
91
%VOUT
1.75
2.5
PG Pin Characteristics
VOUT Error Flag Hysteresis
Error Flag Low Voltage
%VOUT
ISINK = 1mA
5
100
mV
Error Flag Low Voltage
ISINK = 10mA
5
400
mV
Error Flag Leakage Current
VIN = 13.2V, PG = 5.5V
1
µA
8. Parameters with bold face MIN and/or MAX limits are 100% tested at -55°C, 25°C and 125°C.
9. Limits established by characterization and are not production tested.
10. Dropout is defined by the difference in supply VIN and VOUT when the supply produces a 2% drop in VOUT from its nominal value.
11. Refer to thermal package guidelines in “Bottom Metal Mounting Guidelines” on page 8..
12. OCP recovery overshoot should be within ±4% of the nominal VOUT setpoint.
13. SET performance of <±5% at LET = 86MeV.cm2/mg has been evaluated at VOUT = >2.5V with CIN = COUT = 2x100µF 10V 60mΩ in parallel with
0.1µF CDR04 X7R capacitor. Capacitor on BYP = 0.1µF CDR04 X7R.
Applications Information
Input Voltage Requirements
This RH LDO will work from a VIN in the range of 4.0V to 13.2V.
The input supply can have a tolerance of as much as ±10% for
conditions noted in the specification table. The minimum
guaranteed input voltage is 4.0V. However, due to the nature of
an LDO, VIN must be some margin higher than the output voltage
plus dropout at the maximum rated current of the application if
active filtering (PSRR) is expected from VIN to VOUT. The Dropout
spec of this family of LDOs has been generously specified in
order to allow design for efficient operation.
External Capacitor Requirements
GENERAL GUIDELINE
External capacitors are required for proper operation. Careful
attention must be paid to layout guidelines and selection of
capacitor type and value to ensure optimal performance.
7
OUTPUT CAPACITOR
It is recommended to use a combination of Tantalum and
Ceramic capacitors to achieve a good volume to capacitance
ratio. The recommended combination is a 2x100µF 60mΩ rated,
KEMET T541 series tantalum capacitor, in parallel with a 0.1µF
MIL-PRF-49470 ceramic capacitor to be connected to VOUT and
Ground pins of the LDO with PCB traces no longer than 0.5cm.
INPUT CAPACITOR
It is recommended to use a combination of Tantalum and
Ceramic capacitors to achieve a good capacitance to volume
ratio. The recommended combination is a 2x100µF 60mΩ rated,
KEMET T541 series tantalum capacitor in parallel with a 0.1µF
MIL-PRF-49470 ceramic capacitor to be connected to VIN and
Ground pins of the LDO with PCB traces no longer than 0.5cm.
Current Limit Protection
The RH LDO incorporates protection against overcurrent due to
any short or overload condition applied to the output pin. The
current limit circuit performs as a constant current source when
the output current exceeds the current limit threshold which can
be adjusted by means of a resistor connected between the OCP
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May 29, 2013
ISL75052SEH
pin and GND. If the short or overload condition is removed from
VOUT, then the output returns to normal voltage mode regulation.
In the event of an overload condition the LDO will begin to cycle
on and off due to the die temperature exceeding thermal fault
condition. However, one may never witness thermal cycling if the
heatsink used for the package can keep the die temperature
below the limits specified for thermal shutdown. The ROCP can
be calculated using the equation:
Bottom Metal Electrical Potential
The package bottom metal is electrically isolated and unbiased.
The bottom metal may be electrically connected to any potential
which offers the best thermal path through conductive mounting
materials (conductive epoxy, solder, etc.) or may be left unbiased
through the use of electrically non-conductive mounting
materials (non-conductive epoxy, Sil-pad, kapton film, etc.).
Bottom Metal Mounting Guidelines
(EQ. 1)
R OCP = 893 ⁄ I OCP
The package bottom is a solderable metal surface. The following
JESD51-5 guidelines may be used to mount the package:
Where:
• Place a thermal land on the PCB under the bottom metal.
ROCP = The OCP resistor value in ohms.
• The land should be approximately the same size to 1mm
larger than the 0.19x0.41inch bottom metal.
IOCP = The required OCP threshold in amps.
ESD Clamps
• Place an array of thermal vias below the thermal land.
• Via array size: ~4 x 9 = 36 thermal vias
The ESD_CL_12V ESD clamps break down at nominally 17V. The
ESD_RC_7V clamps break down at nominally 7.5V with a
tolerance of ±10%. The PG pin has a diode to GND. The VOUT pin
has a diode to VIN (see “Pin Descriptions” on page 3).
• Via diameter: ~0.3mm drill diameter with plated copper on
the inside of each via.
• Via pitch: ~1.2mm.
Vias should drop to and contact as much buried metal area as
feasible to provide the best thermal path.
COMP Pin
This pin helps compensate the device for various load conditions.
For 4.0V < VIN < 6.0V use RCOMP = 40k and CCOMP = 1nF. For
6V < VIN < 13.2V use RCOMP = 40k and CCOMP = 4.7nF. The
max current of the COMP pin when shorted to GND is 160µA.
Undervoltage Lockout
The undervoltage lockout function detects when VCCX exceeds
3.2V. When that level is reached, the LDO feedback loop is
closed and the LDO can begin regulating. This is achieved by
freeing the BYP net to charge up and act as a reference voltage
to the EA. Prior to that happening, the LDO Power PMOS device is
clamped off.
8
Thermal Fault Protection
In the event the die temperature exceeds +170°C (typ.) the
output of the LDO will shut down until the die temperature can
cool down to +150°C (typ.). The level of power combined with the
thermal impedance of the package (θJC of 5°C/W for the 16 Ld
CDFP package) will determine if the junction temperature
exceeds the thermal shutdown temperature specified in the
specification table (see “Bottom Metal Mounting Guidelines” on
page 8).
FN8456.0
May 29, 2013
ISL75052SEH
Typical Operating Performance
2.605
10.35
2.600
10.30
2.595
10.25
VOUT AT 25°C
2.585
VIN = 12V
VOUT (V)
VOUT (V)
2.590
2.580
2.575
2.570
VOUT AT 125°C
10.15
10.10
VOUT AT -55°C
VIN = 13.2V
VIN = 14.7V
2.565
10.05
2.560
2.555
0
VIN = 10.8V
10.20
2
4
6
8
10
VIN (V)
12
14
16
10.00
18
FIGURE 4. LINE REGULATION vs TEMPERATURE (°C),
VOUT = 2.579V, IOUT = 0mA
0
0.2
0.4
0.6
0.8
IOUT (A)
1.0
10.35
10.30
10.30
10.25
10.25
VOUT (V)
VOUT (V)
VIN = 12V
VIN = 12V
VIN = 10.8V
10.15
VIN = 14.7V
10.05
VIN = 13.2V
10.20
VIN = 14.7V
10.15
10.00
0.2
0.4
0.6
0.8
IOUT (A)
1.0
1.2
1.4
1.6
VIN = 13.2V
0
0.2
0.4
2.61
2.61
2.60
2.60
2.59
VIN = 4.5V
VIN = 4.0V
2.57
2.56
2.55
VIN = 5.5V
2.55
VIN = 5.0V
2.54
2.53
0.6
0.8
IOUT (A)
1.0
1.2
1.4
FIGURE 6A. LOAD REGULATION VOUT = 2.567V AT 25°C
9
1.2
1.4
1.6
VIN = 12V
VIN = 10.5V
2.56
2.53
0.4
1.0
2.57
2.54
0.2
0.8
IOUT (A)
2.58
VOUT (V)
2.58
0.6
FIGURE 5C. LOAD REGULATION VOUT = 10.22V AT -55°C
2.59
VOUT (V)
VIN = 10.8V
10.05
FIGURE 5B. LOAD REGULATION VOUT = 10.13V AT 125°C
2.52
0
1.6
10.10
10.10
10.00
0
1.4
FIGURE 5A. LOAD REGULATION VOUT = 10.17V AT 25°C
10.35
10.20
1.2
1.6
2.52
0
VIN = 14.7V
0.2
0.4
VIN = 13.2V
0.6
0.8
IOUT (A)
1.0
1.2
1.4
1.6
FIGURE 6B. LOAD REGULATION VOUT = 2.571V AT 125°C
FN8456.0
May 29, 2013
ISL75052SEH
Typical Operating Performance (Continued)
2.61
13.00
2.60
12.95
2.59
12.90
VIN = 12V
12.85
VIN = 10.5V
12.80
VOUT (V)
VOUT (V)
2.58
2.57
2.56
2.55
VIN = 14.7V
12.70
12.65
VIN = 13.2V
2.54
12.55
0
0.2
0.4
0.6
0.8
IOUT (A)
1.0
1.2
1.4
12.50
1.6
FIGURE 6C. LOAD REGULATION VOUT = 2.564V AT -55°C
13.00
13.00
12.95
12.95
12.90
12.90
12.85
12.85
12.80
12.80
12.75
VIN = 16.2V
VIN = 13.2V
12.70
VIN = 14.7V
12.65
12.60
12.55
12.55
0.2
0.4
0.6
0.8
IOUT (A)
1.0
1.2
1.4
0.4
0.6
0.8
IOUT (A)
1.0
1.2
1.4
1.6
1.6
FIGURE 7B. LOAD REGULATION VOUT = 12.63V AT 125°C
VIN = 13.2V
12.50
VIN = 16.2V
0
0.2
0.4
0.6
0.8
IOUT (A)
1.0
1.2
1.4
1.6
FIGURE 7C. LOAD REGULATION VOUT = 12.7V AT -55°C
Timebase = 500µs/DIV
VOUT = 20mV/DIV
VIN = 14.7V
12.70
12.60
0
0.2
12.75
12.65
12.50
0
FIGURE 7A. LOAD REGULATION VOUT = 12.75V AT 25°C
VOUT (V)
VOUT (V)
VIN = 16.2V
12.60
2.53
2.52
VIN = 13.2V
VIN = 14.7V
12.75
Timebase = 500µs/DIV
VOUT = 20mV/DIV
IOUT = 500mA/DIV
FIGURE 8. LOAD STEP RESPONSE, 25°C, VIN = 4.0V, VOUT = 2.5V,
IOUT = 0A to 1.6A, COUT = 200µF, 30mΩ
10
IOUT = 500mA/DIV
FIGURE 9. LOAD STEP RESPONSE, 25°C, VIN = 4.0V, VOUT = 2.5V,
IOUT = 0.15A to 1.6A, COUT = 200µF, 30mΩ
FN8456.0
May 29, 2013
ISL75052SEH
Typical Operating Performance (Continued)
Timebase = 500µs/DIV
Timebase = 500µs/DIV
VOUT = 50mV/DIV
VOUT = 50mV/DIV
IOUT = 500mA/DIV
IOUT = 500mA/DIV
180
60
150
50
120
40
120
90
30
90
60
20
60
10
30
30
0
-30
GAIN (dB)
500
5k
50k
500k
180
150
PHASE (°)
0
0
-10
-30
GAIN (dB)
PHASE (°)
PHASE (°)
FIGURE 9B. LOAD STEP RESPONSE, 25°C, VIN = 13.2V, VOUT = 10V,
IOUT = 0.15A to 1.5A, COUT = 200µF, 30mΩ
GAIN (dB)
70
60
50
40
30
20
10
0
-10
-20
-30
-40
-50
-60
-70
PHASE (°)
GAIN (dB)
FIGURE 9A. LOAD STEP RESPONSE, 25°C, VIN = 13.2V, VOUT = 10V,
IOUT = 0A to 1.5A, COUT = 200µF, 30mΩ
-60
-20
-60
-90
-30
-90
-120
-40
-120
-150
-50
-150
-180
-60
500
5k
FREQUENCY (Hz)
50k
500k
-180
FREQUENCY (Hz)
FIGURE 10. GAIN PHASE PLOTS, VIN = 4V, VOUT = 2.5V, IOUT = 0.2A,
RCOMP = 22k, CCOMP = 1nF, COUT = 200µF, 30mΩ,
PHASE MARGIN = 98.68°, GAIN MARGIN = 23.01dB
FIGURE 11. GAIN PHASE PLOTS, VIN = 4V, VOUT = 2.5V, IOUT = 1.5A,
RCOMP = 22k, CCOMP = 1nF, COUT = 200µF, 30mΩ,
PHASE MARGIN = 84.56°, GAIN MARGIN = 18.06dB
-30
-40
125°C PSRR (dB)
PSRR (dB)
-50
-60
-70
25°C PSRR (dB)
-80
-55°C PSRR (dB)
-90
-100
100
1k
10k
100k
FREQUENCY (Hz)
FIGURE 12. PSRR, VIN = 4.9V, VOUT = 4.0V, IOUT = 1.5A, RCOMP = 22k, CCOMP = 1nF, COUT = 200µF, 30mΩ
11
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ISL75052SEH
Typical Operating Performance (Continued)
Timebase = 1ms/DIV
C1 to C4 = 1V/DIV
Timebase = 1ms/DIV
C1 to C4 = 1V/DIV
EN
EN
VIN
VIN
VOUT
VOUT
PGOOD
PGOOD
FIGURE 13. 25°C START-UP WITH ENABLE, VIN = 4V, VOUT = 2.5V,
IOUT = 0.1A
FIGURE 14. 25°C START-UP WITH ENABLE, VIN = 4V, VOUT = 2.5V,
IOUT = 1.5A
Timebase = 5ms/DIV
C1 to C4 = 1V/DIV
VOUT
Timebase = 5ms/DIV
C1 to C4 = 1V/DIV
VOUT
VIN
VIN
PGOOD
PGOOD
EN
EN
FIGURE 15. 25°C SHUTDOWN WITH ENABLE, VIN = 4V, VOUT = 2.5V,
IOUT = 0.1A
FIGURE 16. 25°C SHUTDOWN WITH ENABLE, VIN = 4V, VOUT = 2.5V,
IOUT = 1.5A
Timebase = 200µs/DIV
EN
VIN
VOUT
PGOOD
FIGURE 17. 25°C PROPAGATION DELAY, VIN = 4.5V, VOUT = 4V, IOUT = 1.5A, EN 50% TO VOUT 5%
12
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Package Characteristics
Weight of Packaged Device
0.59 Grams (Typical)
TOP METALLIZATION
Type: AlCu (99.5%/0.5%)
Thickness: 2.7µm ± 0.4µm
SUSTRATE
Lid Characteristics
Type: Silicon
Finish: Gold
Potential: Connected to Pin 13 (GND)
Case Isolation to Any Lead: 20 x 109 Ω (min)
Die Characteristics
BACKSIDE FINISH
Silicon
ASSEMBLY RELATED INFORMATION
SUBSTRATE POTENTIAL
Die Dimensions
2819μm x 5638μm (111 mils x 222 mils).
Thickness: 304.8μm ± 25.4μm (12.0 mils ± 1 mil).
Interface Materials
Ground
ADDITIONAL INFORMATION
WORST CASE CURRENT DENSITY
< 2 x 105 A/cm2
GLASSIVATION
Type: Silicon Oxide and Silicon Nitride
Thickness: 0.3µm ± 0.03µm to 1.2µm ± 0.12µm
TRANSISTOR COUNT
1074
PROCESS
0.6µm BiCMOS Junction Isolated
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ISL75052SEH
Metallization Mask Layout
TABLE 1. DIE LAYOUT X-Y COORDINATES
PAD
X
Y
DX
DY
PIN
NAME
PIN#
1
1019
1021
185
450
VOUT
1,2
2
1249
390
185
449
VOUT
1,2
3
2764
1354
5508
2689
VIN
3,4,5
4
3070
1030
185
450
VIN
3,4,5
5
3300
399
185
450
VIN
3,4,5
6
5037
256
185
185
OCP
8
7
5253
1635
185
185
VCCX
9
8
5099
2436
185
185
PG
10
9
4635
2436
185
185
TMODE
11
10
3824
2436
185
185
COMP
12
11
2840
1660
185
450
VIN
3,4,5
12
1799
2436
185
185
GND
13
13
668
2436
185
185
EN
14
14
168
2381
185
185
ADJ
15
15
168
1972
185
184
BYP
16
16
789
1652
185
450
VOUT
1,2
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
14
FN8456.0
May 29, 2013
ISL75052SEH
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that
you have the latest revision.
DATE
REVISION
May 29, 2013
FN8456.0
CHANGE
Initial Release
About Intersil
Intersil Corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management
semiconductors. The company's products address some of the largest markets within the industrial and infrastructure, personal
computing and high-end consumer markets. For more information about Intersil, visit our website at www.intersil.com.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting
www.intersil.com/en/support/ask-an-expert.html. Reliability reports are also available from our website at
http://www.intersil.com/en/support/qualandreliability.html#reliability
15
FN8456.0
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ISL75052SEH
Package Outline Drawing
K16.E
16 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
Rev 1, 1/12
0.015 (0.38)
0.008 (0.20)
PIN NO. 1
ID OPTIONAL
1
2
A
A
0.050 (1.27 BSC)
PIN NO. 1
ID AREA
0.420
0.400
0.005 (0.13)
MIN
4
TOP VIEW
0.022 (0.56)
0.015 (0.38)
0.115 (2.92)
0.085 (2.16)
0.045 (1.14)
0.026 (0.66)
6
0.009 (0.23)
0.004 (0.10)
0.278 (7.06)
0.262 (6.65)
-D-
0.198 (5.03)
0.182 (4.62)
0.370 (9.40)
0.250 (6.35)
-H-
-C-
BOTTOM
METAL
0.03 (0.76) MIN
7
SEATING AND
BASE PLANE
SIDE VIEW
BOTTOM METAL
0.005 (0.127) REF.
OFFSET FROM
CERAMIC EDGE
OPTIONAL
PIN 1 INDEX
BOTTOM VIEW
NOTES:
0.006 (0.15)
0.004 (0.10)
LEAD FINISH
0.009 (0.23)
BASE
METAL
0.004 (0.10)
0.019 (0.48)
0.015 (0.38)
3. The maximum limits of lead dimensions (section A-A) shall be
measured at the centroid of the finished lead surfaces, when solder
dip or tin plate lead finish is applied.
4. Measure dimension at all four corners.
0.0015 (0.04)
MAX
5. For bottom-brazed lead packages, no organic or polymeric materials
shall be molded to the bottom of the package to cover the leads.
0.022 (0.56)
0.015 (0.38)
3
SECTION A-A
1. Index area: A notch or a pin one identification mark shall be located
adjacent to pin one and shall be located within the shaded area shown.
The manufacturer’s identification shall not be used as a pin one
identification mark. Alternately, a tab may be used to identify pin one.
2. If a pin one identification mark is used in addition to a tab, the limits
of the tab dimension do not apply.
6. Dimension shall be measured at the point of exit (beyond the
meniscus) of the lead from the body. Dimension minimum shall
be reduced by 0.0015 inch (0.038mm) maximum when solder dip
lead finish is applied.
7. The bottom of the package is a solderable metal surface.
8. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
9. Dimensions: INCH (mm). Controlling dimension: INCH.
16
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May 29, 2013