HV230/HV232 Low Charge Injection 8-Channel High Voltage Analog Switches with Bleed Resistors Features ► ► ► ► ► ► ► ► ► ► ► General Description HVCMOS® technology for high performance Very low quiescent power dissipation – 10µA Output On-resistance typically 22Ω Integrated bleed resistors on the outputs Low parasitic capacitances DC to 10MHz analog signal frequency -60dB typical output off isolation at 5.0MHz CMOS logic circuitry for low power Excellent noise immunity On-chip shift register, latch and clear logic circuitry Flexible high voltage supplies Applications The Supertex HV230 and HV232 are low charge injection 8channel high-voltage analog switch integrated circuits(ICs) with bleed resistors. These devices can be used in applications requiring high voltage switching controlled by low voltage control signals, such as ultrasound imaging and printers. The bleed resistors eliminate voltage built up on capacitive loads such as piezoelectric transducers. Input data is shifted into an 8-bit shift register which can then be retained in an 8-bit latch. To reduce any possible clock feed-through noise, Latch Enable Bar (LE) should be left high until all bits are clocked in. Using HVCMOS technology, this switch combines high voltage bilateral DMOS switches and low power CMOS logic to provide efficient control of high voltage analog signals. ► Medical ultrasound imaging ► Piezoelectric transducer drivers These ICs are suitable for various combinations of high voltage supplies, e.g., VPP/VNN: +50V/–150V, or +100V/–100V. Block Diagram Latches DIN Level Shifters Output Switches D LE CL SW0 D LE CL SW1 D LE CL SW2 D LE CL SW3 D LE CL SW4 D LE CL SW5 D LE CL SW6 D LE CL SW7 CLK 8-Bit Shift Register DOUT VDD LE CL VNN VPP RGND HV230/HV232 Ordering Information Package Options Device 28-Lead PLCC 48-Lead LQFP/TQFP (1.4mm) HV230 - - HV232PJ HV232FG HV232PJ-G HV232FG-G HV232 26-Lead BCC 26-Ball fpBGA - HV230GA HV230B1-G HV230GA-G - - -G indicates the part is RoHS compliant (Green) Absolute Maximum Ratings Parameter Value VDD logic power supply voltage -0.5V to +15V VPP - VNN supply voltage 220V VPP positive high voltage supply -0.5V to VNN +200V VNN negative high voltage supply +0.5V to -200V Logic input voltages -0.5V to VDD +0.3V Analog signal range VNN to VPP Peak analog signal current/channel 3.0A O -65 C to +150OC Storage temperature Power dissipation: 28-Lead PLCC 48-Lead LQFP/TQFP(1.4mm) 26-Lead BCC 26-Ball fpBGA 1.2W 1.0W 1.0W 1.0W Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Operating Conditions Symbol Parameter Value VDD Logic power supply voltage 1,3 4.5V to 13.2V VPP 1,3 40V to VNN +200V positive high voltage supply 1,3 VNN negative high voltage supply VIH High level input voltage VDD -1.5V to VDD VIL Low-level input voltage 0V to 1.5V VSIG Analog signal voltage peak-to-peak TA -40V to -160V VNN +10V to VPP -10V2 0OC to 70OC Operating free air temperature Notes: 1. Power up/down sequence is arbtrary except GND must be powered -up first and powered down last. 2. VSIG must be VNN ≤ VSIG ≤ VPP or floating during power up/down transition. 3. Rise and fall times of power supplies VDD, VPP, and VNN should not be less than 1.0msec. 2 HV230/HV232 Electrical Characteristics DC Characteristics (over recommended operating conditions unless otherwise noted) Characteristics Small Signal Switch (ON) Resistance Sym 0°C min max RONS Small Signal Switch (ON) Resistance Matching ∆RONS Large Signal Switch (ON) Resistance RONL Output Switch Shunt Resistance RINT Switch Off Leakage Per Switch ISOL +25°C typ* max 30 26 38 48 ISIG = 5mA 25 22 27 32 ISIG = 200mA VNN = -160V 25 22 27 30 18 18 24 27 ISIG = 200mA VNN = -100V 23 20 25 30 ISIG = 5mA 22 16 25 27 ISIG = 200mA VNN = -40V 20 5.0 20 20 min +70°C min max 15 20 Units Ω Test Conditions ISIG = 5mA VPP = 40V, VPP = 100V, VPP = 160V, % ISW = 5mA, VPP = 100V, VNN = -100V Ω VSIG = VPP - 10V, ISIG = 1A KΩ Output switch to RGND IRINT = 0.5mA 15 µA VSIG = VPP - 10V 300 300 mV No Load 100 500 500 mV No Load 35 50 5.0 1.0 10 DC Offset Switch Off 300 100 DC Offset Switch On 500 Pos. HV Supply Current IPPQ 10 50 µA ALL SWs OFF Neg. HV Supply Current INNQ -10 -50 µA ALL SWs OFF Pos. HV Supply Current IPPQ 10 50 µA ALL SWs ON, ISW = 5mA Neg. HV Supply Current INNQ -10 -50 µA ALL SWs ON, ISW = 5mA 3.0 2.0 A VSIG duty cycle - 0.1% Switch Output Peak Current Output Switch Frequency IPP Supply Current INN Supply Current 3.0 2.0 50 fSW IPP INN KHz Duty Cycle = 50% 6.5 7.0 8.0 VPP = 40V, VNN = -160V 4.0 5.0 5.5 4.0 5.0 5.5 VPP = 160V, VNN = -40V 6.5 7.0 8.0 VPP = 40V, VNN = -160V 4.0 5.0 5.5 4.0 5.0 5.5 mA mA VPP = 100V, VNN = -100V 50KHz Output Switching Frequency with no load VPP = 100V, VNN = -100V VPP = 160V, VNN = -40V Logic Supply Average Current IDD 4.0 4.0 4.0 mA Logic Supply Quiescent Current IDDQ 10 10 10 µA Data Out Source Current ISOR 0.45 0.45 0.70 0.40 mA VOUT = VDD - 0.7V Data Out Sink Current ISINK 0.45 0.45 0.70 0.40 mA VOUT = 0.7V Logic Input Capacitance CIN 10 10 *Typical values only for HV232 3 10 pF fCLK = 5MHz, VDD = 5.0V HV230/HV232 Electrical Characteristics AC Characteristics (over operating conditions VDD = 5V, unless otherwise noted) Characteristics Sym 0°C min +25°C max min typ* +70°C max min max Units Set Up Time Before LE Rises tSD 150 150 150 ns Time Width of LE tWLE 150 150 150 ns Clock Delay Time to Data Out tDO 55 Time Width of CL tWCL 150 150 Set Up Time Data to Clock tSU 15 15 Hold Time Data from Clock th 35 35 150 60 150 8.0 70 150 Test Conditions ns 150 ns 20 ns 35 ns Clock Freq fCLK 5.0 5.0 5.0 MHz Clock Rise and Fall Times tr, tf 1.0 1.0 1.0 µs Turn On Time tON 5.0 5.0 5.0 µs VSIG = VPP -10V, RL = 10KΩ Turn Off Time tOFF 5.0 5.0 5.0 µs VSIG = VPP -10V, RL = 10KΩ 20 20 20 20 20 20 20 20 20 Maximum VSIG Slew Rate Off Isolation Switch Crosstalk Output Switch Isolation Diode Current dv/dt KO KCR -30 -30 -58 -58 -60 -60 -33 -70 300 IID 50% duty cycle fDATA = fCLK/2 VPP = 160V, VNN = -40V V/ns VPP = 100V, VNN = -100V VPP = 40V, VNN = -160V -30 dB f = 5MHz, 1KΩ//15pF load -58 dB f = 5MHz, 50Ω load -60 dB f = 5MHz, 50Ω load 300 mA 300ns pulse width, 2.0% duty cycle 300 Off Capacitance SW to GND CSG(OFF) 5.0 17 5.0 12 17 5.0 17 pF 0V, 1MHz On Capacitance SW to GND CSG(ON) 25 50 25 38 50 25 50 pF 0V, 1MHz *Typical values only for HV232 Electrical Characteristics AC Characteristics (over operating conditions VDD = 5V, unless otherwise noted) Characteristics Output Voltage Spike Sym +25°C min Units typ* max +VSPK 150 -VSPK 150 +VSPK 150 -VSPK 150 +VSPK 150 -VSPK 150 *Typical values only for HV232 4 mV Test Conditions VPP = 40V, VNN = -160V, RL = 50Ω VPP = 100V, VNN = -100V, RL = 50Ω VPP = 160V, VNN = -40V, RL = 50Ω HV230/HV232 Truth Table D0 D1 D2 D3 D4 D5 D6 D7 LE CL SW0 SW1 SW2 SW3 SW4 SW5 SW6 SW7 L L L L L L L L L L L L L L L L L H OFF ON L H X X L L L L L L L L L L L L L L L L H X L H L H L H L H L H L H L H X X X X X X X X X X X X X X OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON HOLD PREVIOUS STATE OFF OFF OFF OFF OFF OFF OFF OFF Notes: 1. The eight switches operate independently. 2. Serial data is clocked in on the L to H transition CLK. 3. The switches go to a state retaining their present condition at the rising edge of LE. When LE is low the shift register data flows through the latch. 4. DOUT is high when data in shift register 7 is high. 5. Shift register clocking has no effect on the switch states if LE is H. 6. The clear input overrides all other inputs. Logic Timing Waveforms DN + 1 D DN DATA IN 50% N-1 50% LE 50% 50% t WLE t SD CLOCK 50% 50% t t SU t DATA OUT DD 50% t VOUT OFF t ON OFF 90% (TYP) 10% ON 50% CLR h 50% t WCL 5 HV230/HV232 Test Circuits VPP –10V VPP –10V RL ISOL 10KΩ VOUT VOUT Open Open RGND RGND VPP VNN RGND VPP VDD VNN GND 5V VPP VPP VDD VNN VNN GND 5V VPP VPP VDD VNN VNN GND TON /TOFF Test Circuit DC Offset ON/OFF Switch OFF Leakage 5V VIN = 10 VP–P @5MHz VIN = 10 VP–P @5MHz VSIG IID VOUT 50Ω NC VNN RL 50Ω RGND RGND RGND VPP VPP VNN VNN VDD VPP 5V VNN GND KO = 20Log VPP 5V VDD VNN VDD VPP VPP VNN VNN GND GND VOUT VIN KCR = 20Log OFF Isolation Isolation Diode Current ∆VOUT Crosstalk +VSPK VOUT VOUT –VSPK 1000pF 50Ω RGND VSIG 1KΩ RGND VPP VPP VDD VNN VNN GND 5V RL VPP VPP VDD VNN VNN GND Q = 1000pF x ∆VOUT Charge Injection Output Voltage Spike 6 VOUT VIN 5V 5V HV230/HV232 28-Lead (J-Lead) PLCC Package Outline (PJ) 0.450 ± 0.005 (11.430 ± 0.127) 1 4 Pin Description 0.020 min. (0.508) 0.1725 ± 0.0075 (4.3815 ± 0.1905) 25 0.027 ± 0.003 (0.6858 ± 0.0762) 0.480 ± 0.010 (12.192 ± 0.254) 0.410 ± 0.010 (10.414 ± 0.254) B. C. of Bend Radii 11 18 0.050 ± 0.010 (1.270 ± 0.254) Measurement Legend = 0.110 ± 0.010 (2.794 ± 0.254) Function 1 SW3 15 N/C 2 SW3 16 DIN 3 SW2 17 CLK 4 SW2 18 LE 5 SW1 19 CL 6 SW1 20 DOUT 7 SW0 21 SW7 8 SW0 22 SW7 N/C 23 SW6 Dimensions in Inches VPP 24 SW6 (Dimensions in Millimeters) 11 RGND 25 SW5 7.00 ± 0.20 0.22 ± 0.05 9.00 ± 0.20 7.00 ± 0.20 48 1 1.75 nom 0.50 BSC (4 places) Top View 0.09 - 0.20 1.40 ± 0.05 0.05 - 0.15 Pin 9 9.00 ± 0.20 1.60 max Function 10 48-Lead LQFP/TQFP (1.4mm) Package Outline (FG) 1.75 nom Pin 0O - 7O 0.45 - 0.75 Side View Linear dimensions in millimeters. Angular dimensions in degrees Pin 1 identifier located within the area indicated Corner shape may differ from . drawing. 7 12 VNN 26 SW5 13 GND 27 SW4 14 VDD 28 SW4 Pin Description Pin Function Pin Function 1 SW5 25 VNN 2 N/C 26 N/C 3 SW4 27 RGND 4 N/C 28 GND 5 SW4 29 VDD 6 N/C 30 N/C 7 N/C 31 N/C 8 SW3 32 N/C 9 N/C 33 DIN 10 SW3 34 CLK 11 N/C 35 LE 12 SW2 36 CLR 13 N/C 37 DOUT 14 SW2 38 N/C 15 N/C 39 SW7 16 SW1 40 N/C 17 N/C 41 SW7 18 SW1 42 N/C 19 N/C 43 SW6 20 SW0 44 N/C 21 N/C 45 SW6 22 SW0 46 N/C 23 N/C 47 SW5 24 VPP 48 N/C HV230/HV232 26-Ball fpBGA Package Outline (GA) Pin Configuration A1 Indicator Top View 6.00±0.10 3.00 A1 Indicator 2.68 5.35±0.10 0.65 1.70 1.70 0.65 Φ0.33±0.05 Bottom View 0.80±0.05 Enlarged Side View 1.0±0.10 0.20±0.05 Note: All dimensions are in millimeters 8 Ball Location Function A4 SW1 C3 SW2 C4 SW1 C5 SW0 C6 VPP C7 VNN D1 SW3 D3 SW3 D4 SW2 D5 SW0 D6 RGND D7 GND D9 VDD E1 SW4 E3 SW4 E4 SW5 E5 SW7 E6 LE E7 CLK E9 DIN F3 SW5 F4 SW6 F5 SW7 F6 DOUT F7 CLR H4 SW6 HV230/HV232 26-Lead BCC Package Outline (B1) Pin Description HV230B1 Package Outline 6.00±0.10 1.05 0.40 0.10 0.725 0.925 18 Pin 1 0.65 4.15 6.00±0. 0.35±0.10 Pin 2 10 0.925 0.725 0.389 0.35±0.10 1.06 4.55 Pin Function 1 SW4 2 SW3 3 SW3 4 SW2 5 SW2 6 SW1 7 SW1 8 SW0 9 SW0 10 VPP 11 VNN 12 RGND 13 GND 14 VDD 15 DIN 16 CLK 17 LE Top View 18 CLR Pad connections are on the backside of the package. 19 DOUT 20 SW7 21 SW7 22 SW6 23 SW6 24 SW5 25 SW5 26 SW4 0.8mm Max 0.075±0.025 (Standoff ) Side View (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Doc.# DSFP-HV230_HV232 A111006 9