TI1 DS90UR124 5-mhz to 43-mhz dc-balanced 24-bit fpd-link ii serializer and deserializer chipset Datasheet

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DS90UR124-Q1, DS90UR241-Q1
SNLS231O – SEPTEMBER 2006 – REVISED APRIL 2015
DS90URxxx-Q1 5-MHz to 43-MHz DC-Balanced 24-Bit FPD-Link II Serializer and
Deserializer Chipset
1 Features
2 Applications
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Supports Displays With 18-Bit Color Depth
5-MHz to 43-MHz Pixel Clock
Automotive-Grade Product AEC-Q100 Grade 2
Qualified
24:1 Interface Compression
Embedded Clock With DC Balancing Supports
AC-Coupled Data Transmission
Capable to Drive up to 10 Meters Shielded
Twisted-Pair Cable
No Reference Clock Required (Deserializer)
Meets ISO 10605 ESD – Greater than 8 kV HBM
ESD Structure
Hot Plug Support
EMI Reduction – Serializer Accepts Spread
Spectrum Input; Data Randomization and
Shuffling on Serial Link; Deserializer Provides
Adjustable PTO (Progressive Turnon) LVCMOS
Outputs
@Speed BIST (Built-In Self-Test) to Validate
LVDS Transmission Path
Individual Power-Down Controls for Both
Transmitter and Receiver
Power Supply Range 3.3 V ±10%
48-Pin TQFP Package for Transmitter and 64-Pin
TQFP Package for Receiver
Temperature Range: –40°C to 105°C
Backward-Compatible Mode With
DS90C241/DS90C124
Automotive Central Information Displays
Automotive Instrument Cluster Displays
Automotive Heads-Up Displays
Remote Camera-Based Driver Assistance
Systems
3 Description
The DS90URxxx-Q1 chipset translates a 24-bit
parallel bus into a fully transparent data/control FPDLink II LVDS serial stream with embedded clock
information. This chipset is ideally suited for driving
graphical data to displays requiring 18-bit color depth:
RGB666 + HS, VS, DE + three additional generalpurpose data channels. This single serial stream
simplifies transferring a 24-bit bus over PCB traces
and cable by eliminating the skew problems between
parallel data and clock paths. The device saves
system cost by narrowing data paths that in turn
reduce PCB layers, cable width, and connector size
and pins.
The DS90URxxx-Q1 incorporates FPD-Link II LVDS
signaling on the high-speed I/O. FPD-Link II LVDS
provides a low-power and low-noise environment for
reliably transferring data over a serial transmission
path. By optimizing the Serializer output edge rate for
the operating frequency range, EMI is further
reduced.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
DS90UR124-Q1
TQFP (64)
10.00 mm × 10.00 mm
DS90UR241-Q1
TQFP (48)
7.00 mm × 7.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Applications Diagram
Block Diagram
Display
Host
DE
VSYNC
TRFB
(LVCMOS)
TCLK
TPWDNB
PLL
Timing
and
Control
SERIALIZER ± DS90UR241
DOUT-
RIN+
RIN-
RAOFF
RRFB
RPWDNB
BISTEN
BISTM
SLEW
PTOSEL
PLL
Output Latch
DIN
DOUT+
Serial to Parallel
HSYNC
24
DC Balance Decoder
LCD
Clock
RT = 100:
(LVCMOS)
(LVDS)
RGB Data
DS90UR124
Deserializer
RT = 100:
VSYNC
1 Pair
Parallel to Serial
HSYNC
DS90UR241
Serializer
Input Latch
RGB Data
Clock
REN
DE
FPD-Link II
DC Balance Encoder
Video
Source
VODSEL
PRE
DEN
RAOFF
(Infotainment, Instrument Cluster, CID)
(Graphics/Video Processor, ECU)
Timing
and
Control
Clock
Recovery
24
ROUT
LOCK
RCLK
PASS
DESERIALIZER ± DS90UR124
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DS90UR124-Q1, DS90UR241-Q1
SNLS231O – SEPTEMBER 2006 – REVISED APRIL 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
8
1
1
1
2
3
3
7
Absolute Maximum Ratings ...................................... 7
ESD Ratings.............................................................. 7
Recommended Operating Conditions....................... 7
Thermal Information .................................................. 8
Electrical Characteristics........................................... 8
Serializer Input Timing Requirements for TCLK ..... 10
Serializer Switching Characteristics........................ 10
Deserializer Switching Characteristics.................... 10
Typical Characteristics ............................................ 17
Detailed Description ............................................ 18
8.1 Overview ................................................................. 18
8.2 Functional Block Diagram ....................................... 18
8.3 Feature Description................................................. 18
8.4 Device Functional Modes........................................ 23
9
Application and Implementation ........................ 24
9.1 Application Information............................................ 24
9.2 Typical Applications ................................................ 25
10 Power Supply Recommendations ..................... 29
11 Layout................................................................... 30
11.1 Layout Guidelines ................................................. 30
11.2 Layout Examples................................................... 32
12 Device and Documentation Support ................. 34
12.1
12.2
12.3
12.4
12.5
12.6
Device Support......................................................
Documentation Support ........................................
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
34
34
34
34
34
34
13 Mechanical, Packaging, and Orderable
Information ........................................................... 34
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision N (March 2013) to Revision O
•
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
Changes from Revision M (March 2013) to Revision N
•
2
Page
Changed layout of National Data Sheet to TI format ........................................................................................................... 23
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Product Folder Links: DS90UR124-Q1 DS90UR241-Q1
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SNLS231O – SEPTEMBER 2006 – REVISED APRIL 2015
5 Description (continued)
In addition, the device features pre-emphasis to boost signals over longer distances using lossy cables. Internal
DC-balanced encoding and decoding is used to support AC-coupled interconnects. Using TI’s proprietary random
lock, the parallel data of the Serializer are randomized to the Deserializer without the need of REFCLK.
6 Pin Configuration and Functions
DIN[9]
DIN[8]
DIN[7]
DIN[6]
DIN[5]
VSS
VDD
DIN[4]
DIN[3]
DIN[2]
DIN[1]
DIN[0]
36
35
34
33
32
31
30
29
28
27
26
25
PFB Package
48-Pin TQFP
Top View
DIN[10]
37
24
VODSEL
DIN[11]
38
23
PRE
DIN[12]
39
22
VDD
DIN[13]
40
21
VSS
DIN[14]
41
20
DOUT+
VDD
42
19
DOUT-
VSS
43
18
DEN
DIN[15]
44
17
VSS
DIN[16]
45
16
VDD
DIN[17]
46
15
VSS
DIN[18]
47
14
VDD
DIN[19]
48
13
RES0
7
8
9
VDD
RES0
TPWDNB
12
6
VSS
RAOFF
5
RES0
11
4
DIN[23]
TRFB
3
DIN[22]
10
2
DIN[21]
TCLK
1
DIN[20]
DS90UR241
Pin Functions: PFB Package
PIN
NO.
NAME
I/O
DESCRIPTION
LVCMOS PARALLEL INTERFACE PINS
4-1,
48-44,
41-32,
29-25
DIN[23:0]
LVCMOS_I
Transmitter Parallel Interface Data Input Pins. Tie LOW if unused; do not float.
10
TCLK
LVCMOS_I
Transmitter Parallel Interface Clock Input Pin. Strobe edge set by TRFB configuration pin.
CONTROL AND CONFIGURATION PINS
18
23
DEN
PRE
LVCMOS_I
Transmitter Data Enable
DEN = H; LVDS Driver Outputs are Enabled (ON).
DEN = L; LVDS Driver Outputs are Disabled (OFF), Transmitter LVDS Driver DOUT (+/-) Outputs
are in Tri-state, PLL still operational and locked to TCLK.
LVCMOS_I
Pre-emphasis Level Select
PRE = NC (No Connect); Pre-emphasis is Disabled (OFF).
Pre-emphasis is active when input is tied to VSS through external resistor RPRE. Resistor value
determines pre-emphasis level. Recommended value RPRE ≥ 6 kΩ; Imax = [48 / RPRE], RPREmin =
6 kΩ
Copyright © 2006–2015, Texas Instruments Incorporated
Product Folder Links: DS90UR124-Q1 DS90UR241-Q1
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DS90UR124-Q1, DS90UR241-Q1
SNLS231O – SEPTEMBER 2006 – REVISED APRIL 2015
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Pin Functions: PFB Package (continued)
PIN
I/O
DESCRIPTION
NO.
NAME
12
RAOFF
LVCMOS_I
Randomizer Control Input Pin
RAOFF = H, Backwards compatible mode for use with DS90C124 Deserializer.
RAOFF = L; Additional randomization ON (Default), Selects 2E7 LSFR setting.
See Table 1 for more details.
5, 8,
13
RES0
LVCMOS_I
Reserved. This pin must be tied LOW.
9
TPWDNB
LVCMOS_I
Transmitter Power Down Bar
TPWDNB = H; Transmitter is Enabled and ON
TPWDNB = L; Transmitter is in power down mode (Sleep), LVDS Driver DOUT (+/-) Outputs are in
Tri-state stand-by mode, PLL is shutdown to minimize power consumption.
11
TRFB
LVCMOS_I
Transmitter Clock Edge Select Pin
TRFB = H; Parallel Interface Data is strobed on the Rising Clock Edge.
TRFB = L; Parallel Interface Data is strobed on the Falling Clock Edge
LVCMOS_I
VOD Level Select
VODSEL = L; LVDS Driver Output is ±500 mV (RL = 100 Ω)
VODSEL = H; LVDS Driver Output is ±900 mV (RL = 100 Ω)
For normal applications, set this pin LOW. For long cable applications where a larger VOD is
required, set this pin HIGH.
24
VODSEL
LVDS SERIAL INTERFACE PINS
20
DOUT+
LVDS_O
Transmitter LVDS True (+) Output.
This output is intended to be loaded with a 100-Ω load to the DOUT+ pin. The interconnect should
be AC coupled to this pin with a 100-nF capacitor.
19
DOUT−
LVDS_O
Transmitter LVDS Inverted (-) Output
This output is intended to be loaded with a 100-Ω load to the DOUT- pin. The interconnect should
be AC coupled to this pin with a 100-nF capacitor.
POWER / GROUND PINS
4
22
VDD
VDD
Analog Voltage Supply, LVDS Output POWER
16
VDD
VDD
Analog Voltage Supply, VCO POWER
14
VDD
VDD
Analog Voltage Supply, PLL POWER
30
VDD
VDD
Digital Voltage Supply, Serializer POWER
7
VDD
VDD
Digital Voltage Supply, Serializer Logic POWER
42
VDD
VDD
Digital Voltage Supply, Serializer INPUT POWER
21
VSS
GND
Analog Ground, LVDS Output GROUND
17
VSS
GND
Analog Ground, VCO GROUND
15
VSS
GND
Analog Ground, PLL GROUND
31
VSS
GND
Digital Ground, Serializer GROUND
6
VSS
GND
Digital Ground, Serializer Logic GROUND
43
VSS
GND
Digital Ground, Serializer Input GROUND
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SNLS231O – SEPTEMBER 2006 – REVISED APRIL 2015
PTOSEL
49
RES0
50
VDD
ROUT[3]
VDD
VSS
ROUT[4]
ROUT[5]
ROUT[6]
ROUT[7]
RES0
RES0
39
38
37
36
35
34
33
ROUT[2]
42
40
ROUT[1]
43
41
PASS
ROUT[0]
46
44
VDD
47
45
RPWDNB
VSS
48
PAG Package
64-Pin TQFP
Top View
32
PTO GROUP 1
VDD
31
VSS
51
30
ROUT[8]
52
29
ROUT[9]
53
28
ROUT[10]
RIN-
54
27
ROUT[11]
RRFB
55
26
VDD
VSS
56
25
VSS
VDD
57
24
RCLK
VSS
58
23
LOCK
VDD
59
22
ROUT[12]
REN
60
21
ROUT[13]
BISTEN
61
20
ROUT[14]
BISTM
62
19
ROUT[15]
RAOFF
63
18
RES0
SLEW
64
17
RES0
PTO GROUP 2
VSS
RIN+
DS90UR124
16
ROUT[16]
12
VSS
15
11
VDD
ROUT[17]
10
ROUT[20]
14
9
ROUT[21]
ROUT[18]
8
ROUT[22]
13
7
ROUT[19]
6
5
RES0
RES0
4
ROUT[23]
3
RES0
2
RES0
RES0
1
RES0
PTO GROUP 3
Pin Functions: PAG Package
PIN
NO.
NAME
I/O
DESCRIPTION
LVCMOS PARALLEL INTERFACE PINS
24
RCLK
LVCMOS_O
Parallel Interface Clock Output Pin. Strobe edge set by RRFB configuration pin.
35-38,
41-44
ROUT[7:0]
LVCMOS_O
Receiver Parallel Interface Data Outputs – Group 1
19-22,
27-30
ROUT[15:8]
LVCMOS_O
Receiver Parallel Interface Data Outputs – Group 2
7-10,
13-16
ROUT[23:16]
LVCMOS_O
Receiver Parallel Interface Data Outputs – Group 3
CONTROL AND CONFIGURATION PINS
23
LOCK
LVCMOS_O
LOCK indicates the status of the receiver PLL
LOCK = H; receiver PLL is locked
LOCK = L; receiver PLL is unlocked, ROUT[23-0] and RCLK are at Tri-state.
49
PTOSEL
LVCMOS_I
Progressive Turn On Operation Selection
PTO = H; ROUT[23:0] are grouped into three groups of eight, with each group switching about ±1
UI to ±2 UI apart relative to RCLK. (Figure 17)
PTO = L; PTO Spread Mode, ROUT[23:0] outputs are spread ±1 UI to ±2 UI and RCLK spread ±1
UI. (Figure 18) See Applications Informations section for more details.
63
RAOFF
LVCMOS_I
Randomizer Control Input Pin (See Table 2 for more details.)
RAOFF = H, Backwards compatible mode for use with DS90C241 Serializer.
RAOFF = L; Additional randomization ON (Default), Selects 2E7 LSFR setting.
60
REN
LVCMOS_I
Receiver Data Enable
REN = H; ROUT[23-0] and RCLK are Enabled (ON).
REN = L; ROUT[23-0] and RCLK are Disabled (OFF), Receiver ROUT[23-0] and RCLK Outputs are
in Tri-state, PLL still operational and locked to TCLK.
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Product Folder Links: DS90UR124-Q1 DS90UR241-Q1
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DS90UR124-Q1, DS90UR241-Q1
SNLS231O – SEPTEMBER 2006 – REVISED APRIL 2015
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Pin Functions: PAG Package (continued)
PIN
NO.
NAME
I/O
DESCRIPTION
50
RES0
LVCMOS_I
1-6,
17,
18,
33, 34
Reserved. This pin MUST be tied LOW.
RES0
NC
48
RPWDNB
LVCMOS_I
Receiver Power Down Bar
RPWDNB = H; Receiver is Enabled and ON
RPWDNB = L; Receiver is in power down mode (Sleep), ROUT[23-0], RCLK, and LOCK are in Tristate standby mode, PLL is shutdown to minimize power consumption.
55
RRFB
LVCMOS_I
Receiver Clock Edge Select Pin
RRFB = H; ROUT LVCMOS Outputs strobed on the Rising Clock Edge.
RRFB = L; ROUT LVCMOS Outputs strobed on the Falling Clock Edge.
64
SLEW
LVCMOS_I
LVCMOS Output Slew Rate Control
SLEW = L; Low drive output at 2 mA (default)
SLEW = H; High drive output at 4 mA
No Connection. Pins are not physically connected to the die. Recommendation is to leave pin
open or tie it to LOW.
BIST MODE PINS (See Application and Implementation for more details.)
61
BISTEN
LVCMOS_I
Control Pin for BIST Mode Enable
BISTEN = L; Default at Low, Normal Mode.
BISTEN = H; BIST mode active. When BISTEN = H and DS90UR241 DIN[23:0] = Low or
Floating; device will go to BIST mode accordingly. Check PASS output pin for test status.
62
BISTM
LVCMOS_I
BIST Mode selection. Control pin for which Deserializer is set for BIST reporting mode.
BISTM = L; Default at Low, Status of all ROUT with respective bit error on cycle-by-cycle basis
BISTM = H; Total accumulated bit error count provided on ROUT[7:0] (binary counter up to 255)
45
PASS
LVCMOS_O
Pass flag output for @Speed BIST Test operation.
PASS = L; BIST failure
PASS = H; LOCK = H before BIST can be enabled, then 1x10-9 error rate achieved across link.
LVDS SERIAL INTERFACE PINS
53
RIN+
LVDS_I
Receiver LVDS True (+) Input — This input is intended to be terminated with a 100Ω load to the
RIN+ pin. The interconnect should be AC Coupled to this pin with a 100 nF capacitor.
54
RIN−
LVDS_I
Receiver LVDS Inverted (−) Input — This input is intended to be terminated with a 100Ω load to
the RIN- pin. The interconnect should be AC Coupled to this pin with a 100 nF capacitor.
POWER / GROUND PINS
6
51
VDD
VDD
Analog LVDS Voltage Supply, POWER
59
VDD
VDD
Analog Voltage Supply, PLL POWER
57
VDD
VDD
Analog Voltage supply, PLL VCO POWER
32
VDD
VDD
Digital Voltage Supply, LOGIC POWER
46
VDD
VDD
Digital Voltage Supply, LOGIC POWER
40
VDD
VDD
Digital Voltage Supply, LVCMOS Output POWER
26
VDD
VDD
Digital Voltage Supply, LVCMOS Output POWER
11
VDD
VDD
Digital Voltage Supply, LVCMOS Output POWER
52
VSS
GND
Analog LVDS GROUND
58
VSS
GND
Analog Ground, PLL GROUND
56
VSS
GND
Analog Ground, PLL VCO GROUND
31
VSS
GND
Digital Ground, Logic GROUND
47
VSS
GND
Digital Ground, LOGIC GROUND
39
VSS
GND
Digital Ground, LVCMOS Output GROUND
25
VSS
GND
Digital Ground, LVCMOS Output GROUND
12
VSS
GND
Digital Ground, LVCMOS Output GROUND
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SNLS231O – SEPTEMBER 2006 – REVISED APRIL 2015
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
UNIT
Supply Voltage (VDD)
–0.3
4
V
LVCMOS Input Voltage
–0.3
VDD +0.3
V
LVCMOS Output Voltage
–0.3
VDD +0.3
V
LVDS Receiver Input Voltage
–0.3
+3.9
V
LVDS Driver Output Voltage
–0.3
+3.9
V
LVDS Output Short Circuit Duration
10
ms
Junction Temperature
150
°C
260
°C
Lead Temperature (Soldering, 4 seconds)
Maximum Package Power
Dissipation Capacity (2)
DS90UR241 − 48L
TQFP
RθJA
45.8 (4L);
75.4 (2L)
RθJC
21.0
DS90UR124 − 64L
TQFP
RθJA
42.8 (4L);
67.2 (2L)
RθJC
14.6
Package
Derating:
Storage temperature, Tstg
(1)
(2)
–65
°C/W
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
1/RθJA °C/W above +25°C
7.2 ESD Ratings
VALUE
UNIT
DS90UR241-Q1 IN PFB PACKAGE
Human body model (HBM), per AEC
Q100-002 (1)
V(ESD)
Electrostatic discharge
Charged device model (CDM), per
AEC Q100-011
(ISO10605) (2)
≥±8000
All pins
Corner pins (1, 12, 13, 24, 25, 36,
37, and 48)
±12500
Other pins
±12500
Contact Discharge (20, 19)
±10000
Air Discharge (20, 19)
±30000
All pins
≥±8000
Corner pins (1, 16, 17, 32, 33, 48,
49, and 64)
±12500
Other pins
±12500
Contact Discharge (RIN+, RIN−)
±10000
Air Discharge (RIN+, RIN−)
±30000
V
DS90UR124-Q1 IN PAG PACKAGE
Human body model (HBM), per AEC
Q100-002 (1)
V(ESD)
Electrostatic discharge
Charged device model (CDM), per
AEC Q100-011
(ISO10605) (2)
(1)
(2)
V
AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
RD = 2 kΩ, CS = 330 pF
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
Supply Voltage (VDD)
3.0
3.3
3.6
Operating Free Air Temperature (TA)
–40
25
105
°C
43
MHz
Clock Rate
5
Supply Noise
±100
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UNIT
V
mVP-P
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SNLS231O – SEPTEMBER 2006 – REVISED APRIL 2015
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7.4 Thermal Information
THERMAL METRIC (1)
DS90UR124-Q1
DS90UR241-Q1
PAG [TQFP]
PFB [TQFP]
64 PINS
48 PINS
RθJA
Junction-to-ambient thermal resistance
58.1
64.3
RθJC(top)
Junction-to-case (top) thermal resistance
13.0
14.1
RθJB
Junction-to-board thermal resistance
30.4
30.2
ψJT
Junction-to-top characterization parameter
0.3
0.4
ψJB
Junction-to-board characterization parameter
30.0
29.8
(1)
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
7.5 Electrical Characteristics
over recommended operating supply and temperature ranges unless otherwise specified
PARAMETER
TEST CONDITIONS
PIN/FREQ.
MIN
TYP
MAX UNIT
LVCMOS DC SPECIFICATIONS
VIH
High-Level Input Voltage
VIL
Low-Level Input Voltage
VCL
Input Clamp Voltage
ICL = −18 mA
IIN
Input Current
VIN = 0 V or 3.6 V
VOH
High-Level Output
Voltage
IOH = −2 mA, SLEW = L
IOH = −4 mA, SLEW = H
VOL
Low-Level Output
Voltage
IOL = 2 mA, SLEW = L
IOL = 4 mA, SLEW = H
IOS
Output Short Circuit
Current
VOUT = 0 V
IOZ
Tri-state Output Current
RPWDNB, REN = 0 V,
VOUT = 0 V or VDD
Tx: DIN[0:23], TCLK,
TPWDNB, DEN, TRFB,
RAOFF, VODSEL, RES0.
Rx: RPWDNB, RRFB, REN,
PTOSEL, BISTEN, BISTM,
SLEW, RES0.
2
VDD
V
GND
0.8
V
–0.8
–1.5
V
Tx: DIN[0:23], TCLK,
TPWDNB, DEN, TRFB,
RAOFF, RES0.
Rx: RRFB, REN, PTOSEL,
BISTEN, BISTM, SLEW,
RES0.
–10
±2
10
Rx: RPWDNB
–20
±5
20
2.3
3
VDD
V
GND
0.33
0.5
V
–40
–70
–110
mA
–30
±0.4
30
µA
50
mV
Rx: ROUT[0:23], RCLK,
LOCK, PASS.
Rx: ROUT[0:23], RCLK,
LOCK, PASS.
µA
LVDS DC SPECIFICATIONS
VTH
Differential Threshold
High Voltage
VTL
Differential Threshold
Low Voltage
IIN
Input Current
8
VCM = 1.8 V
Rx: RIN+, RIN−
–50
mV
VIN = 2.4 V, VDD = 3.6 V
±100
±250
VIN = 0 V, VDD = 3.6 V
±100
±250
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µA
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SNLS231O – SEPTEMBER 2006 – REVISED APRIL 2015
Electrical Characteristics (continued)
over recommended operating supply and temperature ranges unless otherwise specified
PARAMETER
TEST CONDITIONS
PIN/FREQ.
MIN
TYP
MAX UNIT
VODSEL = L
380
500
630
VODSEL = H
500
900
1100
1
50
1.25
1.50
3
50
VOD
RL = 100 Ω, without
Output Differential
pre-emphasis
Voltage (DOUT+)–(DOUT−)
Figure 12
ΔVOD
Output Differential
Voltage Unbalance
RL = 100 Ω,
without pre-emphasis
VODSEL = L
VOS
Offset Voltage
RL = 100 Ω,
without pre-emphasis
VODSEL = L
ΔVOS
Offset Voltage
Unbalance
RL = 100 Ω,
without pre-emphasis
VODSEL = L
Output Short Circuit
Current
DOUT = 0 V, DIN = H,
TPWDNB = 2.4 V
VODSEL = L
–2
–5
–8
VODSEL = H
–4.5
–7.9
–14
TPWDNB = 0 V,
DOUT = 0 V OR VDD
–15
±1
15
TPWDNB = 2.4 V, DEN = 0 V
DOUT = 0 V OR VDD
–15
±1
15
TPWDNB = 2.4 V, DEN = 2.4 V,
DOUT = 0 V OR VDD
NO LOCK (NO TCLK)
–15
±1
15
60
85
65
90
66
90
IOS
IOZ
Tri-state Output Current
VODSEL = H
1
VODSEL = H
VODSEL = H
mV
mV
V
mV
Tx: DOUT+, DOUT−
mA
µA
SER/DES SUPPLY CURRENT (DVDD*, PVDD* AND AVDD* PINS) *DIGITAL, PLL, AND ANALOG VDDS
RL = 100 Ω, PRE = OFF,
RAOFF = H, VODSEL = L
IDDT
Serializer
Total Supply Current
(includes load current)
RL = 100 Ω, PRE = 12 kΩ,
RAOFF = H, VODSEL = L
RL = 100 Ω, PRE = OFF,
RAOFF = H, VODSEL = H
IDDTZ
IDDR
IDDRZ
Serializer
Supply Current Powerdown
Deserializer
Total Supply Current
(includes load current)
Deserializer
Supply Current Powerdown
f = 43 MHz,
checkerboard pattern
Figure 3
f = 43 MHz,
random pattern
TPWDNB = 0V
(All other LVCMOS Inputs = 0 V)
45
CL = 4 pF,
SLEW = H
f = 43 MHz,
checkerboard pattern
LVCMOS Output Figure 4
85
CL = 4 pF,
SLEW = H
f = 43 MHz,
random pattern
LVCMOS Output
80
RPWDNB = 0 V
(All other LVCMOS Inputs = 0 V,
RIN+/RIN- = 0 V)
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mA
µA
105
mA
100
50
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7.6 Serializer Input Timing Requirements for TCLK
over recommended operating supply and temperature ranges unless otherwise specified
MIN
Figure 7
NOM
MAX
UNIT
tTCP
Transmit Clock Period
23.25
T
200
ns
tTCIH
Transmit Clock High Time
0.3 T
0.5 T
0.7 T
ns
tTCIL
Transmit Clock Low Time
0.3 T
0.5 T
0.7 T
ns
tCLKT
TCLK Input Transition Time
tJIT
TCLK Input Jitter
Figure 6
2.5
ns
f = 43 MHz
±100
f = 33 MHz
±130
ps
7.7 Serializer Switching Characteristics
over recommended operating supply and temperature ranges unless otherwise specified
PARAMETER
TEST CONDITIONS
tLLHT
LVDS Low-to-High Transition Time
tLHLT
LVDS High-to-Low Transition Time
tDIS
DIN (0:23) Setup to TCLK
tDIH
DIN (0:23) Hold from TCLK
tHZD
DOUT ± HIGH to Tri-state Delay
tLZD
DOUT ± LOW to Tri-state Delay
tZHD
DOUT ± Tri-state to HIGH Delay
tZLD
DOUT ± Tri-state to LOW Delay
tPLD
Serializer PLL Lock Time
tSD
TxOUT
_E_O
MIN
RL = 100 Ω, VODSEL = L,
CL = 10 pF to GND, Figure 5
TYP
MAX
UNIT
245
550
ps
264
550
ps
4
RL = 100 Ω, CL = 10 pF to GND
Figure 7
ns
4
RL = 100 Ω,
CL = 10 pF to GND
Figure 8
ns
10
15
ns
10
15
ns
75
150
ns
75
150
ns
10
ms
RL = 100 Ω
Serializer Delay
TxOUT_Eye_Opening.
TxOUT_E_O centered on (tBIT/)2
RL = 100 Ω, PRE = OFF,
RAOFF = L, TRFB = H,
Figure 10
3.5T+2
RL = 100 Ω, PRE = OFF,
RAOFF = L, TRFB = L,
Figure 10
3.5T+2
3.5T+10
ns
5 MHz–43 MHz,
RL = 100 Ω, CL = 10 pF to GND,
RANDOM pattern
Figure 11
0.76
3.5T+10
0.84
UI
7.8 Deserializer Switching Characteristics
over recommended operating supply and temperature ranges unless otherwise specified
PARAMETER
TEST CONDITIONS
tRCP
Receiver out Clock Period
tRCP = tTCP,
PTOSEL = H
tRDC
RCLK Duty Cycle
PTOSEL = H,
SLEW = L
tCLH
LVCMOS Low-to-High Transition
Time
tCHL
LVCMOS High-to-Low Transition
Time
tCLH
LVCMOS Low-to-High Transition
Time
tCHL
LVCMOS High-to-Low Transition
Time
tROS
ROUT (0:7) Setup Data to RCLK
(Group 1)
tROH
10
ROUT (0:7) Hold Data to RCLK
(Group 1)
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PIN/FREQ.
RCLK
Figure 17
CL = 4 pF
(lumped load),
SLEW = H
ROUT [0:23],
RCLK, LOCK
CL = 4 pF
(lumped load),
SLEW = L
ROUT [0:23],
RCLK, LOCK
PTOSEL = L,
SLEW = H,
Figure 18
ROUT[0:7]
MIN
TYP
MAX
UNIT
23.25
T
200
ns
45%
50%
55%
1.5
2.5
ns
1.5
2.5
ns
2.0
3.5
ns
2.0
3.5
ns
(0.35)× tRCP
(0.5×tRCP)–
3 UI
ns
(0.35)× tRCP
(0.5×tRCP)–
3 UI
ns
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SNLS231O – SEPTEMBER 2006 – REVISED APRIL 2015
Deserializer Switching Characteristics (continued)
over recommended operating supply and temperature ranges unless otherwise specified
PARAMETER
TEST CONDITIONS
tROS
ROUT (8:15) Setup Data to RCLK
(Group 2)
tROH
ROUT (8:15) Hold Data to RCLK
(Group 2)
tROS
ROUT (16:23) Setup Data to RCLK
(Group 3)
tROH
ROUT (16:23) Setup Data to RCLK
(Group 3)
tROS
ROUT (0:7) Setup Data to RCLK
(Group 1)
PIN/FREQ.
ROUT [8:15],
LOCK
PTOSEL = L,
SLEW = H,
Figure 18
MIN
TYP
(0.35)× tRCP
(0.5×tRCP)–
3 UI
ns
(0.35)× tRCP
(0.5×tRCP)–
3 UI
ns
(0.35)× tRCP
(0.5×tRCP)–
3 UI
ns
(0.35)× tRCP
(0.5×tRCP)–
3 UI
ns
(0.35)× tRCP
(0.5×tRCP)–
2 UI
ns
(0.35)× tRCP
(0.5×tRCP)+
2 UI
ns
(0.35)× tRCP
(0.5×tRCP)−
1 UI
ns
(0.35)× tRCP
(0.5×tRCP)+
1 UI
ns
(0.35)× tRCP
(0.5×tRCP)+
1 UI
ns
(0.35)× tRCP
(0.5×tRCP)–
1 UI
ns
ROUT [16:23]
ROUT[0:7]
tROH
ROUT (0:7) Hold Data to RCLK
(Group 1)
tROS
ROUT (8:15) Setup Data to RCLK
(Group 2)
tROH
ROUT (8:15) Hold Data to RCLK
(Group 2)
tROS
ROUT (16:23) Setup Data to RCLK
(Group 3)
PTOSEL = H,
SLEW = H,
Figure 17
ROUT [8:15],
LOCK
ROUT [16:23]
MAX
UNIT
tROH
ROUT (16:23) Setup Data to RCLK
(Group 3)
tHZR
HIGH to Tri-state Delay
3
10
ns
tLZR
LOW to Tri-state Delay
3
10
ns
tZHR
Tri-state to HIGH Delay
3
10
ns
tZLR
Tri-state to LOW Delay
3
10
ns
[5+(5/56)]T
+3.7
[5+(5/56)]T
+8
ns
PTOSEL = H,
Figure 16
tDD
Deserializer Delay
PTOSEL = H,
Figure 14
tDSR
Deserializer PLL Lock Time from
Powerdown
See Figure 16
ROUT [0:23],
RCLK, LOCK
RCLK
5 MHz
128k*T
43 MHz
128k*T
ms
RxIN_T
Receiver INput TOLerance Left
OL-L
See
Figure 19
5 MHz–43 MHz
0.25
UI
RxIN_T
Receiver INput TOLerance Right
OL-R
See
Figure 19
5 MHz–43 MHz
0.25
UI
Device Pin Name
Signal Pattern
TCLK
ODD DIN
EVEN DIN
Figure 3. Serializer Input Checkerboard Pattern
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Device Pin Name
Signal Pattern
RCLK
ODD ROUT
EVEN ROUT
Figure 4. Deserializer Output Checkerboard Pattern
DOUT+
10 pF
Vdiff
100:
80%
80%
20%
DOUT-
10 pF
Vdiff = 0V
20%
tLLHT
tLHLT
Vdiff = (DOUT+) - (DOUT-)
Figure 5. Serializer LVDS Output Load and Transition Times
80%
VDD
80%
TCLK
20%
20%
0V
tCLKT
tCLKT
Figure 6. Serializer Input Clock Transition Times
tTCP
TCLK
VDD/2
tDIS
VDD/2
VDD/2
tDIH
VDD
DIN [0:23]
VDD/2
Setup
Hold
VDD/2
0V
Figure 7. Serializer Setup and Hold Times
12
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Parasitic package and
Trace capacitance
DOUT+
5 pF
100:
DOUTDEN
tLZD
DEN
VCC/2
(single-ended)
0V
VCC/2
0V
CLK1
CLK1
tTCP
tTCP
DOUT±
(differential)
200 mV
DCA
tZLD
200 mV
DCA
DCA
DCA
$OOGDWD³0´V
DCA
DCA
DCA
DCA
tHZD
DEN
VCC/2
(single-ended)
0V
VCC/2
0V
$OOGDWD³1´V
tZHD
DCA
200 mV
DCA
DCA
DCA
DCA
DCA
DCA
DCA
200 mV
DOUT±
(differential)
tTCP
tTCP
CLK0
CLK0
Figure 8. Serializer Tri-State Test Circuit and Delay
PWDWN
2.0V
0.8V
tHZD or
tLZD
TCLK
tPLD
DOUT±
TRI-STATE
tZHD or
tZLD
Output
Active
TRI-STATE
Figure 9. Serializer PLL Lock Time, and TPWDNB Tri-State Delays
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DS90UR124-Q1, DS90UR241-Q1
DIN
SYMBOL N
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SYMBOL N+1
SYMBOL N+2
| |
SNLS231O – SEPTEMBER 2006 – REVISED APRIL 2015
SYMBOL N+3
|
tSD
TCLK
2
23
0
1
2
23
0
1
2
23
0
1
2
STOP START
BIT BIT
23
0
STOP
BIT
SYMBOL N
1
2
| |
1
STOP START
BIT BIT
SYMBOL N-1
| |
0
| |
DCA, DCB
| |
DOUT0-23
STOP START
BIT BIT
SYMBOL N-2
| |
STOP START
BIT BIT
SYMBOL N-3
SYMBOL N-4
23
Figure 10. Serializer Delay
Ideal Data Bit
End
Ideal Data Bit
Beginning
TxOUT_E_O
tBIT(1/2 UI)
tBIT(1/2 UI)
Ideal Center Position (tBIT/2)
tBIT (1 UI)
24
DIN
PARALLEL-TO-SERIAL
Figure 11. Transmitter Output Eye Opening (TxOUT_E_O)
DOUT+
RL
20194528
DOUT-
TCLK
VOD = (DOUT+) – (DOUT−)
Differential output signal is shown as (DOUT+) – (DOUT−), device in Data Transfer mode.
Figure 12. Serializer VOD Diagram
80%
80%
Deserializer
4 pF
lumped
20%
20%
tCLH
tCHL
Figure 13. Deserializer LVCMOS Output Load and Transition Times
14
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2
23
0
1
2
23
0
1
2
23
0
1
2
STOP
BIT
| |
1
STOP START
BIT BIT
SYMBOL N+3
| |
0
STOP START
BIT BIT
SYMBOL N+2
| |
RIN0-23
DCA, DCB
STOP START
BIT BIT
SYMBOL N+1
SYMBOL N
| |
START
BIT
23
tDD
RCLK
SYMBOL N-3
ROUT0-23
SYMBOL N-2
SYMBOL N-1
SYMBOL N
Figure 14. Deserializer Delay
500:
VREF
CL = 8 pF
VREF = VDD/2 for tZLR or tLZR,
+
-
VREF = 0V for tZHR or tHZR
REN
NOTE:
CL includes instrumentation and fixture capacitance within 6 cm of ROUT [23:0].
VOH
VDD/2
REN
VDD/2
VOL
tLZR
tZLR
VOL + 0.5V
VOL + 0.5V
VOL
tHZR
ROUT [23:0]
tZHR
VOH
VOH - 0.5V
VOH + 0.5V
Figure 15. Deserializer Tri-State Test Circuit and Timing
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2.0V
PWDN
0.8V
| |
tDSR
RIN±
LOCK
}v[
TRI-STATE
TRI-STATE
tHZR or tLZR
ROUT [0:23]
TRI-STATE
TRI-STATE
RCLK
TRI-STATE
TRI-STATE
REN
Figure 16. Deserializer PLL Lock Times and RPWDNB Tri-State Delay
tRCP
tRDC
RCLK
tRDC
VDD/2
VDD/2
tROS
ROUT [7:0]
(group 1)
VDD/2
Data Valid
Before RCLK
tROH
Data Valid
After RCLK
VDD/2
| -2 UI
| +2 UI
tROS
ROUT [15:8]
(group 2)
VDD/2
| -1 UI
ROUT [23:16]
(group 3)
VDD/2
Data Valid
Before RCLK
tROS
Data Valid
Before RCLK
tROH
Data Valid
After RCLK
VDD/2
| +1 UI
tROH
Data Valid
After RCLK
VDD/2
| +1 UI
| -1 UI
Figure 17. Deserializer Setup and Hold Times and PTO, PTOSEL = H
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ROUT
(Ideal)
½ Symbol
½ Symbol
RCLK
ROUT
1 + 3/28 Symbol
GRP1
2 UI EARLY
1 - 2/28 Symbol
1 UI LATE
1 + 3/28 Symbol
1 UI EARLY
1 - 4/28 Symbol
2 UI LATE
2 UI EARLY
Group 1 will be latched internally by sequence of (early 2UI, late 1UI, early 1UI, late 2UI).
Group 2 will be latched internally by sequence of (late 1UI, early 1UI, late 2UI, early 2UI).
Group 3 will be latched internally by sequence of (early 1UI, late 2UI, early 2UI, late 1UI).
Figure 18. Deserializer Setup and Hold Times and PTO Spread, PTOSEL = L
Sampling
Window
Ideal Data Bit
Beginning
Ideal Data Bit
End
RxIN_TOL -L
RxIN_TOL -R
Ideal Center Position (tBIT/2)
tBIT (1 UI)
RxIN_TOL_L is the ideal noise margin on the left of the figure, with respect to ideal.
RxIN_TOL_R is the ideal noise margin on the right of the figure, with respect to ideal.
Figure 19. Receiver Input Tolerance (RxIN_TOL) and Sampling Window
Magnitude (500 mV/DIV)
Magnitude (100 mV/DIV)
7.9 Typical Characteristics
Time (2.5 ns/DIV)
Figure 20. DS90UR241 DOUT± With PCLK at 43 MHz
Measured at RIN± Termination
Time (5 ns/DIV)
Figure 21. DS90UR124 PCLK Output at 43 MHz
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8 Detailed Description
8.1 Overview
The DS90UR241 Serializer and DS90UR124 Deserializer chipset is an easy-to-use transmitter and receiver pair
that sends 24-bits of parallel LVCMOS data over a single serial LVDS link from 120 Mbps to 1.03 Gbps
throughput. The DS90UR241 transforms a 24-bit wide parallel LVCMOS data into a single high speed LVDS
serial data stream with embedded clock and scrambles / DC Balances the data to enhance signal quality to
support AC coupling. The DS90UR124 receives the LVDS serial data stream and converts it back into a 24-bit
wide parallel data and recovered clock. The 24-bit Serializer/Deserializer chipset is designed to transmit data up
to 10 meters over shielded twisted pair (STP) at clock speeds from 5 MHz to 43 MHz.
The Deserializer can attain lock to a data stream without the use of a separate reference clock source, greatly
simplifying system complexity and overall cost. The Deserializer synchronizes to the Serializer regardless of data
pattern, delivering true automatic “plug and lock” performance. It will lock to the incoming serial stream without
the need of special training patterns or sync characters. The Deserializer recovers the clock and data by
extracting the embedded clock information and validating data integrity from the incoming data stream and then
deserializes the data. The Deserializer monitors the incoming clock information, determines lock status, and
asserts the LOCK output high when lock occurs.
In addition, the Deserializer also supports an optional @SPEED BIST (Built In Self Test) mode, BIST error flag,
and LOCK status reporting pin. Signal quality on the wide parallel output is controlled by the SLEW control and
bank slew (PTOSEL) inputs to help reduce noise and system EMI. Each device has a power down control to
enable efficient operation in various applications.
8.2 Functional Block Diagram
TCLK
PLL
Timing
and
Control
TPWDNB
SERIALIZER ± DS90UR241
RAOFF
RRFB
RPWDNB
BISTEN
BISTM
SLEW
PTOSEL
PLL
Output Latch
RIN-
DC Balance Decoder
DOUT-
Serial to Parallel
TRFB
RIN+
RT = 100:
DIN
DOUT+
RT = 100:
24
REN
Parallel to Serial
Input Latch
DC Balance Encoder
VODSEL
PRE
DEN
RAOFF
Timing
and
Control
Clock
Recovery
24
ROUT
LOCK
RCLK
PASS
DESERIALIZER ± DS90UR124
8.3 Feature Description
8.3.1 Initialization and Locking Mechanism
Initialization of the DS90UR241 and DS90UR124 must be established before each device sends or receives
data. Initialization refers to synchronizing the Serializer’s and Deserializer’s PLL’s together. After the Serializers
locks to the input clock source, the Deserializer synchronizes to the Serializers as the second and final
initialization step.
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SNLS231O – SEPTEMBER 2006 – REVISED APRIL 2015
Feature Description (continued)
Step 1: When VDD is applied to both Serializer and/or Deserializer, the respective outputs are held in Tri-state
and internal circuitry is disabled by on-chip power-on circuitry. When VDD reaches VDD OK (approximately 2.2 V)
the PLL in Serializer begins locking to a clock input. For the Serializer, the local clock is the transmit clock,
TCLK. The Serializer outputs are held in Tri-state while the PLL locks to the TCLK. After locking to TCLK, the
Serializer block is now ready to send data patterns. The Deserializer output will remain in Tri-state while its PLL
locks to the embedded clock information in serial data stream. Also, the Deserializer LOCK output will remain low
until its PLL locks to incoming data and sync-pattern on the RIN± pins.
Step 2: The Deserializer PLL acquires lock to a data stream without requiring the Serializer to send special
patterns. The Serializer that is generating the stream to the Deserializer will automatically send random (nonrepetitive) data patterns during this step of the Initialization State. The Deserializer will lock onto embedded clock
within the specified amount of time. An embedded clock and data recovery (CDR) circuit locks to the incoming bit
stream to recover the high-speed receive bit clock and re-time incoming data. The CDR circuit expects a coded
input bit stream. In order for the Deserializer to lock to a random data stream from the Serializer, it performs a
series of operations to identify the rising clock edge and validates data integrity, then locks to it. Because this
locking procedure is independent on the data pattern, total random locking duration may vary. At the point when
the Deserializer’s CDR locks to the embedded clock, the LOCK pin goes high and valid RCLK/data appears on
the outputs. Note that the LOCK signal is synchronous to valid data appearing on the outputs. The Deserializer’s
LOCK pin is a convenient way to ensure data integrity is achieved on receiver side.
8.3.2 Data Transfer
After Serializer lock is established, the inputs DIN0–DIN23 are used to input data to the Serializer. Data is
clocked into the Serializer by the TCLK input. The edge of TCLK used to strobe the data is selectable via the
TRFB pin. TRFB high selects the rising edge for clocking data and low selects the falling edge. The Serializer
outputs (DOUT±) are intended to drive point-to-point connections.
CLK1, CLK0, DCA, DCB are four overhead bits transmitted along the single LVDS serial data stream (Figure 30).
The CLK1 bit is always high and the CLK0 bit is always low. The CLK1 and CLK0 bits function as the embedded
clock bits in the serial stream. DCB functions as the DC Balance control bit. It does not require any pre-coding of
data on transmit side. The DC Balance bit is used to minimize the short and long-term DC bias on the signal
lines. This bit operates by selectively sending the data either unmodified or inverted. The DCA bit is used to
validate data integrity in the embedded data stream. Both DCA and DCB coding schemes are integrated and
automatically performed within Serializer and Deserializer.
The chipset supports clock frequency ranges of 5 MHz to 43 MHz. Every clock cycle, 24 databits are sent along
with 4 additional overhead control bits. Thus the line rate is 1.20 Gbps maximum (140Mbps minimum). The link is
extremely efficient at 86% (24/28). Twenty five (24 data + 1 clock) plus associated ground signals are reduced to
only 1 single LVDS pair providing a compression ratio of better then 25 to 1.
In the serialized data stream, data/embedded clock & control bits (24+4 bits) are transmitted from the Serializer
data output (DOUT±) at 28 times the TCLK frequency. For example, if TCLK is 43 MHz, the serial rate is 43 × 28
= 1.20 Giga bits per second. Since only 24 bits are from input data, the serial “payload” rate is 24 times the
TCLK frequency. For instance, if TCLK = 43 MHz, the payload data rate is 43 x 24 = 1.03 Gbps. TCLK is
provided by the data source and must be in the range of 5 MHz to 43 MHz nominal. The Serializer outputs
(DOUT±) can drive a point-to-point connection as shown in Figure 29. The outputs transmit data when the enable
pin (DEN) is high and TPWDNB is high. The DEN pin may be used to Tri-state the outputs when driven low.
When the Deserializer channel attains lock to the input from a Serializer, it drives its LOCK pin high and
synchronously delivers valid data and recovered clock on the output. The Deserializer locks onto the embedded
clock, uses it to generate multiple internal data strobes, and then drives the recovered clock to the RCLK pin.
The recovered clock (RCLK output pin) is synchronous to the data on the ROUT[23:0] pins. While LOCK is high,
data on ROUT[23:0] is valid. Otherwise, ROUT[23:0] is invalid. The polarity of the RCLK edge is controlled by the
RRFB input. ROUT[23:0], LOCK and RCLK outputs will each drive a maximum of 4-pF load with a 43-MHz clock.
REN controls Tri-state for ROUTn and the RCLK pin on the Deserializer.
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Feature Description (continued)
8.3.3 Resynchronization
If the Deserializer loses lock, it will automatically try to re-establish lock. For example, if the embedded clock
edge is not detected one time in succession, the PLL loses lock and the LOCK pin is driven low. The Deserializer
then enters the operating mode where it tries to lock to a random data stream. It looks for the embedded clock
edge, identifies it, and then proceeds through the locking process.
The logic state of the LOCK signal indicates whether the data on ROUT is valid; when it is high, the data is valid.
The system may monitor the LOCK pin to determine whether data on the ROUT is valid.
8.3.4 Powerdown
The Powerdown state is a low power sleep mode that the Serializer and Deserializer may use to reduce power
when no data is being transferred. The TPWDNB and RPWDNB are used to set each device into powerdown
mode, which reduces supply current to the µA range. The Serializer enters powerdown when the TPWDNB pin is
driven low. In powerdown, the PLL stops and the outputs go into Tri-state, disabling load current and reducing
current supply. To exit Powerdown, TPWDNB must be driven high. When the Serializer exits Powerdown, its PLL
must lock to TCLK before it is ready for the Initialization state. The system must then allow time for Initialization
before data transfer can begin. The Deserializer enters powerdown mode when RPWDNB is driven low. In
powerdown mode, the PLL stops and the outputs enter Tri-state. To bring the Deserializer block out of the
powerdown state, the system drives RPWDNB high.
Both the Serializer and Deserializer must reinitialize and relock before data can be transferred. The Deserializer
will initialize and assert LOCK high when it is locked to the embedded clock.
8.3.5 Tri-State
For the Serializer, Tri-state is entered when the DEN or TPWDNB pin is driven low. This will Tri-state both driver
output pins (DOUT+ and DOUT−). When DEN is driven high, the serializer will return to the previous state as
long as all other control pins remain static (TPWDNB, TRFB).
When you drive the REN or RPWDNB pin low, the Deserializer enters Tri-state. Consequently, the receiver
output pins (ROUT0–ROUT23) and RCLK will enter Tri-state. The LOCK output remains active, reflecting the
state of the PLL. The Deserializer input pins are high impedance during receiver powerdown (RPWDNB low) and
power-off (VDD = 0 V).
8.3.6 Pre-Emphasis
The DS90UR241 features a Pre-Emphasis function used to compensate for long or lossy transmission media.
Cable drive is enhanced with a user selectable Pre-Emphasis feature that provides additional output current
during transitions to counteract cable loading effects. The transmission distance will be limited by the loss
characteristics and quality of the media. Pre-Emphasis adds extra current during LVDS logic transition to reduce
the cable loading effects and increase driving distance. In addition, Pre-Emphasis helps provide faster
transitions, increased eye openings, and improved signal integrity. The ability of the DS90UR241 to use the PreEmphasis feature will extend the transmission distance up to 10 meters in most cases.
To enable the Pre-Emphasis function, the “PRE” pin requires one external resistor (Rpre) to Vss in order to set
the additional current level. Values of Rpre should be between 6 kΩ and 100 MΩ. Values less than 6 kΩ should
not be used. A lower input resistor value on the ”PRE” pin increases the magnitude of dynamic current during
data transition. The additional source current is based on the following formula: PRE = (RPRE ≥ 6 kΩ); IMAX = [48 /
RPRE]. For example if Rpre = 15 kΩ , then the Pre-Emphasis current is increase by an additional 3.2 mA.
The amount of Pre-Emphasis for a given media will depend on the transmission distance of the application. In
general, too much Pre-Emphasis can cause over or undershoot at the receiver input pins. This can result in
excessive noise, crosstalk and increased power dissipation. For short cables or distances, Pre-Emphasis may
not be required. Signal quality measurements are recommended to determine the proper amount of PreEmphasis for each application.
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Feature Description (continued)
8.3.7 AC-Coupling and Termination
The DS90UR241 and DS90UR124 supports AC-coupled interconnects through integrated DC balanced
encoding/decoding scheme. To use the Serializer and Deserializer in an AC-coupled application, insert external
AC-coupling capacitors in series in the LVDS signal path as illustrated in Figure 29. The Deserializer input stage
is designed for AC-coupling by providing a built-in AC bias network which sets the internal VCM to +1.8V. With AC
signal coupling, capacitors provide the AC-coupling path to the signal input.
For the high-speed LVDS transmissions, the smallest available package should be used for the AC-coupling
capacitor. This will help minimize degradation of signal quality due to package parasitics. The most common
used capacitor value for the interface is a 100 nF (0.1 uF). NPO class 1 or X7R class 2 type capacitors are
recommended. 50 WVDC should be the minimum used for the best system-level ESD performance.
A termination resistor across DOUT± and RIN± is also required for proper operation to be obtained. The
termination resistor should be equal to the differential impedance of the media being driven. This should be in the
range of 90 to 132 Ω. 100 Ω is a typical value common used with standard 100-Ω transmission media. This
resistor is required for control of reflections and also completes the current loop. It should be placed as close to
the Serializer DOUT± outputs and Deserializer RIN± inputs to minimize the stub length from the pins. To match
with the deferential impedance on the transmission line, the LVDS I/O are terminated with 100-Ω resistors on
Serializer DOUT± outputs pins and Deserializer RIN± input pins.
8.3.7.1 Receiver Termination Option 1
A single 100-Ω termination resistor is placed across the RIN± pins (see Figure 29). This provides the signal
termination at the Receiver inputs. Other options may be used to increase noise tolerance.
8.3.7.2 Receiver Termination Option 2
For additional EMI tolerance, two 50-Ω resistors may be used in place of the single 100-Ω resistor. A small
capacitor is tied from the center point of the 50-Ω resistors to ground (see Figure 31). This provides a highfrequency low impedance path for noise suppression. Value is not critical, 4.7 nF may be used with general
applications.
8.3.7.3 Receiver Termination Option 3
For high noise environments, an additional voltage divider network may be connected to the center point. This
has the advantage of a providing a DC low-impedance path for noise suppression. Use resistor values in the
range of 100Ω-2KΩ for the pullup and pulldown. Ratio the resistor values to bias the center point at 1.8 V. For
example (see Figure 32): VDD=3.3 V, Rpullup=1 KΩ, Rpulldown=1.2 KΩ; or Rpullup=100 Ω, Rpulldown=120 Ω
(strongest). The smaller values will consume more bias current, but will provide enhanced noise suppression.
8.3.8 Signal Quality Enhancers
The DS90UR124 Deserializer supports two signal quality enhancers. The SLEW pin is used to increase the drive
strength of the LVCMOS outputs when driving heavy loads. SLEW allows output drive strength for high or low
current drive. Default setting is LOW for low drive at 2 mA and HIGH for high drive at 4 mA.
There are two types of Progressive Turnon modes (Fixed and PTO Frequency Spread) to help reduce EMI:
simultaneous switching noise and system ground bounce. The PTOSEL pin introduces bank skew in the
data/clock outputs to limit the number of outputs switching simultaneously. For Fixed-PTO mode, the Deserializer
ROUT[23:0] outputs are grouped into three groups of eight, with each group switching about 2 or 1 UI apart in
phase from RCLK for Group 1 and Groups 2, 3, respectively (see Figure 17). In the PTO Frequency Spread
mode, ROUT[23:0] are also grouped into three groups of eight, with each group is separated out of phase with
the adjacent groups (see Figure 18) per every 4 cycles. Note that in the PTO Frequency Spread operating mode
RCLK is also spreading and separated by 1 UI.
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Feature Description (continued)
8.3.9 @SPEED-BIST Test Feature
To assist vendors with test verification, the DS90UR241 and DS90UR124 is equipped with built-in self-test
(BIST) capability to support both system manufacturing and field diagnostics. BIST mode is intended to check the
entire high-speed serial link at full link-speed, without the use of specialized and expensive test equipment. This
feature provides a simple method for a system host to perform diagnostic testing of both Serializer and
Deserializer. The BIST function is easily configured through the 2 control pins on the DS90UR124. When the
BIST mode is activated, the Serializer has the ability to transfer an internally generated PRBS data pattern. This
pattern traverses across interconnecting links to the Deserializer. The DS90UR124 includes an on-chip PRBS
pattern verification circuit that checks the data pattern for bit errors and reports any errors on the data output pins
on the Deserializer.
The @SPEED-BIST feature uses 2 signal pins (BISTEN and BISTM) on the DS90UR124 Deserializer. The
BISTEN and BISTM pins together determine the functions of the BIST mode. The BISTEN signal (HIGH)
activates the test feature on the Deserializer. After the BIST mode is enabled, all the data input channels
DIN[23:0] on the DS90UR241 Serializer must be set logic LOW or floating in order for Deserializer to start
accepting data. An input clock signal (TCLK) for the Serializer must also be applied during the entire BIST
operation. The BISTM pin selects error reporting status mode of the BIST function. When BIST is configured in
the error status mode (BISTM = LOW), each of the ROUT[23:0] outputs will correspond to bit errors on a cycleby-cycle basis. The result of bit mismatches are indicated on the respective parallel inputs on the ROUT[23:0]
data output pins. In the BIST error-count accumulator mode (BISTM = HIGH), an 8-bit counter on ROUT[7:0] is
used to represent the number of errors detected (0 to 255 max). The successful completion of the BIST test is
reported on the PASS pin on the Deserializer. The Deserializer's PLL must first be locked to ensure the PASS
status is valid. The PASS status pin will stay LOW and then transition to HIGH once a BER of 1x10-9 is achieved
across the transmission link.
8.3.10 Backward-Compatible Mode With DS90C241 and DS90C124
The RAOFF pin allows a backward-compatible mode with DS90C241 and DS90C124 devices. To interface with
either DS90C241 Serializer or DS90C124 Deserializer, the RAOFF pin on DS90UR241 or DS90UR124 must be
tied HIGH to disable the additional LSFR coding. For normal operation directly with DS90UR241 to DS90UR124,
RAOFF pins are set LOW. See Table 1 and Table 2 for more details.
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8.4 Device Functional Modes
Table 1. DS90UR241 Serializer Truth Table
TPWDNB
(Pin 9)
DEN
(Pin 18)
RAOFF
(Pin 12)
Tx PLL Status
(Internal)
LVDS Outputs
(Pins 19 and 20)
L
X
X
X
Hi-Z
H
L
X
X
Hi-Z
H
H
X
Not Locked
Hi-Z
H
H
L
Locked
Serialized Data with Embedded Clock
(DS90UR124 compatible)
H
H
H
Locked
Serialized Data with Embedded Clock
(DS90C124 compatible)
Table 2. DS90UR124 Deserializer Truth Table
RPWDNB
(Pin 48)
REN
(Pin 60)
RAOFF
(Pin 63)
Rx PLL Status
(Internal)
ROUTn and RCLK
(See Pin Diagram)
LOCK
(Pin 23)
L
X
X
X
Hi Z
Hi Z
H
L
X
X
Hi Z
L = PLL Unocked;
H = PLL Locked
H
H
X
Not Locked
Hi Z
L
H
H
L
Locked
Data and RCLK Active
(DS90UR241 compatible)
H
H
H
H
Locked
Data and RCLK Active
(DS90C241 compatible)
H
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.1.1 Using the DS90UR241 and DS90UR124
The DS90UR241/DS90UR124 Serializer/Deserializer (SERDES) pair sends 24 bits of parallel LVCMOS data
over a serial LVDS link up to 1.03 Gbps. Serialization of the input data is accomplished using an onboard PLL at
the Serializer which embeds clock with the data. The Deserializer extracts the clock/control information from the
incoming data stream and deserializes the data. The Deserializer monitors the incoming clock information to
determine lock status and will indicate lock by asserting the LOCK output high.
9.1.2 Display Application
The DS90URxxx-Q1 chipset is intended for interface between a host (graphics processor) and a Display. It
supports an 18-bit color depth (RGB666) and up to 1280 × 480 display formats. In a RGB666 configuration 18
color bits (R[5:0], G[5:0], B[5:0]), Pixel Clock (PCLK) and 3 control bits (VS, HS and DE) along with 3 spare bits
are supported across the serial link with PCLK rates from 5 to 43 MHz.
9.1.3 Typical Application Connection
Figure 22 shows a typical application of the DS90UR241 Serializer (SER). The LVDS outputs use a 100-Ω
termination and 100-nF coupling capacitors to the line. Bypass capacitors are placed near the power supply pins.
At a minimum, three 0.1-uF capacitors should be used for local bypassing. A system GPO (General Purpose
Output) controls the TPWDNB pin. In this application the TRFB pin is tied High to latch data on the rising edge of
the TCLK. The DEN signal is not used and is tied High also. The application is to the companion Deserializer
(DS90UR124) so the RAOFF pin is tied low to scramble the data and improve link signal quality. In this
application the link is typical, therefore the VODSEL pin is tied Low for the standard LVDS swing. The preemphasis input uses a resistor to ground to set the amount of pre-emphasis desired by the application.
Figure 26 shows a typical application of the DS90UR124 Deserializer (DES). The LVDS inputs use a 100-Ω
termination and 100-nF coupling capacitors to the line. Bypass capacitors are placed near the power supply pins.
At a minimum, four 0.1-uF capacitors should be used for local bypassing. A system GPO (general-purpose
output) controls the RPWDNB pin. In this application the RRFB pin is tied High to strobe the data on the rising
edge of the RCLK. The REN signal is not used and is tied High also. The application is to the companion
Serializer (DS90UR241) so the RAOFF pin is tied low to descramble the data. Output (LVCMOS) signal quality is
set by the SLEW pin, and the PTOSEL pin can be used to reduce simultaneous output switching by introducing a
small amount of delay between output banks.
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9.2 Typical Applications
9.2.1 DS90UR241-Q1 Typical Application Connection
DS90UR241 (SER)
DIN0
DIN1
DIN2
DIN3
DIN4
DIN5
DIN6
DIN7
VDD
VDD
DIN16
DIN17
DIN18
DIN19
DIN20
DIN21
DIN22
DIN23
C2
C6
C3
C7
Serial
LVDS
Interface
R1
DOUT-
DEN
TRFB
PRE
Notes:
TPWDNB = System GPO
DEN = High (ON)
TRFB = High (Rising edge)
RAOFF = Low (Default)
VODSEL = Low (500 mV)
PRE = Rpre
RES0 = Low
C5
DOUT+
TPWDNB
3.3V
C1
VDD
VDD
TCLK
GPOs if used, or tie High (ON)
C4
VDD
VDD
DIN8
DIN9
DIN10
DIN11
DIN12
DIN13
DIN14
DIN15
LVCMOS
Parallel
Interface
3.3V
R2
VODSEL
RAOFF
RES0(3)
VSS
VSS
VSS
VSS
VSS
VSS
C8
C1 to C3 = 0.1 PF
C4 to C6 = 0.01 PF (optional)
C7 to C8 = 100 nF50WVDC, NPO or X7R
R1 = 100 :
R2 = Open (OFF)
or Rpre 8 6 k: (ON) (cable specific)
Figure 22. DS90UR241 Connection Diagram
9.2.1.1 Design Requirements
Table 3. DS90UR241 Design Parameter
DESIGN PARAMETER
EXAMPLE VALUE
VDD
3.3 V
AC Coupling Capacitor for DOUT±
100 nF
DOUT± External Termination
100 Ω
PCLK Frequency
33 MHz
9.2.1.2 Detailed Design Procedure
Figure 22 shows a typical application of the DS90UR241 serializer for an 33-MHz 18-bit Color Display
Application. The DOUT± outputs must have a series external 0.1-μF AC-coupling capacitor and 100-Ω parallel
termination on the high-speed serial lines. The serializer does not have an internal termination. Bypass
capacitors are placed near the power supply pins. At a minimum, three 0.1-μF capacitors should be used for
local device bypassing. Additional capacitors may be needed as the number and values of the capacitors will
depend on meeting the power noise specification of the part. Ferrite beads may be needed on the VDDs for
effective noise suppression. The interface to the graphics source is with 3.3-V LVCMOS levels. An RC delay is
placed on the PDB signal to delay the enabling of the device until power is stable.
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9.2.1.2.1 Power Considerations
An all LVCMOS design of the Serializer and Deserializer makes them inherently low-power devices. Additionally,
the constant current source nature of the LVDS outputs minimizes the slope of the speed vs. IDD curve of
LVCMOS designs.
9.2.1.2.2 Noise Margin
The Deserializer noise margin is the amount of input jitter (phase noise) that the Deserializer can tolerate and still
reliably recover data. Various environmental and systematic factors include:
• Serializer: VDD noise, TCLK jitter (noise bandwidth and out-of-band noise)
• Media: ISI, VCM noise
• Deserializer: VDD noise
For a graphical representation of noise margin, see Figure 19.
9.2.1.2.3 Transmission Media
The Serializer and Deserializer are to be used in point-to-point configuration, through a PCB trace, or through
twisted pair cable. In a point-to-point configuration, the transmission media needs be terminated at both ends of
the transmitter and receiver pair. Interconnect for LVDS typically has a differential impedance of 100 Ω. Use
cables and connectors that have matched differential impedance to minimize impedance discontinuities. In most
applications that involve cables, the transmission distance will be determined on data rates involved, acceptable
bit error rate and transmission medium.
The resulting signal quality at the receiving end of the transmission media may be assessed by monitoring the
differential eye opening of the serial data stream. The Receiver Input Tolerance and Differential Threshold
Voltage specifications define the acceptable data eye opening. A differential probe should be used to measure
across the termination resistor at the DS90UR124 inputs. Figure 23 illustrates the eye opening and relationship
to the Receiver Input Tolerance and Differential Threshold Voltage specifications.
Ideal Data Bit
Beginning
RxIN_TOL -L
Minimum Eye
Width
VTH - VTL
Ideal Data Bit
End
RxIN_TOL -R
tBIT
(1UI)
Figure 23. Receiver Input Eye Opening
9.2.1.2.4 Live Link Insertion
The Serializer and Deserializer devices support live pluggable applications. The automatic receiver lock to
random data “plug and go” hot insertion capability allows the DS90UR124 to attain lock to the active data stream
during a live insertion event.
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Magnitude (200 mV/DIV)
Magnitude (100 mV/DIV)
9.2.1.3 Application Curves
Time (125 ps/DIV)
Figure 24. DS90UR241 DOUT± at 1.2 Gbps Measured at
RIN± Termination; VODSEL=LOW
Time (125 ps/DIV)
Figure 25. DS90UR241 DOUT± at 1.2 Gbps Measured at
RIN± Termination; VODSEL=HIGH
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9.2.2 DS90UR124 Typical Application Connection
DS90UR124 (DES)
3.3V
3.3V
VDD
VDD
C1
C5
VDD
VDD
C6
C9
RIN+
R1
RINC10
RPWDNB
GPO if used, or tie High (ON)
BISTEN
GPOs if used,
or tie Low (OFF)
BISTM
3.3V
VSS
VSS
VSS
VSS
Notes:
RPWDNB = System GPO
REN = High (ON)
RRFB = High (Rising edge)
RAOFF = Low (Default)
PTOSEL = Low (Defaut)
SLEW = Low (Default)
RES0 = Low
BISTEN = GPO or Low
BISTM = GPO or Low
REN
RRFB
RAOFF
PTOSEL
SLEW
RES0(11)
C7
C3
C8
C4
VDD
VDD
ROUT0
ROUT1
ROUT2
ROUT3
ROUT4
ROUT5
ROUT6
ROUT7
ROUT8
ROUT9
ROUT10
ROUT11
ROUT12
ROUT13
ROUT14
ROUT15
LVCMOS
Parallel
Interface
ROUT16
ROUT17
ROUT18
ROUT19
ROUT20
ROUT21
ROUT22
ROUT23
RCLK
LOCK
PASS
VSS
VSS
VSS
VSS
C2
Serial
LVDS
Interface
VDD
VDD
C1 to C4 = 0.1 PF
C5 to C8 = 0.01 PF (optional)
C9 to C10 = 100 nF;
50WVDC, NPO or X7R
R1 = 100:
Figure 26. DS90UR124 Connection Diagram
9.2.2.1 Design Requirements
Table 4. DS90UR124 Design Parameters
DESIGN PARAMETER
28
EXAMPLE VALUE
VDD
3.3 V
DS90UR124-Q1 AC-Coupling Capacitor for RIN±
100 nF
DS90UR124-Q1 Termination for RIN±
100 Ω
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9.2.2.2 Detailed Design Procedure
Figure 26 shows a typical application of the DS90UR124 deserializer for an 33-MHz 18-bit Color Display
Application. The RIN± inputs must have an external series 0.1-μF AC-coupling capacitor and 100-Ω parallel
termination on the high-speed serial lines. The deserializer does not have an internal termination. Bypass
capacitors are placed near the power supply pins. At a minimum, four 0.1-μF capacitors should be used for local
device bypassing. Ferrite beads may be needed on the VDDs for effective noise suppression. Additional
capacitors may be needed as the number and values of the capacitors will depend on meeting the power noise
specification of the part. The interface to the display is with 3.3-V LVCMOS levels. An RC delay is placed on the
PDB signal to delay the enabling of the device until power is stable.
9.2.2.3 Application Curves
Magnitude (500 mV/DIV)
43 MHz RX
Pixel Clock
Output
(1 V/DIV)
1.2 Gbps TX
Serial Data
Output
(200 mV/DIV)
Time (10 ns/DIV)
Figure 27. DS90UR241 Serial Stream and DS90UR124
43-MHz PCLK Output
Time (5 ns/DIV)
Figure 28. DS90UR124 PCLK Output at 43 MHz (Enlarged)
10 Power Supply Recommendations
This device is designed to operate from an input core voltage supply of 3.3 V. Some devices provide separate
power and ground pins for different portions of the circuit. This is done to isolate switching noise effects between
different sections of the circuit. Separate planes on the PCB are typically. Pin description tables typically provide
guidance on which circuit blocks are connected to which power pin pairs. In some cases, an external filter may
be used to provide clean power to sensitive circuits such as PLLs.
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11 Layout
11.1 Layout Guidelines
11.1.1 PCB Layout and Power System Considerations
Circuit board layout and stack-up for the LVDS SERDES devices should be designed to provide low-noise power
feed to the device. Good layout practice will also separate high-frequency or high-level inputs and outputs to
minimize unwanted stray noise pickup, feedback and interference. Power system performance may be greatly
improved by using thin dielectrics (2 to 4 mils) for power / ground sandwiches. This arrangement provides plane
capacitance for the PCB power system with low-inductance parasitics, which has proven especially effective at
high frequencies, and makes the value and placement of external bypass capacitors less critical. External bypass
capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the
range of 0.01 μF to 0.1 μF. Tantalum capacitors may be in the range of 2.2 μF to 10 μF. Voltage rating of the
tantalum capacitors should be at least 5× the power supply voltage being used.
Surface-mount capacitors are recommended due to their smaller parasitics. When using multiple capacitors per
supply pin, locate the smaller value closer to the pin. A large bulk capacitor is recommend at the point of power
entry. This is typically in the 50-uF to 100-uF range and will smooth low frequency switching noise. TI
recommends connecting power and ground pins directly to the power and ground planes with bypass capacitors
connected to the plane with via on both ends of the capacitor. Connecting power or ground pins to an external
bypass capacitor will increase the inductance of the path.
A small body size X7R chip capacitor, such as 0603, is recommended for external bypass. Its small body size
reduces the parasitic inductance of the capacitor. The user must pay attention to the resonance frequency of
these external bypass capacitors, usually in the range of 20 MHz to 30 MHz. To provide effective bypassing,
multiple capacitors are often used to achieve low impedance between the supply rails over the frequency of
interest. At high frequency, it is also a common practice to use two vias from power and ground pins to the
planes, reducing the impedance at high frequency.
Some devices provide separate power and ground pins for different portions of the circuit. This is done to isolate
switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not
required. Pin description tables typically provide guidance on which circuit blocks are connected to which power
pin pairs. In some cases, an external filter many be used to provide clean power to sensitive circuits such as
PLLs.
Use at least a 4-layer board with a power and ground plane. Locate LVCMOS signals away from the LVDS lines
to prevent coupling from the LVCMOS lines to the LVDS lines. Closely coupled differential lines of 100 Ω are
typically recommended for LVDS interconnect. The closely coupled lines help to ensure that coupled noise will
appear as common-mode and thus is rejected by the receivers. The tightly coupled lines will also radiate less.
Termination of the LVDS interconnect is required. For point-to-point applications, termination should be located at
both ends of the devices. Nominal value is 100 Ω to match the differential impedance of the line. Place the
resistor as close to the transmitter DOUT± outputs and receiver RIN± inputs as possible to minimize the resulting
stub between the termination resistor and device.
11.1.2 LVDS Interconnect Guidelines
See AN-1108 (SNLA008) and AN-905 (SNLA035) for full details.
• Use 100-Ω coupled differential pairs
• Use the S/2S/3S rule in spacings
– S = space between the pair
– 2S = space between pairs
– 3S = space to LVCMOS signal
• Minimize the number of vias
• Use differential connectors when operating above 500-Mbps line speed
• Maintain balance of the traces
• Minimize skew within the pair
• Terminate as close to the TX outputs and RX inputs as possible
30
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Copyright © 2006–2015, Texas Instruments Incorporated
Product Folder Links: DS90UR124-Q1 DS90UR241-Q1
DS90UR124-Q1, DS90UR241-Q1
www.ti.com
SNLS231O – SEPTEMBER 2006 – REVISED APRIL 2015
Layout Guidelines (continued)
Additional general guidance can be found in the LVDS Owner’s Manual (SNLA187) - available in PDF format
from the TI web site at: www.ti.com/lvds
100 nF
DOUT+
100 nF RIN+
100:
DOUT-
100:
100 nF
RIN-
100 nF
bit23
CLK0
bit21
bit22
bit20
bit19
bit17
bit18
bit16
bit15
bit14
bit12
bit13
DCB
bit11
DCA
bit9
bit10
bit8
bit7
bit6
bit4
bit5
bit3
bit1
bit2
bit0
CLK1
Figure 29. AC-Coupled Application
1 CLK cycle
*Note: bits [0-23] are not physically located in positions shown above since bits [0-23] are scrambled and DC
Balanced
Figure 30. Single Serialized LVDS Bitstream*
0.1 PF
0.1 PF
RIN+
50:
DS90UR241
DS90UR124
100:
4.7 nF
50:
RIN0.1 PF
0.1 PF
Figure 31. Receiver Termination Option 2
VDD
0.1 PF
0.1 PF
RIN+
50:
RPU
DS90UR241
DS90UR124
100:
RPD
4.7 nF
50:
RIN0.1 PF
0.1 PF
Figure 32. Receiver Termination Option 3
Copyright © 2006–2015, Texas Instruments Incorporated
Product Folder Links: DS90UR124-Q1 DS90UR241-Q1
Submit Documentation Feedback
31
DS90UR124-Q1, DS90UR241-Q1
SNLS231O – SEPTEMBER 2006 – REVISED APRIL 2015
www.ti.com
11.2 Layout Examples
LVCMOS
INPUTS
HIGH
SPEED
SERIAL
STREAM
Figure 33. Example DS90UR241-Q1 EMC Layout
AC DECOUPLING
CAPS PLACEMENT
Figure 34. DS90UR241-Q1 EMC EVM Layer 4
HIGH
SPEED
SERIAL
INPUTS
LVCMOS
OUTPUTS
Figure 35. Example DS90UR124-Q1 EMC Layout
32
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Product Folder Links: DS90UR124-Q1 DS90UR241-Q1
DS90UR124-Q1, DS90UR241-Q1
www.ti.com
SNLS231O – SEPTEMBER 2006 – REVISED APRIL 2015
Layout Examples (continued)
AC
DECOUPLING
CAPS
PLACEMENT
Figure 36. DS90UR124-Q1 EMC EVM Layer 4
Copyright © 2006–2015, Texas Instruments Incorporated
Product Folder Links: DS90UR124-Q1 DS90UR241-Q1
Submit Documentation Feedback
33
DS90UR124-Q1, DS90UR241-Q1
SNLS231O – SEPTEMBER 2006 – REVISED APRIL 2015
www.ti.com
12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
• LVDS Interconnect Guidelines AN-1108, SNLA008
• LVDS Interconnect Guidelines AN-905, SNLA035
12.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 5. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
DS90UR124-Q1
Click here
Click here
Click here
Click here
Click here
DS90UR241-Q1
Click here
Click here
Click here
Click here
Click here
12.4 Trademarks
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
34
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Copyright © 2006–2015, Texas Instruments Incorporated
Product Folder Links: DS90UR124-Q1 DS90UR241-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
28-Oct-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
DS90UR124IVS/NOPB
ACTIVE
TQFP
PAG
64
160
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 105
DS90UR124
IVS
DS90UR124IVSX/NOPB
ACTIVE
TQFP
PAG
64
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 105
DS90UR124
IVS
DS90UR124QVS/NOPB
ACTIVE
TQFP
PAG
64
160
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 105
DS90UR124
QVS
DS90UR124QVSX/NOPB
ACTIVE
TQFP
PAG
64
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 105
DS90UR124
QVS
DS90UR241IVS/NOPB
ACTIVE
TQFP
PFB
48
250
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 105
DS90UR24
1IVS
DS90UR241IVSX/NOPB
ACTIVE
TQFP
PFB
48
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 105
DS90UR24
1IVS
DS90UR241QVS/NOPB
ACTIVE
TQFP
PFB
48
250
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 105
DS90UR24
1QVS
DS90UR241QVSX/NOPB
ACTIVE
TQFP
PFB
48
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 105
DS90UR24
1QVS
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
(4)
28-Oct-2014
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF DS90UR124, DS90UR124-Q1, DS90UR241, DS90UR241-Q1 :
• Catalog: DS90UR124, DS90UR241
• Automotive: DS90UR124-Q1, DS90UR241-Q1
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Oct-2014
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
DS90UR124IVSX/NOPB
TQFP
PAG
64
1000
330.0
24.4
13.0
13.0
1.45
16.0
24.0
Q2
DS90UR124QVSX/NOPB
TQFP
PAG
64
1000
330.0
24.4
13.0
13.0
1.45
16.0
24.0
Q2
DS90UR241IVSX/NOPB
TQFP
PFB
48
1000
330.0
16.4
9.3
9.3
2.2
12.0
16.0
Q2
DS90UR241QVSX/NOPB
TQFP
PFB
48
1000
330.0
16.4
9.3
9.3
2.2
12.0
16.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Oct-2014
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DS90UR124IVSX/NOPB
TQFP
PAG
64
1000
367.0
367.0
45.0
DS90UR124QVSX/NOPB
TQFP
PAG
64
1000
367.0
367.0
45.0
DS90UR241IVSX/NOPB
TQFP
PFB
48
1000
367.0
367.0
38.0
DS90UR241QVSX/NOPB
TQFP
PFB
48
1000
367.0
367.0
38.0
Pack Materials-Page 2
MECHANICAL DATA
MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996
PAG (S-PQFP-G64)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
48
0,08 M
33
49
32
64
17
0,13 NOM
1
16
7,50 TYP
Gage Plane
10,20
SQ
9,80
12,20
SQ
11,80
0,25
0,05 MIN
1,05
0,95
0°– 7°
0,75
0,45
Seating Plane
0,08
1,20 MAX
4040282 / C 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MTQF019A – JANUARY 1995 – REVISED JANUARY 1998
PFB (S-PQFP-G48)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
36
0,08 M
25
37
24
48
13
0,13 NOM
1
12
5,50 TYP
7,20
SQ
6,80
9,20
SQ
8,80
Gage Plane
0,25
0,05 MIN
0°– 7°
1,05
0,95
Seating Plane
0,75
0,45
0,08
1,20 MAX
4073176 / B 10/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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