Fairchild FT7511 Reset timer with fixed delay and reset pulse Datasheet

FT7511
Reset Timer with Fixed Delay and Reset Pulse
Features
Description
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The FT7511 is a timer for resetting a mobile device
where long reset times are needed. The long delay
helps avoid unintended resets caused by accidental key
presses. It has a fixed delay of 7.5 ±20% seconds. The
DSR pin enables Test Mode operation by immediately
forcing /RST1 LOW for factory testing.
Fixed Reset Delay: 7.5 Seconds
One Input Reset Pin
Open-Drain Output Pin with Fixed 80ms Pulse
1.8V to 5.0V Operation (TA=-40°C to +85°C)
1.7V to 5.0V Operation (TA=-25°C to +85°C)
The FT7511 has one input for single-button resetting
capability. The device has a single open-drain output
with 0.5mA pull-down drive.
1.65V to 5.0V Operation (TA=0°C to +85°C)
<1µA ICCQ Consumption
FT7511 draws minimal ICC current when inactive and
functions over a power supply range of 1.65V to 5.0V.
Zero-Second Test Mode Enable
Applications
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Cell Phones
Portable Media Players
Tablets
Mobile Devices
Consumer Medical
Figure 1.
Block Diagram
Ordering Information
Part Number
Operating
Temperature Range
Top
Mark
FT7511L6X
-40C to +85C
PD
© 2012 Fairchild Semiconductor Corporation
FT7511 • Rev. 1.0.0
Package
6-Lead, MicroPak™ 1.0 x 1.45mm,
JEDEC MO-252
Packing Method
5000 Units on
Tape and Reel
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FT7511 — Reset Timer with Fixed Delay and Reset Pulse
July 2012
Figure 2.
Pad Assignments (Top-Through View)
Pin Definitions
Description
Pin #
Name
1
/RST1
Open-Drain Output, Active LOW
Open-Drain Output, Active LOW
2
GND
GND
GND
3
/SR0
Reset Input, Active LOW
Reset Input, Active LOW
4
VCC
Power Supply
Power Supply
5
DSR
Delay Selection Input. Tie to GND(1) during
normal operation.
Delay Selection Input. Pull HIGH to enable the
0-second delay for factory test.
6
TEST
Used for device testing; should be tied to GND
during normal operation.
Used for device testing; should be tied to GND
during normal operation.
Normal Operation
0-Second Factory-Test Mode
Note:
1. The DSR pin must always be tied to either GND or VCC; it must not float.
© 2012 Fairchild Semiconductor Corporation
FT7511 • Rev. 1.0.0
www.fairchildsemi.com
2
FT7511 — Reset Timer with Fixed Delay and Reset Pulse
Pin Configuration
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
VCC
Supply Voltage
VIN
DC Input Voltage
VOUT
Min.
Max.
Unit
-0.5
7.0
V
/SR0, DSR
-0.5
7.0
V
/RST1
-0.5
7.0
V
IIK
DC Input Diode Current
VIN < 0V
-50
mA
IOK
DC Output Diode Current
VOUT < 0V
-50
mA
IOL
DC Output Sink Current
+50
mA
ICC
DC VCC or Ground Current per Supply Pin
100
mA
+150
C
TSTG
Output Voltage
(2)
Condition
Storage Temperature Range
-65
TJ
Junction Temperature Under Bias
+150
C
TL
Junction Lead Temperature, Soldering 10 Seconds
+260
C
PD
Power Dissipation
5
mW
ESD
Electrostatic Discharge Capability
Human Body Model, JESD22-A114
4
Charged Device Model, JESD22-C101
2
kV
Note:
2. All output current Absolute Maximum Ratings must be observed.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
VCC
Parameter
Supply Voltage
(3)
Condition
Min.
Max.
-40C to +85C
1.8
5.0
-25C to +85C
1.7
5.0
0C to +85C
1.65
5.00
Unit
V
tRFC
VCC Recovery Time After Power Down
VCC=0V After Power Down, Rising to
0.5V
5
VIN
Input Voltage(3)
/SR0
0
5
V
VOUT
Output Voltage
/RST1
0
5
V
IOL
DC Output Sink Current
/RST1, VCC=1.8V to 5.0V
+0.5
mA
TA
Free-Air Operating Temperature
+85
C
JA
Thermal Resistance
350
°C/W
-40
ms
Note:
3. VCC should never be allowed to float while input pins are driven.
© 2012 Fairchild Semiconductor Corporation
FT7511 • Rev. 1.0.0
www.fairchildsemi.com
3
FT7511 — Reset Timer with Fixed Delay and Reset Pulse
Absolute Maximum Ratings
Unless otherwise specified; conditions of TA=-40 to 80°C with VCC=1.8 - 5.0V, OR TA=-25 to 85°C with VCC=1.7 – 5V,
OR TA=0 to 85°C with VCC=1.65 – 5V produce the performance characteristics below.
Symbol
VIH
Parameter
Condition
Min.
Max.
Unit
Input High Voltage
DSR, /SR0
VIL
Input Low Voltage
DSR, /SR0
0.25 x VCC
V
VOL
Low Level Output Voltage
RST, IOL=500µA
0.3
V
Input Leakage Current (/SR0, DSR)
0V  VIN  5.0V
1.0
µA
1
µA
100
µA
IIN
ICC
0.65 x VCC
V
Quiescent Supply Current (Timer Inactive) /SR0=VCC
Dynamic Supply Current (Timer Active)
/SR0=0V
AC Electrical Characteristics
Unless otherwise specified; conditions of TA=-40 to 80°C with VCC=1.8 - 5.0V, OR TA=-25 to 85°C with VCC=1.7 – 5V,
OR TA=0 to 85°C with VCC=1.65 – 5V produce the performance characteristics below.
Symbol
tPHL1
Parameter
Condition
Timer Delay, /SR0 to RST (DSR=0)
Min.
Typ.
Max.
Unit
6.0
7.5
9.0
s
60
80
100
ms
CL=5pF, RL=5K, See Figure 6
tREC
Reset Timeout Delay
Capacitance Specifications
TA=+25C.
Symbol
CIN
COUT
Parameter
Condition
Typical
Unit
Input Capacitance
VCC=GND
4.0
pF
Output Capacitance
VCC=5.0V
5.0
pF
© 2012 Fairchild Semiconductor Corporation
FT7511 • Rev. 1.0.0
www.fairchildsemi.com
4
FT7511 — Reset Timer with Fixed Delay and Reset Pulse
DC Electrical Characteristics
original HIGH state 80ms after time tREC has expired,
regardless of the state of /SR0. The /RST1 output is an
open-drain driver. When the count time exceeds 7.5
seconds, the /RST1 output pulls LOW.
Device default operation time N is 7.5s. If the DSR pin is
pulled HIGH prior to VCC ramp, the FT7511 enters Test
Mode and the reset output, /RST1, is immediately pulled
LOW for factory testing. The DSR pin MUST be forced
to GND during normal operation. The DSR pin should
never be driven HIGH or left to float during normal
operation. The DSR pin state should never be changed
during device operation; it must be biased prior to
supplying the VCC supply. If there is a need to use the
DSR=VCC Test Mode, the /SR0 must be HIGH when the
DSR pin is moved from LOW to HIGH to enter ZeroSecond Factory-Test Mode. To return to the standard
7.5-second reset time, the same procedure must be
followed with DSR=GND. The DSR pin should never be
allowed to change state while the /SR0 pin is LOW.
Short Duration (tW < 7.5s)
When the /SR0 input goes LOW, the internal timer starts
counting. If the /SR0 input goes HIGH before 7.5s has
elapsed, the timer stops counting and resets; no
changes occur on the outputs.
Long Duration (tW > 7.5s)
When the /SR0 input goes LOW, the internal timer starts
counting. If the /SR0 input stays LOW for at least 7.5s, the
RST output is enabled and pulled LOW. The output RST
is held LOW for tREC, 80ms, as soon as the reset time of
7.5s is met, regardless of the state of the /SR0 pin.
When the /SR0 input has returned HIGH and tREC has
expired, the internal timer resets and awaits the next
RESET event.
Operation Modes
A low input signal on /SR0 starts the oscillator. There
are two scenarios for counting: short duration and long
duration. In the short-duration scenario, output /RST1 is
not affected. In the long-duration scenario, the output
/RST1 goes LOW after /SR0 has been held LOW for at
least 7.5 seconds. The /RST1 output returns to its
Figure 3.
© 2012 Fairchild Semiconductor Corporation
FT7511 • Rev. 1.0.0
0-Second Test Mode
/RST1 goes LOW immediately after /SR0 goes LOW.
Reset Timing Waveforms
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FT7511 — Reset Timer with Fixed Delay and Reset Pulse
Functional Description
FT7511 — Reset Timer with Fixed Delay and Reset Pulse
Application Diagram
Figure 4.
Recommended Application Diagram
AC Test Circuit and Waveforms
Figure 5.
AC Test Circuit
© 2012 Fairchild Semiconductor Corporation
FT7511 • Rev. 1.0.0
Figure 6.
Waveforms for /RST1 Output
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6
2X
0.05 C
1.45
B
2X
(1)
0.05 C
(0.254)
(0.49)
5X
1.00
(0.75)
PIN 1 IDENTIFIER
5
(0.52)
1X
A
TOP VIEW
0.55MAX
(0.30)
6X
PIN 1
0.05 C
0.05
0.00
RECOMMENED
LAND PATTERN
0.05 C
C
0.25
0.15 6X
1.0
DETAIL A
0.10
0.05
0.45
0.35
0.10
0.00 6X
C B A
C
0.40
0.30
0.35 5X
0.25
0.40 5X
0.30
0.5
(0.05)
6X
0.075 X 45
CHAMFER
DETAIL A
PIN 1 TERMINAL
(0.13)
4X
BOTTOM VIEW
Notes:
1. CONFORMS TO JEDEC STANDARD M0-252 VARIATION UAAD
2. DIMENSIONS ARE IN MILLIMETERS
3. DRAWING CONFORMS TO ASME Y14.5M-1994
4. FILENAME AND REVISION: MAC06AREV4
5. PIN ONE IDENTIFIER IS 2X LENGTH OF ANY
OTHER LINE IN THE MARK CODE LAYOUT.
Figure 7.
6-Lead MicroPak™ 1.0 x 1.45mm, JEDEC MO-252
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2012 Fairchild Semiconductor Corporation
FT7511 • Rev. 1.0.0
www.fairchildsemi.com
7
FT7511 — Reset Timer with Fixed Delay and Reset Pulse
Physical Dimensions
FT7511 — Reset Timer with Fixed Delay and Reset Pulse
© 2012 Fairchild Semiconductor Corporation
FT7511 • Rev. 1.0.0
www.fairchildsemi.com
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