NSC COP988GD 8-bit cmos rom based microcontrollers with 16k Datasheet

COP888GD
8-Bit CMOS ROM Based Microcontrollers with 16k
Memory and 8-Channel A/D
General Description
The COP888GD ROM based microcontrollers are highly integrated COP8™ Feature core devices with 16k memory
and advanced features including an A/D Converter. These
multi-chip CMOS devices are suited for applications requiring a full featured controller with an 8-bit A/D converter, and
as pre-production devices for a masked ROM design. Pin
and software compatible 16k or 32k OTP EPROM versions
are available (COP87L88GD/RD Family) for pre-production,
and for use with a range of COP8 software and hardware development tools.
Family features include an 8-bit memory mapped architecture, 10 MHz CKI with 1µs instruction cycle, three multifunction 16-bit timer/counters, MICROWIRE/PLUS™ serial
I/O, one 8-bit/8-channel A/D converter with prescaler and
both differential and single ended modes, two power saving
HALT/IDLE modes, MIWU, idle timer, high current outputs,
software selectable I/O options, WATCHDOG™ timer and
Clock Monitor, 2.5V to 5.5V operation, program code security, and 44 pin package.
Devices included in this datasheet are:
Device
Memory (bytes)
RAM (bytes)
I/O Pins
Packages
Temperature
COP688GD
16k ROM
256
40
44 PLCC
-55 to +125˚C
4.5V to 5.5V
Comments
COP888GD
16k ROM
256
40
44 PLCC
-40 to +85˚C
2.5V to 5.5V
COP988GD
16k ROM
256
40
44 PLCC
0 to +70˚C
2.5V to 4.0V, GDH = 4.0V to
6.0V
Key Features
CPU/Instruction Set Features
n 8-channel A/D converter with prescaler and both
differential and single ended modes
n Three 16-bit timers, each with two 16-bit registers
supporting:
— Processor Independent PWM mode
— External Event counter mode
— Input Capture mode
n Quiet design (low radiated emissions)
n 16 kbytes on-board ROM
n 256 bytes on-board RAM
n 1 µs instruction cycle time
n Twelve multi-source vectored interrupts servicing
— External Interrupt
— Idle Timer T0
— Three Timers (each with 2 Interrupts)
— MICROWIRE/PLUS
— Multi-Input Wake Up
— Software Trap
— Default VIS (default interrupt)
n Versatile and easy to use instruction set
n 8-bit Stack Pointer (SP) – stack in RAM
n Two 8-bit Register Indirect Data Memory Pointers (B
and X)
Additional Peripheral Features
n
n
n
n
Idle Timer
Multi-Input Wakeup (MIWU) with optional interrupts (8)
WATCHDOG and clock monitor logic
MICROWIRE/PLUS serial I/O
I/O Features
n Memory mapped I/O
n Software selectable I/O options (TRI-STATE ® Output,
Push-Pull Output, Weak Pull Up Input, High Impedance
Input)
n Schmitt trigger inputs on ports G and L
n Package:
— 44 PLCC with 40 I/O pins
Fully Static CMOS
n Two power saving modes: HALT and IDLE
n Single supply operation: 2.5V to 5.5V
n Temperature range: −0˚C to +70˚C and −40˚C to +85˚C
Development Support
n Emulation and OTP devices
n Real time emulation and full program debug offered by
MetaLink Development System
TRI-STATE ® is a registered trademark of National Semiconductor Corporation.
MICROWIRE/PLUS™, COP8™, MICROWIRE™ and WATCHDOG™ are trademarks of National Semiconductor Corporation.
iceMASTER ® is a registered trademark of MetaLink Corporation.
© 1999 National Semiconductor Corporation
DS100076
www.national.com
COP888GD 8-Bit CMOS ROM Based Microcontrollers with 16k Memory and 8-Channel A/D
July 1999
Block Diagram
DS100076-1
FIGURE 1. Block Diagram
Connection Diagrams
Plastic Chip Carrier
DS100076-2
Top View
Order Number COP888GD-XXXV, COP988GD-XXX/V
See NS Plastic Chip Package Number V44A
FIGURE 2. Connection Diagrams
www.national.com
2
Connection Diagrams
(Continued)
Pinouts for 44-Pin Package
Port
Type
Alt. Fun
Alt. Fun
44-Pin
Pack.
L0
I/O
MIWU
17
L1
I/O
MIWU
18
L2
I/O
MIWU
19
L3
I/O
MIWU
L4
I/O
MIWU
T2A
25
L5
I/O
MIWU
T2B
26
L6
I/O
MIWU
T3A
27
L7
I/O
MIWU
T3B
G0
I/O
INT
G1
WDOUT
G2
I/O
T1B
41
G3
I/O
T1A
42
G4
I/O
SO
3
G5
I/O
SK
4
G6
I
SI
5
G7
I/CKO
HALT Restart
D0
O
29
D1
O
30
D2
O
31
D3
O
32
D4
O
33
D5
O
34
D6
O
35
D7
O
I0
I
ACH0
9
I1
I
ACH1
10
I2
I
ACH2
11
I3
I
ACH3
12
I4
I
ACH4
13
I5
I
ACH5
14
I6
I
ACH6
15
I7
I
ACH7
16
C0
I/O
43
C1
I/O
44
C2
I/O
1
C3
I/O
2
C4
I/O
21
C5
I/O
22
C6
I/O
23
C7
I/O
24
20
28
39
40
6
36
VCC
8
GND
37
CKI
7
RESET
38
3
www.national.com
Absolute Maximum Ratings (Note 1)
(Source)
Total Current out of GND Pin
(Sink)
Storage Temperature Range
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (VCC)
Voltage at Any Pin
Total Current into VCC Pin
100 mA
110 mA
−65˚C to +140˚C
Note 1: Absolute maximum ratings indicate limits beyond which damage to
the device may occur. DC and AC electrical specifications are not ensured
when operating the device at absolute maximum ratings.
7V
−0.3V to VCC + 0.3V
DC Electrical Characteristics
−0˚C ≤ TA ≤ +70˚C unless otherwise specified
Parameter
Conditions
Operating Voltage
Power Supply Ripple (Note 3)
Min
2.5
Peak-to-Peak
Typ
Max
Units
5.5
V
0.1 VCC
V
Supply Current (Note 4)
CKI = 10 MHz
VCC = 5.5V, tc = 1 µs
20
mA
CKI = 4 MHz
VCC = 4.0V, tc = 2.5
µs
10
mA
VCC = 5.5V, CKI = 0
MHz
12
µA
VCC = 4.0V, CKI = 0
MHz
10
µA
CKI = 10 MHz
VCC = 5.5V, tc = 1 µs
1.2
mA
CKI = 4 MHz
VCC = 4.0V, tc = 2.5
µs
1
mA
HALT Current (Note 5)
IDLE Current (Note 4)
Input Levels
RESET , CKI
Logic High
0.8
VCC
Logic Low
V
0.2 VCC
V
All Other Inputs (L0-L7, G0-G6, C0-C7,
I0-I7)
Logic High
0.7
VCC
V
0.2 VCC
V
Hi-Z Input Leakage
VCC = 5.5V
−2
+2
µA
Input Pullup Current
VCC = 5.5V, VIN = 0V
−40
−250
µA
0.35
VCC
V
Logic Low
G and L Port Input Hysteresis (Note 9)
Output Current Levels
D Outputs
Source
VCC = 4.5V, VOH =
3.3V
Sink (Note 6)
−0.4
mA
VCC = 4.5V, VOL = 1V
10
mA
Source (Weak Pull-Up Mode)
VCC = 4.5V, VOH =
2.7V
−10
Source (Push-Pull Mode)
VCC = 4.5V, VOH =
3.3V
−0.4
mA
Sink (Push-Pull Mode)
VCC = 4.5V, VOL =
0.4V
1.6
mA
VCC = 5.5V
−2
All Others
TRI-STATE Leakage
−100
µA
+2
µA
15
mA
Allowable Sink/Source Current per Pin
D Outputs (Sink)
www.national.com
4
DC Electrical Characteristics
(Continued)
−0˚C ≤ TA ≤ +70˚C unless otherwise specified
Parameter
Conditions
Min
Typ
All others
Maximum Input Current
Room Temp
Max
Units
3
mA
± 100
mA
without Latchup (Note 7) (Note 9)
RAM Retention Voltage, Vr
500 ns Rise
2
V
and Fall Time (min)
Input Capacitance
Load Capacitance on D2
7
pF
1000
pF
Note 2: tc = Instruction Cycle Time
Note 3: Maximum rate of voltage change must be < 0.5 V/ms.
Note 4: Supply and IDLE currents are measured with CKI driven with a square wave Oscillator, CKO driven 180˚ out of phase with CKI, inputs connected to VCC
and outputs driven low but not connected to a load.
Note 5: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations by bringing CKI high. Measurement of IDD HALT is done with device
neither sourcing nor sinking current; with L, C, G0, and G2–G5 programmed as low outputs and not driving a load; all outputs programmed low and not driving a load;
all inputs tied to VCC; clock monitor and comparator disabled. Parameter refers to HALT mode entered via setting bit 7 of the G Port data register. Part will pull up
CKI during HALT in crystal clock mode.
Note 6: The user must guarantee that D2 pin does not source more than 10 mA during RESET. If D2 sources more than 10 mA during reset, the device will go into
programming mode.
Note 7: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages VCC and the pins will have sink current to VCC when
biased at voltages VCC (the pins do not have source current when biased at a voltage below VCC). The effective resistance to VCC is 750Ω (typical). These two pins
will not latch up. The voltage at the pins must be limited to < 14V. WARNING: Voltages in excess of 14V will cause damage to the pins. This warning excludes ESD
transients.
Note 8: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.
Note 9: Parameter characterized but not tested.
AC Electrical Characteristics
−40˚C ≤ TA ≤ +85˚C unless otherwise specified
Parameter
Conditions
Min
Typ
Max
Units
Instruction Cycle Time (tc)
Crystal, Resonator,
4.5V ≤ VCC ≤ 5.5V
1.0
DC
µs
R/C Oscillator
4.5V ≤ VCC ≤ 5.5V
3.0
DC
µs
fr = Max
40
60
CKI Clock Duty Cycle (Note 9)
Rise Time (Note 9)
fr = 10 MHz Ext Clock
5
ns
Fall Time (Note 9)
fr = 10 MHz Ext Clock
5
ns
Inputs
tSETUP
4.5V ≤ VCC ≤ 5.5V
200
ns
tHOLD
4.5V ≤ VCC ≤ 5.5V
60
ns
Output Propagation Delay (Note 8)
RL = 2.2k, CL = 100 pF
tPD1, tPD0
SO, SK
4.5V ≤ VCC ≤ 5.5V
0.7
µs
All Others
4.5V ≤ VCC ≤ 5.5V
1.0
µs
MICROWIRE™ Setup Time (tUWS) (Note
9)
20
MICROWIRE Hold Time (tUWH) (Note 9)
56
ns
ns
220
MICROWIRE Output Propagation Delay
(tUPD)
ns
Input Pulse Width (Note 9)
Interrupt Input High Time
1.0
tc
Interrupt Input Low Time
1.0
tc
Timer 1, 2, 3 Input High Time
1.0
tc
Timer 1, 2, 3 Input Low Time
1.0
tc
1.0
µs
Reset Pulse Width
Note 10: tc = Instruction Cycle Time
Note 11: Maximum rate of voltage change must be < 0.5 V/ms.
5
www.national.com
AC Electrical Characteristics
(Continued)
Note 12: Supply and IDLE currents are measured with CKI driven with a square wave Oscillator, CKO driven 180˚ out of phase with CKI, inputs connected to VCC
and outputs driven low but not connected to a load.
Note 13: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations by bringing CKI high. Measurement of IDD HALT is done with device
neither sourcing nor sinking current; with L, C, G0, and G2–G5 programmed as low outputs and not driving a load; all outputs programmed low and not driving a load;
all inputs tied to VCC; clock monitor and comparator disabled. Parameter refers to HALT mode entered via setting bit 7 of the G Port data register. Part will pull up
CKI during HALT in crystal clock mode.
Note 14: The user must guarantee that D2 pin does not source more than 10 mA during RESET. If D2 sources more than 10 mA during reset, the device will go into
programming mode.
Note 15: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages VCC and the pins will have sink current to VCC when
biased at voltages VCC (the pins do not have source current when biased at a voltage below VCC). The effective resistance to VCC is 750Ω (typical). These two pins
will not latch up. The voltage at the pins must be limited to < 14V. WARNING: Voltages in excess of 14V will cause damage to the pins. This warning excludes ESD
transients.
Note 16: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.
Note 17: Parameter characterized but not tested.
www.national.com
6
Absolute Maximum Ratings (Note 1)
(Source)
Total Current out of GND Pin
(Sink)
Storage Temperature Range
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (VCC)
Voltage at Any Pin
Total Current into VCC Pin
100 mA
110 mA
−65˚C to +140˚C
Note 18: Absolute maximum ratings indicate limits beyond which damage to
the device may occur. DC and AC electrical specifications are not ensured
when operating the device at absolute maximum ratings.
7V
−0.3V to VCC + 0.3V
DC Electrical Characteristics
−40˚C ≤ TA ≤ +85˚C unless otherwise specified
Parameter
Conditions
Operating Voltage
Power Supply Ripple (Note 3)
Min
2.7
Peak-to-Peak
Typ
Max
Units
5.5
V
0.1 VCC
V
Supply Current (Note 4)
CKI = 10 MHz
VCC = 5.5V, tc = 1 µs
20
mA
CKI = 4 MHz
VCC = 4.0V, tc = 2.5
µs
10
mA
VCC = 5.5V, CKI = 0
MHz
12
µA
VCC = 4.0V, CKI = 0
MHz
10
µA
CKI = 10 MHz
VCC = 5.5V, tc = 1 µs
1.2
mA
CKI = 4 MHz
VCC = 4.0V, tc = 2.5
µs
1
mA
HALT Current (Note 5)
IDLE Current (Note 4)
Input Levels
RESET , CKI
Logic High
0.8
VCC
Logic Low
V
0.2 VCC
V
All Other Inputs (L0-L7, G0-G6, C0-C7,
I0-I7)
Logic High
0.7
VCC
V
0.2 VCC
V
Hi-Z Input Leakage
VCC = 5.5V
−2
+2
µA
Input Pullup Current
VCC = 5.5V, VIN = 0V
−40
−250
µA
0.35
VCC
V
Logic Low
G and L Port Input Hysteresis (Note 9)
Output Current Levels
D Outputs
Source
VCC = 4.5V, VOH =
3.3V
Sink (Note 6)
−0.4
mA
VCC = 4.5V, VOL = 1V
10
mA
Source (Weak Pull-Up Mode)
VCC = 4.5V, VOH =
2.7V
−10
Source (Push-Pull Mode)
VCC = 4.5V, VOH =
3.3V
−0.4
mA
Sink (Push-Pull Mode)
VCC = 4.5V, VOL =
0.4V
1.6
mA
VCC = 5.5V
−2
All Others
TRI-STATE Leakage
−100
µA
+2
µA
15
mA
Allowable Sink/Source Current per Pin
D Outputs (Sink)
7
www.national.com
DC Electrical Characteristics
(Continued)
−40˚C ≤ TA ≤ +85˚C unless otherwise specified
Parameter
Conditions
Min
Typ
All others
Maximum Input Current
Room Temp
Max
Units
3
mA
± 100
mA
without Latchup (Note 7) (Note 9)
RAM Retention Voltage, Vr
500 ns Rise
2
V
and Fall Time (min)
Input Capacitance
Load Capacitance on D2
7
pF
1000
pF
AC Electrical Characteristics
−40˚C ≤ TA ≤ +85˚C unless otherwise specified
Parameter
Conditions
Min
Typ
Max
Units
Instruction Cycle Time (tc)
Crystal, Resonator,
4.5V ≤ VCC ≤ 5.5V
1.0
DC
µs
R/C Oscillator
4.5V ≤ VCC ≤ 5.5V
3.0
DC
µs
fr = Max
40
60
CKI Clock Duty Cycle (Note 9)
Rise Time (Note 9)
fr = 10 MHz Ext Clock
5
ns
Fall Time (Note 9)
fr = 10 MHz Ext Clock
5
ns
Inputs
tSETUP
4.5V ≤ VCC ≤ 5.5V
200
ns
tHOLD
4.5V ≤ VCC ≤ 5.5V
60
ns
Output Propagation Delay (Note 8)
RL = 2.2k, CL = 100 pF
tPD1, tPD0
SO, SK
4.5V ≤ VCC ≤ 5.5V
0.7
µs
All Others
4.5V ≤ VCC ≤ 5.5V
1.0
µs
MICROWIRE Setup Time (tUWS) (Note 9)
20
MICROWIRE Hold Time (tUWH) (Note 9)
56
ns
ns
220
MICROWIRE Output Propagation Delay
(tUPD)
ns
Input Pulse Width (Note 9)
Interrupt Input High Time
1.0
tc
Interrupt Input Low Time
1.0
tc
Timer 1, 2, 3 Input High Time
1.0
tc
Timer 1, 2, 3 Input Low Time
1.0
tc
1.0
µs
Reset Pulse Width
Note 19: tc = Instruction Cycle Time
Note 20: Maximum rate of voltage change must be < 0.5 V/ms.
Note 21: Supply and IDLE currents are measured with CKI driven with a square wave Oscillator, CKO driven 180˚ out of phase with CKI, inputs connected to VCC
and outputs driven low but not connected to a load.
Note 22: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations by bringing CKI high. Measurement of IDD HALT is done with device
neither sourcing nor sinking current; with L, C, G0, and G2–G5 programmed as low outputs and not driving a load; all outputs programmed low and not driving a load;
all inputs tied to VCC; clock monitor and comparator disabled. Parameter refers to HALT mode entered via setting bit 7 of the G Port data register. Part will pull up
CKI during HALT in crystal clock mode.
Note 23: The user must guarantee that D2 pin does not source more than 10 mA during RESET. If D2 sources more than 10 mA during reset, the device will go into
programming mode.
Note 24: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages VCC and the pins will have sink current to VCC when
biased at voltages VCC (the pins do not have source current when biased at a voltage below VCC). The effective resistance to VCC is 750Ω (typical). These two pins
will not latch up. The voltage at the pins must be limited to < 14V. WARNING: Voltages in excess of 14V will cause damage to the pins. This warning excludes ESD
transients.
Note 25: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.
Note 26: Parameter characterized but not tested.
www.national.com
8
A/D Converter Specifications
VCC = 5V ± 10%, (VSS–0.050V) ≤ Any Input ≤ (VCC + 0.050V)
Parameter
Conditions
Min
Typ
Resolution
Absolute Accuracy
Non-Linearity
Deviation from the Best Straight
Line
Differential Non-Linearity
Common Mode Input Range
GND
DC Common Mode Error
Max
Units
8
Bits
±2
±1
LSB
±1
LSB
LSB
VCC
V
± 1/2
LSB
µA
Off Channel Leakage Current
1
2
On Channel Leakage Current
1
2
µA
1.67
MHz
A/D Clock Frequency
0.1
Converison Time
17
Internal Reference Resistance
A/D Clock Cycles
1
µs
Tum-on Time
Note 27: Conversion Time includes 7 A/D clock cycles sample and hold time.
Note 28: See Prescaler description.
Note 29: For VIN(−) = VIN (+) the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input. The diodes will forward conduct for analog
input voltages below ground or above the VCC supply. Be careful, during testing at low VCC levels (4.5V), as high level analog inputs (5V) can cause this input diode
to conduct — especially at elevated temperatures, and cause errors for analog inputs near full-scale. The spec allows 50 mV forward bias of either diode. This means
that as long as the analog VIN does not exceed the supply voltage by more than 50 mV, the output code will be correct. To achieve an absolute 0 VDC to 5 VDC input
voltage range will therefore require a minimum supply voltage of 4.950 VDC over temperature variations, initial tolerance and loading.
Note 30: Time or internal reference reistance to turn on and settle after coming out of HALT or IDLE mode.
DS100076-4
FIGURE 3. MICROWIRE/PLUS Timing
9
www.national.com
Typical Performance Characteristics
(−55˚C ≤ TA = +125˚C)
DS100076-19
DS100076-20
DS100076-21
DS100076-22
DS100076-23
www.national.com
10
configuration registers for G6 and G7 are used for special
purpose functions as outlined on the next page. Reading the
G6 and G7 data bits will return zeros.
Pin Descriptions
VCC and GND are the power supply pins. All VCC and GND
pins must be connected.
CKI is the clock input. This can come from an R/C generated
oscillator, or a crystal oscillator (in conjunction with CKO).
See Oscillator Description section.
RESET is the master reset input. See Reset Description section.
The device contains three bidirectional 8-bit I/O ports (C, G
and L), where each individual bit may be independently configured as an input (Schmitt Trigger inputs on ports L and G),
output or TRI-STATE under program control. Three data
memory address locations are allocated for each of these
I/O ports. Each I/O port has two associated 8-bit memory
mapped registers, the CONFIGURATION register and the
output DATA register. A memory mapped address is also reserved for the input pins of each I/O port. (See the memory
map for the various addresses associated with the I/O ports.)
Figure 4 shows the I/O port configurations. The DATA and
CONFIGURATION registers allow for each port bit to be individually configured under software control as shown below:
CONFIGURATION
DATA
Register
Register
0
0
0
1
Input with Weak Pull-Up
1
0
Push-Pull Zero Output
1
1
Push-Pull One Output
DS100076-5
FIGURE 4. I/O Port Configurations
Note that the chip will be placed in the HALT mode by writing
a “1” to bit 7 of the Port G Data Register. Similarly the chip
will be placed in the IDLE mode by writing a “1” to bit 6 of the
Port G Data Register.
Writing a “1” to bit 6 of the Port G Configuration Register enables the MICROWIRE/PLUS to operate with the alternate
phase of the SK clock. The G7 configuration bit, if set high,
enables the clock start up delay after HALT when the R/C
clock configuration is used.
Port Set-Up
Hi-Z Input
(TRI-STATE Output)
Config Reg.
PORT L is an 8-bit I/O port. All L-pins have Schmitt triggers
on the inputs.
Port L supports Multi-Input Wake Up on all eight pins. L4 and
L5 are used for the timer input functions T2A and T2B. L6
and L7 are used for the timer input functions T3A and T3B.
Port L has the following alternate features:
L7
MIWU or T3B
L6
MIWU or T3A
L5
MIWU or T2B
L4
MIWU or T2A
L3
MIWU
L2
MIWU
L1
MIWU
L0
MIWU
Port G is an 8-bit port with 5 I/O pins (G0, G2–G5), an input
pin (G6), and a dedicated output pin (G7). Pins G0 and
G2–G6 all have Schmitt Triggers on their inputs. Pin G1
serves as the dedicated WDOUT WATCHDOG output, while
pin G7 is either input or output depending on the oscillator
mask option selected. With the crystal oscillator option selected, G7 serves as the dedicated output pin for the CKO
clock output. With the single-pin R/C oscillator mask option
selected, G7 serves as a general purpose input pin but is
also used to bring the device out of HALT mode with a low to
high transition on G7. There are two registers associated
with the G Port, a data register and a configuration register.
Therefore, each of the 5 I/O bits (G0, G2–G5) can be individually configured under software control.
Data Reg.
G7
CLKDLY
HALT
G6
Alternate SK
IDLE
Port G has the following alternate features:
G6 SI (MICROWIRE Serial Data Input)
G5 SK (MICROWIRE Serial Clock)
G4 SO (MICROWIRE Serial Data Output)
G3 T1A (Timer T1 I/O)
G2 T1B (Timer T1 Capture Input)
G0 INTR (External Interrupt Input)
Port G has the following dedicated functions:
G7 CKO Oscillator dedicated output or general purpose
input
G1 WDOUT WATCHDOG and/or Clock Monitor dedicated output
Port C is an 8-bit I/O port. The 40-pin device does not have
a full complement of Port C pins. The unavailable pins are
not terminated. A read operation for these unterminated pins
will return unpredicatable values.
Port I is an 8-bit Hi-Z input port, and also provides the analog
inputs to the A/D converter. The 28-pin device does not have
a full complement of Port I pins. The unavailable pins are not
terminated (i.e. they are floating). A read operation from
these unterminated pins will return unpredictable values.
The user should ensure that the software takes this into account by either masking out these inputs, or else restricting
the accesses to bit operations only. If unterminated, Port I
pins will draw power only when addressed.
Since G6 is an input only pin and G7 is the dedicated CKO
clock output pin (crystal clock option) or general purpose input (R/C clock option), the associated bits in the data and
11
www.national.com
Pin Descriptions
registers X, SP, B and S are memory mapped into this space
at address locations 0FC to 0FF Hex respectively, with the
other registers being available for general usage.
The instruction set permits any bit in memory to be set, reset
or tested. All I/O and registers (except A and PC) are
memory mapped; therefore, I/O bits and register bits can be
directly and individually set, reset and tested. The accumulator (A) bits can also be directly and individually tested.
(Continued)
Port D is an 8-bit output port that is preset high when RESET
goes low. The user can tie two or more D port outputs (except D2) together in order to get a higher drive.
Note: Care must be exercised with the D2 pin operation. At RESET, the external loads on this pin must ensure that the output voltages stay
above 0.8 VCC to prevent the chip from entering special modes. Also
keep the external loading on D2 to < 1000 pF.
Note: RAM contents are undefined upon power-up.
Functional Description
Data Memory Segment RAM
Extension
The architecture of the device is modified Harvard architecture. With the Harvard architecture, the control store program memory (ROM) is separated from the data store
memory (RAM). Both ROM and RAM have their own separate addressing space with separate address buses. The architecture, though based on Harvard architecture, permits
transfer of data from ROM to RAM.
Data memory address 0FF is used as a memory mapped location for the Data Segment Address Register (S).
The data store memory is either addressed directly by a
single byte address within the instruction, or indirectly relative to the reference of the B, X, or SP pointers (each contains a single-byte address). This single-byte address allows
an addressing range of 256 locations from 00 to FF hex. The
upper bit of this single-byte address divides the data store
memory into two separate sections as outlined previously.
With the exception of the RAM register memory from address locations 00F0 to 00FF, all RAM memory is memory
mapped with the upper bit of the single-byte address being
equal to zero. This allows the upper bit of the single-byte address to determine whether or not the base address range
(from 0000 to 00FF) is extended. If this upper bit equals one
(representing address range 0080 to 00FF), then address
extension does not take place. Alternatively, if this upper bit
equals zero, then the data segment extension register S is
used to extend the base address range (from 0000 to 007F)
from XX00 to XX7F, where XX represents the 8 bits from the
S register. Thus the 128-byte data segment extensions are
located from addresses 0100 to 017F for data segment 1,
0200 to 027F for data segment 2, etc., up to FF00 to FF7F
for data segment 255. The base address range from 0000 to
007F represents data segment 0.
CPU REGISTERS
The CPU can do an 8-bit addition, subtraction, logical or shift
operation in one instruction (tc) cycle time.
There are six CPU registers:
A is the 8-bit Accumulator Register
PC is the 15-bit Program Counter Register
PU is the upper 7 bits of the program counter (PC)
PL is the lower 8 bits of the program counter (PC)
B is an 8-bit RAM address pointer, which can be optionally
post auto incremented or decremented.
X is an 8-bit alternate RAM address pointer, which can be
optionally post auto incremented or decremented.
SP is the 8-bit stack pointer, which points to the subroutine/
interrupt stack (in RAM). The SP is initialized to RAM address 06F with reset.
S is the 8-bit Data Segment Address Register used to extend
the lower half of the address range (00 to 7F) into 256 data
segments of 128 bytes each.
All the CPU registers are memory mapped with the exception of the Accumulator (A) and the Program Counter (PC).
Figure 5 illustrates how the S register data memory extension is used in extending the lower half of the base address
range (00 to 7F hex) into 256 data segments of 128 bytes
each, with a total addressing range of 32 kbytes from XX00
to XX7F. This organization allows a total of 256 data segments of 128 bytes each with an additional upper base segment of 128 bytes. Furthermore, all addressing modes are
available for all data segments. The S register must be
changed under program control to move from one data segment (128 bytes) to another. However, the upper base segment (containing the 16 memory registers, I/O registers,
control registers, etc.) is always available regardless of the
contents of the S register, since the upper base segment
(address range 0080 to 00FF) is independent of data segment extension.
The instructions that utilize the stack pointer (SP) always reference the stack as part of the base segment (Segment 0),
regardless of the contents of the S register. The S register is
not changed by these instructions. Consequently, the stack
(used with subroutine linkage and interrupts) is always located in the base segment. The stack pointer will be initialized to point at data memory location 006F as a result of
reset.
PROGRAM MEMORY
The program memory consists of 16 kbytes of ROM. These
bytes may hold program instructions or constant data (data
tables for the LAID instruction, jump vectors for the JID instruction, and interrupt vectors for the VIS instruction). The
program memory is addressed by the 15-bit program
counter (PC). All interrupts in the devices vector to program
memory location 0FF Hex.
DATA MEMORY
The data memory address space includes the on-chip RAM
and data registers, the I/O registers (Configuration, Data and
Pin), the control registers, the MICROWIRE/PLUS SIO shift
register, and the various registers, and counters associated
with the timers (with the exception of the IDLE timer). Data
memory is addressed directly by the instruction or indirectly
by the B, X, SP pointers and S register.
The data memory consists of 256 bytes of RAM. Sixteen
bytes of RAM are mapped as “registers” at addresses 0F0 to
0FF Hex. These registers can be loaded immediately, and
also decremented and tested with the DRSZ (decrement
register and skip if zero) instruction. The memory pointer
www.national.com
12
Data Memory Segment RAM
Extension (Continued)
output will continue until 16 tC–32 tC clock cycles following
the clock frequency reaching the minimum specified value,
at which time the G1 output will enter the TRI-STATE mode.
The external RC network shown in Figure 6 should be used
to ensure that the RESET pin is held low until the power supply to the chip stabilizes.
DS100076-7
RC > 5 x Power Supply Rise Time
FIGURE 6. Recommended Reset Circuit
Oscillator Circuits
The chip can be driven by a clock input on the CKI input pin
which can be between DC and 10 MHz. The CKO output
clock is on pin G7 (crystal configuration). The CKI input frequency is divided down by 10 to produce the instruction
cycle clock (1/tc).
DS100076-6
*Reads as all ones.
FIGURE 5. RAM Organization
Note: External clocks with frequencies above about 4 MHz require the user
to drive the CKO (G7) pin with a signal 180 degrees out of phase with
CKI.
The 128 bytes of RAM contained in the base segment are
split between the lower and upper base segments. The first
112 bytes of RAM are resident from address 0000 to 006F in
the lower base segment, while the remaining 16 bytes of
RAM represent the 16 data memory registers located at addresses 00F0 to 00FF of the upper base segment. No RAM
is located at the upper sixteen addresses (0070 to 007F) of
the lower base segment.
Additional RAM beyond these initial 128 bytes, however, will
always be memory mapped in groups of 128 bytes (or less)
at the data segment address extensions (XX00 to XX7F) of
the lower base segment. The additional 128 bytes of RAM
are memory mapped at address locations 0100 to 017F hex.
Figure 7 shows the Crystal and R/C oscillator diagrams.
CRYSTAL OSCILLATOR
CKI and CKO can be connected to make a closed loop crystal (or resonator) controlled oscillator.
Table 1 shows the component values required for various
standard crystal values.
R/C OSCILLATOR
By selecting CKI as a single pin oscillator input, a single pin
R/C oscillator circuit can be connected to it. CKO is available
as a general purpose input, and/or HALT restart input.
Reset
Note: Use of the R/C oscillator option will result in higher electromagnetic
emissions.
The RESET input when pulled low initializes the microcontroller. Initialization will occur whenever the RESET input is
pulled low. Upon initialization, the data and configuration
registers for ports L, G and C are cleared, resulting in these
Ports being initialized to the TRI-STATE mode. Pin G1 of the
G Port is an exception (as noted below) since pin G1 is dedicated as the WATCHDOG and/or Clock Monitor error output
pin. Port D is set high. The PC, PSW, ICNTRL, CNTRL,
T2CNTRL and T3CNTRL control registers are cleared. The
Comparator Select Register is cleared. The S register is initialized to zero. The Multi-Input Wakeup registers WKEN and
WKEDG are cleared. Wakeup register WKPND is unknown.
The stack pointer, SP, is initialized to 6F hex.
The device comes out of reset with both the WATCHDOG
logic and the Clock Monitor detector armed, with the
WATCHDOG service window bits set and the Clock Monitor
bit set. The WATCHDOG and Clock Monitor circuits are inhibited during reset. The WATCHDOG service window bits
being initialized high default to the maximum WATCHDOG
service window of 64k tC clock cycles. The Clock Monitor bit
being initialized high will cause a Clock Monitor error following reset if the clock has not reached the minimum specified
frequency at the termination of reset. A Clock Monitor error
will cause an active low error output on pin G1. This error
Table 1 shows the variation in the oscillator frequencies as
functions of the component (R and C) values.
13
www.national.com
Oscillator Circuits
SL1 & SL0
(Continued)
Select the MICROWIRE/PLUS clock divide
by (00 = 2, 01 = 4, 1x = 8)
PSW Register (Address X'00EF)
HC
C
T1PNDA
T1ENA
EXPND
BUSY
EXEN
Bit 7
GIE
Bit 0
The PSW register contains the following select bits:
HC
Half Carry Flag
C
Carry Flag
T1PNDA Timer T1 Interrupt Pending Flag (Autoreload
RA in mode 1, T1 Underflow in Mode 2, T1A
capture edge in mode 3)
T1ENA
DS100076-8
EXPND
BUSY
EXEN
Enable external interrupt
GIE
Global interrupt enable (enables interrupts)
The Half-Carry flag is also affected by all the instructions that
affect the Carry flag. The SC (Set Carry) and R/C (Reset
Carry) instructions will respectively set or clear both the carry
flags. In addition to the SC and R/C instructions, ADC,
SUBC, RRC and RLC instructions affect the Carry and Half
Carry flags.
DS100076-9
FIGURE 7. Crystal and R/C Oscillator Diagrams
TABLE 1. Crystal Oscillator Configuration, TA = 25˚C
R1
R2
C1
C2
CKI Freq
(kΩ)
(MΩ)
(pF)
(pF)
(MHz)
0
1
30
30–36
10
0
1
30
30–36
4
0
1
200
100–150
0.455
ICNTRL Register (Address X'00E8)
Conditions
Reserved
C
CKI Freq
Instr. Cycle
(kΩ)
(pF)
(MHz)
(µs)
3.3
82
2.2 to 2.7
3.7 to 4.6
5.6
100
1.1 to 1.3
7.4 to 9.0
6.8
100
0.9 to 1.1
8.8 to 10.8
Conditions
VCC = 5V
VCC = 5V
VCC = 5V
50 pF ≤ C ≤ 200 pF
T2C3
T1C1
T1C0
MSEL
IEDG
MSEL
IEDG
www.national.com
µWEN
T1PNDB
T1ENB
T2C2
SL1
T2C1
T2C0
T2PNDA
T2ENA
T2PNDB
T2ENB
Bit 0
The T2CNTRL control register contains the following bits:
T2C3
Timer T2 mode control bit
SL0
Bit 0
T2C2
T2C1
T2C0
The Timer1 (T1) and MICROWIRE/PLUS control register
contains the following bits:
T1C3
Timer T1 mode control bit
T1C2
Timer T1 mode control bit
T1C1
Timer T1 mode control bit
T1C0
µWPND
Bit 0
Bit 7
CNTRL Register (Address X'00EE)
T1C2
T0EN
T2CNTRL Register (Address X'00C6)
CONTROL REGISTERS
T1C3
T0PND
The ICNTRL register contains the following bits:
Reserved This bit is reserved and should to zero
LPEN
L Port Interrupt Enable (Multi-Input Wakeup/
Interrupt)
T0PND
Timer T0 Interrupt pending
T0EN
Timer T0 Interrupt Enable (Bit 12 toggle)
µWPND
MICROWIRE/PLUS interrupt pending
µWEN
Enable MICROWIRE/PLUS interrupt
T1PNDB Timer T1 Interrupt Pending Flag for T1B capture edge
T1ENB
Timer T1 Interrupt Enable for T1B Input capture edge
Note 31: 3k ≤ R ≤ 200k
Bit 7
LPEN
Bit 7
VCC = 5V
VCC = 5V
VCC = 5V
TABLE 2. RC Oscillator Configuration, TA = 25˚C
R
Timer T1 Interrupt Enable for Timer Underflow
or T1A Input capture edge
External interrupt pending
MICROWIRE/PLUS busy shifting flag
T2PNDA
Timer T1 Start/Stop control in timer
modes 1 and 2, T1 Underflow Interrupt
Pending Flag in timer mode 3
Selects G5 and G4 as MICROWIRE/PLUS
signals SK and SO respectively
External interrupt edge polarity select
(0 = Rising edge, 1 = Falling edge)
T2ENA
T2PNDB
14
Timer T2 mode control bit
Timer T2 mode control bit
Timer T2 Start/Stop control in timer
modes 1 and 2, T2 Underflow Interrupt Pending Flag in timer mode 3
Timer T2 Interrupt Pending Flag (Autoreload
RA in mode 1, T2 Underflow in mode 2, T2A
capture edge in mode 3)
Timer T2 Interrupt Enable for Timer Underflow
or T2A Input capture edge
Timer T2 Interrupt Pending Flag for T2B capture edge
CONTROL REGISTERS
T2ENB
Bits 11 through 15 of the ITMR register can be selected for
triggering the IDLE Timer interrupt. Each time the selected
bit underflows (every 4k, 8k, 16k, 32k or 64k instruction
cycles), the IDLE Timer interrupt pending bit T0PND is set,
thus generating an interrupt (if enabled), and bit 6 of the Port
G data register is reset, thus causing an exit from the IDLE
mode if the device is in that mode.
In order for an interrupt to be generated, the IDLE Timer interrupt enable bit T0EN must be set, and the GIE (Global Interrupt Enable) bit must also be set. The T0PND flag and
T0EN bit are bits 5 and 4 of the ICNTRL register, respectively. The interrupt can be used for any purpose. Typically, it
is used to perform a task upon exit from the IDLE mode. For
more information on the IDLE mode, refer to the Power Save
Modes section.
The Idle Timer period is selected by bits 0–2 of the ITMR
register Bits 3–7 of the ITMR Register are reserved and
should not be used as software flags.
(Continued)
Timer T2 Interrupt Enable for Timer Underflow
or T2B Input capture edge
T3CNTRL Register (Address X'00B6)
T3C3
T3C2
T3C1
T3C0
T3PNDA
T3ENA
T3PNDB
T3ENB
Bit 7
Bit 0
The T3CNTRL control register contains the following bits:
T3C3
Timer T3 mode control bit
T3C2
T3C1
T3C0
T3PNDA
T3ENA
T3PNDB
T3ENB
Timer T3 mode control bit
Timer T3 mode control bit
Timer T3 Start/Stop control in timer
modes 1 and 2, T3 Underflow Interrupt Pending Flag in timer mode 3
Timer T3 Interrupt Pending Flag (Autoreload
RA in mode 1, T3 Underflow in mode 2, T3A
capture edge in mode 3)
Timer T3 Interrupt Enable for Timer Underflow
or T3A Input capture edge
Timer T3 Interrupt Pending Flag for T3B capture edge
Timer T3 Interrupt Enable for Timer Underflow
or T3B Input capture edge
TABLE 3. Idle Timer Window Length
ITSEL2
ITSEL1
ITSEL0
Idle Timer Period
(Instruction Cycles)
0
0
0
0
0
1
4,096
8,192
0
1
0
16,384
Timers
0
1
1
32,768
The device contains a very versatile set of timers (T0, T1,
T2, T3). All timers and associated autoreload/capture registers power up containing random data.
1
X
X
65,536
The ITMR is cleared on Reset and the Idle Timer period is reset to 4,096 instruction cycles.
TIMER T0 (IDLE TIMER)
The device supports applications that require maintaining
real time and low power with the IDLE mode. This IDLE
mode support is furnished by the IDLE timer T0, which is a
16-bit timer. The Timer T0 runs continuously at the fixed rate
of the instruction cycle clock, tc. The user cannot read or
write to the IDLE Timer T0, which is a count down timer.
The Timer T0 supports the following functions:
ITMR Register (Address X’0xCF)
Reserved
Bit 7
ITSEL2
ITSEL1
ITSEL0
Bit 0
Any time the IDLE Timer period is changed there is the possibility of generating a spurious IDLE Timer interrupt by setting the T0PND bit. The user is advised to disable IDLE
Timer interrupts prior to changing the value of the ITSEL bits
of the ITMR Register and then clear the T0PND bit before attempting to synchronize operation to the IDLE Timer.
j Exit out of the Idle Mode (See Idle Mode description)
j WATCHDOG logic (See WATCHDOG description)
j Start up delay out of the HALT mode
Figure 8 is a functional block diagram showing the structure
of the IDLE Timer and its associated interrupt logic.
15
www.national.com
Timers
(Continued)
DS100076-17
FIGURE 8. Functional Block Diagram for Idle Timer T0
the register RxA. Subsequent underflows cause the timer to
be reloaded from the registers alternately beginning with the
register RxB.
The Tx Timer control bits, TxC3, TxC2 and TxC1 set up the
timer for PWM mode operation.
TIMER T1, TIMER T2 AND TIMER T3
The device has a set of three powerful timer/counter blocks,
T1, T2 and T3. The associated features and functioning of a
timer block are described by referring to the timer block Tx.
Since the three timer blocks, T1, T2 and T3 are identical, all
comments are equally applicable to any of the three timer
blocks.
Each timer block consists of a 16-bit timer, Tx, and two supporting 16-bit autoreload/capture registers, RxA and RxB.
Each timer block has two pins associated with it, TxA and
TxB. The pin TxA supports I/O required by the timer block,
while the pin TxB is an input to the timer block. The powerful
and flexible timer block allows the device to easily perform all
timer functions with minimal software overhead. The timer
block has three operating modes: Processor Independent
PWM mode, External Event Counter mode, and Input Capture mode.
Figure 9 shows a block diagram of the timer in PWM mode.
The underflows can be programmed to toggle the TxA output
pin. The underflows can also be programmed to generate interrupts.
Underflows from the timer are alternately latched into two
pending flags, TxPNDA and TxPNDB. The user must reset
these pending flags under software control. Two control enable flags, TxENA and TxENB, allow the interrupts from the
timer underflow to be enabled or disabled. Setting the timer
enable flag TxENA will cause an interrupt when a timer underflow causes the RxA register to be reloaded into the timer.
Setting the timer enable flag TxENB will cause an interrupt
when a timer underflow causes the RxB register to be reloaded into the timer. Resetting the timer enable flags will
disable the associated interrupts.
Either or both of the timer underflow interrupts may be enabled. This gives the user the flexibility of interrupting once
per PWM period on either the rising or falling edge of the
PWM output. Alternatively, the user may choose to interrupt
on both edges of the PWM output.
The control bits TxC3, TxC2, and TxC1 allow selection of the
different modes of operation.
Mode 1. Processor Independent PWM Mode
As the name suggests, this mode allows the device to generate a PWM signal with very minimal user intervention. The
user only has to define the parameters of the PWM signal
(ON time and OFF time). Once begun, the timer block will
continuously generate the PWM signal completely independent of the microcontroller. The user software services the
timer block only when the PWM parameters require updating.
In this mode the timer Tx counts down at a fixed rate of tc.
Upon every underflow the timer is alternately reloaded with
the contents of supporting registers, RxA and RxB. The very
first underflow of the timer causes the timer to reload from
www.national.com
16
Timers
TxC3, TxC2 and TxC1, allow the trigger events to be specified either as a positive or a negative edge. The trigger condition for each input pin can be specified independently.
(Continued)
The trigger conditions can also be programmed to generate
interrupts. The occurrence of the specified trigger condition
on the TxA and TxB pins will be respectively latched into the
pending flags, TxPNDA and TxPNDB. The control flag TxENA allows the interrupt on TxA to be either enabled or disabled. Setting the TxENA flag enables interrupts to be generated when the selected trigger condition occurs on the TxA
pin. Similarly, the flag TxENB controls the interrupts from the
TxB pin.
Underflows from the timer can also be programmed to generate interrupts. Underflows are latched into the timer TxC0
pending flag (the TxC0 control bit serves as the timer underflow interrupt pending flag in the Input Capture mode). Consequently, the TxC0 control bit should be reset when entering the Input Capture mode. The timer underflow interrupt is
enabled with the TxENA control flag. When a TxA interrupt
occurs in the Input Capture mode, the user must check both
the TxPNDA and TxC0 pending flags in order to determine
whether a TxA input capture or a timer underflow (or both)
caused the interrupt.
DS100076-10
FIGURE 9. Timer in PWM Mode
Mode 2. External Event Counter Mode
This mode is quite similar to the processor independent
PWM mode described above. The main difference is that the
timer, Tx, is clocked by the input signal from the TxA pin. The
Tx timer control bits, TxC3, TxC2 and TxC1 allow the timer to
be clocked either on a positive or negative edge from the
TxA pin. Underflows from the timer are latched into the TxPNDA pending flag. Setting the TxENA control flag will cause
an interrupt when the timer underflows.
In this mode the input pin TxB can be used as an independent positive edge sensitive interrupt input if the TxENB control flag is set. The occurrence of a positive edge on the TxB
input pin is latched into the TxPNDB flag.
Figure 11 shows a block diagram of the timer in Input Capture mode.
Figure 10 shows a block diagram of the timer in External
Event Counter mode.
Note: The PWM output is not available in this mode since the TxA pin is being
used as the counter input clock.
DS100076-12
FIGURE 11. Timer in Input Capture Mode
TIMER CONTROL FLAGS
The control bits and their functions are summarized below.
TxC3
Timer mode control
TxC2
TxC1
TxC0
DS100076-11
FIGURE 10. Timer in External Event Counter Mode
Timer mode control
Timer mode control
Timer Start/Stop control in Modes 1 and 2 (Processor Independent PWM and External Event
Counter), where 1 = Start, 0 = Stop
Timer
Mode
TxPNDA Timer
TxENA
Timer
Mode 3. Input Capture Mode
The device can precisely measure external frequencies or
time external events by placing the timer block, Tx, in the input capture mode.
In this mode, the timer Tx is constantly running at the fixed tc
rate. The two registers, RxA and RxB, act as capture registers. Each register acts in conjunction with a pin. The register
RxA acts in conjunction with the TxA pin and the register RxB
acts in conjunction with the TxB pin.
The timer value gets copied over into the register when a
trigger event occurs on its corresponding pin. Control bits,
Underflow Interrupt Pending Flag in
3 (Input Capture)
Interrupt Pending Flag
Interrupt Enable Flag
1 = Timer Interrupt Enabled
0 = Timer Interrupt Disabled
TxPNDB Timer Interrupt Pending Flag
TxENB
Timer Interrupt Enable Flag
1 = Timer Interrupt Enabled
0 = Timer Interrupt Disabled
17
www.national.com
Timers
(Continued)
The timer mode control bits (TxC3, TxC2 and TxC1) are detailed below:
1
0
1
PWM: TxA Toggle
Autoreload RA
Autoreload RB
1
0
0
PWM: No TxA
Toggle
Autoreload RA
Autoreload RB
0
0
0
External Event
Counter
Timer
Underflow
Pos. TxB Edge
Pos. TxA
Edge
0
0
1
External Event
Counter
Timer
Underflow
Pos. TxB Edge
Pos. TxA
Edge
0
1
0
Captures:
Pos. TxA Edge
Pos. TxB Edge
tC
TxA Pos. Edge
or Timer
tC
3
0
1
1
1
1
0
1
1
Description
Timer
Counts On
1
1
TxC1
Interrupt B
Source
TxC3
2
TxC2
Interrupt A
Source
Mode
TxB Pos. Edge
Underflow
Captures:
Pos. TxA
Neg. TxB
TxA Pos. Edge
Edge or Timer
Edge
TxB Neg. Edge
Underflow
Captures:
Neg. TxA
Neg. TxB
TxA Neg. Edge
Edge or Timer
Edge
TxB Neg. Edge
Underflow
Captures:
Neg. TxA
Neg. TxB
TxA Neg. Edge
Edge or Timer
Edge
TxB Neg. Edge
Underflow
tC
tC
tC
resonators have a delayed start up time to reach full amplitude and frequency stability. The IDLE timer is used to generate a fixed delay to ensure that the oscillator has indeed
stabilized before allowing instruction execution. In this case,
upon detecting a valid Wakeup signal, only the oscillator circuitry is enabled. The IDLE timer is loaded with a value of
256 and is clocked with the tc instruction cycle clock. The tc
clock is derived by dividing the oscillator clock down by a factor of 10. The Schmitt trigger following the CKI inverter on
the chip ensures that the IDLE timer is clocked only when the
oscillator has a sufficiently large amplitude to meet the
Schmitt trigger specifications. This Schmitt trigger is not part
of the oscillator closed loop. The startup timeout from the
IDLE timer enables the clock signals to be routed to the rest
of the chip.
If an RC clock option is being used, the fixed delay is introduced optionally. A control bit, CLKDLY, mapped as configuration bit G7, controls whether the delay is to be introduced
or not. The delay is included if CLKDLY is set, and excluded
if CLKDLY is reset. The CLKDLY bit is cleared on reset.
The device has two mask options associated with the HALT
mode. The first mask option enables the HALT mode feature,
while the second mask option disables the HALT mode. With
the HALT mode enable mask option, the device will enter
and exit the HALT mode as described above. With the HALT
disable mask option, the device cannot be placed in the
HALT mode (writing a “1” to the HALT flag will have no effect,
the HALT flag will remain “0”).
The WATCHDOG detector circuit is inhibited during the
HALT mode. However, the clock monitor circuit if enabled remains active during HALT mode in order to ensure a clock
monitor error if the device inadvertently enters the HALT
mode as a result of a runaway program or power glitch.
Power Save Modes
The device offers the user two power save modes of operation: HALT and IDLE. In the HALT mode, all microcontroller
activities are stopped. In the IDLE mode, the on-board oscillator circuitry the WATCHDOG logic, the Clock Monitor and
timer T0 are active but all other microcontroller activities are
stopped. In either mode, all on-board RAM, registers, I/O
states, and timers (with the exception of T0) are unaltered.
HALT MODE
The device can be placed in the HALT mode by writing a “1”
to the HALT flag (G7 data bit). All microcontroller activities,
including the clock and timers, are stopped. The WATCHDOG logic is disabled during the HALT mode. However, the
clock monitor circuitry if enabled remains active and will
cause the WATCHDOG output pin (WDOUT) to go low. If the
HALT mode is used and the user does not want to activate
the WDOUT pin, the Clock Monitor should be disabled after
the device comes out of reset (resetting the Clock Monitor
control bit with the first write to the WDSVR register). In the
HALT mode, the power requirements of the device are minimal and the applied voltage (VCC) may be decreased to Vr
(Vr = 2.0V) without altering the state of the machine.
The device supports three different ways of exiting the HALT
mode. The first method of exiting the HALT mode is with the
Multi-Input Wakeup feature on the L port. The second
method is with a low to high transition on the CKO (G7) pin.
This method precludes the use of the crystal clock configuration (since CKO becomes a dedicated output), and so may
be used with an RC clock configuration. The third method of
exiting the HALT mode is by pulling the RESET pin low.
Since a crystal or ceramic resonator may be selected as the
oscillator, the Wakeup signal is not allowed to start the chip
running immediately since crystal oscillators and ceramic
www.national.com
tC
18
Power Save Modes
Alternatively, the user can enter the IDLE mode with the
IDLE Timer T0 interrupt disabled. In this case, the device will
resume normal operation with the instruction immediately
following the “Enter IDLE Mode” instruction.
(Continued)
IDLE MODE
The device is placed in the IDLE mode by writing a “1” to the
IDLE flag (G6 data bit). In this mode, all activities, except the
associated on-board oscillator circuitry, the WATCHDOG
logic, the clock monitor and the IDLE Timer T0, are stopped.
The power supply requirements of the microcontroller in this
mode of operation are typically around 30% of normal power
requirement of the microcontroller.
As with the HALT mode, the device can be returned to normal operation with a reset, or with a Multi-Input Wakeup from
the L Port.
The microcontroller may also be awakened from the IDLE
mode after a selectable amount of time up to 65,536 instruction cycles, or 65.536 milliseconds with a 1 MHz instruction
clock frequency.
The IDLE timer period is selectable from one of five values,
4k, 8k, 16k, 32k or 64k instruction cycles. Selection of this
value is made through the ITMR register.
The user has the option of being interrupted with a transition
on the thirteenth bit of the IDLE Timer T0. The interrupt can
be enabled or disabled via the T0EN control bit. Setting the
T0EN flag enables the interrupt and vice versa.
The user can enter the IDLE mode with the Timer T0 interrupt enabled. In this case, when the T0PND bit gets set, the
device will first execute the Timer T0 interrupt service routine
and then return to the instruction following the “Enter Idle
Mode” instruction.
The IDLE timer cannot be started or stopped under software
control, and it is not memory mapped, so it cannot be read or
written by the software. Its state upon Reset is unknown.
Therefore, if the device is put into the IDLE mode at an arbitrary time, it will stay in the IDLE mode for somewhere between 1 and the selected number of instruction cycles.
Upon reset the ITMR register is cleared and selects the
4,096 instruction cycle tap of the Idle Timer.
Note: It is necessary to program two NOP instructions following both the set
HALT mode and set IDLE mode instructions. These NOP instructions
are necessary to allow clock resynchronization following the HALT or
IDLE modes.
For more information on the IDLE Timer and its associated
interrupt, see the description in the Timers Section.
Multi-Input Wakeup
The Multi-Input Wakeup feature is ued to return (wakeup) the
device from either the HALT or IDLE modes. Alternately
Multi-Input Wakeup/Interrupt feature may also be used to
generate up to 8 edge selectable external interrupts.
Figure 12 shows the Multi-Input Wakeup logic.
DS100076-13
FIGURE 12. Multi-Input Wake Up Logic
The user can select whether the trigger condition on the selected L Port pin is going to be either a positive edge (low to
high transition) or a negative edge (high to low transition).
This selection is made via the Reg: WKEDG, which is an
8-bit control register with a bit assigned to each L Port pin.
Setting the control bit will select the trigger condition to be a
negative edge on that particular L Port pin. Resetting the bit
The Multi-Input Wakeup feature utilizes the L Port. The user
selects which particular L port bit (or combination of L Port
bits) will cause the device to exit the HALT or IDLE modes.
The selection is done through the Reg: WKEN. The Reg:
WKEN is an 8-bit read/write register, which contains a control bit for every L port bit. Setting a particular WKEN bit enables a Wakeup from the associated L port pin.
19
www.national.com
Multi-Input Wakeup
modes. In the other case, the device will first execute the interrupt service routine and then revert to normal operation.
(See HALT MODE for clock option wakeup information.)
(Continued)
selects the trigger condition to be a positive edge. Changing
an edge select entails several steps in order to avoid a
pseudo Wakeup condition as a result of the edge change.
First, the associated WKEN bit should be reset, followed by
the edge select change in WKEDG. Next, the associated
WKPND bit should be cleared, followed by the associated
WKEN bit being re-enabled.
An example may serve to clarify this procedure. Suppose we
wish to change the edge select from positive (low going high)
to negative (high going low) for L Port bit 5, where bit 5 has
previously been enabled for an input interrupt. The program
would be as follows:
RBIT 5, WKEN
; Disable MIWU
SBIT 5, WKEDG ; Change edge polarity
RBIT 5, WKPND ; Reset pending flag
SBIT 5, WKEN
; Enable MIWU
A/D Converter
The device contains an 8-channel, multiplexed input, successive approximation, Analog-to Digital converter. The device’s VCC and GND pins are used for voltage reference.
OPERATING MODES
The A/D converter supports ratiometric measurements. It
supports both Single Ended and Differential modes of operation.
Four specific analog channel selection modes are supported. These are as follows:
Allow any specific channel to be selected at one time. The
A/D converter performs the specific conversion requested
and stops.
Allow any specific channel to be scanned continuously. In
other words, the user specifies the channel and the A/D converter scans it continuously. At any arbitrary time the user
can immediately read the result of the last conversion. The
user must wait for only the first conversion to complete.
Allow any differential channel pair to be selected at one time.
The A/D converter performs the specific differential conversion requested and stops.
If the L port bits have been used as outputs and then
changed to inputs with Multi-Input Wakeup/Interrupt, a safety
procedure should also be followed to avoid inherited pseudo
wakeup conditions. After the selected L port bits have been
changed from output to input but before the associated
WKEN bits are enabled, the associated edge select bits in
WKEDG should be set or reset for the desired edge selects,
followed by the associated WKPND bits being cleared.
This same procedure should be used following reset, since
the L port inputs are left floating as a result of reset.
The occurrence of the selected trigger condition for
Multi-Input Wakeup is latched into a pending register called
WKPND. The respective bits of the WKPND register will be
set on the occurrence of the selected trigger edge on the corresponding Port L pin. The user has the responsibility of
clearing these pending flags. Since WKPND is a pending
register for the occurrence of selected wakeup conditions,
the device will not enter the HALT mode if any Wakeup bit is
both enabled and pending. Consequently, the user has the
responsibility of clearing the pending flags before attempting
to enter the HALT mode.
WKEN, WKPND and WKEDG are all read/write registers,
and are cleared at reset.
Allow any differential channel pair to be scanned continuously. In other words, the user specifies the differential channel pair and the A/D converter scans it continuously. At any
arbitrary time the user can immediately read the result of the
last differential conversion. The user must wait for only the
first conversion to complete.
The A/D converter is supported by two memory mapped registers, the result register and the mode control register.
When the device is reset, the mode control register (ENAD)
is cleared, the A/D is powered down and the A/D result register has unknown data.
A/D Control Register
The ENAD control register contains 3 bits for channel selection, 2 bits for prescaler selection, 2 bits for mode selection
and a Busy bit. An A/D conversion is initiated by setting the
ADBSY bit in the ENAD control register. The result of the
conversion is available to the user in the A/D result register,
ADRSLT, when ADBSY is cleared by the hardware on
completion of the conversion.
ENAD (Address 0xCB)
PORT L INTERRUPTS
Port L provides the user with an additional eight fully selectable, edge sensitive interrupts which are all vectored into the
same service subroutine.
The interrupt from Port L shares logic with the wake up circuitry. The register WKEN allows interrupts from Port L to be
individually enabled or disabled. The register WKEDG specifies the trigger condition to be either a positive or a negative
edge. Finally, the register WKPND latches in the pending
trigger conditions.
The GIE (Global Interrupt Enable) bit enables the interrupt
function.
A control flag, LPEN, functions as a global interrupt enable
for Port L interrupts. Setting the LPEN flag will enable interrupts and vice versa. A separate global pending flag is not
needed since the register WKPND is adequate.
ADCH2
Bit 7
Since Port L is also used for waking the device out of the
HALT or IDLE modes, the user can elect to exit the HALT or
IDLE modes either with or without the interrupt enabled. If he
elects to disable the interrupt, then the device will restart execution from the instruction immediately following the instruction that placed the microcontroller in the HALT or IDLE
www.national.com
20
CHANNEL
MODE
PRESCALER
SELECT
SELECT
SELECT
ADCH1
ADCH0 ADMOD1 ADMOD0
PSC1
PSC0
BUSY
ADBSY
Bit 0
A/D Converter
BUSY BIT
The ADBSY bit of the ENAD register is used to control starting and stopping of the A/D conversion. When ADBSY is
cleared, the prescale logic is disabled and the A/D clock is
turned off. Setting the ADBSY bit starts the A/D clock and initiates a conversion based on the mode select value currently
in the ENAD register. Normal completion of an A/D conversion clears the ADBSY bit and turns off the A/D converter.
The ADBSY bit remains a one during continuous conversion.
The user can stop continuous conversion by writing a zero to
the ADBSY bit.
If the user wishes to restart a conversion which is already in
progress, this can be accomplished only by writing a zero to
the ADBSY bit to stop the current conversion and then by
writing a one to ADBSY to start a new conversion. This can
be done in two consecutive instructions.
(Continued)
CHANNEL SELECT
This 3-bit field selects one of eight channels to be the VIN+.
The mode selection determines the VIN− input.
Single Ended mode:
Bit 7
Bit 6
Bit 5
Channel No.
0
0
0
0
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
7
ADC Operation
Differential mode:
Bit 7
Bit 6
Bit 5
Channel Pairs (+, −)
0
0
0
0, 1
0
0
1
1, 0
0
1
0
2, 3
0
1
1
3, 2
1
0
0
4, 5
1
0
1
5, 4
1
1
0
6, 7
1
1
1
7, 6
The A/D converter interface works as follows. Setting the
ADBSY bit in the A/D control register ENAD initiates an A/D
conversion. The conversion sequence starts at the beginning of the write to ENAD operation which sets ADBSY, thus
powering up the A/D. At the first falling edge of the converter
clock following the write operation, the sample signal turns
on for seven clock cycles. If the A/D is in single conversion
mode, the conversion complete signal from the A/D will generate a power down for the A/D converter and will clear the
ADBSY bit in the ENAD register at the next instruction cycle
boundary. If the A/D is in continuous mode, the conversion
complete signal will restart the conversion sequence by deselecting the A/D for one converter clock cycle before starting the next sample. The A/D 8-bit result is immediately
loaded into the A/D result register (ADRSLT) upon completion. Internal logic prevents transient data (resulting from the
A/D writing a new result over an old one) being read from
ADRSLT.
Inadvertent changes to the ENAD register during conversion
are prevented by the control logic of the A/D. Any attempt to
write any bit of the ENAD Register except ADBSY, while
ADBSY is a one, is ignored. ADBSY must be cleared either
by completion of an A/D conversion or by the user before the
prescaler, conversion mode or channel select values can be
changed. After stopping the current conversion, the user can
load different values for the prescaler, conversion mode or
channel select and start a new conversion in one instruction.
It is important for the user to realize that, when used in differential mode, only the positive input to the A/D converter is
sampled and held. The negative input is constantly connected and should be held stable for the duration of the conversion. Failure to maintain a stable negative input will result
in incorrect conversion.
MODE SELECT
This 2-bit field is used to select the mode of operation (single
conversion, continuous conversions, differential, single
ended) as shown in the following table.
Bit 4
Bit 3
0
0
Single Ended mode, single
conversion
Mode
0
1
Single Ended mode, continuous scan
of a single channel into the result
register
1
0
Differential mode, single conversion
1
1
Differential mode, continuous scan of
a channel pair into the result register
PRESCALER SELECT
This 2-bit field is used to select one of the four prescaler
clocks for the A/D converter. The following table shows the
various prescaler options.
A/D Converter Clock Prescale
Bit 2
Bit 1
Clock Select
0
0
Divide by 2
0
1
Divide by 4
1
0
Divide by 6
1
1
Divide by 12
PRESCALER
The A/D Converter (A/D) contains a prescaler option that allows four different clock selections. The A/D clock frequency
is equal to CKI divided by the prescaler value. Note that the
prescaler value must be chosen such that the A/D clock falls
within the specified range. The maximum A/D frequency is
1.67 MHz. This equates to a 600 ns A/D clock cycle.
21
www.national.com
A/D Converter
cause conversion errors. The clock lead should be kept
away from the analog input line to reduce coupling. The A/D
channel input pins do not have any internal output driver circuitry connected to them because this circuitry would load
the analog input signals due to output buffer leakage current.
Source impedances greater than 3 kΩ on the analog input
lines will adversely affect the internal RC charging time during input sampling. As shown in Figure 13, the analog switch
to the DAC array is closed only during the 7 A/D cycle
sample time. Large source impedances on the analog inputs
may result in the DAC array not being charged to the correct
voltage levels, causing scale errors.
If large source resistance is necessary, the recommended
solution is to slow down the A/D clock speed in proportion to
the source resistance. The A/D converter may be operated
at the maximum speed for RS less than 3 kΩ. For RS greater
than 3 kΩ, A/D clock speed needs to be reduced. For example, with RS = 6 kΩ, the A/D converter may be operated
at half the maximum speed. A/D converter clock speed may
be slowed down by either increasing the A/D prescaler
divide-by or decreasing the CKI clock frquency. The A/D
minimum clock speed is 100 kHz.
(Continued)
The A/D converter takes 17 A/D clock cycles to complete a
conversion. Thus the minimum A/D conversion time for the
device is 10.2 µs when a prescaler of 6 has been selected.
The 17 A/D clock cycles needed for conversion consist of 1
cycle at the beginning for reset, 7 cycles for sampling, 8
cycles for converting, and 1 cycle for loading the result into
the A/D result register (ADRSLT). This A/D result register is a
read-only register. The user cannot write into ADRSLT.
The ADBSY flag provides an A/D clock inhibit function, which
saves power by powering down the A/D when it is not in use.
Note: The A/D converter is also powered down when the device is in either
the HALT or IDLE modes. If the A/D is running when the device enters
the HALT or IDLE modes, the A/D powers down and then restarts the
conversion with a corrupted sampled voltage (and thus an invalid result) when the device comes out of the HALT or IDLE modes.
Analog Input and Source Resistance Considerations
Figure 13 shows the A/D pin model in single ended mode.
The differential mode has a similar A/D pin model. The leads
to the analog inputs should be kept as short as possible.
Both noise and digital clock coupling to an A/D input can
DS100076-18
*The analog switch is closed only during the sample time.
FIGURE 13. A/D Pin Model (Single Ended Mode)
The Software trap has the highest priority while the default
VIS has the lowest priority.
Each of the 11 maskable inputs has a fixed arbitration ranking and vector.
Interrupts
INTRODUCTION
Each device supports eleven vectored interrupts. Interrupt
sources include Timer 0, Timer 1, Timer 2, Timer 3, Port L
Wakeup, Software Trap, MICROWIRE/PLUS, and External
Input.
All interrupts force a branch to location 00FF Hex in program
memory. The VIS instruction may be used to vector to the
appropriate service routine from location 00FF Hex.
www.national.com
Figure 14 shows the Interrupt Block Diagram.
22
Interrupts
(Continued)
DS100076-14
FIGURE 14. Interrupt Block Diagram
edged until the start of the next normally executed instruction
is to be skipped, the skip is performed before the pending interrupt is acknowledged.
At the start of interrupt acknowledgment, the following actions occur:
1. The GIE bit is automatically reset to zero, preventing any
subsequent maskable interrupt from interrupting the current service routine. This feature prevents one maskable
interrupt from interrupting another one being serviced.
2. The address of the instruction about to be executed is
pushed onto the stack.
3. The program counter (PC) is loaded with 00FF Hex,
causing a jump to that program memory location.
The device requires seven instruction cycles to perform the
actions listed above.
If the user wishes to allow nested interrupts, the interrupts
service routine may set the GIE bit to 1 by writing to the PSW
register, and thus allow other maskable interrupts to interrupt
the current service routine. If nested interrupts are allowed,
caution must be exercised. The user must write the program
in such a way as to prevent stack overflow, loss of saved
context information, and other unwanted conditions.
The interrupt service routine stored at location 00FF Hex
should use the VIS instruction to determine the cause of the
interrupt, and jump to the interrupt handling routine corresponding to the highest priority enabled and active interrupt.
Alternately, the user may choose to poll all interrupt pending
and enable bits to determine the source(s) of the interrupt. If
more than one interrupt is active, the user’s program must
decide which interrupt to service.
Within a specific interrupt service routine, the associated
pending bit should be cleared. This is typically done as early
as possible in the service routine in order to avoid missing
the next occurrence of the same type of interrupt event.
Thus, if the same event occurs a second time, even while the
first occurrence is still being serviced, the second occurrence will be serviced immediately upon return from the current interrupt routine.
MASKABLE INTERRUPTS
All interrupts other than the Software Trap are maskable.
Each maskable interrupt has an associated enable bit and
pending flag bit. The pending bit is set to 1 when the interrupt
condition occurs. The state of the interrupt enable bit, combined with the GIE bit determines whether an active pending
flag actually triggers an interrupt. All of the maskable interrupt pending and enable bits are contained in mapped control registers, and thus can be controlled by the software.
A maskable interrupt condition triggers an interrupt under the
following conditions:
1. The enable bit associated with that interrupt is set.
2. The GIE bit is set.
3. The device is not processing a non-maskable interrupt.
(If a non-maskable interrupt is being serviced, a
maskable interrupt must wait until that service routine is
completed.)
An interrupt is triggered only when all of these conditions are
met at the beginning of an instruction. If different maskable
interrupts meet these conditions simultaneously, the highest
priority interrupt will be serviced first, and the other pending
interrupts must wait.
Upon Reset, all pending bits, individual enable bits, and the
GIE bit are reset to zero. Thus, a maskable interrupt condition cannot trigger an interrupt until the program enables it by
setting both the GIE bit and the individual enable bit. When
enabling an interrupt, the user should consider whether or
not a previously activated (set) pending bit should be acknowledged. If, at the time an interrupt is enabled, any previous occurrences of the interrupt should be ignored, the associated pending bit must be reset to zero prior to enabling
the interrupt. Otherwise, the interrupt may be simply enabled; if the pending bit is already set, it will immediately trigger an interrupt. A maskable interrupt is active if its associated enable and pending bits are set.
An interrupt is an asychronous event which may occur before, during, or after an instruction cycle. Any interrupt which
occurs during the execution of an instruction is not acknowl-
23
www.national.com
Interrupts
The vector table should be filled by the user with the memory
locations of the specific interrupt service routines. For example, if the Software Trap routine is located at 0310 Hex,
then the vector location 0yFE and -0yFF should contain the
data 03 and 10 Hex, respectively. When a Software Trap interrupt occurs and the VIS instruction is executed, the program jumps to the address specified in the vector table.
(Continued)
An interrupt service routine typically ends with an RETI instruction. This instruction sets the GIE bit back to 1, pops the
address stored on the stack, and restores that address to the
program counter. Program execution then proceeds with the
next instruction that would have been executed had there
been no interrupt. If there are any valid interrupts pending,
the highest-priority interrupt is serviced immediately upon return from the previous interrupt.
The interrupt sources in the vector table are listed in order of
rank, from highest to lowest priority. If two or more enabled
and pending interrupts are detected at the same time, the
one with the highest priority is serviced first. Upon return
from the interrupt service routine, the next highest-level
pending interrupt is serviced.
If the VIS instruction is executed, but no interrupts are enabled and pending, the lowest-priority interrupt vector is
used, and a jump is made to the corresponding address in
the vector table. This is an unusual occurrence, and may be
the result of an error. It can legitimately result from a change
in the enable bits or pending flags prior to the execution of
the VIS instruction, such as executing a single cycle instruction which clears an enable flag at the same time that the
pending flag is set. It can also result, however, from inadvertent execution of the VIS command outside of the context of
an interrupt.
The default VIS interrupt vector can be useful for applications in which time critical interrupts can occur during the
servicing of another interrupt. Rather than restoring the program context (A, B, X, etc.) and executing the RETI instruction, an interrupt service routine can be terminated by returning to the VIS instruction. In this case, interrupts will be
serviced in turn until no further interrupts are pending and
the default VIS routine is started. After testing the GIE bit to
ensure that execution is not erroneous, the routine should
restore the program context and execute the RETI to return
to the interrupted program.
This technique can save up to fifty instruction cycles (tc), or
more, (50µs at 10 MHz oscillator) of latency for pending interrupts with a penalty of fewer than ten instruction cycles if
no further interrupts are pending.
To ensure reliable operation, the user should always use the
VIS instruction to determine the source of an interrupt. Although it is possible to poll the pending bits to detect the
source of an interrupt, this practice is not recommended. The
use of polling allows the standard arbitration ranking to be altered, but the reliability of the interrupt system is compromised. The polling routine must individually test the enable
and pending bits of each maskable interrupt. If a Software
Trap interrupt should occur, it will be serviced last, even
though it should have the highest priority. Under certain conditions, a Software Trap could be triggered but not serviced,
resulting in an inadvertent “locking out” of all maskable interrupts by the Software Trap pending flag. Problems such as
this can be avoided by using VIS instruction.
VIS INSTRUCTION
The general interrupt service routine, which starts at address
00FF Hex, must be capable of handling all types of interrupts. The VIS instruction, together with an interrupt vector
table, directs the device to the specific interrupt handling routine based on the cause of the interrupt.
VIS is a single-byte instruction, typically used at the very beginning of the general interrupt service routine at address
00FF Hex, or shortly after that point, just after the code used
for context switching. The VIS instruction determines which
enabled and pending interrupt has the highest priority, and
causes an indirect jump to the address corresponding to that
interrupt source. The jump addresses (vectors) for all possible interrupts sources are stored in a vector table.
The vector table may be as long as 32 bytes (maximum of 16
vectors) and resides at the top of the 256-byte block containing the VIS instruction. However, if the VIS instruction is at
the very top of a 256-byte block (such as at 00FF Hex), the
vector table resides at the top of the next 256-byte block.
Thus, if the VIS instruction is located somewhere between
00FF and 01DF Hex (the usual case), the vector table is located between addresses 01E0 and 01FF Hex. If the VIS instruction is located between 01FF and 02DF Hex, then the
vector table is located between addresses 02E0 and 02FF
Hex, and so on.
Each vector is 15 bits long and points to the beginning of a
specific interrupt service routine somewhere in the 32 kbyte
memory space. Each vector occupies two bytes of the vector
table, with the higher-order byte at the lower address. The
vectors are arranged in order of interrupt priority. The vector
of the maskable interrupt with the lowest rank is located to
0yE0 (higher-order byte) and 0yE1 (lower-order byte). The
next priority interrupt is located at 0yE2 and 0yE3, and so
forth in increasing rank. The Software Trap has the highest
rank and its vector is always located at 0yFE and 0yFF. The
number of interrupts which can become active defines the
size of the table.
Table 4 shows the types of interrupts, the interrupt arbitration
ranking, and the locations of the corresponding vectors in
the vector table.
www.national.com
24
Interrupts
(Continued)
TABLE 4. Interupt Vector Table
Arbitration
Ranking
Vector (Note 32)
Source
Description
Address
Hi-Low Byte
(1) Highest
Software
(2)
Reserved
INTR Instruction
0yFE–0yFF
(3)
External
Pin G0 Edge
(4)
Timer T0
Underflow
0yF8–0yF9
(5)
Timer T1
T1A/Underflow
0yF6–0yF7
(6)
Timer T1
T1B
0yF4–0yF5
(7)
MICROWIRE/PLUS
BUSY Low
0yF2–0yF3
(8)
Reserved
0yF0–0yF1
(9)
Reserved
0yEE–0yEF
(10)
Reserved
(11)
Timer T2
T2A/Underflow
(12)
Timer T2
T2B
0yE8–0yE9
(13)
Timer T3
T3A/Underflow
0yE6–0yE7
(14)
Timer T3
T3B
0yE4–0yE5
(15)
Port L/Wakeup
Port L Edge
0yE2–0yE3
(16) Lowest
Default
VIS Instr. Execution
0yE0–0yE1
0yFC–0yFD
0yFA–0yFB
0yEC–0yED
0yEA–0yEB
without Any Interrupts
Note 32: y is a variable which represents the VIS block. VIS and the vector table must be located in the same 256-byte block except if VIS is located at the last address of a block. In this case, the table must be in the next block.
vector of the active interrupt with the highest arbitration ranking. This vector is read from program memory and placed
into the PC which is now pointed to the 1st instruction of the
service routine of the active interrupt with the highest arbitration ranking.
VIS Execution
When the VIS instruction is executed it activates the arbitration logic. The arbitration logic generates an even number
between E0 and FE (E0, E2, E4, E6 etc...) depending on
which active interrupt has the highest arbitration ranking at
the time of the 1st cycle of VIS is executed. For example, if
the software trap interrupt is active, FE is generated. If the
external interrupt is active and the software trap interrupt is
not, then FA is generated and so forth. If the only active interrupt is software trap, than E0 is generated. This number replaces the lower byte of the PC. The upper byte of the PC remains unchanged. The new PC is therefore pointing to the
Figure 15 illustrates the different steps performed by the VIS
instruction. Figure 16 shows a flowchart for the VIS instruction.
The non-maskable interrupt pending flag is cleared by the
RPND (Reset Non-Maskable Pending Bit) instruction (under
certain conditions) and upon RESET.
25
www.national.com
Interrupts
(Continued)
DS100076-29
FIGURE 15. VIS Operation
DS100076-30
FIGURE 16. VIS Flowchart
www.national.com
26
Interrupts
(Continued)
Programming Example: External Interrupt
WAIT:
PSW
CNTRL
RBIT
RBIT
SBIT
SBIT
SBIT
JP
.
.
.
.=0FF
VIS
=00EF
=00EE
0,PORTGC
0,PORTGD
IEDG, CNTRL
EXEN, PSW
GIE, PSW
WAIT
;
;
;
;
;
G0 pin configured Hi-Z
Ext interrupt polarity; falling edge
Enable the external interrupt
Set the GIE bit
Wait for external interrupt
; The interrupt causes a
; branch to address 0FF
; The VIS causes a branch to
;interrupt vector table
.
.
.
.=01FA
.ADDRW SERVICE
; Vector table (within 256 byte
; of VIS inst.) containing the ext
; interrupt service routine
.
.
INT_EXIT:
SERVICE:
RETI
.
.
RBIT
.
.
.
JP
EXPND, PSW
INT_EXIT
; Interrupt Service Routine
; Reset ext interrupt pend. bit
; Return, set the GIE bit
27
www.national.com
Interrupts
flag; upon return to the first Software Trap routine, the
STPND flag will have the wrong state. This will allow
maskable interrupts to be acknowledged during the servicing
of the first Software Trap. To avoid problems such as this, the
user program should contain the Software Trap routine to
perform a recovery procedure rather than a return to normal
execution.
Under normal conditions, the STPND flag is reset by a
RPND instruction in the Software Trap service routine. If a
programming error or hardware condition (brownout, power
supply glitch, etc.) sets the STPND flag without providing a
way for it to be cleared, all other interrupts will be locked out.
To alleviate this condition, the user can use extra RPND instructions in the main program and in the WATCHDOG service routine (if present). There is no harm in executing extra
RPND instructions in these parts of the program.
(Continued)
NON-MASKABLE INTERRUPT
Pending Flag
There is a pending flag bit associated with the non-maskable
interrupt, called STPND. This pending flag is not memorymapped and cannot be accessed directly by the software.
The pending flag is reset to zero when a device Reset occurs. When the non-maskable interrupt occurs, the associated pending bit is set to 1. The interrupt service routine
should contain an RPND instruction to reset the pending flag
to zero. The RPND instruction always resets the STPND
flag.
Software Trap
The Software Trap is a special kind of non-maskable interrupt which occurs when the INTR instruction (used to acknowledge interrupts) is fetched from program memory and
placed in the instruction register. This can happen in a variety of ways, usually because of an error condition. Some examples of causes are listed below.
If the program counter incorrectly points to a memory location beyond the available program memory space, the nonexistent or unused memory location returns zeroes which is
interpreted as the INTR instruction.
If the stack is popped beyond the allowed limit (address 06F
Hex), a 7FFF will be loaded into the PC, if this last location in
program memory is unprogrammed or unavailable, a Software Trap will be triggered.
A Software Trap can be triggered by a temporary hardware
condition such as a brownout or power supply glitch.
The Software Trap has the highest priority of all interrupts.
When a Software Trap occurs, the STPND bit is set. The GIE
bit is not affected and the pending bit (not accessible by the
user) is used to inhibit other interrupts and to direct the program to the ST service routine with the VIS instruction. Nothing can interrupt a Software Trap service routine except for
another Software Trap. The STPND can be reset only by the
RPND instruction or a chip Reset.
The Software Trap indicates an unusual or unknown error
condition. Generally, returning to normal execution at the
point where the Software Trap occurred cannot be done reliably. Therefore, the Software Trap service routine should
reinitialize the stack pointer and perform a recovery procedure that restarts the software at some known point, similar
to a device Reset, but not necessarily performing all the
same functions as a device Reset. The routine must also execute the RPND instruction to reset the STPND flag. Otherwise, all other interrupts will be locked out. To the extent possible, the interrupt routine should record or indicate the
context of the device so that the cause of the Software Trap
can be determined.
PORT L INTERRUPTS
Port L provides the user with an additional eight fully selectable, edge sensitive interrupts which are all vectored into the
same service subroutine.
The interrupt from Port L shares logic with the wake up circuitry. The register WKEN allows interrupts from Port L to be
individually enabled or disabled. The register WKEDG specifies the trigger condition to be either a positive or a negative
edge. Finally, the register WKPND latches in the pending
trigger conditions.
The GIE (Global Interrupt Enable) bit enables the interrupt
function.
A control flag, LPEN, functions as a global interrupt enable
for Port L interrupts. Setting the LPEN flag will enable interrupts and vice versa. A separate global pending flag is not
needed since the register WKPND is adequate.
Since Port L is also used for waking the device out of the
HALT or IDLE modes, the user can elect to exit the HALT or
IDLE modes either with or without the interrupt enabled. If he
elects to disable the interrupt, then the device will restart execution from the instruction immediately following the instruction that placed the microcontroller in the HALT or IDLE
modes. In the other case, the device will first execute the interrupt service routine and then revert to normal operation.
(See HALT MODE for clock option wakeup information.)
INTERRUPT SUMMARY
The device uses the following types of interrupts, listed below in order of priority:
1. The Software Trap non-maskable interrupt, triggered by
the INTR (00 opcode) instruction. The Software Trap is
acknowledged immediately. This interrupt service routine can be interrupted only by another Software Trap.
The Software Trap should end with two RPND instructions followed by a restart procedure.
2. Maskable interrupts, triggered by an on-chip peripheral
block or an external device connected to the device. Under ordinary conditions, a maskable interrupt will not interrupt any other interrupt routine in progress. A
maskable interrupt routine in progress can be interrupted by the non-maskable interrupt request. A
maskable interrupt routine should end with an RETI instruction or, prior to restoring context, should return to
execute the VIS instruction. This is particularly useful
when exiting long interrupt service routiness if the time
between interrupts is short. In this case the RETI instruction would only be executed when the default VIS routine is reached.
If the user wishes to return to normal execution from the
point at which the Software Trap was triggered, the user
must first execute RPND, followed by RETSK rather than
RETI or RET. This is because the return address stored on
the stack is the address of the INTR instruction that triggered
the interrupt. The program must skip that instruction in order
to proceed with the next one. Otherwise, an infinite loop of
Software Traps and returns will occur.
Programming a return to normal execution requires careful
consideration. If the Software Trap routine is interrupted by
another Software Trap, the RPND instruction in the service
routine for the second Software Trap will reset the STPND
www.national.com
28
occur after coming out of reset, if the instruction cycle clock
frequency has not reached a minimum specified value, including the case where the oscillator fails to start.
The WDSVR register can be written to only once after reset
and the key data (bits 5 through 1 of the WDSVR Register)
must match to be a valid write. This write to the WDSVR register involves two irrevocable choices: (i) the selection of the
WATCHDOG service window (ii) enabling or disabling of the
Clock Monitor. Hence, the first write to WDSVR Register involves selecting or deselecting the Clock Monitor, select the
WATCHDOG service window and match the WATCHDOG
key data. Subsequent writes to the WDSVR register will
compare the value being written by the user to the WATCHDOG service window value and the key data (bits 7 through
1) in the WDSVR Register. Table 5 shows the sequence of
events that can occur.
WATCHDOG
The device contains a WATCHDOG and clock monitor. The
WATCHDOG is designed to detect the user program getting
stuck in infinite loops resulting in loss of program control or
“runaway” programs. The Clock Monitor is used to detect the
absence of a clock or a very slow clock below a specified
rate on the CKI pin.
The WATCHDOG consists of two independent logic blocks:
WD UPPER and WD LOWER. WD UPPER establishes the
upper limit on the service window and WD LOWER defines
the lower limit of the service window.
Servicing the WATCHDOG consists of writing a specific
value to a WATCHDOG Service Register named WDSVR
which is memory mapped in the RAM. This value is composed of three fields, consisting of a 2-bit Window Select, a
5-bit Key Data field, and the 1-bit Clock Monitor Select field.
Table 5 shows the WDSVR register.
The user must service the WATCHDOG at least once before
the upper limit of the service window expires. The WATCHDOG may not be serviced more than once in every lower
limit of the service window. The user may service the
WATCHDOG as many times as wished in the time period between the lower and upper limits of the service window. The
first write to the WDSVR Register is also counted as a
WATCHDOG service.
The WATCHDOG has an output pin associated with it. This
is the WDOUT pin, on pin 1 of the port G. WDOUT is active
low. The WDOUT pin is in the high impedance state in the inactive state. Upon triggering the WATCHDOG, the logic will
pull the WDOUT (G1) pin low for an additional 16 tc–32 tc
cycles after the signal level on WDOUT pin goes below the
lower Schmitt trigger threshold. After this delay, the device
will stop forcing the WDOUT output low.
The WATCHDOG service window will restart when the WDOUT pin goes high. It is recommended that the user tie the
WDOUT pin back to VCC through a resistor in order to pull
WDOUT high.
A WATCHDOG service while the WDOUT signal is active will
be ignored. The state of the WDOUT pin is not guaranteed
on reset, but if it powers up low then the WATCHDOG will
time out and WDOUT will enter high impedance state.
The Clock Monitor forces the G1 pin low upon detecting a
clock frequency error. The Clock Monitor error will continue
until the clock frequency has reached the minimum specified
value, after which the G1 output will enter the high impedance TRI-STATE mode following 16 tc–32 tc clock cycles.
The Clock Monitor generates a continual Clock Monitor error
if the oscillator fails to start, or fails to reach the minimum
specified frequency. The specification for the Clock Monitor
is as follows:
1/tc > 10 kHz — No clock rejection.
TABLE 5. WATCHDOG Service Register (WDSVR)
Window
Key Data
Clock
Select
Monitor
X
X
0
1
1
0
0
Y
7
6
5
4
3
2
1
0
The lower limit of the service window is fixed at 2048 instruction cycles. Bits 7 and 6 of the WDSVR register allow the
user to pick an upper limit of the service window.
Table 6 shows the four possible combinations of lower and
upper limits for the WATCHDOG service window. This flexibility in choosing the WATCHDOG service window prevents
any undue burden on the user software.
Bits 5, 4, 3, 2 and 1 of the WDSVR register represent the
5-bit Key Data field. The key data is fixed at 01100. Bit 0 of
the WDSVR Register is the Clock Monitor Select bit.
TABLE 6. WATCHDOG Service Window Select
WDSVR WDSVR
Bit 7
Bit 6
Clock
Service Window
Monitor
(Lower-Upper Limits)
0
0
x
2048–8k tC Cycles
0
1
x
2048–16k tC Cycles
1
0
x
2048–32k tC Cycles
1
1
x
2048–64k tC Cycles
x
x
0
Clock Monitor Disabled
x
x
1
Clock Monitor Enabled
Clock Monitor
1/tc < 10 Hz — Guaranteed clock rejection.
The Clock Monitor aboard the device can be selected or deselected under program control. The Clock Monitor is guaranteed not to reject the clock if the instruction cycle clock (1/
tc) is greater or equal to 10 kHz. This equates to a clock input
rate on CKI of greater or equal to 100 kHz.
WATCHDOG AND CLOCK MONITOR SUMMARY
The following salient points regarding the WATCHDOG and
CLOCK MONITOR should be noted:
• Both the WATCHDOG and CLOCK MONITOR detector
circuits are inhibited during RESET.
WATCHDOG Operation
The WATCHDOG and Clock Monitor are disabled during reset. The device comes out of reset with the WATCHDOG
armed, the WATCHDOG Window Select bits (bits 6, 7 of the
WDSVR Register) set, and the Clock Monitor bit (bit 0 of the
WDSVR Register) enabled. Thus, a Clock Monitor error will
29
•
Following RESET, the WATCHDOG and CLOCK MONITOR are both enabled, with the WATCHDOG having the
maximum service window selected.
•
The WATCHDOG service window and CLOCK MONITOR enable/disable option can only be changed once,
during the initial WATCHDOG service following RESET.
www.national.com
WATCHDOG Operation
The subroutine stack grows down for each call (jump to subroutine), interrupt, or PUSH, and grows up for each return or
POP. The stack pointer is initialized to RAM location 06F Hex
during reset. Consequently, if there are more returns than
calls, the stack pointer will point to addresses 070 and 071
Hex (which are undefined RAM). Undefined RAM from addresses 070 to 07F (Segment 0), 140 to 17F (Segment 1),
and all other segments (i.e., Segments 2 … etc.) is read as
all 1’s, which in turn will cause the program to return to address 7FFF Hex. This is an undefined ROM location and the
instruction fetched (all 0’s) from this location will generate a
software interrupt signaling an illegal condition.
(Continued)
• The initial WATCHDOG service must match the key data
value in the WATCHDOG Service register WDSVR in order to avoid a WATCHDOG error.
• Subsequent WATCHDOG services must match all three
data fields in WDSVR in order to avoid WATCHDOG errors.
• The correct key data value cannot be read from the
WATCHDOG Service register WDSVR. Any attempt to
read this key data value of 01100 from WDSVR will read
as key data value of all 0’s.
• The WATCHDOG detector circuit is inhibited during both
the HALT and IDLE modes.
• The CLOCK MONITOR detector circuit is active during
both the HALT and IDLE modes. Consequently, the device inadvertently entering the HALT mode will be detected as a CLOCK MONITOR error (provided that the
CLOCK MONITOR enable option has been selected by
the program).
• With the single-pin R/C oscillator mask option selected
and the CLKDLY bit reset, the WATCHDOG service window will resume following HALT mode from where it left
off before entering the HALT mode.
• With the crystal oscillator mask option selected, or with
the single-pin R/C oscillator mask option selected and the
CLKDLY bit set, the WATCHDOG service window will be
set to its selected value from WDSVR following HALT.
Consequently, the WATCHDOG should not be serviced
for at least 2048 instruction cycles following HALT, but
must be serviced within the selected window to avoid a
WATCHDOG error.
• The IDLE timer T0 is not initialized with RESET.
• The user can sync in to the IDLE counter cycle with an
IDLE counter (T0) interrupt or by monitoring the T0PND
flag. The T0PND flag is set whenever the thirteenth bit of
the IDLE counter toggles (every 4096 instruction cycles).
The user is responsible for resetting the T0PND flag.
• A hardware WATCHDOG service occurs just as the device exits the IDLE mode. Consequently, the WATCHDOG should not be serviced for at least 2048 instruction
cycles following IDLE, but must be serviced within the selected window to avoid a WATCHDOG error.
• Following RESET, the initial WATCHDOG service (where
the service window and the CLOCK MONITOR enable/
disable must be selected) may be programmed anywhere within the maximum service window (65,536 instruction cycles) initialized by RESET. Note that this initial
WATCHDOG service may be programmed within the initial 2048 instruction cycles without causing a WATCHDOG error.
Thus, the chip can detect the following illegal conditions:
1. Executing from undefined ROM
2. Over “POP”ing the stack by having more returns than
calls.
When the software interrupt occurs, the user can re-initialize
the stack pointer and do a recovery procedure before restarting (this recovery program is probably similar to that following reset, but might not contain the same program initialization procedures).
MICROWIRE/PLUS
MICROWIRE/PLUS is a serial synchronous communications
interface. The MICROWIRE/PLUS capability enables the device to interface with any of National Semiconductor’s MICROWIRE peripherals (i.e. A/D converters, display drivers,
E2PROMs etc.) and with other microcontrollers which support the MICROWIRE interface. It consists of an 8-bit serial
shift register (SIO) with serial data input (SI), serial data output (SO) and serial shift clock (SK). Figure 17 shows a block
diagram of the MICROWIRE/PLUS logic.
DS100076-15
FIGURE 17. MICROWIRE/PLUS Block Diagram
The shift clock can be selected from either an internal source
or an external source. Operating the MICROWIRE/PLUS arrangement with the internal clock source is called the Master
mode of operation. Similarly, operating the MICROWIRE/
PLUS arrangement with an external shift clock is called the
Slave mode of operation.
The CNTRL register is used to configure and control the
MICROWIRE/PLUS mode. To use the MICROWIRE/PLUS,
the MSEL bit in the CNTRL register is set to one. In the master mode, the SK clock rate is selected by the two bits, SL0
and SL1, in the CNTRL register. Table 8 details the different
clock rates that may be selected.
Detection of Illegal Conditions
The device can detect various illegal conditions resulting
from coding errors, transient noise, power supply voltage
drops, runaway programs, etc.
Reading of undefined ROM gets zeros. The opcode for software interrupt is zero. If the program fetches instructions
from undefined ROM, this will force a software interrupt, thus
signaling that an illegal condition has occurred.
www.national.com
30
MICROWIRE/PLUS
(Continued)
TABLE 7. WATCHDOG Service Actions
Key
Window
Clock
Data
Data
Monitor
Action
Match
Match
Match
Don’t Care
Mismatch
Don’t Care
Valid Service: Restart Service Window
Error: Generate WATCHDOG Output
Mismatch
Don’t Care
Don’t Care
Error: Generate WATCHDOG Output
Don’t Care
Don’t Care
Mismatch
Error: Generate WATCHDOG Output
onto the G Port. The SK pin must be selected as an input
and the SO pin is selected as an output pin by setting and resetting the appropriate bits in the Port G configuration register. Table 9 summarizes the settings required to enter the
Slave mode of operation.
TABLE 8. MICROWIRE/PLUS
Master Mode Clock Selection
SL1
SL0
0
0
2 x tc
SK
0
1
4 x tc
1
x
8 x tc
Where tc is the
instruction cycle clock
The user must set the BUSY flag immediately upon entering
the Slave mode. This will ensure that all data bits sent by the
Master will be shifted properly. After eight clock pulses the
BUSY flag will be cleared and the sequence may be repeated.
MICROWIRE/PLUS OPERATION
Setting the BUSY bit in the PSW register causes the
MICROWIRE/PLUS to start shifting the data. It gets reset
when eight data bits have been shifted. The user may reset
the BUSY bit by software to allow less than 8 bits to shift. If
enabled, an interrupt is generated when eight data bits have
been shifted. The device may enter the MICROWIRE/PLUS
mode either as a Master or as a Slave. Figure 18 shows how
two microcontroller devices and several peripherals may be
interconnected using the MICROWIRE/PLUS arrangements.
Alternate SK Phase Operation
The device allows either the normal SK clock or an alternate
phase SK clock to shift data in and out of the SIO register. In
both the modes the SK is normally low. In the normal mode
data is shifted in on the rising edge of the SK clock and the
data is shifted out on the falling edge of the SK clock. The
SIO register is shifted on each falling edge of the SK clock.
In the alternate SK phase operation, data is shifted in on the
falling edge of the SK clock and shifted out on the rising edge
of the SK clock.
A control flag, SKSEL, allows either the normal SK clock or
the alternate SK clock to be selected. Resetting SKSEL
causes the MICROWIRE/PLUS logic to be clocked from the
normal SK signal. Setting the SKSEL flag selects the alternate SK clock. The SKSEL is mapped into the G6 configuration bit. The SKSEL flag will power up in the reset condition,
selecting the normal SK signal.
Warning:
The SIO register should only be loaded when the SK clock is
low. Loading the SIO register while the SK clock is high will
result in undefined data in the SIO register. SK clock is normally low when not shifting.
Setting the BUSY flag when the input SK clock is high in the
MICROWIRE/PLUS slave mode may cause the current SK
clock for the SIO shift register to be narrow. For safety, the
BUSY flag should only be set when the input SK clock is low.
TABLE 9. MICROWIRE/PLUS Mode Settings
This table assumes that the control flag MSEL is set.
MICROWIRE/PLUS Master Mode Operation
In the MICROWIRE/PLUS Master mode of operation the
shift clock (SK) is generated internally by the device. The MICROWIRE Master always initiates all data exchanges. The
MSEL bit in the CNTRL register must be set to enable the
SO and SK functions onto the G Port. The SO and SK pins
must also be selected as outputs by setting appropriate bits
in the Port G configuration register. Table 9 summarizes the
bit settings required for Master mode of operation.
G4 (SO)
G5 (SK)
G4
G5
Config. Bit
Config. Bit
Fun.
Fun.
1
1
SO
Int.
MICROWIRE/PLUS
SK
Master
0
1
0
MICROWIRE/PLUS Slave Mode Operation
In the MICROWIRE/PLUS Slave mode of operation the SK
clock is generated by an external source. Setting the MSEL
bit in the CNTRL register enables the SO and SK functions
31
1
0
0
Operation
TRI-
Int.
MICROWIRE/PLUS
STATE
SK
Master
SO
Ext.
MICROWIRE/PLUS
SK
Slave
TRI-
Ext.
MICROWIRE/PLUS
STATE
SK
Slave
www.national.com
MICROWIRE/PLUS
(Continued)
DS100076-16
FIGURE 18. MICROWIRE/PLUS Application
www.national.com
32
Memory Map
Address
Address
Contents
S/ADD REG
All RAM, ports and registers (except A and PC) are mapped
into data memory address space.
Contents
S/ADD REG
xxDA
Port C Input Pins (Read Only)
xxDB
Reserved for Port C
xxDC
Port D
Reserved
0000 to 006F
On-Chip RAM bytes (112 bytes)
xxDD to xxDF
0070 to 007F
Unused RAM Address Space (Reads
As All Ones)
xxE0 to xxE5
Reserved
xxE6
Timer T1 Autoload Register T1RB
Lower Byte
xxE7
Timer T1 Autoload Register T1RB
Upper Byte
xx80 to xxAF
Unused RAM Address Space (Reads
Undefined Data)
xxB0
Timer T3 Lower Byte
xxB1
Timer T3 Upper Byte
xxE8
ICNTRL Register
xxB2
Timer T3 Autoload Register T3RA
Lower Byte
xxE9
MICROWIRE/PLUS Shift Register
xxEA
Timer T1 Lower Byte
Timer T3 Autoload Register T3RA
Upper Byte
xxEB
Timer T1 Upper Byte
xxEC
Timer T1 Autoload Register T1RA
Lower Byte
xxB3
xxB4
Timer T3 Autoload Register T3RB
Lower Byte
xxED
xxB5
Timer T3 Autoload Register T3RB
Upper Byte
Timer T1 Autoload Register T1RA
Upper Byte
xxEE
CNTRL Control Register
xxB6
Timer T3 Control Register
xxEF
PSW Register
xxB7
Comparator Select Register (CMPSL)
xxF0 to FB
On-Chip RAM, Mapped as Registers
xxB8 to xxBF
Reserved
xxFC
X Register
xxC0
Timer T2 Lower Byte
xxFD
SP Register
xxC1
Timer T2 Upper Byte
xxFE
B Register
xxC2
Timer T2 Autoload Register T2RA
Lower Byte
xxFF
S Register
0100 to 017F
On-Chip RAM, 128 Bytes
xxC3
Timer T2 Autoload Register T2RA
Upper Byte
xxC4
Timer T2 Autoload Register T2RB
Lower Byte
xxC5
Timer T2 Autoload Register T2RB
Upper Byte
xxC6
Timer T2 Control Register
xxC7
WATCHDOG Service Register
(Reg:WDSVR)
xxC8
MIWU Edge Select Register
(Reg:WKEDG)
xxC9
MIWU Enable Register (Reg:WKEN)
xxCA
MIWU Pending Register (Reg:WKPND)
xxCB
Reserved
xxCC
Reserved
xxCD to xxCF
Reserved
xxD0
Port L Data Register
xxD1
Port L Configuration Register
xxD2
Port L Input Pins (Read Only)
xxD3
Reserved for Port L
xxD4
Port G Data Register
xxD5
Port G Configuration Register
xxD6
Port G Input Pins (Read Only)
xxD7
Port I Input Pins (Read Only)
xxD8
Port C Data Register
xxD9
Port C Configuration Register
Reading memory locations 0070H–007FH (Segment 0) will return all ones.
Reading unused memory locations 0080H–00AFH (Segment 0) will return
undefined data. Reading memory locations from other unused Segments
(i.e., Segment 2, Segment 3, … etc.) will return undefined data.
33
www.national.com
Addressing Modes
Indirect
This mode is used with the JID instruction. The contents of
the accumulator are used as a partial address (lower 8 bits of
PC) for accessing a location in the program memory. The
contents of this program memory location serve as a partial
address (lower 8 bits of PC) for the jump to the next instruction.
There are ten addressing modes, six for operand addressing
and four for transfer of control.
OPERAND ADDRESSING MODES
Register Indirect
This is the “normal” addressing mode. The operand is the
data memory addressed by the B pointer or X pointer.
Register Indirect (with auto post increment or
decrement of pointer)
Note: The VIS is a special case of the Indirect Transfer of Control addressing
mode, where the double byte vector associated with the interrupt is
transferred from adjacent addresses in the program memory into the
program counter (PC) in order to jump to the associated interrupt service routine.
This addressing mode is used with the LD and X instructions. The operand is the data memory addressed by the B
pointer or X pointer. This is a register indirect mode that automatically post increments or decrements the B or X register after executing the instruction.
Direct
The instruction contains an 8-bit address field that directly
points to the data memory for the operand.
Immediate
The instruction contains an 8-bit immediate field as the operand.
Short Immediate
This addressing mode is used with the Load B Immediate instruction. The instruction contains a 4-bit immediate field as
the operand.
Indirect
Instruction Set
Register and Symbol Definition
Registers
This addressing mode is used with the LAID instruction. The
contents of the accumulator are used as a partial address
(lower 8 bits of PC) for accessing a data operand from the
program memory.
A
8-Bit Accumulator Register
B
8-Bit Address Register
X
8-Bit Address Register
S
8-Bit Segment Register
SP
8-Bit Stack Pointer Register
PC
15-Bit Program Counter Register
PU
Upper 7 Bits of PC
PL
Lower 8 Bits of PC
C
1 Bit of PSW Register for Carry
HC
1 Bit of PSW Register for Half Carry
GIE
1 Bit of PSW Register for Global Interrupt
Enable
VU
Interrupt Vector Upper Byte
VL
Interrupt Vector Lower Byte
[B]
Memory Indirectly Addressed by B Register
[X]
Memory Indirectly Addressed by X Register
MD
Direct Addressed Memory
Mem
Direct Addressed Memory or [B]
Absolute
This mode is used with the JMP and JSR instructions, with
the instruction field of 12 bits replacing the lower 12 bits of
the program counter (PC). This allows jumping to any location in the current 4k program memory segment.
Meml
Direct Addressed Memory or [B] or
Immediate Data
Imm
8-Bit Immediate Data
Reg
Register Memory: Addresses F0 to FF
(Includes B, X and SP)
Absolute Long
This mode is used with the JMPL and JSRL instructions, with
the instruction field of 15 bits replacing the entire 15 bits of
the program counter (PC). This allows jumping to any location up to 32k in the program memory space.
Bit
←
Bit Number (0 to 7)
↔
Exchanged with
TRANSFER OF CONTROL ADDRESSING MODES
Relative
This mode is used for the JP instruction, with the instruction
field being added to the program counter to get the new program location. JP has a range from −31 to +32 to allow a
1-byte relative jump (JP + 1 is implemented by a NOP instruction). There are no “pages” when using JP, since all 15
bits of PC are used.
www.national.com
Symbols
34
Loaded with
Instruction Set
(Continued)
INSTRUCTION SET
A ←A + Meml
A ←A + Meml + C, C← Carry
HC ←Half Carry
ADD
A,Meml
ADD
ADC
A,Meml
ADD with Carry
SUBC
A,Meml
Subtract with Carry
A ←A − MemI + C, C←Carry
HC ←Half Carry
A ←A and Meml
AND
A,Meml
Logical AND
ANDSZ
A,Imm
Logical AND Immed., Skip if Zero
Skip next if (A and Imm) = 0
OR
A,Meml
Logical OR
XOR
A,Meml
Logical EXclusive OR
A ←A or Meml
A ←A xor Meml
IFEQ
MD,Imm
IF EQual
IFEQ
A,Meml
IF EQual
Compare MD and Imm, Do next if MD = Imm
Compare A and Meml, Do next if A = Meml
IFNE
A,Meml
IF Not Equal
Compare A and Meml, Do next if A ≠ Meml
IFGT
A,Meml
IF Greater Than
Compare A and Meml, Do next if A > Meml
Do next if lower 4 bits of B ≠ Imm
IFBNE
#
If B Not Equal
DRSZ
Reg
Decrement Reg., Skip if Zero
SBIT
#,Mem
Set BIT
Reg ←Reg − 1, Skip if Reg = 0
1 to bit, Mem (bit = 0 to 7 immediate)
RBIT
#,Mem
Reset BIT
0 to bit, Mem
IFBIT
#,Mem
IF BIT
If bit in A or Mem is true do next instruction
Reset PeNDing Flag
Reset Software Interrupt Pending Flag
RPND
X
A,Mem
EXchange A with Memory
A↔Mem
X
A,[X]
EXchange A with Memory [X]
LD
A,Meml
LoaD A with Memory
A ↔[X]
A ←Meml
LD
A,[X]
LoaD A with Memory [X]
LD
B,Imm
LoaD B with Immed.
LD
Mem,Imm
LoaD Memory Immed
Mem ←Imm
LD
Reg,Imm
LoaD Register Memory Immed.
Reg ←Imm
A↔[B], (B ←B ± 1)
A ←[X]
B ←Imm
X
A, [B ± ]
EXchange A with Memory [B]
X
A, [X ± ]
EXchange A with Memory [X]
LD
A, [B ± ]
LoaD A with Memory [B]
LD
A, [X ± ]
LoaD A with Memory [X]
A←[X], (X←X ± 1)
LD
[B ± ],Imm
LoaD Memory [B] Immed.
CLR
A
CLeaR A
[B] ←Imm, (B←B ± 1)
A←0
INC
A
INCrement A
DEC
A
DECrement A
LAID
A↔[X], (X ←X ± 1)
A←[B], (B←B ± 1)
A←A + 1
A←A − 1
A←ROM (PU,A)
Load A InDirect from ROM
DCOR
A
Decimal CORrect A
RRC
A
Rotate A Right thru C
A←BCD correction of A (follows ADC, SUBC)
C →A7→… →A0→C
RLC
A
Rotate A Left thru C
C←A7←…←A0←C
SWAP
A
SWAP nibbles of A
SC
Set C
RC
Reset C
A7…A4↔A3…A0
C←1, HC ←1
C←0, HC ←0
IFC
IF C
IF C is true, do next instruction
IFNC
IF Not C
If C is not true, do next instruction
SP←SP + 1, A←[SP]
POP
A
POP the stack into A
PUSH
A
PUSH A onto the stack
VIS
[SP]←A, SP←SP − 1
PU ←[VU], PL ←[VL]
Vector to Interrupt Service Routine
JMPL
Addr.
Jump absolute Long
JMP
Addr.
Jump absolute
PC ←ii (ii = 15 bits, 0 to 32k)
PC9…0 ←i (i = 12 bits)
JP
Disp.
Jump relative short
PC ←PC + r (r is −31 to +32, except 1)
35
www.national.com
Instruction Set
(Continued)
INSTRUCTION SET (Continued)
JSRL
Addr.
Jump SubRoutine Long
JSR
Addr
Jump SubRoutine
JID
Jump InDirect
RET
RETurn from subroutine
RETSK
RETurn and SKip
RETI
RETurn from Interrupt
INTR
Generate an Interrupt
NOP
No OPeration
www.national.com
[SP] ←PL, [SP−1]←PU,SP−2, PC ←ii
[SP] ← PL, [SP−1]←PU,SP−2, PC9…0←i
PL←ROM (PU,A)
SP + 2, PL ← [SP], PU ← [SP−1]
SP + 2, PL ←[SP],PU ← [SP−1]
SP + 2, PL ←[SP],PU ←[SP−1],GIE ←1
[SP] ←PL, [SP−1]←PU, SP−2, PC ←0FF
PC ← PC + 1
36
Instruction Execution Time
Instructions Using A & C
Most instructions are single byte (with immediate addressing
mode instructions taking two bytes).
CLRA
1/1
INCA
1/1
Most single byte instructions take one cycle time to execute.
See the BYTES and CYCLES per INSTRUCTION table for
details.
Bytes and Cycles per Instruction
DECA
1/1
The following table shows the number of bytes and cycles for
each instruction in the format of byte/cycle.
Arithmetic and Logic Instructions
[B]
ADD
1/1
Direct
Immed.
3/4
2/2
ADC
1/1
3/4
2/2
SUBC
1/1
3/4
2/2
AND
1/1
3/4
2/2
LAID
1/3
DCOR
1/1
RRCA
1/1
RLCA
1/1
SWAPA
1/1
SC
1/1
RC
1/1
IFC
1/1
IFNC
1/1
PUSHA
1/3
POPA
1/3
ANDSZ
2/2
OR
1/1
3/4
2/2
XOR
1/1
3/4
2/2
IFEQ
1/1
3/4
2/2
IFNE
1/1
3/4
2/2
JMPL
3/4
IFGT
1/1
3/4
2/2
JMP
2/3
IFBNE
1/1
JP
1/3
Transfer of Control Instructions
1/3
JSRL
SBIT
1/1
3/4
JSR
2/5
RBIT
1/1
3/4
JID
1/3
IFBIT
1/1
3/4
VIS
1/5
DRSZ
RPND
1/1
3/5
RET
1/5
RETSK
1/5
RETI
1/5
INTR
1/7
NOP
1/1
Memory Transfer Instructions
Register
Direct
Immed.
Indirect
[B]
[X]
X A, (Note *NO
TARGET FOR
FNXref
NS7829*)
1/1
1/3
2/3
LD A, (Note
*NO TARGET
FOR FNXref
NS7829*)
1/1
1/3
2/3
2/2
LD B, Imm
1/1
LD B, Imm
2/2
LD Mem, Imm
2/2
Register Indirect
Auto Incr. & Decr.
3/3
LD Reg, Imm
2/3
IFEQ MD, Imm
3/3
[B+, B−]
[X+, X−]
1/2
1/3
1/2
1/3
(IF B < 16)
(IF B > 15)
2/2
Note 33: = > Memory location addressed by B or X or directly.
37
www.national.com
www.national.com
38
JP−18
JP−17
JP−16
JP−2
JP−1
JP−0
LD 0FF, #i
LD 0FE, #i
LD 0FD, #i
LD 0FC, #i
LD 0FB, #i
LD 0FA, #i
LD 0F9, #i
LD 0F8, #i
LD 0F7, #i
LD 0F6, #i
LD 0F5, #i
LD 0F4, #i
LD 0F3, #i
LD 0F2, #i
LD 0F1, #i
LD 0F0, #i
D
DRSZ
0FF
DRSZ
0FE
DRSZ
0FD
DRSZ
0FC
DRSZ
0FB
DRSZ
0FA
DRSZ
0F9
DRSZ
0F8
DRSZ
0F7
DRSZ
0F6
DRSZ
0F5
DRSZ
0F4
DRSZ
0F3
DRSZ
0F2
DRSZ
0F1
DRSZ
0F0
C
B
*
LD
A,[X]
DIR
LD
Md,#i
LD
A,[X−]
LD
A,[X+]
IFNE
A,[B]
NOP
*
X A,[X]
RPND
VIS
X
A,[X−]
X
A,[X+]
*
RRCA
Where,
i is the immediate data
Md is a directly addressed memory location
* is an unused opcode
The opcode 60 Hex is also the opcode for IFBIT #i,A
JP−19
JP−3
JP−24
JP−8
JP−20
JP−25
JP−9
JP−4
JP−26
JP−10
JP−21
JP−27
JP−11
JP−5
JP−28
JP−12
JP−22
JP−29
JP−13
JP−6
JP−30
JP−14
JP−23
JP−31
JP−15
JP−7
E
F
Opcode Table
OR A,#i
XOR
A,#i
AND
A,#i
ADD
A,#i
IFGT
A,#i
IFEQ
A,#i
SUBC
A, #i
ADC
A,#i
9
LD
[B−],#i
LD
[B+],#i
IFNE
A,#i
*
LD
A,[B]
JSRL
LD B,#i
LD
[B],#i
LD
A,Md
JMPL X A,Md
LD
A,[B−]
LD
A,[B+]
IFEQ
Md,#i
RLCA LD A,#i
*
X
A,[B]
JID
LAID
X
A,[B−]
X
A,[B+]
SC
RC
A
RETI
RET
6
CLRA
*
*
*
5
LD
B,#0B
LD
B,#0C
LD
B,#0D
LD
B,#0E
LD
B,#0F
SBIT
7,[B]
SBIT
6,[B]
SBIT
5,[B]
SBIT
4,[B]
SBIT
3,[B]
SBIT
2,[B]
SBIT
1,[B]
SBIT
0,[B]
RBIT
7,[B]
RBIT
6,[B]
RBIT
5,[B]
RBIT
4,[B]
RBIT
3,[B]
RBIT
2,[B]
RBIT
1,[B]
RBIT
0,[B]
IFBIT PUSHA
7,[B]
IFBIT DCORA
6,[B]
LD
B,#00
LD
B,#01
LD
B,#02
LD
B,#03
LD
B,#04
LD
B,#05
LD
B,#06
LD
B,#07
LD
B,#08
LD
B,#09
IFBIT SWAPA
LD
5,[B]
B,#0A
IFBIT
4,[B]
IFBIT
3,[B]
IFBIT
2,[B]
IFBIT
1,[B]
IFBIT ANDSZ
0,[B]
A, #i
7
Upper Nibble
RETSK
POPA
DECA
INCA
IFNC
IFC
OR
A,[B]
XOR
A,[B]
AND
A,[B]
ADD
A,[B]
IFGT
A,[B]
IFEQ
A,[B]
SUBC
A,[B]
ADC
A,[B]
8
4
IFBNE 0F
IFBNE 0E
IFBNE 0D
IFBNE 0C
IFBNE 0B
IFBNE 0A
IFBNE 9
IFBNE 8
IFBNE 7
IFBNE 6
IFBNE 5
IFBNE 4
IFBNE 3
IFBNE 2
IFBNE 1
IFBNE 0
3
2
1
0
8
7
6
5
4
3
2
1
0
JMP
JP+26 JP+10 9
x900–x9FF
JMP
JP+25 JP+9
x800–x8FF
JMP
JP+24 JP+8
x700–x7FF
JMP
JP+23 JP+7
x600–x6FF
JMP
JP+22 JP+6
x500–x5FF
JMP
JP+21 JP+5
x400–x4FF
JMP
JP+20 JP+4
x300–x3FF
JMP
JP+19 JP+3
x200–x2FF
JMP
JP+18 JP+2
x100–x1FF
JMP
JP+17 INTR
x000–x0FF
JSR
JMP
JP+32 JP+16 F
xF00–xFFF xF00–xFFF
JSR
JMP
JP+31 JP+15 E
xE00–xEFF xE00–xEFF
JSR
JMP
JP+30 JP+14 D
xD00–xDFF xD00–xDFF
JSR
JMP
JP+29 JP+13 C
xC00–xCFF xC00–xCFF
JSR
JMP
JP+28 JP+12 B
xB00–xBFF xB00–xBFF
JSR
JMP
JP+27 JP+11 A
xA00–xAFF xA00–xAFF
JSR
x900–x9FF
JSR
x800–x8FF
JSR
x700–x7FF
JSR
x600–x6FF
JSR
x500–x5FF
JSR
x400–x4FF
JSR
x300–x3FF
JSR
x200–x2FF
JSR
x100–x1FF
JSR
x000–x0FF
Lower Nibble
COP8 Integrated Software/Hardware Design Development Kits
Mask Options
The mask programmable options are shown below. The options are programmed at the same time as the ROM pattern
submission.
•
OPTION 1: CLOCK CONFIGURATION
= 1
Crystal Oscillator (CKI/10)
G7 (CKO) is clock generator
output to crystal/resonator
CKI is the clock input
= 2
Single-pin RC controlled
oscillator (CKI/10)
G7 is available as a HALT
restart and/or general
purpose input
OPTION 2: HALT
= 1
Enable HALT mode
= 2
Disable HALT mode
OPTION 3: BONDING
= 1
44-Pin PLCC
•
COP8-DM: Moderate cost Debug Module from MetaLink.
A Windows based, real-time in-circuit emulation tool with
COP8 device programmer. Includes COP8-NSDEV,
DriveWay COP8 Demo, MetaLink Debugger, power supply, emulation cables and adapters.
COP8 Development Languages and Environments
Development Tools Support
OVERVIEW
National is engaged with an international community of independent 3rd party vendors who provide hardware and software development tool support. Through National’s interaction and guidance, these tools cooperate to form a choice of
solutions that fits each developer’s needs.
This section provides a summary of the tool and development kits currently available. Up-to-date information, selection guides, free tools, demos, updates, and purchase information can be obtained at our web site at:
www.national.com/cop8.
•
COP8-NSASM: Free COP8 Assembler v5 for Win32.
Macro assembler, linker, and librarian for COP8 software
development. Supports all COP8 devices. (DOS/Win16
v4.10.2 available with limited support). (Compatible with
WCOP8 IDE, COP8C, and DriveWay COP8).
•
COP8-NSDEV: Very low cost Software Development
Package for Windows. An integrated development environment for COP8, including WCOP8 IDE, COP8NSASM, COP8-MLSIM.
•
COP8C: Moderately priced C Cross-Compiler and Code
Development System from Byte Craft (no code limit). Includes BCLIDE (Byte Craft Limited Integrated Development Environment) for Win32, editor, optimizing C CrossCompiler, macro cross assembler, BC-Linker, and
MetaLink tools support. (DOS/SUN versions available;
Compiler is installable under WCOP8 IDE; Compatible
with DriveWay COP8).
•
EWCOP8-KS: Very Low cost ANSI C-Compiler and Embedded Workbench from IAR (Kickstart version:
COP8Sx/Fx only with 2k code limit; No FP). A fully integrated Win32 IDE, ANSI C-Compiler, macro assembler,
editor, linker, Liberian, C-Spy simulator/debugger, PLUS
MetaLink EPU/DM emulator support.
•
EWCOP8-AS: Moderately priced COP8 Assembler and
Embedded Workbench from IAR (no code limit). A fully integrated Win32 IDE, macro assembler, editor, linker, librarian, and C-Spy high-level simulator/debugger with
I/O and interrupts support. (Upgradeable with optional
C-Compiler and/or MetaLink Debugger/Emulator support).
•
EWCOP8-BL: Moderately priced ANSI C-Compiler and
Embedded Workbench from IAR (Baseline version: All
COP8 devices; 4k code limit; no FP). A fully integrated
Win32 IDE, ANSI C-Compiler, macro assembler, editor,
linker, librarian, and C-Spy high-level simulator/debugger.
(Upgradeable; CWCOP8-M MetaLink tools interface support optional).
•
EWCOP8: Full featured ANSI C-Compiler and Embedded Workbench for Windows from IAR (no code limit). A
fully integrated Win32 IDE, ANSI C-Compiler, macro assembler, editor, linker, librarian, and C-Spy high-level
simulator/debugger. (CWCOP8-M MetaLink tools interface support optional).
•
EWCOP8-M: Full featured ANSI C-Compiler and Embedded Workbench for Windows from IAR (no code limit). A
fully integrated Win32 IDE, ANSI C-Compiler, macro assembler, editor, linker, librarian, C-Spy high-level
simulator/debugger, PLUS MetaLink debugger/hardware
interface (CWCOP8-M).
SUMMARY OF TOOLS
COP8 Evaluation Tools
•
COP8–NSEVAL: Free Software Evaluation package for
Windows. A fully integrated evaluation environment for
COP8, including versions of WCOP8 IDE (Integrated Development Environment), COP8-NSASM, COP8-MLSIM,
COP8C, DriveWay™ COP8, Manuals, and other COP8
information.
•
COP8–MLSIM: Free Instruction Level Simulator tool for
Windows. For testing and debugging software instructions only (No I/O or interrupt support).
•
COP8–EPU: Very Low cost COP8 Evaluation & Programming Unit. Windows based evaluation and
hardware-simulation tool, with COP8 device programmer
and erasable samples. Includes COP8-NSDEV, Driveway COP8 Demo, MetaLink Debugger, I/O cables and
power supply.
•
COP8–EVAL-ICUxx: Very Low cost evaluation and design test board for COP8ACC and COP8SGx Families,
from ICU. Real-time environment with add-on A/D, D/A,
and EEPROM. Includes software routines and reference
designs.
•
Manuals, Applications Notes, Literature: Available free
from our web site at: www.national.com/cop8.
COP8-EPU: Very Low cost Evaluation & Programming
Unit. Windows based development and hardwaresimulation tool for COPSx/xG families, with COP8 device
programmer and samples. Includes COP8-NSDEV,
Driveway COP8 Demo, MetaLink Debugger, cables and
power supply.
39
www.national.com
Development Tools Support
COP8 Real-Time Emulation Tools
• COP8-DM: MetaLink Debug Module. A moderately
priced real-time in-circuit emulation tool, with COP8 device programmer. Includes COP8-NSDEV, DriveWay
COP8 Demo, MetaLink Debugger, power supply, emulation cables and adapters.
• IM-COP8: MetaLink iceMASTER ® . A full featured, realtime in-circuit emulator for COP8 devices. Includes MetaLink Windows Debugger, and power supply. Packagespecific probes and surface mount adaptors are ordered
separately.
COP8 Device Programmer Support
• MetaLink’s EPU and Debug Module include development
device programming capability for COP8 devices.
• Third-party programmers and automatic handling equipment cover needs from engineering prototype and pilot
production, to full production environments.
• Factory programming available for high-volume requirements.
(Continued)
COP8 Productivity Enhancement Tools
• WCOP8 IDE: Very Low cost IDE (Integrated Development Environment) from KKD. Supports COP8C, COP8NSASM, COP8-MLSIM, DriveWay COP8, and MetaLink
debugger under a common Windows Project Management environment. Code development, debug, and emulation tools can be launched from the project window
framework.
• DriveWay-COP8: Low cost COP8 Peripherals Code
Generation tool from Aisys Corporation. Automatically
generates tested and documented C or Assembly source
code modules containing I/O drivers and interrupt handlers for each on-chip peripheral. Application specific
code can be inserted for customization using the integrated editor. (Compatible with COP8-NSASM, COP8C,
and WCOP8 IDE.)
• COP8-UTILS: Free set of COP8 assembly code examples, device drivers, and utilities to speed up code development.
• COP8-MLSIM: Free Instruction Level Simulator tool for
Windows. For testing and debugging software instructions only (No I/O or interrupt support).
TOOLS ORDERING NUMBERS FOR THE COP888GD FAMILY DEVICES
Vendor
National
Tools
COP8-NSEVAL
Order Number
COP8-NSEVAL
Cost
Free
Notes
Web site download
COP8-NSASM
COP8-NSASM
Free
Included in EPU and DM. Web site download
COP8-MLSIM
COP8-MLSIM
Free
Included in EPU and DM. Web site download
COP8-NSDEV
COP8-NSDEV
VL
Included in EPU and DM. Order CD from website
COP8-EPU
Not available for this device
COP8-DM
Contact MetaLink
Development
Devices
COP87L84GD/RD
VL
16k or 32k OTP devices.
IM-COP8
MetaLink COP8-EPU
Contact MetaLink
Not available for this device
COP8-DM
DM4-COP8-888GD (10
MHz), plus PS-10, plus
DM-COP8/xxx (ie. 28D)
M
Included p/s (PS-10), target cable of choice (DIP or
PLCC; i.e. DM-COP8/40D), 16/20/28/40 DIP/SO and
44 PLCC programming sockets. Add target adapter (if
needed)
DM Target
Adapters
MHW-CONV39
L
DM target converters for 28SO
IM-COP8
IM-COP8-AD-464 (-220)
(10 MHz maximum)
H
Base unit 10 MHz; -220 = 220V; add probe card
(required) and target adapter (if needed); included
software and manuals
IM Probe Card
PC-888GD40DW-AD-10
M
10 MHz 40 DIP probe card; 2.5V to 6.0V
PC-888GD44PW-AD-10
M
10 MHz 44 PLCC probe card; 2.5V to 6.0V
Included in EPU and DM
ICU
COP8-EVAL
Not available for this device
KKD
WCOP8-IDE
WCOP8-IDE
VL
IAR
EWCOP8-xx
See summary above
L-H
Included all software and manuals
Byte
Craft
COP8C
COP8C
M
Included all software and manuals
Aisys
DriveWay COP8
DriveWay COP8
L
Included all software and manuals
www.national.com
40
Development Tools Support
OTP Programmers
(Continued)
Contact vendors
L-H
For approved programmer listings and vendor
information, go to our OTP support page at:
www.national.com/cop8
Cost: Free; VL = < $100; L = $100 - $300; M = $300 - $1k; H = $1k - $3k; VH = $3k - $5k
WHERE TO GET TOOLS
Tools are ordered directly from the following vendors. Please go to the vendor’s web site for current listings of distributors.
Vendor
Aisys
Home Office
Electronic Sites
U.S.A.: Santa Clara, CA
www.aisysinc.com
1-408-327-8820
[email protected]
Other Main Offices
Distributors
fax: 1-408-327-8830
Byte Craft
U.S.A.
www.bytecraft.com
1-519-888-6911
info @bytecraft.com
Distributors
fax: 1-519-746-6751
IAR
Sweden: Uppsala
www.iar.se
U.S.A.: San Francisco
+46 18 16 78 00
[email protected]
1-415-765-5500
fax: +46 18 16 78 38
[email protected]
fax: 1-415-765-5503
[email protected]
U.K.: London
[email protected]
+44 171 924 33 34
fax: +44 171 924 53 41
Germany: Munich
+49 89 470 6022
fax: +49 89 470 956
ICU
Sweden: Polygonvaegen
www.icu.se
Switzeland: Hoehe
+46 8 630 11 20
[email protected]
+41 34 497 28 20
fax: +46 8 630 11 70
support @icu.ch
fax: +41 34 497 28 21
KKD
Denmark:
www.kkd.dk
MetaLink
U.S.A.: Chandler, AZ
www.metaice.com
Germany: Kirchseeon
1-800-638-2423
sales @metaice.com
80-91-5696-0
fax: 1-602-926-1198
support @metaice.com
fax: 80-91-2386
National
bbs: 1-602-962-0013
[email protected]
www.metalink.de
Distributors Worldwide
U.S.A.: Santa Clara, CA
www.national.com/cop8
Europe: +49 (0) 180 530 8585
1-800-272-9959
support @nsc.com
fax: +49 (0) 180 530 8586
fax: 1-800-737-7018
europe.support @nsc.com
Distributors Worldwide
Customer Support
The following companies have approved COP8 programmers in a variety of configurations. Contact your local office
or distributor. You can link to their web sites and get the latest listing of approved programmers from National’s COP8
OTP Support page at: www.national.com/cop8.
Complete product information and technical support is available from National’s customer response centers, and from
our on-line COP8 customer support sites.
Advantech; Advin; BP Microsystems; Data I/O; Hi-Lo Systems; ICE Technology; Lloyd Research; Logical Devices;
MQP; Needhams; Phyton; SMS; Stag Programmers; System General; Tribal Microsystems; Xeltek.
41
www.national.com
COP888GD 8-Bit CMOS ROM Based Microcontrollers with 16k Memory and 8-Channel A/D
Physical Dimensions
inches (millimeters) unless otherwise noted
Plastic Leaded Chip Carrier (V)
Order Number COP888GD-XXX/V or COP988GD-XXX/V
NS Package Number V44A
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
National Semiconductor
Corporation
Americas
Tel: 1-800-272-9959
Fax: 1-800-737-7018
Email: [email protected]
www.national.com
National Semiconductor
Europe
Fax: +49 (0) 1 80-530 85 86
Email: [email protected]
Deutsch Tel: +49 (0) 1 80-530 85 85
English Tel: +49 (0) 1 80-532 78 32
Français Tel: +49 (0) 1 80-532 93 58
Italiano Tel: +49 (0) 1 80-534 16 80
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
National Semiconductor
Asia Pacific Customer
Response Group
Tel: 65-2544466
Fax: 65-2504466
Email: [email protected]
National Semiconductor
Japan Ltd.
Tel: 81-3-5639-7560
Fax: 81-3-5639-7507
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.