October 2006 HYS64T32[0/9]00EU-[25F/2.5/3/3S/3.7]-B2 HYS[64/72]T64[0/9]00EU-[25F/2.5/3/3S/3.7]-B2 HYS[64/72]T128[0/9]20EU-[25F/2.5/3/3S/3.7]-B2 2 4 0 - P i n u n b u f f e r e d D D R 2 S D R A M Mo d u l e s DDR2 SDRAM UDIMM SDRAM RoHs Compliant Internet Data Sheet Rev. 1.0 Internet Data Sheet HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module HYS64T32[0/9]00EU-[25F/2.5/3/3S/3.7]-B2, HYS[64/72]T64[0/9]00EU-[25F/2.5/3/3S/3.7]-B2, HYS[64/72]T128[0/9]20EU[25F/2.5/3/3S/3.7]-B2 Revision History: 2006-10, Rev. 1.0 Page Subjects (major changes since last revision) All Qimonda update All Adapted internet edition 4,5 Ordering information table. Added 6LayerWhiteBox Products 16 – 20 Block Diagrams: Clock Signal Load Tables and Notes updated 34, 35 ODT table update 38 – 42 Added IDD values 45 – 92 SPD codes updated Previous Revision: 2006-07, Rev. 0.5 We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: [email protected] qag_techdoc_rev400 / 3.2 QAG / 2006-08-07 10202006-L0SM-FEYT 2 Internet Data Sheet HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module 1 Overview This chapter gives an overview of the 240-Pin unbuffered DDR2 SDRAM Modules product family and describes its main characteristics. 1.1 Features Feature list and performance tables • 240-Pin PC2–6400, PC2–5300 and PC2–4200 DDR2 SDRAM memory modules. • Module organization 32M × 64, 64M × 64, 64M × 72, 128M × 64 and 128M × 72. Chip organization 32M × 16 and 64M × 8. • Standard Double-Data-Rate-Two Synchronous DRAMs (DDR2 SDRAM) with a single + 1.8 V (± 0.1 V) power supply • 256MB, 512MB and 1GB modules built with 512-Mbit DDR2 SDRAMs in P-TFBGA-60 and PG-TFBGA-84 chipsize packages • All speed grades faster than DDR2–400 comply with DDR400 timing specifications. • Programmable CAS Latencies (3, 4, 5 and 6), Burst Length (8 & 4) and Burst Type • • • • • • • • • • Auto Refresh (CBR) and Self Refresh Programmable self refresh rate via EMRS2 setting Programmable partial array refresh via EMRS2 settings DCC enabling via EMRS2 setting All inputs and outputs SSTL_1.8 compatible Off-Chip Driver Impedance Adjustment (OCD) and On-Die Termination (ODT) Serial Presence Detect with E2PROM UDIMM Dimensions (nominal): 30 mm high and 133.35 mm wide Based on standard reference layouts Raw Card “C” “D”, “E”, “F” and “G” RoHS compliant products1) TABLE 1 Performance Table Product Type Speed Code –25F –2.5 –3 –3S –3.7 Unit Speed Grade PC2–6400 5–5–5 PC2–6400 6–6–6 PC2–5300 4–4–4 PC2–5300 5–5–5 PC2–4200 4–4–4 — 400 400 – – – MHz 400 333 333 333 266 MHz 266 266 333 266 266 MHz Max. Clock Frequency @CL6 @CL5 @CL4 @CL3 Min. RAS-CAS-Delay Min. Row Precharge Time Min. Row Active Time Min. Row Cycle Time fCK6 fCK5 fCK4 fCK3 tRCD tRP tRAS tRC 200 200 200 200 200 MHz 12.5 15 12 15 15 ns 12.5 15 12 15 15 ns 45 45 45 45 45 ns 57.5 60 57 60 60 ns 1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers. Rev. 1.0, 2006-10 10202006-L0SM-FEYT 3 Internet Data Sheet HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module 1.2 Description The Qimonda HYS[64/72]T[32/64/128][0/9]xxEU[25F/2.5/3/3S/3.7]-B2 module family are unbuffered DIMM modules “UDIMMs” with 30,0 mm height based on DDR2 technology. DIMMs are available as non-ECC modules in 32M × 64 (256 MB), 64M × 64 (512 MB) and 128M × 64 (1 GB) and ECC modules in 64M × 72 (512 MB), 128M × 72 (1 GB) organization and density, intended for mounting into 240-pin connector sockets. The memory array is designed with 512-Mbit Double-DataRate-Two (DDR2) Synchronous DRAMs. Decoupling capacitors are mounted on the PCB board. The DIMMs feature serial presence detect based on a serial E2PROM device using the 2-pin I2C protocol. The first 128 bytes are programmed with configuration data and are write protected; the second 128 bytes are available to the customer. TABLE 2 Ordering Information for RoHS Compliant Products Product Type1) Compliance Code2) Description SDRAM Technology HYS64T32000EU–25F–B2 HYS64T32900EU–25F–B2 256MB 1R×16 PC2–6400U–555–12–C1 1 Rank, Non-ECC 512 Mbit (×16) HYS64T64000EU–25F–B2 HYS64T64900EU–25F–B2 512 MB 1R×8 PC2–6400U–555–12–D0 1 Rank, Non-ECC 512 Mbit (×8) HYS72T64000EU–25F–B2 HYS72T64900EU–25F–B2 512MB 1R×8 PC2–6400E–555–12–F0 1 Rank, ECC 512 Mbit (×8) HYS64T128020EU–25F–B2 HYS64T128920EU–25F–B2 1GB 2R×8 PC2–6400U–555–12–E0 2 Ranks, Non-ECC 512 Mbit (×8) HYS72T128020EU–25F–B2 HYS72T128920EU–25F–B2 1GB 2R×8 PC2–6400E–555–12–G0 2 Ranks, ECC 512 Mbit (×8) HYS64T32000EU–2.5–B2 HYS64T32900EU–2.5–B2 256MB 1R×16 PC2–6400U–666–12–C1 1 Rank, Non-ECC 512 Mbit (×16) HYS64T64000EU–2.5–B2 HYS64T64900EU–2.5–B2 512 MB 1R×8 PC2–6400U–666–12–D0 1 Rank, Non-ECC 512 Mbit (×8) HYS72T64000EU-2.5–B2 HYS72T64900EU-2.5–B2 512MB 1R×8 PC2–6400E–666–12–F0 1 Rank, ECC 512 Mbit (×8) HYS64T128020EU–2.5–B2 HYS64T128920EU–2.5–B2 1GB 2R×8 PC2–6400U–666–12–E0 2 Ranks, Non-ECC 512 Mbit (×8) HYS72T128020EU–2.5–B2 HYS72T128920EU–2.5–B2 1GB 2R×8 PC2–6400E–666–12–G0 2 Ranks, ECC 512 Mbit (×8) HYS64T32000EU–3–B2 HYS64T32900EU–3–B2 256MB 1R×16 PC2-5300U–444–12–C1 1 Rank, Non-ECC 512 Mbit (×16) HYS64T64000EU–3–B2 HYS64T64900EU–3–B2 512MB 1R×8 PC2–5300U–444–12–D0 1 Rank, Non-ECC 512 Mbit (×8) HYS72T64000EU–3–B2 HYS72T64900EU–3–B2 512MB 1R×8 PC2–5300E–444–12–F0 1 Rank, ECC 512 Mbit (×8) PC2–6400 PC2–6400 PC2–5300 Rev. 1.0, 2006-10 10202006-L0SM-FEYT 4 Internet Data Sheet HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module Product Type1) Compliance Code2) Description SDRAM Technology HYS64T128020EU–3–B2 HYS64T128920EU–3–B2 1GB 2R×8 PC2–5300U–444–12–E0 2 Ranks, Non-ECC 512 Mbit (×8) HYS72T128020EU–3–B2 HYS72T128920EU–3–B2 1GB 2R× 8 PC2-5300E–444–12–G0 2 Ranks, ECC 512 Mbit (×8) HYS64T32000EU–3S–B2 HYS64T32900EU–3S–B2 256MB 1R×16 PC2–5300U–555–12–C1 1 Rank, Non-ECC 512 Mbit (×16) HYS64T64000EU–3S–B2 HYS64T64900EU–3S–B2 512MB 1R×8 PC2–5300U–555–12–D0 1 Rank, Non-ECC 512 Mbit (×8) HYS72T64000EU–3S–B2 HYS72T64900EU–3S–B2 512MB 1R×8 PC2–5300E–555–12–F0 1 Rank, ECC 512 Mbit (×8) HYS64T128020EU–3S–B2 HYS64T128920EU–3S–B2 1GB 2R×8 PC2–5300U–555–12–E0 2 Ranks, Non-ECC 512 Mbit (×8) HYS72T128020EU–3S–B2 HYS72T128920EU–3S–B2 1GB 2R×8 PC2–5300E–555–12–G0 2 Ranks, ECC 512 Mbit (×8) HYS64T32000EU–3.7–B2 HYS64T32900EU–3.7–B2 256MB 1R×16 PC2–4200U–444–12–C1 1 Rank, Non-ECC 512 Mbit (×16) HYS64T64000EU–3.7–B2 HYS64T64900EU–3.7–B2 512MB 1R×8 PC2–4200U–444–12–D0 1 Rank, Non-ECC 512 Mbit (×8) HYS72T64000EU–3.7–B2 HYS72T64900EU–3.7–B2 512MB 1R×8 PC2–4200E–444–12–F0 1 Rank, ECC 512 Mbit (×8) HYS64T128020EU–3.7–B2 HYS64T128920EU–3.7–B2 1GB 2R×8 PC2–4200U–444–12–E0 2 Ranks, Non-ECC 512 Mbit (×8) HYS72T128020EU–3.7–B2 HYS72T128920EU–3.7–B2 1GB 2R×8 PC2–4200E–444–12–G0 2 Ranks, ECC 512 Mbit (×8) PC2–5300 PC2–4200 1) All Product Type end with a place code, designating the silicon die revision. Example: HYS64T64000EU–3–B2, indicating Rev. “B2” dies are used for DDR2 SDRAM components. For all Qimonda DDR2 module and component nomenclature see Chapter 6 of this data sheet. 2) The Compliance Code is printed on the module label and describes the speed grade, for example “PC2–4200U–444–12–D0”, where 4200U means Unbuffered DIMM modules with 4.26 GB/sec. Module Bandwidth and “444-12-D0” means Column Address Strobe (CAS) latency = 4, Row Column Delay (RCD) latency = 4 and Row Precharge (RP) latency = 4 using the latest JEDEC SPD Revision 1.2 and produced on the Raw Card “D”. Rev. 1.0, 2006-10 10202006-L0SM-FEYT 5 Internet Data Sheet HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module TABLE 3 Address Format DIMM Density Module Organization Memory Ranks ECC/ Non-ECC # of SDRAMs # of row/bank/column bits Raw Card 256 MByte 32M × 64 1 Non-ECC 4 13/2/10 C 512 MByte 64M × 64 1 Non-ECC 8 14/2/10 D 512 MByte 72M × 64 1 ECC 9 14/2/10 F 1 GByte 128M × 64 2 Non-ECC 16 14/2/10 E 1 GByte 128M × 72 2 ECC 18 14/2/10 G TABLE 4 Components on Modules Product Type1)2) DRAM Components1) DRAM Density DRAM Organization HYS64T32[0/9]00EU HYB18T512160B2F 512 Mbit 32M × 16 HYS64T64[0/9]00EU HYB18T512800B2F 512 Mbit 64M × 8 HYS72T64[0/9]00EU HYB18T512800B2F 512 Mbit 64M × 8 HYS64T128[0/9]20EU HYB18T512800B2F 512 Mbit 64M × 8 HYS72T128[0/9]20EU HYB18T512800B2F 512 Mbit 64M × 8 1) Green Product 2) For a detailed description of all functionalities of the DRAM components on these modules see the component data sheet. Rev. 1.0, 2006-10 10202006-L0SM-FEYT 6 Internet Data Sheet HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module 2 Pin Configuration The pin configuration of the Unbuffered DDR2 SDRAM DIMM is listed by function in Table 5 (240 pins). The abbreviations used in columns Pin and Buffer Type are explained in Table 6 and Table 7 respectively. The pin numbering is depicted in Figure 1 for non-ECC modules (×64) and Figure 2 for ECC modules (×72). TABLE 5 Pin Configuration of UDIMM Ball No. Name Pin Type Buffer Type Function Clock Signals 2:0, Complement Clock Signals 2:0 Clock Signals 185 CK0 I SSTL 137 CK1 I SSTL 220 CK2 I SSTL 186 CK0 I SSTL 138 CK1 I SSTL 221 CK2 I SSTL 52 CKE0 I SSTL 171 CKE1 I SSTL Clock Enable Rank 1:0 Note: 2 Ranks module NC NC — Not Connected Note: 1 Rank module 193 S0# I SSTL 76 S1# I SSTL Chip Select Rank 1:0 Note: 2 Ranks module NC NC — Not Connected Note: 1 Rank module Control Signals 192 RAS I SSTL Row Address Strobe 74 CAS I SSTL Column Address Strobe 73 WE I SSTL Write Enable 71 BA0 I SSTL Bank Address Bus 1:0 190 BA1 I SSTL 54 BA2 I SSTL Bank Address Bus 2 Greater than 512Mb DDR2 SDRAMS NC NC — Not Connected Less than 1Gb DDR2 SDRAMS Address Signals Rev. 1.0, 2006-10 10202006-L0SM-FEYT 7 Internet Data Sheet HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module Ball No. Name Pin Type Buffer Type Function 188 A0 I SSTL Address Bus 12:0 183 A1 I SSTL 63 A2 I SSTL 182 A3 I SSTL 61 A4 I SSTL 60 A5 I SSTL 180 A6 I SSTL 58 A7 I SSTL 179 A8 I SSTL 177 A9 I SSTL 70 A10 I SSTL AP I SSTL 57 A11 I SSTL 176 A12 I SSTL 196 A13 I SSTL Address Signal 13 Note: 1 Gbit based module and 512M ×4/×8 NC NC — Not Connected Note: Module based on 1 Gbit ×16 Module based on 512 Mbit ×16 or smaller A14 I SSTL Address Signal 14 Note: Modules based on 2 Gbit NC NC — Not Connected Note: Modules based on 1 Gbit or smaller 3 DQ0 I/O SSTL 4 DQ1 I/O SSTL Data Bus 63:0 Data Input/Output pins 9 DQ2 I/O SSTL 10 DQ3 I/O SSTL 122 DQ4 I/O SSTL 123 DQ5 I/O SSTL 128 DQ6 I/O SSTL 129 DQ7 I/O SSTL 174 Data Signals Rev. 1.0, 2006-10 10202006-L0SM-FEYT 8 Internet Data Sheet HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module Ball No. Name Pin Type Buffer Type Function 12 DQ8 I/O SSTL 13 DQ9 I/O SSTL Data Bus 63:0 Data Input/Output pins 21 DQ10 I/O SSTL 22 DQ11 I/O SSTL 131 DQ12 I/O SSTL 132 DQ13 I/O SSTL 140 DQ14 I/O SSTL 141 DQ15 I/O SSTL 24 DQ16 I/O SSTL 25 DQ17 I/O SSTL 30 DQ18 I/O SSTL 31 DQ19 I/O SSTL 143 DQ20 I/O SSTL 144 DQ21 I/O SSTL 149 DQ22 I/O SSTL 150 DQ23 I/O SSTL 33 DQ24 I/O SSTL 34 DQ25 I/O SSTL 39 DQ26 I/O SSTL 40 DQ27 I/O SSTL 152 DQ28 I/O SSTL 153 DQ29 I/O SSTL 158 DQ30 I/O SSTL 159 DQ31 I/O SSTL 80 DQ32 I/O SSTL 81 DQ33 I/O SSTL 86 DQ34 I/O SSTL 87 DQ35 I/O SSTL 199 DQ36 I/O SSTL 200 DQ37 I/O SSTL 205 DQ38 I/O SSTL 206 DQ39 I/O SSTL 89 DQ40 I/O SSTL 90 DQ41 I/O SSTL 95 DQ42 I/O SSTL 96 DQ43 I/O SSTL 208 DQ44 I/O SSTL 209 DQ45 I/O SSTL 214 DQ46 I/O SSTL 215 DQ47 I/O SSTL Rev. 1.0, 2006-10 10202006-L0SM-FEYT 9 Internet Data Sheet HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module Ball No. Name Pin Type Buffer Type Function 98 DQ48 I/O SSTL 99 DQ49 I/O SSTL Data Bus 63:0 Data Input/Output pins 107 DQ50 I/O SSTL 108 DQ51 I/O SSTL 217 DQ52 I/O SSTL 218 DQ53 I/O SSTL 226 DQ54 I/O SSTL 227 DQ55 I/O SSTL 110 DQ56 I/O SSTL 111 DQ57 I/O SSTL 116 DQ58 I/O SSTL 117 DQ59 I/O SSTL 229 DQ60 I/O SSTL 230 DQ61 I/O SSTL 235 DQ62 I/O SSTL 236 DQ63 I/O SSTL CB0 I/O SSTL Check Bit 0 NC NC — Not Connected 43 CB1 I/O SSTL Check Bit 1 NC NC — Not Connected 48 CB2 I/O SSTL Check Bit 2 NC NC — Not Connected CB3 I/O SSTL Check Bit 3 NC NC — Not Connected CB4 I/O SSTL Check Bit 4 NC NC — Not Connected 162 CB5 I/O SSTL Check Bit 5 NC NC — Not Connected 167 CB6 I/O SSTL Check Bit 6 NC NC — Not Connected CB7 I/O SSTL Check Bit 7 NC NC — Not Connected Check Bit Signals 42 49 161 168 Rev. 1.0, 2006-10 10202006-L0SM-FEYT 10 Internet Data Sheet HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module Ball No. Name Pin Type Buffer Type Function Data Strobe Bus 8:0 Data Strobe Bus 7 DQS0 I/O SSTL 16 DQS1 I/O SSTL 28 DQS2 I/O SSTL 37 DQS3 I/O SSTL 84 DQS4 I/O SSTL 93 DQS5 I/O SSTL 105 DQS6 I/O SSTL 114 DQS7 I/O SSTL 46 DQS8 I/O SSTL 6 DQS0 I/O SSTL 15 DQS1 I/O SSTL 27 DQS2 I/O SSTL 36 DQS3 I/O SSTL 83 DQS4 I/O SSTL 92 DQS5 I/O SSTL 104 DQS6 I/O SSTL 113 DQS7 I/O SSTL 45 DQS8 I/O SSTL Complement Data Strobe Bus 8:0 Data Mask Signals 125 DM0 I SSTL 134 DM1 I SSTL 146 DM2 I SSTL 155 DM3 I SSTL 202 DM4 I SSTL 211 DM5 I SSTL 223 DM6 I SSTL 232 DM7 I SSTL 164 DM8 I SSTL SCL I CMOS Data Mask Bus 8:0 EEPROM 120 Serial Bus Clock 119 SDA I/O OD Serial Bus Data 239 SA0 I CMOS Serial Address Select Bus 2:0 240 SA1 I CMOS 101 SA2 I CMOS Rev. 1.0, 2006-10 10202006-L0SM-FEYT 11 Internet Data Sheet HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module Ball No. Name Pin Type Buffer Type Function Power Supplies VREF AI VDDSPD PWR VDDQ PWR — I/O Reference Voltage — EEPROM Power Supply — I/O Driver Power Supply 53,59,64,67,69,, 172,178,184,187, 189,197 VDD PWR — Power Supply 2,5,8,11,14,17,, 20,23,26,29,32, 35,38,41,44,47,, 50,65,66,79,82, 85,88,91,94,97,, 100,103,106, 109,112,115,118, 121,124,127,, 130,133,136,139, 142,145,148,, 151,154,157,160, 163,166,169, 198,201,204,207, 210,213,216,, 219,222,225,228, 231,234,237 VSS GND — Ground Plane 195 ODT0 I SSTL On-Die Termination Control 0 77 ODT1 I SSTL On-Die Termination Control 1 Note: 2 Rank modules NC NC — Not Connected Note: 1 Rank modules 18,19,55,68,102,1 NC 26,135,147, 156,165,173,203, 212, 224,233 NC — Not connected 1 238 51,56,62,72,75,, 78,170,175,181,, 191,194 Other Pins Rev. 1.0, 2006-10 10202006-L0SM-FEYT 12 Internet Data Sheet HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module TABLE 6 Abbreviations for Pin Type Abbreviation Description I Standard input-only pin. Digital levels. O Output. Digital levels. I/O I/O is a bidirectional input/output signal. AI Input. Analog levels. PWR Power GND Ground NC Not Connected TABLE 7 Abbreviations for Buffer Type Abbreviation Description SSTL Serial Stub Terminated Logic (SSTL_18) LV-CMOS Low Voltage CMOS CMOS CMOS Levels OD Open Drain. The corresponding pin has 2 operational states, active low and tri-state, and allows multiple devices to share as a wire-OR. Rev. 1.0, 2006-10 10202006-L0SM-FEYT 13 Internet Data Sheet HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module FIGURE 1 Pin Configuration UDIMM ×64 (240 Pin) 95() 3LQ '4 3LQ 966 3LQ '46 3LQ '4 3LQ 966 3LQ '4 3LQ '46 3LQ 966 3LQ 1& 3LQ '4 3LQ 3LQ 966 '4 3LQ '46 3LQ 966 3LQ '4 3LQ '4 3LQ 966 3LQ '46 3LQ '4 3LQ 966 3LQ 1& 3LQ 1& 3LQ 966 3LQ 1& 3LQ 3LQ 9''4 9'' 3LQ 1& 3LQ $ 3LQ 9'' 3LQ 3LQ $ 3LQ $ 966 3LQ 9'' 3LQ 9'' 3LQ %$ 3LQ :( 3LQ 3LQ 9''4 2'7 3LQ 966 3LQ '4 3LQ '46 3LQ 966 3LQ '4 3LQ '4 3LQ 966 3LQ '46 3LQ '4 3LQ 966 3LQ '4 3LQ 6$ 3LQ 966 3LQ '46 3LQ '4 3LQ 966 3LQ '4 3LQ '46 3LQ 966 3LQ '4 3LQ 6'$ 3LQ Rev. 1.0, 2006-10 10202006-L0SM-FEYT 966 3LQ 3LQ '4 '46 3LQ 3LQ 966 '4 3LQ '4 3LQ 966 3LQ '46 3LQ 1& 3LQ 966 3LQ '4 3LQ '4 3LQ 3LQ 966 '46 3LQ '4 3LQ 3LQ 966 '4 3LQ '46 3LQ 3LQ 966 '4 3LQ 3LQ 1& 3LQ 966 3LQ 1& 3LQ 1& 3LQ 966 &.( 3LQ 1&%$ 3LQ 3LQ 9''4 3LQ $ 3LQ $ 3LQ 9''4 3LQ 9'' ) 5 2 1 7 6 , ' ( % $ & . 6 , ' ( 3LQ '4 3LQ 966 3LQ 1& 3LQ '4 3LQ 966 3LQ '4 3LQ '0 3LQ 966 3LQ &. 3LQ '4 3LQ 966 3LQ '4 3LQ '0 3LQ 966 3LQ '4 3LQ '4 3LQ 966 3LQ 1& 3LQ '4 3LQ 966 3LQ 1& 3LQ 1& 3LQ 966 1& 3LQ 3LQ 9''4 3LQ 9'' 3LQ $ 3LQ $ 3LQ 9'' 3LQ $ 3LQ $ 3LQ 9'' 3LQ &. 3LQ $ 3LQ %$ 3LQ 5$6 3LQ 9''4 3LQ 1&$ 3LQ 966 3LQ '4 3LQ '0 3LQ 966 3LQ '4 3LQ '4 3LQ 966 3LQ 1& 3LQ '4 3LQ 966 3LQ '4 3LQ &. 3LQ 966 3LQ 1& '4 3LQ 3LQ 966 3LQ '4 3LQ '0 3LQ 966 3LQ '4 3LQ 9''6 3' 3LQ 6$ 3LQ 966 3LQ 1& $$3 3LQ 3LQ 9''4 3LQ &$6 1&6 3LQ 3LQ 9''4 '4 3LQ 3LQ 966 '46 3LQ '4 3LQ 3LQ 966 '4 3LQ '46 3LQ 3LQ 966 '4 3LQ '4 3LQ 3LQ 966 3LQ 1& '46 3LQ 3LQ 966 '4 3LQ '4 3LQ 3LQ 966 '46 3LQ '4 3LQ 3LQ 966 3LQ 6&/ 14 3LQ 966 3LQ '4 3LQ '0 3LQ 966 3LQ '4 3LQ '4 3LQ 966 3LQ 1& 3LQ &. 3LQ 966 3LQ '4 3LQ '4 3LQ 966 3LQ 1& 3LQ '4 3LQ 966 3LQ '4 3LQ '0 3LQ 966 3LQ '4 3LQ 1& 3LQ 966 3LQ 1& 3LQ 1& 3LQ 966 3LQ &.( 3LQ 1& 3LQ 9''4 3LQ $ 3LQ $ 3LQ 9''4 3LQ $ 3LQ &. 3LQ 9'' 3LQ 9'' 3LQ 9''4 3LQ 6 3LQ 2'7 3LQ 9'' 3LQ '4 3LQ 966 3LQ 1& 3LQ '4 3LQ 966 3LQ '4 3LQ '0 3LQ 966 3LQ '4 3LQ '4 3LQ 966 3LQ &. 3LQ '0 3LQ 966 3LQ '4 3LQ '4 3LQ 966 1& 3LQ 3LQ '4 3LQ 966 3LQ 6$ 033 7 Internet Data Sheet HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module FIGURE 2 Pin Configuration UDIMM ×72 (240 Pin) 95() 3LQ '4 3LQ 966 3LQ '46 3LQ '4 3LQ 966 3LQ '4 3LQ '46 3LQ 966 3LQ 1& 3LQ '4 3LQ 3LQ 966 '4 3LQ '46 3LQ 966 3LQ '4 3LQ '4 3LQ 966 3LQ '46 3LQ '4 3LQ 966 3LQ &% 3LQ '46 3LQ 966 3LQ &% 3LQ 3LQ 9''4 9'' 3LQ 1& 3LQ $ 3LQ 9'' 3LQ 3LQ $ 3LQ $ 966 3LQ 9'' 3LQ 9'' 3LQ %$ 3LQ :( 3LQ 3LQ 9''4 2'7 3LQ 966 3LQ '4 3LQ '46 3LQ 966 3LQ '4 3LQ '4 3LQ 966 3LQ '46 3LQ 966 3LQ 966 3LQ '4 3LQ 6$ 3LQ 966 3LQ '46 3LQ '4 3LQ 966 3LQ '4 3LQ '46 3LQ 966 3LQ '4 3LQ 6'$ 3LQ Rev. 1.0, 2006-10 10202006-L0SM-FEYT 966 3LQ 3LQ '4 '46 3LQ 3LQ 966 '4 3LQ '4 3LQ 66 9 3LQ '46 3LQ 3LQ 1& 3LQ 966 '4 3LQ '4 3LQ 3LQ 966 '46 3LQ 3LQ 966 3LQ 966 '4 3LQ '46 3LQ 3LQ 966 '4 3LQ 3LQ &% 3LQ 966 '46 3LQ 3LQ &% 3LQ 966 &.( 3LQ 1&%$ 3LQ 3LQ 9''4 3LQ $ 3LQ $ 3LQ 9''4 3LQ 9'' ) 5 2 1 7 6 , ' ( % $ & . 6 , ' ( 3LQ '4 3LQ 966 3LQ 1& 3LQ '4 3LQ 966 3LQ '4 3LQ '0 3LQ 1& 3LQ &. 3LQ '4 3LQ 966 3LQ '4 3LQ '0 3LQ 966 3LQ '4 3LQ '4 3LQ 966 3LQ 1& 3LQ '4 3LQ 966 3LQ &% 3LQ '0 966 3LQ 3LQ &% 3LQ 9''4 3LQ 9'' 3LQ $ 3LQ $ 3LQ 9'' 3LQ $ 3LQ $ 3LQ 9'' 3LQ &. 3LQ $ 3LQ %$ 3LQ 5$6 9''4 3LQ 3LQ 1&$ 3LQ 966 3LQ '4 3LQ '0 3LQ 966 3LQ '4 3LQ '4 3LQ 966 3LQ 1& 3LQ '4 3LQ 966 3LQ '4 3LQ &. 3LQ 966 3LQ 1& 3LQ '4 3LQ 966 3LQ '4 3LQ '0 3LQ 966 3LQ '4 3LQ 9''6 3' 3LQ 6$ 3LQ 966 3LQ 1& $$ 3 3LQ 3LQ 9''4 3LQ &$6 1&6 3LQ 3LQ 9''4 '4 3LQ 3LQ 966 '46 3LQ '4 3LQ 3LQ 966 '4 3LQ '46 3LQ 3LQ 966 '4 3LQ '4 3LQ 3LQ 966 3LQ 1& '46 3LQ 3LQ 966 '4 3LQ '4 3LQ 3LQ 966 '46 3LQ '4 3LQ 3LQ 966 3LQ 6&/ 15 3LQ 966 3LQ '4 3LQ '0 3LQ 966 3LQ '4 3LQ '4 3LQ 966 3LQ 1& 3LQ &. 3LQ 966 3LQ '4 3LQ '4 3LQ 966 3LQ 1& 3LQ '4 3LQ 966 3LQ '4 3LQ '0 3LQ 966 3LQ '4 3LQ &% 3LQ 966 3LQ 1& 3LQ &% 3LQ 966 3LQ &.( 3LQ 1& 3LQ 9''4 3LQ $ 3LQ $ 3LQ 9''4 3LQ $ 3LQ &. 3LQ 9'' 3LQ 9'' 3LQ 9''4 3LQ 6 3LQ 2'7 3LQ 9'' 3LQ '4 3LQ 966 3LQ 1& 3LQ '4 3LQ 966 3LQ '4 3LQ '0 3LQ 966 3LQ '4 3LQ '4 3LQ 966 3LQ &. 3LQ '0 3LQ 966 3LQ '4 3LQ '4 3LQ 966 1& 3LQ 3LQ '4 3LQ 966 3LQ 6$ 033 7 Internet Data Sheet HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module 3 Electrical Characteristics 3.1 Absolute Maximum Ratings 3.1.1 Absolute Maximum Ratings Caution is needed not to exceed absolute maximum ratings of the DRAM device listed in Table 8 at any time. TABLE 8 Absolute Maximum Ratings Symbol VDD VDDQ VDDL VIN, VOUT TSTG Parameter Rating Unit Note Min. Max. Voltage on VDD pin relative to VSS –1.0 +2.3 V 1) Voltage on VDDQ pin relative to VSS –0.5 +2.3 V 1)2) Voltage on VDDL pin relative to VSS –0.5 +2.3 V 1)2) Voltage on any pin relative to VSS –0.5 +2.3 V 1) °C 1)2) Storage Temperature –55 +100 1) When VDD and VDDQ and VDDL are less than 500 mV; VREF may be equal to or less than 300 mV. 2) Storage Temperature is the case surface temperature on the center/top side of the DRAM. Attention: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. TABLE 9 DRAM Component Operating Temperature Range Symbol TOPER Parameter Rating Operating Temperature Min. Max. 0 95 Unit Note °C 1)2)3)4) 1) Operating Temperature is the case surface temperature on the center / top side of the DRAM. 2) The operating temperature range are the temperatures where all DRAM specification will be supported. During operation, the DRAM case temperature must be maintained between 0 - 95 °C under all other specification parameters. 3) Above 85 °C the Auto-Refresh command interval has to be reduced to tREFI= 3.9 µs 4) When operating this product in the 85 °C to 95 °C TCASE temperature range, the High Temperature Self Refresh has to be enabled by setting EMR(2) bit A7 to “1”. When the High Temperature Self Refresh is enabled there is an increase of IDD6 by approximately 50% Rev. 1.0, 2006-10 10202006-L0SM-FEYT 16 Internet Data Sheet HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module 3.2 DC Operating Conditions TABLE 10 Operating Conditions Parameter Symbol Values Unit Min. Max. 0 +65 °C 0 +95 °C Storage Temperature TOPR TCASE TSTG – 50 +100 °C Barometric Pressure (operating & storage) PBar +69 +105 kPa Operating Humidity (relative) HOPR 10 90 % Operating temperature (ambient) DRAM Case Temperature Note 1)2)3)4) 5) 1) 2) 3) 4) DRAM Component Case Temperature is the surface temperature in the center on the top side of any of the DRAMs. Within the DRAM Component Case Temperature Range all DRAM specifications will be supported Above 85 °C DRAM Case Temperature the Auto-Refresh command interval has to be reduced to tREFI = 3.9 µs When operating this product in the 85 °C to 95 °C TCASE temperature range, the High Temperature Self Refresh has to be enabled by setting EMR(2) bit A7 to “1”. When the High Temperature Self Refresh is enabled there is an increase of IDD6 by approximately 50%. 5) Up to 3000 m. TABLE 11 Supply Voltage Levels and DC Operating Conditions Parameter Device Supply Voltage Output Supply Voltage Input Reference Voltage SPD Supply Voltage DC Input Logic High DC Input Logic Low Symbol VDD VDDQ VREF VDDSPD VIH(DC) VIL (DC) IL Values Unit Min. Typ. Max. 1.7 1.8 1.9 V 1.7 1.8 1.9 V 1) 0.49 × VDDQ 0.5 × VDDQ 0.51 × VDDQ V 2) 1.7 — 3.6 V VREF + 0.125 — V – 0.30 — VDDQ + 0.3 VREF – 0.125 V In / Output Leakage Current –5 — 5 µA 1) Under all conditions, VDDQ must be less than or equal to VDD 2) Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC).VREF is also expected to track noise in VDDQ. 3) Input voltage for any connector pin under test of 0 V ≤ VIN ≤ VDDQ + 0.3 V; all other pins at 0 V. Current is per pin Rev. 1.0, 2006-10 10202006-L0SM-FEYT Note 17 3) Internet Data Sheet HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module 3.3 Timing Characteristics All Speed grades faster than DDR2-DDR400B comply with DDR2-DDR400B timing specifications (tCK = 5ns with tRAS = 40ns). 3.3.1 Speed Grade Definitions Speed Grade Definition: Table 12 for DDR2–800; Table 13 for DDR2–667 and Table 14 for DDR2–533C TABLE 12 Speed Grade Definition Speed Bins for DDR2–800 Speed Grade DDR2–800D DDR2–800E QAG Sort Name –2.5F –2.5 CAS-RCD-RP latencies 5–5–5 6–6–6 Parameter Clock Frequency @ CL = 3 @ CL = 4 @ CL = 5 @ CL = 6 Row Active Time Row Cycle Time RAS-CAS-Delay Row Precharge Time Unit Note tCK Symbol Min. Max. Min. Max. — tCK tCK tCK tCK tRAS tRC tRCD tRP 5 8 5 8 ns 1)2)3)4) 3.75 8 3.75 8 ns 1)2)3)4) 2.5 8 3 8 ns 1)2)3)4) 2.5 8 2.5 8 ns 1)2)3)4) 45 70000 45 70000 ns 1)2)3)4)5) 57.5 — 60 — ns 1)2)3)4) 12.5 — 15 — ns 1)2)3)4) 12.5 — 15 — ns 1)2)3)4) 1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0) 2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode. 3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 4) The output timing reference voltage level is VTT. 5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI. Rev. 1.0, 2006-10 10202006-L0SM-FEYT 18 Internet Data Sheet HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module TABLE 13 Speed Grade Definition Speed Bins for DDR2–667 Speed Grade DDR2–667C DDR2–667D QAG Sort Name –3 –3S CAS-RCD-RP latencies 4–4–4 5–5–5 Parameter Clock Frequency @ CL = 3 @ CL = 4 @ CL = 5 Row Active Time Row Cycle Time RAS-CAS-Delay Row Precharge Time Unit Note tCK Symbol Min. Max. Min. Max. — tCK tCK tCK tRAS tRC tRCD tRP 5 8 5 8 ns 1)2)3)4) 3 8 3.75 8 ns 1)2)3)4) 3 8 3 8 ns 1)2)3)4) 45 70000 45 70000 ns 1)2)3)4)5) 57 — 60 — ns 1)2)3)4) 12 — 15 — ns 1)2)3)4) 12 — 15 — ns 1)2)3)4) 1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0) 2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode. 3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 4) The output timing reference voltage level is VTT. 5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI. Rev. 1.0, 2006-10 10202006-L0SM-FEYT 19 Internet Data Sheet HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module TABLE 14 Speed Grade Definition Speed Bins for DDR2–533C Speed Grade DDR2–533C QAG Sort Name –3.7 CAS-RCD-RP latencies 4–4–4 Parameter Clock Frequency @ CL = 3 @ CL = 4 @ CL = 5 Row Active Time Row Cycle Time RAS-CAS-Delay Row Precharge Time Unit Note tCK Symbol Min. Max. — tCK tCK tCK tRAS tRC tRCD tRP 5 8 ns 1)2)3)4) 3.75 8 ns 1)2)3)4) 3.75 8 ns 1)2)3)4) 45 70000 ns 1)2)3)4)5) 60 — ns 1)2)3)4) 15 — ns 1)2)3)4) 15 — ns 1)2)3)4) 1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0) 2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode. 3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 4) The output timing reference voltage level is VTT. 5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI. Rev. 1.0, 2006-10 10202006-L0SM-FEYT 20 Internet Data Sheet HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module 3.3.2 DRAM Component Timing Parameters DRAM Component Timing Parameters: Table 15 for DDR2–800; Table 16 for DDR2–667 and Table 17 for DDR2–533C. TABLE 15 DRAM Component Timing Parameter by Speed Grade - DDR2–800 Parameter Symbol DDR2–800 Unit Note1)2)3)4)5)6)7) 8) Min. Max. –400 +400 ps 9) –350 +350 ps 9) 0.48 0.52 tCK.AVG 10)11) 0.48 0.52 tCK.AVG 10)11) 2500 8000 ps 10)11) 50 –– ps 12)13)14) 125 –– ps 13)14)15) 0.6 — 0.35 — tCK.AVG tCK.AVG — tAC.MAX tAC.MAX ps 9)16) ps 9)16) tAC.MAX ps 9)16) — 200 ps 17) Min(tCH.ABS, tCL.ABS) __ ps 18) — 300 ps 19) DQ/DQS output hold time from DQS tQHS tQH tHP – tQHS — ps 20) Write command to DQS associated clock edges WL RL – 1 DQ output access time from CK / CK DQS output access time from CK / CK Average clock high pulse width tAC tDQSCK tCH.AVG tCL.AVG Average clock period tCK.AVG DQ and DM input setup time tDS.BASE DQ and DM input hold time tDH.BASE Control & address input pulse width for each input tIPW DQ and DM input pulse width for each input tDIPW Data-out high-impedance time from CK / CK tHZ DQS/DQS low-impedance time from CK / CK tLZ.DQS DQ low impedance time from CK/CK tLZ.DQ DQS-DQ skew for DQS & associated DQ signals tDQSQ CK half pulse width tHP Average clock low pulse width DQ hold skew factor tAC.MIN 2 x tAC.MIN nCK 21) DQS latching rising transition to associated clock tDQSS edges – 0.25 + 0.25 tCK.AVG tDQSH DQS input low pulse width tDQSL DQS falling edge to CK setup time tDSS DQS falling edge hold time from CK tDSH Write postamble tWPST Write preamble tWPRE Address and control input setup time tIS.BASE Address and control input hold time tIH.BASE Read preamble tRPRE Read postamble tRPST CAS to CAS command delay tCCD Write recovery time tWR Auto-Precharge write recovery + precharge time tDAL Internal write to read command delay tWTR 0.35 — 0.35 — 0.2 — 0.2 — 0.4 0.6 0.35 — tCK.AVG tCK.AVG tCK.AVG tCK.AVG tCK.AVG tCK.AVG 175 — ps 22)23) 250 — ps 23)24) 0.9 1.1 25)26) 0.4 0.6 tCK.AVG tCK.AVG 2 — nCK 15 — ns 1) WR + tnRP — nCK 28)29) 7.5 — ns 1)30) DQS input high pulse width Rev. 1.0, 2006-10 10202006-L0SM-FEYT 21 21) 21) 25)27) Internet Data Sheet HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module Parameter Symbol DDR2–800 Unit Note1)2)3)4)5)6)7) 8) Min. Max. tRTP tXSNR tXSRD tXP 7.5 — ns 1) tRFC +10 — ns 1) 200 — nCK 2 — nCK tXARD tXARDS 2 — nCK 8 – AL — nCK CKE minimum pulse width ( high and low pulse width) tCKE 3 — nCK Mode register set command cycle time tMRD tMOD tOIT tDELAY 2 — nCK 0 12 ns 1) 0 12 ns 1) tIS + tCK .AVG + tIH –– ns Internal Read to Precharge command delay Exit self-refresh to a non-read command Exit self-refresh to read command Exit precharge power-down to any valid command (other than NOP or Deselect) Exit power down to read command Exit active power-down mode to read command (slow exit, lower power) MRS command to ODT update delay OCD drive mode output delay Minimum time clocks remain ON after CKE asynchronously drops LOW 31) 1) For details and notes see the relevant Qimonda component data sheet 2) VDDQ = 1.8 V ± 0.1V; VDD = 1.8 V ± 0.1 V. See notes 5)6)7)8) 3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue. 4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. 5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode. 6) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 7) The output timing reference voltage level is VTT. 8) New units, ‘tCK.AVG‘ and ‘nCK‘, are introduced in DDR2–667 and DDR2–800. Unit ‘tCK.AVG‘ represents the actual tCK.AVG of the input clock under operation. Unit ‘nCK‘ represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2–400 and DDR2–533, ‘tCK‘ is used for both concepts. Example: tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command may be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x tCK.AVG + tERR.2PER(Min). 9) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(6-10per) of the input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tERR(6-10PER).MIN = – 272 ps and tERR(6- 10PER).MAX = + 293 ps, then tDQSCK.MIN(DERATED) = tDQSCK.MIN – tERR(6-10PER).MAX = – 400 ps – 293 ps = – 693 ps and tDQSCK.MAX(DERATED) = tDQSCK.MAX – tERR(6-10PER).MIN = 400 ps + 272 ps = + 672 ps. Similarly, tLZ.DQ for DDR2–667 derates to tLZ.DQ.MIN(DERATED) = - 900 ps – 293 ps = – 1193 ps and tLZ.DQ.MAX(DERATED) = 450 ps + 272 ps = + 722 ps. (Caution on the MIN/MAX usage!) 10) Input clock jitter spec parameter. These parameters are referred to as 'input clock jitter spec parameters' and these parameters apply to DDR2–667 and DDR2–800 only. The jitter specified is a random jitter meeting a Gaussian distribution. 11) These parameters are specified per their average values, however it is understood that the relationship between the average timing and the absolute instantaneous timing holds all the times (min. and max of SPEC values are to be used for calculations ). 12) Input waveform timing tDS with differential data strobe enabled MR[bit10] = 0, is referenced from the input signal crossing at the VIH.AC level to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the VIL.AC level to the differential data strobe crosspoint for a falling signal applied to the device under test. DQS, DQS signals must be monotonic between Vil(DC)MAX and Vih(DC)MIN. See Figure 4. 13) If tDS or tDH is violated, data corruption may occur and the data must be re-written with valid data before a valid READ can be executed. 14) These parameters are measured from a data signal ((L/U)DM, (L/U)DQ0, (L/U)DQ1, etc.) transition edge to its respective data strobe signal ((L/U/R)DQS / DQS) crossing. 15) Input waveform timing tDH with differential data strobe enabled MR[bit10] = 0, is referenced from the differential data strobe crosspoint to the input signal crossing at the VIH.DC level for a falling signal and from the differential data strobe crosspoint to the input signal crossing at the VIL.DC level for a rising signal applied to the device under test. DQS, DQS signals must be monotonic between VIL.DC.MAX and VIH.DC.MIN. See Figure 4. Rev. 1.0, 2006-10 10202006-L0SM-FEYT 22 Internet Data Sheet HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module 16) tHZ and tLZ transitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level which specifies when the device output is no longer driving (tHZ), or begins driving (tLZ) . 17) tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output slew rate mismatch between DQS / DQS and associated DQ in any given cycle. 18) tHP is the minimum of the absolute half period of the actual input clock. tHP is an input parameter but not an input specification parameter. It is used in conjunction with tQHS to derive the DRAM output timing tQH. The value to be used for tQH calculation is determined by the following equation; tHP = MIN (tCH.ABS, tCL.ABS), where, tCH.ABS is the minimum of the actual instantaneous clock high time; tCL.ABS is the minimum of the actual instantaneous clock low time. 19) tQHS accounts for: 1) The pulse duration distortion of on-chip clock circuits, which represents how well the actual tHP at the input is transferred to the output; and 2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition, both of which are independent of each other, due to data pin skew, output pattern effects, and pchannel to n-channel variation of the output drivers. 20) tQH = tHP – tQHS, where: tHP is the minimum of the absolute half period of the actual input clock; and tQHS is the specification value under the max column. {The less half-pulse width distortion present, the larger the tQH value is; and the larger the valid data eye will be.} Examples: 1) If the system provides tHP of 1315 ps into a DDR2–667 SDRAM, the DRAM provides tQH of 975 ps minimum. 2) If the system provides tHP of 1420 ps into a DDR2–667 SDRAM, the DRAM provides tQH of 1080 ps minimum. 21) These parameters are measured from a data strobe signal ((L/U/R)DQS / DQS) crossing to its respective clock signal (CK / CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT.PER, tJIT.CC, etc.), as these are relative to the clock signal crossing. That is, these parameters should be met whether clock jitter is present or not. 22) Input waveform timing is referenced from the input signal crossing at the VIH.AC level for a rising signal and VIL.AC for a falling signal applied to the device under test. See Figure 5. 23) These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition edge to its respective clock signal (CK / CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT.PER, tJIT.CC, etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these parameters should be met whether clock jitter is present or not. 24) Input waveform timing is referenced from the input signal crossing at the VIL.DC level for a rising signal and VIH.DC for a falling signal applied to the device under test. See Figure 5. 25) tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving (tRPST), or begins driving (tRPRE). Figure 3 shows a method to calculate these points when the device is no longer driving (tRPST), or begins driving (tRPRE) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is consistent. 26) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT.PER of the input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tJIT.PER.MIN = – 72 ps and tJIT.PER.MAX = + 93 ps, then tRPRE.MIN(DERATED) = tRPRE.MIN + tJIT.PER.MIN = 0.9 x tCK.AVG – 72 ps = + 2178 ps and tRPRE.MAX(DERATED) = tRPRE.MAX + tJIT.PER.MAX = 1.1 x tCK.AVG + 93 ps = + 2843 ps. (Caution on the MIN/MAX usage!). 27) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT.DUTY of the input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tJIT.DUTY.MIN = – 72 ps and tJIT.DUTY.MAX = + 93 ps, then tRPST.MIN(DERATED) = tRPST.MIN + tJIT.DUTY.MIN = 0.4 x tCK.AVG – 72 ps = + 928 ps and tRPST.MAX(DERATED) = tRPST.MAX + tJIT.DUTY.MAX = 0.6 x tCK.AVG + 93 ps = + 1592 ps. (Caution on the MIN/MAX usage!). 28) DAL = WR + RU{tRP(ns) / tCK(ns)}, where RU stands for round up. WR refers to the tWR parameter stored in the MRS. For tRP, if the result of the division is not already an integer, round up to the next highest integer. tCK refers to the application clock period. Example: For DDR2–533 at tCK = 3.75 ns with tWR programmed to 4 clocks. tDAL = 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks. 29) tDAL.nCK = WR [nCK] + tnRP.nCK = WR + RU{tRP [ps] / tCK.AVG[ps] }, where WR is the value programmed in the EMR. 30) tWTR is at lease two clocks (2 x tCK) independent of operation frequency. 31) tCKE.MIN of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during the time period of tIS + 2 x tCK + tIH. Rev. 1.0, 2006-10 10202006-L0SM-FEYT 23 Internet Data Sheet HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module TABLE 16 DRAM Component Timing Parameter by Speed Grade - DDR2–667 Parameter Symbol DDR2–667 Unit Note1)2)3)4)5)6)7) 8) Min. Max. –450 +450 ps 9) –400 +400 ps 9) 0.48 0.52 tCK.AVG 10)11) 0.48 0.52 tCK.AVG 10)11) 3000 8000 ps 100 –– ps 12)13)14) 175 –– ps 13)14)15) 0.6 — 0.35 — tCK.AVG tCK.AVG — ps 9)16) tAC.MIN 2 x tAC.MIN tAC.MAX tAC.MAX tAC.MAX ps 9)16) ps 9)16) — 240 ps 17) Min(tCH.ABS, tCL.ABS) __ ps 18) — 340 ps 19) DQ/DQS output hold time from DQS tQHS tQH tHP – tQHS — ps 20) Write command to DQS associated clock edges WL RL–1 DQ output access time from CK / CK DQS output access time from CK / CK Average clock high pulse width tAC tDQSCK tCH.AVG tCL.AVG Average clock period tCK.AVG DQ and DM input setup time tDS.BASE DQ and DM input hold time tDH.BASE Control & address input pulse width for each input tIPW DQ and DM input pulse width for each input tDIPW Data-out high-impedance time from CK / CK tHZ DQS/DQS low-impedance time from CK / CK tLZ.DQS DQ low impedance time from CK/CK tLZ.DQ DQS-DQ skew for DQS & associated DQ signals tDQSQ CK half pulse width tHP Average clock low pulse width DQ hold skew factor nCK DQS latching rising transition to associated clock tDQSS edges – 0.25 + 0.25 tCK.AVG DQS input high pulse width tDQSH tDQSL DQS falling edge to CK setup time tDSS DQS falling edge hold time from CK tDSH Write postamble tWPST Write preamble tWPRE Address and control input setup time tIS.BASE Address and control input hold time tIH.BASE Read preamble tRPRE Read postamble tRPST CAS to CAS command delay tCCD Write recovery time tWR Auto-Precharge write recovery + precharge time tDAL Internal write to read command delay tWTR Internal Read to Precharge command delay tRTP Exit self-refresh to a non-read command tXSNR Exit self-refresh to read command tXSRD 0.35 — DQS input low pulse width 0.35 — 0.2 — 0.2 — 0.4 0.6 Rev. 1.0, 2006-10 10202006-L0SM-FEYT 24 21) 0.35 — tCK.AVG tCK.AVG tCK.AVG tCK.AVG tCK.AVG tCK.AVG 200 — ps 22)23) 275 — ps 23)24) 0.9 1.1 25)26) 0.4 0.6 tCK.AVG tCK.AVG 2 — nCK 15 — ns 1) WR + tnRP — nCK 28)29) 7.5 — ns 1)30) 7.5 — ns 1) tRFC +10 — ns 1) 200 — nCK 21) 21) 25)27) Internet Data Sheet HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module Parameter Symbol DDR2–667 Unit Note1)2)3)4)5)6)7) 8) Min. Max. — Exit precharge power-down to any valid command (other than NOP or Deselect) tXP 2 Exit power down to read command tXARD tXARDS 2 — nCK 7 – AL — nCK CKE minimum pulse width ( high and low pulse width) tCKE 3 — nCK Mode register set command cycle time tMRD tMOD tOIT tDELAY 2 — nCK 0 12 ns 1) 0 12 ns 1) tIS + tCK .AVG + tIH –– ns Exit active power-down mode to read command (slow exit, lower power) MRS command to ODT update delay OCD drive mode output delay Minimum time clocks remain ON after CKE asynchronously drops LOW nCK 31) 1) For details and notes see the relevant Qimonda component data sheet 2) VDDQ = 1.8 V ± 0.1V; VDD = 1.8 V ± 0.1 V. See notes 5)6)7)8) 3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue. 4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. 5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode. 6) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 7) The output timing reference voltage level is VTT. 8) New units, ‘tCK.AVG‘ and ‘nCK‘, are introduced in DDR2–667 and DDR2–800. Unit ‘tCK.AVG‘ represents the actual tCK.AVG of the input clock under operation. Unit ‘nCK‘ represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2–400 and DDR2–533, ‘tCK‘ is used for both concepts. Example: tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command may be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x tCK.AVG + tERR.2PER(Min). 9) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(6-10per) of the input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tERR(6-10PER).MIN = – 272 ps and tERR(6- 10PER).MAX = + 293 ps, then tDQSCK.MIN(DERATED) = tDQSCK.MIN – tERR(6-10PER).MAX = – 400 ps – 293 ps = – 693 ps and tDQSCK.MAX(DERATED) = tDQSCK.MAX – tERR(6-10PER).MIN = 400 ps + 272 ps = + 672 ps. Similarly, tLZ.DQ for DDR2–667 derates to tLZ.DQ.MIN(DERATED) = - 900 ps – 293 ps = – 1193 ps and tLZ.DQ.MAX(DERATED) = 450 ps + 272 ps = + 722 ps. (Caution on the MIN/MAX usage!) 10) Input clock jitter spec parameter. These parameters are referred to as 'input clock jitter spec parameters' and these parameters apply to DDR2–667 and DDR2–800 only. The jitter specified is a random jitter meeting a Gaussian distribution. 11) These parameters are specified per their average values, however it is understood that the relationship between the average timing and the absolute instantaneous timing holds all the times (min. and max of SPEC values are to be used for calculations ). 12) Input waveform timing tDS with differential data strobe enabled MR[bit10] = 0, is referenced from the input signal crossing at the VIH.AC level to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the VIL.AC level to the differential data strobe crosspoint for a falling signal applied to the device under test. DQS, DQS signals must be monotonic between Vil(DC)MAX and Vih(DC)MIN. See Figure 4. 13) If tDS or tDH is violated, data corruption may occur and the data must be re-written with valid data before a valid READ can be executed. 14) These parameters are measured from a data signal ((L/U)DM, (L/U)DQ0, (L/U)DQ1, etc.) transition edge to its respective data strobe signal ((L/U/R)DQS / DQS) crossing. 15) Input waveform timing tDH with differential data strobe enabled MR[bit10] = 0, is referenced from the differential data strobe crosspoint to the input signal crossing at the VIH.DC level for a falling signal and from the differential data strobe crosspoint to the input signal crossing at the VIL.DC level for a rising signal applied to the device under test. DQS, DQS signals must be monotonic between VIL.DC.MAX and VIH.DC.MIN. See Figure 4. 16) tHZ and tLZ transitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level which specifies when the device output is no longer driving (tHZ), or begins driving (tLZ) . 17) tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output slew rate mismatch between DQS / DQS and associated DQ in any given cycle. Rev. 1.0, 2006-10 10202006-L0SM-FEYT 25 Internet Data Sheet HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module 18) tHP is the minimum of the absolute half period of the actual input clock. tHP is an input parameter but not an input specification parameter. It is used in conjunction with tQHS to derive the DRAM output timing tQH. The value to be used for tQH calculation is determined by the following equation; tHP = MIN (tCH.ABS, tCL.ABS), where, tCH.ABS is the minimum of the actual instantaneous clock high time; tCL.ABS is the minimum of the actual instantaneous clock low time. 19) tQHS accounts for: 1) The pulse duration distortion of on-chip clock circuits, which represents how well the actual tHP at the input is transferred to the output; and 2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition, both of which are independent of each other, due to data pin skew, output pattern effects, and pchannel to n-channel variation of the output drivers. 20) tQH = tHP – tQHS, where: tHP is the minimum of the absolute half period of the actual input clock; and tQHS is the specification value under the max column. {The less half-pulse width distortion present, the larger the tQH value is; and the larger the valid data eye will be.} Examples: 1) If the system provides tHP of 1315 ps into a DDR2–667 SDRAM, the DRAM provides tQH of 975 ps minimum. 2) If the system provides tHP of 1420 ps into a DDR2–667 SDRAM, the DRAM provides tQH of 1080 ps minimum. 21) These parameters are measured from a data strobe signal ((L/U/R)DQS / DQS) crossing to its respective clock signal (CK / CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT.PER, tJIT.CC, etc.), as these are relative to the clock signal crossing. That is, these parameters should be met whether clock jitter is present or not. 22) Input waveform timing is referenced from the input signal crossing at the VIH.AC level for a rising signal and VIL.AC for a falling signal applied to the device under test. See Figure 5. 23) These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition edge to its respective clock signal (CK / CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT.PER, tJIT.CC, etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these parameters should be met whether clock jitter is present or not. 24) Input waveform timing is referenced from the input signal crossing at the VIL.DC level for a rising signal and VIH.DC for a falling signal applied to the device under test. See Figure 5. 25) tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving (tRPST), or begins driving (tRPRE). Figure 3 shows a method to calculate these points when the device is no longer driving (tRPST), or begins driving (tRPRE) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is consistent. 26) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT.PER of the input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tJIT.PER.MIN = – 72 ps and tJIT.PER.MAX = + 93 ps, then tRPRE.MIN(DERATED) = tRPRE.MIN + tJIT.PER.MIN = 0.9 x tCK.AVG – 72 ps = + 2178 ps and tRPRE.MAX(DERATED) = tRPRE.MAX + tJIT.PER.MAX = 1.1 x tCK.AVG + 93 ps = + 2843 ps. (Caution on the MIN/MAX usage!). 27) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT.DUTY of the input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tJIT.DUTY.MIN = – 72 ps and tJIT.DUTY.MAX = + 93 ps, then tRPST.MIN(DERATED) = tRPST.MIN + tJIT.DUTY.MIN = 0.4 x tCK.AVG – 72 ps = + 928 ps and tRPST.MAX(DERATED) = tRPST.MAX + tJIT.DUTY.MAX = 0.6 x tCK.AVG + 93 ps = + 1592 ps. (Caution on the MIN/MAX usage!). 28) DAL = WR + RU{tRP(ns) / tCK(ns)}, where RU stands for round up. WR refers to the tWR parameter stored in the MRS. For tRP, if the result of the division is not already an integer, round up to the next highest integer. tCK refers to the application clock period. Example: For DDR2–533 at tCK = 3.75 ns with tWR programmed to 4 clocks. tDAL = 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks. 29) tDAL.nCK = WR [nCK] + tnRP.nCK = WR + RU{tRP [ps] / tCK.AVG[ps] }, where WR is the value programmed in the EMR. 30) tWTR is at lease two clocks (2 x tCK) independent of operation frequency. 31) tCKE.MIN of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during the time period of tIS + 2 x tCK + tIH. FIGURE 3 Method for calculating transitions and endpoint VOH - x mV VTT + 2x mV VOH - 2x mV VTT + x mV tLZ tHZ tRPRE begin point tRPST end point VOL + 2x mV VTT - x mV VOL + x mV VTT - 2x mV T1 T2 T1 T2 tHZ,tRPST end point = 2*T1-T2 Rev. 1.0, 2006-10 10202006-L0SM-FEYT tLZ,tRPRE begin point = 2*T1-T2 26 Internet Data Sheet HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module FIGURE 4 Differential input waveform timing - tDS and tDS DQS DQS tDS tDH tDS tDH VDDQ VIH(ac) min VIH(dc) min VREF(dc) VIL(dc) max VIL(ac) max VSS FIGURE 5 Differential input waveform timing - tlS and tlH CK CK tIS tIH tIS tIH VDDQ VIH(ac) min VIH(dc) min VREF(dc) VIL(dc) max VIL(ac) max VSS Rev. 1.0, 2006-10 10202006-L0SM-FEYT 27 Internet Data Sheet HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module TABLE 17 DRAM Component Timing Parameter by Speed Grade - DDR2–533 Parameter Symbol DDR2–533 Unit Note1)2)3)4)5) 6)7) Min. Max. tAC tCCD tCH tCKE tCL tDAL –500 +500 ps 2 — 0.45 0.55 3 — 0.45 0.55 WR + tRP — tCK tCK tCK tCK tCK Minimum time clocks remain ON after CKE asynchronously drops LOW tDELAY tIS + tCK + tIH –– ns 9) DQ and DM input hold time (differential data strobe) tDH(base) 225 –– ps 10) –25 — ps 11) tDIPW tDQSCK tDQSL,H tDQSQ 0.35 — tCK –450 +450 ps 0.35 — tCK — 300 ps tDQSS tDS(base) – 0.25 + 0.25 tCK 100 — ps 11) –25 — ps 11) tDSH 0.2 — tCK DQS falling edge to CK setup time (write cycle) tDSS 0.2 — tCK DQ output access time from CK / CK CAS A to CAS B command period CK, CK high-level width CKE minimum high and low pulse width CK, CK low-level width Auto-Precharge write recovery + precharge time DQ and DM input hold time (single ended data tDH1(base) strobe) DQ and DM input pulse width (each input) DQS output access time from CK / CK DQS input low (high) pulse width (write cycle) DQS-DQ skew (for DQS & associated DQ signals) Write command to 1st DQS latching transition DQ and DM input setup time (differential data strobe) DQ and DM input setup time (single ended data tDS1(base) strobe) DQS falling edge hold time from CK (write cycle) Clock half period Data-out high-impedance time from CK / CK Address and control input hold time Address and control input pulse width (each input) Address and control input setup time DQ low-impedance time from CK / CK DQS low-impedance from CK / CK Mode register set command cycle time OCD drive mode output delay Data output hold time from DQS Data hold skew factor Rev. 1.0, 2006-10 10202006-L0SM-FEYT tHP tHZ tIH(base) tIPW 28 11) 12) MIN. (tCL, tCH) tIS(base) tLZ(DQ) tLZ(DQS) tMRD tOIT tQH tQHS 8)18) — tAC.MAX ps 13) 375 — ps 11) 0.6 — tCK 250 — ps 11) 2 × tAC.MIN ps 14) tAC.MIN tAC.MAX tAC.MAX ps 14) 2 — tCK 0 12 ns tHP –tQHS — — 400 ps Internet Data Sheet HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module Parameter Symbol DDR2–533 Unit Note1)2)3)4)5) 6)7) Average periodic refresh Interval tREFI Min. Max. — 7.8 µs 14)15) — 3.9 µs 16)18) 17) Auto-Refresh to Active/Auto-Refresh command period tRFC 105 — ns Precharge-All (4 banks) command period tRP tRP tRPRE tRPST tRRD tRP + 1tCK — ns 15 + 1tCK — ns 0.9 1.1 14) 0.40 0.60 tCK tCK Precharge-All (8 banks) command period Read preamble Read postamble Active bank A to Active bank B command period 7.5 — ns 10 — ns 16)20) tRTP tWPRE tWPST tWR 7.5 — ns 0.25 x tCK — 0.40 0.60 tCK tCK 15 — ns Write recovery time for write with AutoPrecharge WR tWR/tCK Internal Write to Read command delay tWTR tXARD 7.5 Exit active power-down mode to Read command (slow exit, lower power) Internal Read to Precharge command delay Write preamble Write postamble Write recovery time for write without AutoPrecharge 14) 14)18) 19) tCK 20) — ns 21) 2 — tCK 22) tXARDS 6 – AL — tCK 22) Exit precharge power-down to any valid command (other than NOP or Deselect) tXP 2 — tCK Exit Self-Refresh to non-Read command tXSNR tXSRD tRFC +10 — ns 200 — tCK Exit power down to any valid command (other than NOP or Deselect) Exit Self-Refresh to Read command 1) For details and notes see the relevant Qimonda component data sheet 2) VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ±0.1 V. See notes 5)6)7)8) 3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue. 4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. 5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS/ RDQS, input reference level is the crosspoint when in differential strobe mode. 6) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 7) The output timing reference voltage level is VTT. 8) For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to the WR parameter stored in the MR. 9) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode. 10) For timing definition, refer to the Component data sheet. 11) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output Slew Rate mis-match between DQS / DQS and associated DQ in any given cycle. 12) MIN (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH). Rev. 1.0, 2006-10 10202006-L0SM-FEYT 29 Internet Data Sheet HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module 13) The tHZ, tRPST and tLZ, tRPRE parameters are referenced to a specific voltage level, which specify when the device output is no longer driving (tHZ, tRPST), or begins driving (tLZ, tRPRE). tHZ and tLZ transitions occur in the same access time windows as valid data transitions.These parameters are verified by design and characterization, but not subject to production test. 14) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range between 85 °C and 95 °C. 15) 0 °C≤ TCASE ≤ 85 °C 16) 85 °C < TCASE ≤ 95 °C 17) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device. 18) The tRRD timing parameter depends on the page size of the DRAM organization. See Table 2 “Ordering Information for RoHS Compliant Products” on Page 4. 19) The maximum limit for the tWPST parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 20) WR must be programmed to fulfill the minimum requirement for the tWR timing parameter, where WRMIN[cycles] = tWR(ns)/tCK(ns) rounded up to the next integer value. tDAL = WR + (tRP/tCK). For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to the WR parameter stored in the MRS. 21) Minimum tWTR is two clocks when operating the DDR2-SDRAM at frequencies ≤ 200 ΜΗz. 22) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard active powerdown mode” (MR, A12 = “0”) a fast power-down exit timing tXARD can be used. In “low active power-down mode” (MR, A12 =”1”) a slow power-down exit timing tXARDS has to be satisfied. 3.3.3 ODT AC Electrical Characteristics ODT AC Character. & Operating Conditions: Table 18 for DDR2–667 & DDR2–800 and Table 19 for DDR2–533 & DDR2–400 TABLE 18 ODT AC Character. and Operating Conditions for DDR2-667 & DDR2-800 Symbol tAOND tAON tAONPD tAOFD tAOF tAOFPD tANPD tAXPD Parameter / Condition Values Unit Note Min. Max. ODT turn-on delay 2 2 nCK 1) ODT turn-on tAC.MAX + 0.7 ns 2 tCK + tAC.MAX + 1 ns ns 1)2) ODT turn-on (Power-Down Modes) tAC.MIN tAC.MIN + 2 ns ns 1) ODT turn-off delay 2.5 2.5 nCK 1) ODT turn-off tAC.MAX + 0.6 ns 2.5 tCK + tAC.MAX + 1 ns ns 1)3) ODT turn-off (Power-Down Modes) tAC.MIN tAC.MIN + 2 ns ns 1) ODT to Power Down Mode Entry Latency 3 — nCK 1) 1) ODT Power Down Exit Latency 8 — nCK 1) New units, 'tCK.AVG' and 'nCK', are introduced in DDR2-667 and DDR2-800. Unit 'tCK.AVG' represents the actual tCK.AVG of the input clock under operation. Unit 'nCK' represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2-400 and DDR2-533, 'tCK' is used for both concepts. Example: tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command may be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 × tCK.AVG+ tEPR.2PER(MIN). 2) ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the ODT resistance is fully on. Both are measured from tAOND, which is interpreted differently per speed bin. For DDR2-667/800, tAOND is 2 clock cycles after the clock edge that registered a first ODT HIGH counting the actual input clock edges. 3) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD. Both are measured from tAOFD, which is interpreted differently per speed bin. For DDR2-667/800,if tCK.AVG = 3 ns is assumed, tAOFD= 1.5 ns (0.5 × 3 ns) after the second trailing clock edge counting from the clock edge that registered a first ODT LOW and by counting the actual input clock edge. Rev. 1.0, 2006-10 10202006-L0SM-FEYT 30 Internet Data Sheet HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module TABLE 19 ODT AC Character. and Operating Conditions for DDR2-533 & DDR2-400 Symbol tAOND tAON tAONPD tAOFD tAOF tAOFPD tANPD tAXPD Parameter / Condition Values Unit Min. Max. ODT turn-on delay 2 2 tCK ODT turn-on tAC.MAX + 1 ns 2 tCK + tAC.MAX + 1 ns ns ODT turn-on (Power-Down Modes) tAC.MIN tAC.MIN + 2 ns ODT turn-off delay 2.5 2.5 tCK ODT turn-off tAC.MAX + 0.6 ns 2.5 tCK + tAC.MAX + 1 ns ns ODT turn-off (Power-Down Modes) tAC.MIN tAC.MIN + 2 ns ODT to Power Down Mode Entry Latency 3 — ODT Power Down Exit Latency 8 — tCK tCK Note 1) ns 2) ns 1) ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the ODT resistance is fully on. Both are measured from tAOND, which is interpreted differently per speed bin. For DDR2-400/533, tAOND is 10 ns (= 2 x 5 ns) after the clock edge that registered a first ODT HIGH if tCK = 5 ns. 2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD. Both are measured from tAOFD, which is interpreted differently per speed bin. For DDR2-400/533, tAOFD is 12.5 ns (= 2.5 x 5 ns) after the clock edge that registered a first ODT HIGH if tCK = 5 ns. Rev. 1.0, 2006-10 10202006-L0SM-FEYT 31 Internet Data Sheet HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module 3.4 IDD Specifications and Conditions List of tables defining IDD Specifications and Conditions. • Table 20 “IDD Measurement Conditions” on Page 32 • Table 21 “Definitions for IDD” on Page 33 • Table 22 “I DD Specification for HYS[64/72]T[32/64/128][0/9]xxEU-25F-B2” on Page 34 • Table 23 “I DD Specification for HYS[64/72]T[32/64/128][0/9]xxEU-2.5-B2” on Page 35 • Table 24 “I DD Specification for HYS[64/72]T[32/64/128][0/9]xxEU-3-B2” on Page 36 • Table 25 “I DD Specification for HYS[64/72]T[32/64/128][0/9]xxEU-3S-B2” on Page 37 • Table 26 “I DD Specification for HYS[64/72]T[32/64/128][0/9]xxEU-3.7-B2” on Page 38 TABLE 20 IDD Measurement Conditions Parameter Symbol Note 1)2)3)4)5) Operating Current 0 IDD0 One bank Active - Precharge; tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN, CKE is HIGH, CS is HIGH between valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING. Operating Current 1 One bank Active - Read - Precharge; IOUT = 0 mA, BL = 4, tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN, tRCD = tRCD.MIN, AL = 0, CL = CLMIN; CKE is HIGH, CS is HIGH between valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING. IDD1 6) Precharge Standby Current IDD2N All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are SWITCHING, Databus inputs are SWITCHING. Precharge Power-Down Current Other control and address inputs are STABLE, Data bus inputs are FLOATING. IDD2P Precharge Quiet Standby Current All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are STABLE, Data bus inputs are FLOATING. IDD2Q Active Standby Current Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN; tRAS = tRAS.MAX, tRP = tRP.MIN; CKE is HIGH, CS is HIGH between valid commands. Address inputs are SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0 mA. IDD3N Active Power-Down Current IDD3P(0) All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs are FLOATING. MRS A12 bit is set to LOW (Fast Power-down Exit); Active Power-Down Current IDD3P(1) All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs are FLOATING. MRS A12 bit is set to HIGH (Slow Power-down Exit); Operating Current - Burst Read IDD4R All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCKMIN; tRAS = tRASMAX; tRP = tRPMIN; CKE is HIGH, CS is HIGH between valid commands; Address inputs are SWITCHING; Data bus inputs are SWITCHING; IOUT = 0mA. Operating Current - Burst Write All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN; tRAS = tRAS.MAX., tRP = tRP.MAX; CKE is HIGH, CS is HIGH between valid commands. Address inputs are SWITCHING; Data Bus inputs are SWITCHING; Rev. 1.0, 2006-10 10202006-L0SM-FEYT 32 IDD4W 6) Internet Data Sheet HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module Parameter Symbol Note 1)2)3)4)5) Burst Refresh Current tCK = tCK.MIN., Refresh command every tRFC = tRFC.MIN interval, CKE is HIGH, CS is HIGH between valid commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING. IDD5B Distributed Refresh Current tCK = tCK.MIN., Refresh command every tRFC = tREFI interval, CKE is LOW and CS is HIGH between valid commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING. IDD5D Self-Refresh Current IDD6 CKE ≤ 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are FLOATING, Data bus inputs are FLOATING. IDD6 current values are guaranteed up to TCASE of 85 °C max. All Bank Interleave Read Current IDD7 All banks are being interleaved at minimum tRC without violating tRRD using a burst length of 4. Control and address bus inputs are STABLE during DESELECTS. Iout = 0 mA. 1) VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ± 0.1 V 2) IDD specifications are tested after the device is properly initialized and IDD parameter are specified with ODT disabled. 3) Definitions for IDD see Table 21 4) For two rank modules: for all active current measurements the other rank is in Precharge Power-Down Mode IDD2P 6) 5) For details and notes see the relevant Qimonda component data sheet 6) IDD1, IDD4R and IDD7 current measurements are defined with the outputs disabled (IOUT = 0 mA). To achieve this on module level the output buffers can be disabled using an EMRS(1) (Extended Mode Register Command) by setting A12 bit to HIGH. TABLE 21 Definitions for IDD Parameter Description LOW VIN ≤ VIL(ac).MAX, HIGH is defined as VIN ≥ VIH(ac).MIN STABLE Inputs are stable at a HIGH or LOW level FLOATING Inputs are VREF = VDDQ /2 SWITCHING Inputs are changing between HIGH and LOW every other clock (once per 2 cycles) for address and control signals, and inputs changing between HIGH and LOW every other data transfer (once per cycle) for DQ signals not including mask or strobes Rev. 1.0, 2006-10 10202006-L0SM-FEYT 33 Internet Data Sheet HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module TABLE 22 IDD Specification for HYS[64/72]T[32/64/128][0/9]xxEU-25F-B2 870 980 mA 2) 459 820 920 mA 3) 72 81 140 160 mA 3) 180 360 405 720 810 mA 3) 240 480 540 960 1080 mA 3) 156 312 351 620 700 mA 3)4) 52 104 117 210 230 mA 3)5) 720 1240 1395 1310 1480 mA 2) 800 1240 1395 1310 1480 mA 2) 580 1160 1305 1230 1390 mA 2) 44 88 99 180 200 mA 3)6) 36 72 81 144 162 mA 3)6) 1060 1360 HYS72T128020EU–25F–B2 HYS72T128920EU–25F–B2 2) HYS64T128020EU–25F–B2 HYS64T128920EU–25F–B2 mA HYS72T64000EU–25F–B2 HYS72T64900EU–25F–B2 840 HYS64T64000EU–25F–B2 HYS64T64900EU–25F–B2 Note1) HYS64T32000EU–25F–B2 HYS64T32900EU–25F–B2 Unit Product Type Organization 256MB 512MB 512MB 1GB 1GB 1 Rank 1 Rank 1 Rank 2 Ranks 2 Ranks ×64 ×64 ×72 ×64 ×72 -25F -25F -25F -25F -25F Symbol Max Max Max Max. Max. IDD0 IDD1 IDD2N IDD2P IDD2Q IDD3N IDD3P_0 (fast) IDD3P_1 (slow) IDD4R IDD4W IDD5B IDD5D IDD6 IDD7 420 672 756 740 480 800 900 204 408 36 1530 1430 1610 mA 1) Calculated values from component data. ODT disabled. IDD1, IDD4R and IDD7 are defined with the outputs disabled. 2) The other rank is in IDD2P Precharge Power-Down Current mode 3) Both ranks are in the same IDDcurrent mode 4) Fast: MRS(12)=0 5) Slow: MRS(12)=1 6) IDD5D and IDD6 values are for 0°C ≤ TCase ≤ 85°C Rev. 1.0, 2006-10 10202006-L0SM-FEYT 34 2) Internet Data Sheet HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module TABLE 23 IDD Specification for HYS[64/72]T[32/64/128][0/9]xxEU-2.5-B2 830 940 mA 2) 459 820 920 mA 3) 72 81 140 160 mA 3) 180 360 405 720 810 mA 3) 240 480 540 960 1080 mA 3) 156 312 351 620 700 mA 3)4) 52 104 117 210 230 mA 3)5) 720 1240 1395 1310 1480 mA 2) 800 1240 1395 1310 1480 mA 2) 580 1160 1305 1230 1390 mA 2) 44 88 99 180 200 mA 3)6) 36 72 81 144 162 mA 3)6) 1020 1280 HYS72T128020EU–2.5–B2 HYS72T128920EU–2.5–B2 2) HYS64T128020EU–2.5–B2 HYS64T128920EU–2.5–B2 mA HYS72T64000EU–2.5–B2 HYS72T64900EU–2.5–B2 800 HYS64T64000EU–2.5–B2 HYS64T64900EU–2.5–B2 Note1) HYS64T32000EU–2.5–B2 HYS64T32900EU–2.5–B2 Unit Product Type Organization 256MB 512MB 512MB 1GB 1GB 1 Rank 1 Rank 1 Rank 2 Ranks 2 Ranks ×64 ×64 ×72 ×64 ×72 -2.5 -2.5 -2.5 -2.5 -2.5 Symbol Max Max Max Max. Max. IDD0 IDD1 IDD2N IDD2P IDD2Q IDD3N IDD3P_0 (fast) IDD3P_1 (slow) IDD4R IDD4W IDD5B IDD5D IDD6 IDD7 400 640 720 710 460 760 855 204 408 36 1440 1350 1520 mA 1) Calculated values from component data. ODT disabled. IDD1, IDD4R and IDD7 are defined with the outputs disabled. 2) The other rank is in IDD2P Precharge Power-Down Current mode 3) Both ranks are in the same IDDcurrent mode 4) Fast: MRS(12)=0 5) Slow: MRS(12)=1 6) IDD5D and IDD6 values are for 0°C ≤ TCase ≤ 85°C Rev. 1.0, 2006-10 10202006-L0SM-FEYT 35 2) Internet Data Sheet HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module TABLE 24 Product Type HYS64T32000EU–3–B2 HYS64T32900EU–3–B2 HYS64T64000EU–3–B2 HYS64T64900EU–3–B2 HYS72T64000EU–3–B2 HYS72T64900EU–3–B2 HYS64T128020EU–3–B2 HYS64T128920EU–3–B2 HYS72T128020EU–3–B2 HYS72T128920EU–3–B2 IDD Specification for HYS[64/72]T[32/64/128][0/9]xxEU-3-B2 Organization 256MB 512MB 512MB 1GB 1GB 1 Rank 1 Rank 1 Rank 2 Ranks 2 Ranks ×64 ×64 ×72 ×64 ×72 -3 -3 -3 -3 -3 Symbol Max Max Max Max. Max. IDD0 IDD1 IDD2N IDD2P IDD2Q IDD3N IDD3P_0 (fast) IDD3P_1 (slow) IDD4R IDD4W IDD5B IDD5D IDD6 IDD7 380 600 675 670 420 720 810 180 360 36 Unit Note1) 760 mA 2) 790 890 mA 2) 405 720 810 mA 3) 72 81 140 160 mA 3) 160 320 360 640 720 mA 3) 200 400 450 800 900 mA 3) 132 264 297 530 590 mA 3)4) 52 104 117 210 230 mA 3)5) 620 1040 1170 1110 1250 mA 2) 680 1040 1170 1110 1250 mA 2) 560 1120 1260 1190 1340 mA 2) 44 88 99 180 200 mA 3)6) 36 72 81 144 162 mA 3)6) 1008 1280 1440 1350 1520 mA 1) Calculated values from component data. ODT disabled. IDD1, IDD4R and IDD7 are defined with the outputs disabled. 2) The other rank is in IDD2P Precharge Power-Down Current mode 3) Both ranks are in the same IDDcurrent mode 4) Fast: MRS(12)=0 5) Slow: MRS(12)=1 6) IDD5D and IDD6 values are for 0°C ≤ TCase ≤ 85°C Rev. 1.0, 2006-10 10202006-L0SM-FEYT 36 2) Internet Data Sheet HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module TABLE 25 Product Type HYS64T32000EU–3S–B2 HYS64T32900EU–3S–B2 HYS64T64000EU–3S–B2 HYS64T64900EU–3S–B2 HYS72T64000EU–3S–B2 HYS72T64900EU–3S–B2 HYS64T128020EU–3S–B2 HYS64T128920EU–3S–B2 HYS72T128020EU–3S–B2 HYS72T128920EU–3S–B2 IDD Specification for HYS[64/72]T[32/64/128][0/9]xxEU-3S-B2 Organization 256MB 512MB 512MB 1GB 1GB 1 Rank 1 Rank 1 Rank 2 Ranks 2 Ranks ×64 ×64 ×72 ×64 ×72 -3S -3S 3S -3S -3S Symbol Max Max Max Max. Max. IDD0 IDD1 IDD2N IDD2P IDD2Q IDD3N IDD3P_0 (fast) IDD3P_1 (slow) IDD4R IDD4W IDD5B IDD5D IDD6 IDD7 360 568 639 640 400 680 765 180 360 36 Unit Note1) 720 mA 2) 750 850 mA 2) 405 720 810 mA 3) 72 81 140 160 mA 3) 160 320 360 640 720 mA 3) 200 400 450 800 900 mA 3) 132 264 297 530 590 mA 3)4) 52 104 117 210 230 mA 3)5) 620 1040 1170 1110 1250 mA 2) 680 1040 1170 1110 1250 mA 2) 560 1120 1260 1190 1340 mA 2) 44 88 99 180 200 mA 3)6) 36 72 81 144 162 mA 3)6) 960 1216 1368 1290 1450 mA 1) Calculated values from component data. ODT disabled. IDD1, IDD4R and IDD7 are defined with the outputs disabled. 2) The other rank is in IDD2P Precharge Power-Down Current mode 3) Both ranks are in the same IDDcurrent mode 4) Fast: MRS(12)=0 5) Slow: MRS(12)=1 6) IDD5D and IDD6 values are for 0°C ≤ TCase ≤ 85°C Rev. 1.0, 2006-10 10202006-L0SM-FEYT 37 2) Internet Data Sheet HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module TABLE 26 IDD Specification for HYS[64/72]T[32/64/128][0/9]xxEU-3.7-B2 670 760 mA 2) 342 610 680 mA 3) 72 81 140 160 mA 3) 140 280 315 560 630 mA 3) 172 344 387 690 770 mA 3) 112 224 252 450 500 mA 3)4) 52 104 117 210 230 mA 3)5) 520 880 990 950 1070 mA 2) 580 880 990 950 1070 mA 2) 520 1040 1170 1110 1250 mA 2) IDD5D 44 88 99 180 200 mA 3)6) IDD6 36 72 81 144 162 mA 3)6) IDD7 920 1160 HYS72T128020EU–3.7–B2 HYS72T128920EU–3.7–B2 2) HYS64T128020EU–3.7–B2 HYS64T128920EU–3.7–B2 mA HYS72T64000EU–3.7–B2 HYS72T64900EU–3.7–B2 670 HYS64T64000EU–3.7–B2 HYS64T64900EU–3.7–B2 Note1) HYS64T32000EU–3.7–B2 HYS64T32900EU–3.7–B2 Unit Product Type Organization 256MB 512MB 512MB 1GB 1GB 1 Rank 1 Rank 1 Rank 2 Ranks 2 Ranks ×64 ×64 ×72 ×64 ×72 -3.7 -3.7 -3.7 -3.7 -3.7 Symbol Max Max Max Max. Max. IDD0 IDD1 IDD2N IDD2P IDD2Q IDD3N IDD3P_0 (fast) IDD3P_1 (slow) IDD4R IDD4W IDD5B 320 520 585 590 360 600 675 152 304 36 1305 1230 1390 mA 1) Calculated values from component data. ODT disabled. IDD1, IDD4R and IDD7 are defined with the outputs disabled. 2) The other rank is in IDD2P Precharge Power-Down Current mode 3) Both ranks are in the same IDDcurrent mode 4) Fast: MRS(12)=0 5) Slow: MRS(12)=1 6) IDD5D and IDD6 values are for 0°C ≤ TCase ≤ 85°C Rev. 1.0, 2006-10 10202006-L0SM-FEYT 38 2) Internet Data Sheet HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module 4 SPD Codes This chapter lists all hexadecimal byte values stored in the EEPROM of the products described in this data sheet. SPD stands for serial presence detect. All values with XX in the table are module specific bytes which are defined during production. List of SPD Code Tables • • • • • • • • • • Table 27 “SPD Codes for PC2–6400–555” on Page 39 Table 28 “SPD Codes for PC2–6400–555” on Page 44 Table 29 “SPD Codes for PC2–6400–666” on Page 49 Table 30 “SPD Codes for PC2–6400–666” on Page 54 Table 31 “SPD Codes for PC2–5300–444” on Page 59 Table 32 “SPD Codes for PC2–5300–444” on Page 64 Table 33 “SPD Codes for PC2–5300–555” on Page 68 Table 34 “SPD Codes for PC2–5300–555” on Page 73 Table 35 “SPD Codes for PC2–4200–444” on Page 77 Table 36 “SPD Codes for PC2–4200–444” on Page 82 TABLE 27 Product Type HYS64T32000EU–25F–B2 HYS64T32900EU–25F–B2 HYS64T64000EU–25F–B2 HYS64T64900EU–25F–B2 HYS72T64000EU–25F–B2 HYS72T64900EU–25F–B2 SPD Codes for PC2–6400–555 Organization 256MB 256MB 512MB 512MB 512MB 512MB ×64 ×64 ×64 ×64 ×72 ×72 1 Rank (×16) 1 Rank (×16) 1 Rank (×8) 1 Rank (×8) 1 Rank (×8) 1 Rank (×8) Label Code PC2– 6400U– 555 PC2– 6400U– 555 PC2– 6400U– 555 PC2– 6400U– 555 PC2– 6400E– 555 PC2– 6400E– 555 JEDEC SPD Revision Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Byte# Description HEX HEX HEX HEX HEX HEX 0 Programmed SPD Bytes in EEPROM 80 80 80 80 80 80 1 Total number of Bytes in EEPROM 08 08 08 08 08 08 2 Memory Type (DDR2) 08 08 08 08 08 08 3 Number of Row Addresses 0D 0D 0E 0E 0E 0E 4 Number of Column Addresses 0A 0A 0A 0A 0A 0A 5 DIMM Rank and Stacking Information 60 60 60 60 60 60 Rev. 1.0, 2006-10 10202006-L0SM-FEYT 39 Internet Data Sheet Product Type HYS64T32000EU–25F–B2 HYS64T32900EU–25F–B2 HYS64T64000EU–25F–B2 HYS64T64900EU–25F–B2 HYS72T64000EU–25F–B2 HYS72T64900EU–25F–B2 HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module Organization 256MB 256MB 512MB 512MB 512MB 512MB ×64 ×64 ×64 ×64 ×72 ×72 1 Rank (×16) 1 Rank (×16) 1 Rank (×8) 1 Rank (×8) 1 Rank (×8) 1 Rank (×8) Label Code PC2– 6400U– 555 PC2– 6400U– 555 PC2– 6400U– 555 PC2– 6400U– 555 PC2– 6400E– 555 PC2– 6400E– 555 JEDEC SPD Revision Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Byte# Description HEX HEX HEX HEX HEX HEX 6 Data Width 40 40 40 40 48 48 7 Not used 00 00 00 00 00 00 8 Interface Voltage Level 05 05 05 05 05 05 9 tCK @ CLMAX (Byte 18) [ns] tAC SDRAM @ CLMAX (Byte 18) [ns] 25 25 25 25 25 25 10 40 40 40 40 40 40 11 Error Correction Support (non-ECC, ECC) 00 00 00 00 02 02 12 Refresh Rate and Type 82 82 82 82 82 82 13 Primary SDRAM Width 10 10 08 08 08 08 14 Error Checking SDRAM Width 00 00 00 00 08 08 15 Not used 00 00 00 00 00 00 16 Burst Length Supported 0C 0C 0C 0C 0C 0C 17 Number of Banks on SDRAM Device 04 04 04 04 04 04 18 Supported CAS Latencies 70 70 70 70 70 70 19 DIMM Mechanical Characteristics 01 01 01 01 01 01 20 DIMM Type Information 02 02 02 02 02 02 21 DIMM Attributes 00 00 00 00 00 00 22 Component Attributes 07 07 07 07 07 07 23 tCK @ CLMAX -1 (Byte 18) [ns] tAC SDRAM @ CLMAX -1 [ns] tCK @ CLMAX -2 (Byte 18) [ns] tAC SDRAM @ CLMAX -2 [ns] tRP.MIN [ns] tRRD.MIN [ns] tRCD.MIN [ns] 24 25 26 27 28 29 Rev. 1.0, 2006-10 10202006-L0SM-FEYT 25 25 25 25 25 25 40 40 40 40 40 40 3D 3D 3D 3D 3D 3D 50 50 50 50 50 50 32 32 32 32 32 32 28 28 1E 1E 1E 1E 32 32 32 32 32 32 40 Internet Data Sheet Product Type HYS64T32000EU–25F–B2 HYS64T32900EU–25F–B2 HYS64T64000EU–25F–B2 HYS64T64900EU–25F–B2 HYS72T64000EU–25F–B2 HYS72T64900EU–25F–B2 HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module Organization 256MB 256MB 512MB 512MB 512MB 512MB ×64 ×64 ×64 ×64 ×72 ×72 1 Rank (×16) 1 Rank (×16) 1 Rank (×8) 1 Rank (×8) 1 Rank (×8) 1 Rank (×8) Label Code PC2– 6400U– 555 PC2– 6400U– 555 PC2– 6400U– 555 PC2– 6400U– 555 PC2– 6400E– 555 PC2– 6400E– 555 JEDEC SPD Revision Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Byte# Description HEX HEX HEX HEX HEX HEX 30 tRAS.MIN [ns] 2D 2D 2D 2D 2D 2D 31 Module Density per Rank 40 40 80 80 80 80 32 17 17 17 17 17 17 25 25 25 25 25 25 05 05 05 05 05 05 12 12 12 12 12 12 38 tAS.MIN and tCS.MIN [ns] tAH.MIN and tCH.MIN [ns] tDS.MIN [ns] tDH.MIN [ns] tWR.MIN [ns] tWTR.MIN [ns] tRTP.MIN [ns] 39 40 33 34 35 3C 3C 3C 3C 3C 3C 1E 1E 1E 1E 1E 1E 1E 1E 1E 1E 1E 1E Analysis Characteristics 00 00 00 00 00 00 30 30 30 30 30 30 39 39 39 39 39 39 69 69 69 69 69 69 80 80 80 80 80 80 14 14 14 14 14 14 45 tRC and tRFC Extension tRC.MIN [ns] tRFC.MIN [ns] tCK.MAX [ns] tDQSQ.MAX [ns] tQHS.MAX [ns] 1E 1E 1E 1E 1E 1E 46 PLL Relock Time 00 00 00 00 00 00 36 37 41 42 43 44 47 TCASE.MAX Delta / ∆T4R4W Delta 56 56 50 50 50 50 48 Psi(T-A) DRAM 7A 7A 7A 7A 7A 7A 49 ∆T0 (DT0) 7F 7F 5F 5F 5F 5F 50 ∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM) 3B 3B 3B 3B 3B 3B 51 ∆T2P (DT2P) 36 36 36 36 36 36 52 ∆T3N (DT3N) 2E 2E 2E 2E 2E 2E 53 ∆T3P.fast (DT3P fast) 5A 5A 5A 5A 5A 5A Rev. 1.0, 2006-10 10202006-L0SM-FEYT 41 Internet Data Sheet Product Type HYS64T32000EU–25F–B2 HYS64T32900EU–25F–B2 HYS64T64000EU–25F–B2 HYS64T64900EU–25F–B2 HYS72T64000EU–25F–B2 HYS72T64900EU–25F–B2 HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module Organization 256MB 256MB 512MB 512MB 512MB 512MB ×64 ×64 ×64 ×64 ×72 ×72 1 Rank (×16) 1 Rank (×16) 1 Rank (×8) 1 Rank (×8) 1 Rank (×8) 1 Rank (×8) Label Code PC2– 6400U– 555 PC2– 6400U– 555 PC2– 6400U– 555 PC2– 6400U– 555 PC2– 6400E– 555 PC2– 6400E– 555 JEDEC SPD Revision Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Byte# Description HEX HEX HEX HEX HEX HEX 54 ∆T3P.slow (DT3P slow) 2A 2A 2A 2A 2A 2A 55 ∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W) 68 68 5A 5A 5A 5A 56 ∆T5B (DT5B) 22 22 22 22 22 22 57 ∆T7 (DT7) 3D 3D 27 27 27 27 58 Psi(ca) PLL 00 00 00 00 00 00 59 Psi(ca) REG 00 00 00 00 00 00 60 ∆TPLL (DTPLL) 00 00 00 00 00 00 61 ∆TREG (DTREG) / Toggle Rate 00 00 00 00 00 00 62 SPD Revision 12 12 12 12 12 12 63 Checksum of Bytes 0-62 52 52 37 37 49 49 64 Manufacturer’s JEDEC ID Code (1) 7F 7F 7F 7F 7F 7F 65 Manufacturer’s JEDEC ID Code (2) 7F 7F 7F 7F 7F 7F 66 Manufacturer’s JEDEC ID Code (3) 7F 7F 7F 7F 7F 7F 67 Manufacturer’s JEDEC ID Code (4) 7F 7F 7F 7F 7F 7F 68 Manufacturer’s JEDEC ID Code (5) 7F 7F 7F 7F 7F 7F 69 Manufacturer’s JEDEC ID Code (6) 51 51 51 51 51 51 70 Manufacturer’s JEDEC ID Code (7) 00 00 00 00 00 00 71 Manufacturer’s JEDEC ID Code (8) 00 00 00 00 00 00 72 Module Manufacturer Location xx xx xx xx xx xx 73 Product Type, Char 1 36 36 36 36 37 37 74 Product Type, Char 2 34 34 34 34 32 32 75 Product Type, Char 3 54 54 54 54 54 54 76 Product Type, Char 4 33 33 36 36 36 36 77 Product Type, Char 5 32 32 34 34 34 34 Rev. 1.0, 2006-10 10202006-L0SM-FEYT 42 Internet Data Sheet Product Type HYS64T32000EU–25F–B2 HYS64T32900EU–25F–B2 HYS64T64000EU–25F–B2 HYS64T64900EU–25F–B2 HYS72T64000EU–25F–B2 HYS72T64900EU–25F–B2 HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module Organization 256MB 256MB 512MB 512MB 512MB 512MB ×64 ×64 ×64 ×64 ×72 ×72 1 Rank (×16) 1 Rank (×16) 1 Rank (×8) 1 Rank (×8) 1 Rank (×8) 1 Rank (×8) Label Code PC2– 6400U– 555 PC2– 6400U– 555 PC2– 6400U– 555 PC2– 6400U– 555 PC2– 6400E– 555 PC2– 6400E– 555 JEDEC SPD Revision Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Byte# Description HEX HEX HEX HEX HEX HEX 78 Product Type, Char 6 30 39 30 39 30 39 79 Product Type, Char 7 30 30 30 30 30 30 80 Product Type, Char 8 30 30 30 30 30 30 81 Product Type, Char 9 45 45 45 45 45 45 82 Product Type, Char 10 55 55 55 55 55 55 83 Product Type, Char 11 32 32 32 32 32 32 84 Product Type, Char 12 35 35 35 35 35 35 85 Product Type, Char 13 46 46 46 46 46 46 86 Product Type, Char 14 42 42 42 42 42 42 87 Product Type, Char 15 32 32 32 32 32 32 88 Product Type, Char 16 20 20 20 20 20 20 89 Product Type, Char 17 20 20 20 20 20 20 90 Product Type, Char 18 20 20 20 20 20 20 91 Module Revision Code 3x 0x 3x 0x 3x 0x 92 Test Program Revision Code xx xx xx xx xx xx 93 Module Manufacturing Date Year xx xx xx xx xx xx 94 Module Manufacturing Date Week xx xx xx xx xx xx 95 - 98 Module Serial Number xx xx xx xx xx xx 99 127 Not used 00 00 00 00 00 00 128 255 Blank for customer use FF FF FF FF FF FF Rev. 1.0, 2006-10 10202006-L0SM-FEYT 43 Internet Data Sheet HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module TABLE 28 Product Type HYS64T128020EU–25F–B2 HYS64T128920EU–25F–B2 HYS72T128020EU–25F–B2 HYS72T128920EU–25F–B2 SPD Codes for PC2–6400–555 Organization 1 GByte 1 GByte 1 GByte 1 GByte ×64 ×64 ×72 ×72 2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8) Label Code PC2– 6400U–555 PC2– 6400U–555 PC2– 6400E–555 PC2– 6400E–555 JEDEC SPD Revision Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Byte# Description HEX HEX HEX HEX 0 Programmed SPD Bytes in EEPROM 80 80 80 80 1 Total number of Bytes in EEPROM 08 08 08 08 2 Memory Type (DDR2) 08 08 08 08 3 Number of Row Addresses 0E 0E 0E 0E 4 Number of Column Addresses 0A 0A 0A 0A 5 DIMM Rank and Stacking Information 61 61 61 61 6 Data Width 40 40 48 48 7 Not used 00 00 00 00 8 Interface Voltage Level 05 05 05 05 9 tCK @ CLMAX (Byte 18) [ns] tAC SDRAM @ CLMAX (Byte 18) [ns] 25 25 25 25 40 40 40 40 11 Error Correction Support (non-ECC, ECC) 00 00 02 02 12 Refresh Rate and Type 82 82 82 82 13 Primary SDRAM Width 08 08 08 08 10 14 Error Checking SDRAM Width 00 00 08 08 15 Not used 00 00 00 00 16 Burst Length Supported 0C 0C 0C 0C 17 Number of Banks on SDRAM Device 04 04 04 04 18 Supported CAS Latencies 70 70 70 70 19 DIMM Mechanical Characteristics 01 01 01 01 20 DIMM Type Information 02 02 02 02 21 DIMM Attributes 00 00 00 00 Rev. 1.0, 2006-10 10202006-L0SM-FEYT 44 Internet Data Sheet Product Type HYS64T128020EU–25F–B2 HYS64T128920EU–25F–B2 HYS72T128020EU–25F–B2 HYS72T128920EU–25F–B2 HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module Organization 1 GByte 1 GByte 1 GByte 1 GByte ×64 ×64 ×72 ×72 2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8) Label Code PC2– 6400U–555 PC2– 6400U–555 PC2– 6400E–555 PC2– 6400E–555 JEDEC SPD Revision Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Byte# Description HEX HEX HEX HEX 22 Component Attributes 07 07 07 07 23 25 25 25 25 40 40 40 40 3D 3D 3D 3D 50 50 50 50 30 tCK @ CLMAX -1 (Byte 18) [ns] tAC SDRAM @ CLMAX -1 [ns] tCK @ CLMAX -2 (Byte 18) [ns] tAC SDRAM @ CLMAX -2 [ns] tRP.MIN [ns] tRRD.MIN [ns] tRCD.MIN [ns] tRAS.MIN [ns] 31 Module Density per Rank 32 38 tAS.MIN and tCS.MIN [ns] tAH.MIN and tCH.MIN [ns] tDS.MIN [ns] tDH.MIN [ns] tWR.MIN [ns] tWTR.MIN [ns] tRTP.MIN [ns] 39 Analysis Characteristics 40 45 tRC and tRFC Extension tRC.MIN [ns] tRFC.MIN [ns] tCK.MAX [ns] tDQSQ.MAX [ns] tQHS.MAX [ns] 46 PLL Relock Time 24 25 26 27 28 29 33 34 35 36 37 41 42 43 44 Rev. 1.0, 2006-10 10202006-L0SM-FEYT 45 32 32 32 32 1E 1E 1E 1E 32 32 32 32 2D 2D 2D 2D 80 80 80 80 17 17 17 17 25 25 25 25 05 05 05 05 12 12 12 12 3C 3C 3C 3C 1E 1E 1E 1E 1E 1E 1E 1E 00 00 00 00 30 30 30 30 39 39 39 39 69 69 69 69 80 80 80 80 14 14 14 14 1E 1E 1E 1E 00 00 00 00 Internet Data Sheet Product Type HYS64T128020EU–25F–B2 HYS64T128920EU–25F–B2 HYS72T128020EU–25F–B2 HYS72T128920EU–25F–B2 HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module Organization 1 GByte 1 GByte 1 GByte 1 GByte ×64 ×64 ×72 ×72 2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8) Label Code PC2– 6400U–555 PC2– 6400U–555 PC2– 6400E–555 PC2– 6400E–555 JEDEC SPD Revision Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Byte# Description HEX HEX HEX HEX 47 TCASE.MAX Delta / ∆T4R4W Delta 50 50 50 50 48 Psi(T-A) DRAM 7A 7A 7A 7A 49 ∆T0 (DT0) 5F 5F 5F 5F 50 ∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM) 3B 3B 3B 3B 51 ∆T2P (DT2P) 36 36 36 36 52 ∆T3N (DT3N) 2E 2E 2E 2E 53 ∆T3P.fast (DT3P fast) 5A 5A 5A 5A 54 ∆T3P.slow (DT3P slow) 2A 2A 2A 2A 55 ∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W) 5A 5A 5A 5A 56 ∆T5B (DT5B) 22 22 22 22 57 ∆T7 (DT7) 27 27 27 27 58 Psi(ca) PLL 00 00 00 00 59 Psi(ca) REG 00 00 00 00 60 ∆TPLL (DTPLL) 00 00 00 00 61 ∆TREG (DTREG) / Toggle Rate 00 00 00 00 62 SPD Revision 12 12 12 12 63 Checksum of Bytes 0-62 38 38 4A 4A 64 Manufacturer’s JEDEC ID Code (1) 7F 7F 7F 7F 65 Manufacturer’s JEDEC ID Code (2) 7F 7F 7F 7F 66 Manufacturer’s JEDEC ID Code (3) 7F 7F 7F 7F 67 Manufacturer’s JEDEC ID Code (4) 7F 7F 7F 7F 68 Manufacturer’s JEDEC ID Code (5) 7F 7F 7F 7F 69 Manufacturer’s JEDEC ID Code (6) 51 51 51 51 70 Manufacturer’s JEDEC ID Code (7) 00 00 00 00 71 Manufacturer’s JEDEC ID Code (8) 00 00 00 00 Rev. 1.0, 2006-10 10202006-L0SM-FEYT 46 Internet Data Sheet Product Type HYS64T128020EU–25F–B2 HYS64T128920EU–25F–B2 HYS72T128020EU–25F–B2 HYS72T128920EU–25F–B2 HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module Organization 1 GByte 1 GByte 1 GByte 1 GByte ×64 ×64 ×72 ×72 2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8) Label Code PC2– 6400U–555 PC2– 6400U–555 PC2– 6400E–555 PC2– 6400E–555 JEDEC SPD Revision Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Byte# Description HEX HEX HEX HEX 72 Module Manufacturer Location xx xx xx xx 73 Product Type, Char 1 36 36 37 37 74 Product Type, Char 2 34 34 32 32 75 Product Type, Char 3 54 54 54 54 76 Product Type, Char 4 31 31 31 31 77 Product Type, Char 5 32 32 32 32 78 Product Type, Char 6 38 38 38 38 79 Product Type, Char 7 30 39 30 39 80 Product Type, Char 8 32 32 32 32 81 Product Type, Char 9 30 30 30 30 82 Product Type, Char 10 45 45 45 45 83 Product Type, Char 11 55 55 55 55 84 Product Type, Char 12 32 32 32 32 85 Product Type, Char 13 35 35 35 35 86 Product Type, Char 14 46 46 46 46 87 Product Type, Char 15 42 42 42 42 88 Product Type, Char 16 32 32 32 32 89 Product Type, Char 17 20 20 20 20 90 Product Type, Char 18 20 20 20 20 91 Module Revision Code 3x 0x 3x 0x 92 Test Program Revision Code xx xx xx xx 93 Module Manufacturing Date Year xx xx xx xx 94 Module Manufacturing Date Week xx xx xx xx 95 - 98 Module Serial Number xx xx xx xx Rev. 1.0, 2006-10 10202006-L0SM-FEYT 47 Internet Data Sheet Product Type HYS64T128020EU–25F–B2 HYS64T128920EU–25F–B2 HYS72T128020EU–25F–B2 HYS72T128920EU–25F–B2 HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module Organization 1 GByte 1 GByte 1 GByte 1 GByte ×64 ×64 ×72 ×72 2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8) Label Code PC2– 6400U–555 PC2– 6400U–555 PC2– 6400E–555 PC2– 6400E–555 JEDEC SPD Revision Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Byte# HEX HEX HEX HEX 99 - 127 Not used 00 00 00 00 128 255 FF FF FF FF Description Blank for customer use Rev. 1.0, 2006-10 10202006-L0SM-FEYT 48 Internet Data Sheet HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module TABLE 29 Product Type HYS64T32000EU–2.5–B2 HYS64T32900EU–2.5–B2 HYS64T64000EU–2.5–B2 HYS64T64900EU–2.5–B2 HYS72T64000EU–2.5–B2 HYS72T64900EU–2.5–B2 SPD Codes for PC2–6400–666 Organization 256MB 256MB 512MB 512MB 512MB 512MB ×64 ×64 ×64 ×64 ×72 ×72 1 Rank (×16) 1 Rank (×16) 1 Rank (×8) 1 Rank (×8) 1 Rank (×8) 1 Rank (×8) Label Code PC2– PC2– PC2– PC2– PC2– 6400U– 6400U– 6400U– 6400U– 6400E– 666 666 666 666 666 PC2– 6400E– 666 JEDEC SPD Revision Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Byte# Description HEX 0 Programmed SPD Bytes in EEPROM 80 80 80 80 80 80 1 Total number of Bytes in EEPROM 08 08 08 08 08 08 2 Memory Type (DDR2) 08 08 08 08 08 08 3 Number of Row Addresses 0D 0D 0E 0E 0E 0E 4 Number of Column Addresses 0A 0A 0A 0A 0A 0A 5 DIMM Rank and Stacking Information 60 60 60 60 60 60 6 Data Width 40 40 40 40 48 48 7 Not used 00 00 00 00 00 00 8 Interface Voltage Level 05 05 05 05 05 05 9 25 25 25 25 25 25 10 tCK @ CLMAX (Byte 18) [ns] tAC SDRAM @ CLMAX (Byte 18) [ns] 40 40 40 40 40 40 11 Error Correction Support (non-ECC, ECC) 00 00 00 00 02 02 12 Refresh Rate and Type 82 82 82 82 82 82 13 Primary SDRAM Width 10 10 08 08 08 08 14 Error Checking SDRAM Width 00 00 00 00 08 08 15 Not used 00 00 00 00 00 00 16 Burst Length Supported 0C 0C 0C 0C 0C 0C 17 Number of Banks on SDRAM Device 04 04 04 04 04 04 18 Supported CAS Latencies 70 70 70 70 70 70 19 DIMM Mechanical Characteristics 01 01 01 01 01 01 20 DIMM Type Information 02 02 02 02 02 02 Rev. 1.0, 2006-10 10202006-L0SM-FEYT 49 HEX HEX HEX HEX HEX Internet Data Sheet Product Type HYS64T32000EU–2.5–B2 HYS64T32900EU–2.5–B2 HYS64T64000EU–2.5–B2 HYS64T64900EU–2.5–B2 HYS72T64000EU–2.5–B2 HYS72T64900EU–2.5–B2 HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module Organization 256MB 256MB 512MB 512MB 512MB 512MB ×64 ×64 ×64 ×64 ×72 ×72 1 Rank (×16) 1 Rank (×16) 1 Rank (×8) 1 Rank (×8) 1 Rank (×8) 1 Rank (×8) Label Code PC2– PC2– PC2– PC2– PC2– 6400U– 6400U– 6400U– 6400U– 6400E– 666 666 666 666 666 PC2– 6400E– 666 JEDEC SPD Revision Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Byte# Description HEX HEX HEX HEX HEX HEX 21 DIMM Attributes 00 00 00 00 00 00 22 Component Attributes 07 07 07 07 07 07 23 30 30 30 30 30 30 45 45 45 45 45 45 30 tCK @ CLMAX -1 (Byte 18) [ns] tAC SDRAM @ CLMAX -1 [ns] tCK @ CLMAX -2 (Byte 18) [ns] tAC SDRAM @ CLMAX -2 [ns] tRP.MIN [ns] tRRD.MIN [ns] tRCD.MIN [ns] tRAS.MIN [ns] 2D 2D 2D 2D 2D 2D 31 Module Density per Rank 40 40 80 80 80 80 32 17 17 17 17 17 17 38 tAS.MIN and tCS.MIN [ns] tAH.MIN and tCH.MIN [ns] tDS.MIN [ns] tDH.MIN [ns] tWR.MIN [ns] tWTR.MIN [ns] tRTP.MIN [ns] 1E 1E 1E 1E 1E 1E 39 Analysis Characteristics 00 00 00 00 00 00 40 tRC and tRFC Extension tRC.MIN [ns] tRFC.MIN [ns] tCK.MAX [ns] tDQSQ.MAX [ns] 00 00 00 00 00 00 24 25 26 27 28 29 33 34 35 36 37 41 42 43 44 Rev. 1.0, 2006-10 10202006-L0SM-FEYT 50 3D 3D 3D 3D 3D 3D 50 50 50 50 50 50 3C 3C 3C 3C 3C 3C 28 28 1E 1E 1E 1E 3C 3C 3C 3C 3C 3C 25 25 25 25 25 25 05 05 05 05 05 05 12 12 12 12 12 12 3C 3C 3C 3C 3C 3C 1E 1E 1E 1E 1E 1E 3C 3C 3C 3C 3C 3C 69 69 69 69 69 69 80 80 80 80 80 80 14 14 14 14 14 14 Internet Data Sheet Product Type HYS64T32000EU–2.5–B2 HYS64T32900EU–2.5–B2 HYS64T64000EU–2.5–B2 HYS64T64900EU–2.5–B2 HYS72T64000EU–2.5–B2 HYS72T64900EU–2.5–B2 HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module Organization 256MB 256MB 512MB 512MB 512MB 512MB ×64 ×64 ×64 ×64 ×72 ×72 1 Rank (×16) 1 Rank (×16) 1 Rank (×8) 1 Rank (×8) 1 Rank (×8) 1 Rank (×8) Label Code PC2– PC2– PC2– PC2– PC2– 6400U– 6400U– 6400U– 6400U– 6400E– 666 666 666 666 666 PC2– 6400E– 666 JEDEC SPD Revision Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Byte# Description HEX HEX HEX HEX HEX HEX 45 tQHS.MAX [ns] 1E 1E 1E 1E 1E 1E 46 PLL Relock Time 00 00 00 00 00 00 47 TCASE.MAX Delta / ∆T4R4W Delta 56 56 50 50 50 50 48 Psi(T-A) DRAM 7A 7A 7A 7A 7A 7A 49 ∆T0 (DT0) 77 77 5B 5B 5B 5B 50 ∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM) 3B 3B 3B 3B 3B 3B 51 ∆T2P (DT2P) 36 36 36 36 36 36 52 ∆T3N (DT3N) 2E 2E 2E 2E 2E 2E 53 ∆T3P.fast (DT3P fast) 5A 5A 5A 5A 5A 5A 54 ∆T3P.slow (DT3P slow) 2A 2A 2A 2A 2A 2A 55 ∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W) 68 68 5A 5A 5A 5A 56 ∆T5B (DT5B) 22 22 22 22 22 22 57 ∆T7 (DT7) 3B 3B 25 25 25 25 58 Psi(ca) PLL 00 00 00 00 00 00 59 Psi(ca) REG 00 00 00 00 00 00 60 ∆TPLL (DTPLL) 00 00 00 00 00 00 61 ∆TREG (DTREG) / Toggle Rate 00 00 00 00 00 00 62 SPD Revision 12 12 12 12 12 12 63 Checksum of Bytes 0-62 3F 3F 28 28 3A 3A 64 Manufacturer’s JEDEC ID Code (1) 7F 7F 7F 7F 7F 7F 65 Manufacturer’s JEDEC ID Code (2) 7F 7F 7F 7F 7F 7F 66 Manufacturer’s JEDEC ID Code (3) 7F 7F 7F 7F 7F 7F 67 Manufacturer’s JEDEC ID Code (4) 7F 7F 7F 7F 7F 7F 68 Manufacturer’s JEDEC ID Code (5) 7F 7F 7F 7F 7F 7F Rev. 1.0, 2006-10 10202006-L0SM-FEYT 51 Internet Data Sheet Product Type HYS64T32000EU–2.5–B2 HYS64T32900EU–2.5–B2 HYS64T64000EU–2.5–B2 HYS64T64900EU–2.5–B2 HYS72T64000EU–2.5–B2 HYS72T64900EU–2.5–B2 HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module Organization 256MB 256MB 512MB 512MB 512MB 512MB ×64 ×64 ×64 ×64 ×72 ×72 1 Rank (×16) 1 Rank (×16) 1 Rank (×8) 1 Rank (×8) 1 Rank (×8) 1 Rank (×8) Label Code PC2– PC2– PC2– PC2– PC2– 6400U– 6400U– 6400U– 6400U– 6400E– 666 666 666 666 666 PC2– 6400E– 666 JEDEC SPD Revision Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Byte# Description HEX HEX HEX HEX HEX HEX 69 Manufacturer’s JEDEC ID Code (6) 51 51 51 51 51 51 70 Manufacturer’s JEDEC ID Code (7) 00 00 00 00 00 00 71 Manufacturer’s JEDEC ID Code (8) 00 00 00 00 00 00 72 Module Manufacturer Location xx xx xx xx xx xx 73 Product Type, Char 1 36 36 36 36 37 37 74 Product Type, Char 2 34 34 34 34 32 32 75 Product Type, Char 3 54 54 54 54 54 54 76 Product Type, Char 4 33 33 36 36 36 36 77 Product Type, Char 5 32 32 34 34 34 34 78 Product Type, Char 6 30 39 30 39 30 39 79 Product Type, Char 7 30 30 30 30 30 30 80 Product Type, Char 8 30 30 30 30 30 30 81 Product Type, Char 9 45 45 45 45 45 45 82 Product Type, Char 10 55 55 55 55 55 55 83 Product Type, Char 11 32 32 32 32 32 32 84 Product Type, Char 12 2E 2E 2E 2E 2E 2E 85 Product Type, Char 13 35 35 35 35 35 35 86 Product Type, Char 14 42 42 42 42 42 42 87 Product Type, Char 15 32 32 32 32 32 32 88 Product Type, Char 16 20 20 20 20 20 20 89 Product Type, Char 17 20 20 20 20 20 20 90 Product Type, Char 18 20 20 20 20 20 20 91 Module Revision Code 3x 0x 3x 0x 3x 0x 92 Test Program Revision Code xx xx xx xx xx xx Rev. 1.0, 2006-10 10202006-L0SM-FEYT 52 Internet Data Sheet Product Type HYS64T32000EU–2.5–B2 HYS64T32900EU–2.5–B2 HYS64T64000EU–2.5–B2 HYS64T64900EU–2.5–B2 HYS72T64000EU–2.5–B2 HYS72T64900EU–2.5–B2 HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module Organization 256MB 256MB 512MB 512MB 512MB 512MB ×64 ×64 ×64 ×64 ×72 ×72 1 Rank (×16) 1 Rank (×16) 1 Rank (×8) 1 Rank (×8) 1 Rank (×8) 1 Rank (×8) Label Code PC2– PC2– PC2– PC2– PC2– 6400U– 6400U– 6400U– 6400U– 6400E– 666 666 666 666 666 PC2– 6400E– 666 JEDEC SPD Revision Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Byte# Description HEX HEX HEX HEX HEX HEX 93 Module Manufacturing Date Year xx xx xx xx xx xx 94 Module Manufacturing Date Week xx xx xx xx xx xx 95 - 98 Module Serial Number xx xx xx xx xx xx 99 - 127 Not used 00 00 00 00 00 00 128 255 FF FF FF FF FF FF Blank for customer use Rev. 1.0, 2006-10 10202006-L0SM-FEYT 53 Internet Data Sheet HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module TABLE 30 Product Type HYS64T128020EU–2.5–B2 HYS64T128920EU–2.5–B2 HYS72T128020EU–2.5–B2 HYS72T128920EU–2.5–B2 SPD Codes for PC2–6400–666 Organization 1 GByte 1 GByte 1 GByte 1 GByte ×64 ×64 ×72 ×72 2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8) Label Code PC2– 6400U–666 PC2– 6400U–666 PC2– 6400E–666 PC2– 6400E–666 JEDEC SPD Revision Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Byte# Description HEX HEX HEX HEX 0 Programmed SPD Bytes in EEPROM 80 80 80 80 1 Total number of Bytes in EEPROM 08 08 08 08 2 Memory Type (DDR2) 08 08 08 08 3 Number of Row Addresses 0E 0E 0E 0E 4 Number of Column Addresses 0A 0A 0A 0A 5 DIMM Rank and Stacking Information 61 61 61 61 6 Data Width 40 40 48 48 7 Not used 00 00 00 00 8 Interface Voltage Level 05 05 05 05 9 tCK @ CLMAX (Byte 18) [ns] tAC SDRAM @ CLMAX (Byte 18) [ns] 25 25 25 25 10 40 40 40 40 11 Error Correction Support (non-ECC, ECC) 00 00 02 02 12 Refresh Rate and Type 82 82 82 82 13 Primary SDRAM Width 08 08 08 08 14 Error Checking SDRAM Width 00 00 08 08 15 Not used 00 00 00 00 16 Burst Length Supported 0C 0C 0C 0C 17 Number of Banks on SDRAM Device 04 04 04 04 18 Supported CAS Latencies 70 70 70 70 19 DIMM Mechanical Characteristics 01 01 01 01 20 DIMM Type Information 02 02 02 02 21 DIMM Attributes 00 00 00 00 22 Component Attributes 07 07 07 07 Rev. 1.0, 2006-10 10202006-L0SM-FEYT 54 Internet Data Sheet Product Type HYS64T128020EU–2.5–B2 HYS64T128920EU–2.5–B2 HYS72T128020EU–2.5–B2 HYS72T128920EU–2.5–B2 HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module Organization 1 GByte 1 GByte 1 GByte 1 GByte ×64 ×64 ×72 ×72 2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8) Label Code PC2– 6400U–666 PC2– 6400U–666 PC2– 6400E–666 PC2– 6400E–666 JEDEC SPD Revision Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Byte# Description HEX HEX HEX HEX 23 tCK @ CLMAX -1 (Byte 18) [ns] tAC SDRAM @ CLMAX -1 [ns] tCK @ CLMAX -2 (Byte 18) [ns] tAC SDRAM @ CLMAX -2 [ns] tRP.MIN [ns] tRRD.MIN [ns] tRCD.MIN [ns] tRAS.MIN [ns] 24 25 26 27 28 29 30 30 30 30 30 45 45 45 45 3D 3D 3D 3D 50 50 50 50 3C 3C 3C 3C 1E 1E 1E 1E 3C 3C 3C 3C 2D 2D 2D 2D 31 Module Density per Rank 80 80 80 80 32 tAS.MIN and tCS.MIN [ns] tAH.MIN and tCH.MIN [ns] tDS.MIN [ns] tDH.MIN [ns] tWR.MIN [ns] tWTR.MIN [ns] tRTP.MIN [ns] 17 17 17 17 25 25 25 25 05 05 05 05 12 12 12 12 3C 3C 3C 3C 1E 1E 1E 1E 1E 1E 1E 1E 33 34 35 36 37 38 39 Analysis Characteristics 00 00 00 00 40 00 00 00 00 3C 3C 3C 3C 69 69 69 69 80 80 80 80 14 14 14 14 45 tRC and tRFC Extension tRC.MIN [ns] tRFC.MIN [ns] tCK.MAX [ns] tDQSQ.MAX [ns] tQHS.MAX [ns] 1E 1E 1E 1E 46 PLL Relock Time 00 00 00 00 47 TCASE.MAX Delta / ∆T4R4W Delta 50 50 50 50 41 42 43 44 Rev. 1.0, 2006-10 10202006-L0SM-FEYT 55 Internet Data Sheet Product Type HYS64T128020EU–2.5–B2 HYS64T128920EU–2.5–B2 HYS72T128020EU–2.5–B2 HYS72T128920EU–2.5–B2 HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module Organization 1 GByte 1 GByte 1 GByte 1 GByte ×64 ×64 ×72 ×72 2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8) Label Code PC2– 6400U–666 PC2– 6400U–666 PC2– 6400E–666 PC2– 6400E–666 JEDEC SPD Revision Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Byte# Description HEX HEX HEX HEX 48 Psi(T-A) DRAM 7A 7A 7A 7A 49 ∆T0 (DT0) 5B 5B 5B 5B 50 ∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM) 3B 3B 3B 3B 51 ∆T2P (DT2P) 36 36 36 36 52 ∆T3N (DT3N) 2E 2E 2E 2E 53 ∆T3P.fast (DT3P fast) 5A 5A 5A 5A 54 ∆T3P.slow (DT3P slow) 2A 2A 2A 2A 55 ∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W) 5A 5A 5A 5A 56 ∆T5B (DT5B) 22 22 22 22 57 ∆T7 (DT7) 25 25 25 25 58 Psi(ca) PLL 00 00 00 00 59 Psi(ca) REG 00 00 00 00 60 ∆TPLL (DTPLL) 00 00 00 00 61 ∆TREG (DTREG) / Toggle Rate 00 00 00 00 62 SPD Revision 12 12 12 12 63 Checksum of Bytes 0-62 29 29 3B 3B 64 Manufacturer’s JEDEC ID Code (1) 7F 7F 7F 7F 65 Manufacturer’s JEDEC ID Code (2) 7F 7F 7F 7F 66 Manufacturer’s JEDEC ID Code (3) 7F 7F 7F 7F 67 Manufacturer’s JEDEC ID Code (4) 7F 7F 7F 7F 68 Manufacturer’s JEDEC ID Code (5) 7F 7F 7F 7F 69 Manufacturer’s JEDEC ID Code (6) 51 51 51 51 70 Manufacturer’s JEDEC ID Code (7) 00 00 00 00 71 Manufacturer’s JEDEC ID Code (8) 00 00 00 00 72 Module Manufacturer Location xx xx xx xx Rev. 1.0, 2006-10 10202006-L0SM-FEYT 56 Internet Data Sheet Product Type HYS64T128020EU–2.5–B2 HYS64T128920EU–2.5–B2 HYS72T128020EU–2.5–B2 HYS72T128920EU–2.5–B2 HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module Organization 1 GByte 1 GByte 1 GByte 1 GByte ×64 ×64 ×72 ×72 2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8) Label Code PC2– 6400U–666 PC2– 6400U–666 PC2– 6400E–666 PC2– 6400E–666 JEDEC SPD Revision Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Byte# Description HEX HEX HEX HEX 73 Product Type, Char 1 36 36 37 37 74 Product Type, Char 2 34 34 32 32 75 Product Type, Char 3 54 54 54 54 76 Product Type, Char 4 31 31 31 31 77 Product Type, Char 5 32 32 32 32 78 Product Type, Char 6 38 38 38 38 79 Product Type, Char 7 30 39 30 39 80 Product Type, Char 8 32 32 32 32 81 Product Type, Char 9 30 30 30 30 82 Product Type, Char 10 45 45 45 45 83 Product Type, Char 11 55 55 55 55 84 Product Type, Char 12 32 32 32 32 85 Product Type, Char 13 2E 2E 2E 2E 86 Product Type, Char 14 35 35 35 35 87 Product Type, Char 15 42 42 42 42 88 Product Type, Char 16 32 32 32 32 89 Product Type, Char 17 20 20 20 20 90 Product Type, Char 18 20 20 20 20 91 Module Revision Code 3x 0x 3x 0x 92 Test Program Revision Code xx xx xx xx 93 Module Manufacturing Date Year xx xx xx xx 94 Module Manufacturing Date Week xx xx xx xx 95 - 98 Module Serial Number xx xx xx xx Rev. 1.0, 2006-10 10202006-L0SM-FEYT 57 Internet Data Sheet Product Type HYS64T128020EU–2.5–B2 HYS64T128920EU–2.5–B2 HYS72T128020EU–2.5–B2 HYS72T128920EU–2.5–B2 HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module Organization 1 GByte 1 GByte 1 GByte 1 GByte ×64 ×64 ×72 ×72 2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8) Label Code PC2– 6400U–666 PC2– 6400U–666 PC2– 6400E–666 PC2– 6400E–666 JEDEC SPD Revision Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Byte# HEX HEX HEX HEX 99 - 127 Not used 00 00 00 00 128 255 FF FF FF FF Description Blank for customer use Rev. 1.0, 2006-10 10202006-L0SM-FEYT 58 Internet Data Sheet HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module TABLE 31 Product Type HYS64T32000EU–3–B2 HYS64T32900EU–3–B2 HYS64T64000EU–3–B2 HYS64T64900EU–3–B2 HYS72T64000EU–3–B2 HYS72T64900EU–3–B2 SPD Codes for PC2–5300–444 Organization 256MB 256MB 512MB 512MB 512MB 512MB ×64 ×64 ×64 ×64 ×72 ×72 1 Rank (×16) 1 Rank (×16) 1 Rank (×8) 1 Rank (×8) 1 Rank (×8) 1 Rank (×8) Label Code PC2– PC2– PC2– PC2– PC2– PC2– 5300U– 5300U– 5300U– 5300U– 5300E– 5300E– 444 444 444 444 444 444 JEDEC SPD Revision Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Byte# Description HEX HEX HEX HEX HEX HEX 0 Programmed SPD Bytes in EEPROM 80 80 80 80 80 80 1 Total number of Bytes in EEPROM 08 08 08 08 08 08 2 Memory Type (DDR2) 08 08 08 08 08 08 3 Number of Row Addresses 0D 0D 0E 0E 0E 0E 4 Number of Column Addresses 0A 0A 0A 0A 0A 0A 5 DIMM Rank and Stacking Information 60 60 60 60 60 60 6 Data Width 40 40 40 40 48 48 7 Not used 00 00 00 00 00 00 8 Interface Voltage Level 05 05 05 05 05 05 9 30 30 30 30 30 30 10 tCK @ CLMAX (Byte 18) [ns] tAC SDRAM @ CLMAX (Byte 18) [ns] 45 45 45 45 45 45 11 Error Correction Support (non-ECC, ECC) 00 00 00 00 02 02 12 Refresh Rate and Type 82 82 82 82 82 82 13 Primary SDRAM Width 10 10 08 08 08 08 14 Error Checking SDRAM Width 00 00 00 00 08 08 15 Not used 00 00 00 00 00 00 16 Burst Length Supported 0C 0C 0C 0C 0C 0C 17 Number of Banks on SDRAM Device 04 04 04 04 04 04 18 Supported CAS Latencies 38 38 38 38 38 38 19 DIMM Mechanical Characteristics 01 01 01 01 01 01 20 DIMM Type Information 02 02 02 02 02 02 21 DIMM Attributes 00 00 00 00 00 00 Rev. 1.0, 2006-10 10202006-L0SM-FEYT 59 Internet Data Sheet Product Type HYS64T32000EU–3–B2 HYS64T32900EU–3–B2 HYS64T64000EU–3–B2 HYS64T64900EU–3–B2 HYS72T64000EU–3–B2 HYS72T64900EU–3–B2 HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module Organization 256MB 256MB 512MB 512MB 512MB 512MB ×64 ×64 ×64 ×64 ×72 ×72 1 Rank (×16) 1 Rank (×16) 1 Rank (×8) 1 Rank (×8) 1 Rank (×8) 1 Rank (×8) Label Code PC2– PC2– PC2– PC2– PC2– PC2– 5300U– 5300U– 5300U– 5300U– 5300E– 5300E– 444 444 444 444 444 444 JEDEC SPD Revision Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Byte# Description HEX HEX HEX HEX HEX HEX 22 Component Attributes 07 07 07 07 07 07 23 tCK @ CLMAX -1 (Byte 18) [ns] tAC SDRAM @ CLMAX -1 [ns] tCK @ CLMAX -2 (Byte 18) [ns] tAC SDRAM @ CLMAX -2 [ns] tRP.MIN [ns] tRRD.MIN [ns] tRCD.MIN [ns] tRAS.MIN [ns] 24 25 26 27 28 29 30 30 30 30 30 30 30 45 45 45 45 45 45 50 50 50 50 50 50 60 60 60 60 60 60 30 30 30 30 30 30 28 28 1E 1E 1E 1E 30 30 30 30 30 30 2D 2D 2D 2D 2D 2D 31 Module Density per Rank 40 40 80 80 80 80 32 tAS.MIN and tCS.MIN [ns] tAH.MIN and tCH.MIN [ns] tDS.MIN [ns] tDH.MIN [ns] tWR.MIN [ns] tWTR.MIN [ns] tRTP.MIN [ns] 20 20 20 20 20 20 27 27 27 27 27 27 10 10 10 10 10 10 17 17 17 17 17 17 3C 3C 3C 3C 3C 3C 1E 1E 1E 1E 1E 1E 1E 1E 1E 1E 1E 1E 33 34 35 36 37 38 39 Analysis Characteristics 00 00 00 00 00 00 40 00 00 00 00 00 00 39 39 39 39 39 39 69 69 69 69 69 69 80 80 80 80 80 80 18 18 18 18 18 18 45 tRC and tRFC Extension tRC.MIN [ns] tRFC.MIN [ns] tCK.MAX [ns] tDQSQ.MAX [ns] tQHS.MAX [ns] 46 PLL Relock Time 41 42 43 44 Rev. 1.0, 2006-10 10202006-L0SM-FEYT 60 22 22 22 22 22 22 00 00 00 00 00 00 Internet Data Sheet Product Type HYS64T32000EU–3–B2 HYS64T32900EU–3–B2 HYS64T64000EU–3–B2 HYS64T64900EU–3–B2 HYS72T64000EU–3–B2 HYS72T64900EU–3–B2 HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module Organization 256MB 256MB 512MB 512MB 512MB 512MB ×64 ×64 ×64 ×64 ×72 ×72 1 Rank (×16) 1 Rank (×16) 1 Rank (×8) 1 Rank (×8) 1 Rank (×8) 1 Rank (×8) Label Code PC2– PC2– PC2– PC2– PC2– PC2– 5300U– 5300U– 5300U– 5300U– 5300E– 5300E– 444 444 444 444 444 444 JEDEC SPD Revision Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Byte# Description HEX HEX HEX HEX HEX HEX 47 TCASE.MAX Delta / ∆T4R4W Delta 54 54 50 50 50 50 48 Psi(T-A) DRAM 7A 7A 7A 7A 7A 7A 49 ∆T0 (DT0) 6F 6F 53 53 53 53 50 ∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM) 34 34 34 34 34 34 51 ∆T2P (DT2P) 36 36 36 36 36 36 52 ∆T3N (DT3N) 27 27 27 27 27 27 53 ∆T3P.fast (DT3P fast) 4C 4C 4C 4C 4C 4C 54 ∆T3P.slow (DT3P slow) 2A 2A 2A 2A 2A 2A 55 ∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W) 5A 5A 4C 4C 4C 4C 56 ∆T5B (DT5B) 20 20 20 20 20 20 57 ∆T7 (DT7) 3A 3A 25 25 25 25 58 Psi(ca) PLL 00 00 00 00 00 00 59 Psi(ca) REG 00 00 00 00 00 00 60 ∆TPLL (DTPLL) 00 00 00 00 00 00 61 ∆TREG (DTREG) / Toggle Rate 00 00 00 00 00 00 62 SPD Revision 12 12 12 12 12 12 63 Checksum of Bytes 0-62 0B 0B F7 F7 09 09 64 Manufacturer’s JEDEC ID Code (1) 7F 7F 7F 7F 7F 7F 65 Manufacturer’s JEDEC ID Code (2) 7F 7F 7F 7F 7F 7F 66 Manufacturer’s JEDEC ID Code (3) 7F 7F 7F 7F 7F 7F 67 Manufacturer’s JEDEC ID Code (4) 7F 7F 7F 7F 7F 7F 68 Manufacturer’s JEDEC ID Code (5) 7F 7F 7F 7F 7F 7F 69 Manufacturer’s JEDEC ID Code (6) 51 51 51 51 51 51 70 Manufacturer’s JEDEC ID Code (7) 00 00 00 00 00 00 71 Manufacturer’s JEDEC ID Code (8) 00 00 00 00 00 00 Rev. 1.0, 2006-10 10202006-L0SM-FEYT 61 Internet Data Sheet Product Type HYS64T32000EU–3–B2 HYS64T32900EU–3–B2 HYS64T64000EU–3–B2 HYS64T64900EU–3–B2 HYS72T64000EU–3–B2 HYS72T64900EU–3–B2 HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module Organization 256MB 256MB 512MB 512MB 512MB 512MB ×64 ×64 ×64 ×64 ×72 ×72 1 Rank (×16) 1 Rank (×16) 1 Rank (×8) 1 Rank (×8) 1 Rank (×8) 1 Rank (×8) Label Code PC2– PC2– PC2– PC2– PC2– PC2– 5300U– 5300U– 5300U– 5300U– 5300E– 5300E– 444 444 444 444 444 444 JEDEC SPD Revision Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Byte# Description HEX HEX HEX HEX HEX HEX 72 Module Manufacturer Location xx xx xx xx xx xx 73 Product Type, Char 1 36 36 36 36 37 37 74 Product Type, Char 2 34 34 34 34 32 32 75 Product Type, Char 3 54 54 54 54 54 54 76 Product Type, Char 4 33 33 36 36 36 36 77 Product Type, Char 5 32 32 34 34 34 34 78 Product Type, Char 6 30 39 30 39 30 39 79 Product Type, Char 7 30 30 30 30 30 30 80 Product Type, Char 8 30 30 30 30 30 30 81 Product Type, Char 9 45 45 45 45 45 45 82 Product Type, Char 10 55 55 55 55 55 55 83 Product Type, Char 11 33 33 33 33 33 33 84 Product Type, Char 12 42 42 42 42 42 42 85 Product Type, Char 13 32 32 32 32 32 32 86 Product Type, Char 14 20 20 20 20 20 20 87 Product Type, Char 15 20 20 20 20 20 20 88 Product Type, Char 16 20 20 20 20 20 20 89 Product Type, Char 17 20 20 20 20 20 20 90 Product Type, Char 18 20 20 20 20 20 20 91 Module Revision Code 2x 0x 2x 0x 2x 0x 92 Test Program Revision Code xx xx xx xx xx xx 93 Module Manufacturing Date Year xx xx xx xx xx xx 94 Module Manufacturing Date Week xx xx xx xx xx xx 95 - 98 Module Serial Number xx xx xx xx xx xx Rev. 1.0, 2006-10 10202006-L0SM-FEYT 62 Internet Data Sheet Product Type HYS64T32000EU–3–B2 HYS64T32900EU–3–B2 HYS64T64000EU–3–B2 HYS64T64900EU–3–B2 HYS72T64000EU–3–B2 HYS72T64900EU–3–B2 HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module Organization 256MB 256MB 512MB 512MB 512MB 512MB ×64 ×64 ×64 ×64 ×72 ×72 1 Rank (×16) 1 Rank (×16) 1 Rank (×8) 1 Rank (×8) 1 Rank (×8) 1 Rank (×8) Label Code PC2– PC2– PC2– PC2– PC2– PC2– 5300U– 5300U– 5300U– 5300U– 5300E– 5300E– 444 444 444 444 444 444 JEDEC SPD Revision Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Byte# HEX HEX HEX HEX HEX HEX 99 - 127 Not used 00 00 00 00 00 00 128 255 FF FF FF FF FF FF Description Blank for customer use Rev. 1.0, 2006-10 10202006-L0SM-FEYT 63 Internet Data Sheet HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module TABLE 32 Product Type HYS64T128020EU–3–B2 HYS64T128920EU–3–B2 HYS72T128020EU–3–B2 HYS72T128920EU–3–B2 SPD Codes for PC2–5300–444 Organization 1 GByte 1 GByte 1 GByte 1 GByte ×64 ×64 ×72 ×72 2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8) Label Code PC2– 5300U–444 PC2– 5300U–444 PC2– 5300E–444 PC2– 5300E–444 JEDEC SPD Revision Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Byte# Description HEX HEX HEX HEX 0 Programmed SPD Bytes in EEPROM 80 80 80 80 1 Total number of Bytes in EEPROM 08 08 08 08 2 Memory Type (DDR2) 08 08 08 08 3 Number of Row Addresses 0E 0E 0E 0E 4 Number of Column Addresses 0A 0A 0A 0A 5 DIMM Rank and Stacking Information 61 61 61 61 6 Data Width 40 40 48 48 7 Not used 00 00 00 00 8 Interface Voltage Level 05 05 05 05 9 tCK @ CLMAX (Byte 18) [ns] tAC SDRAM @ CLMAX (Byte 18) [ns] 30 30 30 30 10 45 45 45 45 11 Error Correction Support (non-ECC, ECC) 00 00 02 02 12 Refresh Rate and Type 82 82 82 82 13 Primary SDRAM Width 08 08 08 08 14 Error Checking SDRAM Width 00 00 08 08 15 Not used 00 00 00 00 16 Burst Length Supported 0C 0C 0C 0C 17 Number of Banks on SDRAM Device 04 04 04 04 18 Supported CAS Latencies 38 38 38 38 19 DIMM Mechanical Characteristics 01 01 01 01 20 DIMM Type Information 02 02 02 02 21 DIMM Attributes 00 00 00 00 22 Component Attributes 07 07 07 07 Rev. 1.0, 2006-10 10202006-L0SM-FEYT 64 Internet Data Sheet Product Type HYS64T128020EU–3–B2 HYS64T128920EU–3–B2 HYS72T128020EU–3–B2 HYS72T128920EU–3–B2 HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module Organization 1 GByte 1 GByte 1 GByte 1 GByte ×64 ×64 ×72 ×72 2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8) Label Code PC2– 5300U–444 PC2– 5300U–444 PC2– 5300E–444 PC2– 5300E–444 JEDEC SPD Revision Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Byte# Description HEX HEX HEX HEX 23 tCK @ CLMAX -1 (Byte 18) [ns] tAC SDRAM @ CLMAX -1 [ns] tCK @ CLMAX -2 (Byte 18) [ns] tAC SDRAM @ CLMAX -2 [ns] tRP.MIN [ns] tRRD.MIN [ns] tRCD.MIN [ns] tRAS.MIN [ns] 24 25 26 27 28 29 30 30 30 30 30 45 45 45 45 50 50 50 50 60 60 60 60 30 30 30 30 1E 1E 1E 1E 30 30 30 30 2D 2D 2D 2D 31 Module Density per Rank 80 80 80 80 32 tAS.MIN and tCS.MIN [ns] tAH.MIN and tCH.MIN [ns] tDS.MIN [ns] tDH.MIN [ns] tWR.MIN [ns] tWTR.MIN [ns] tRTP.MIN [ns] 20 20 20 20 27 27 27 27 10 10 10 10 17 17 17 17 3C 3C 3C 3C 1E 1E 1E 1E 1E 1E 1E 1E 33 34 35 36 37 38 39 Analysis Characteristics 00 00 00 00 40 00 00 00 00 39 39 39 39 69 69 69 69 80 80 80 80 18 18 18 18 45 tRC and tRFC Extension tRC.MIN [ns] tRFC.MIN [ns] tCK.MAX [ns] tDQSQ.MAX [ns] tQHS.MAX [ns] 46 PLL Relock Time 41 42 43 44 22 22 22 22 00 00 00 00 47 TCASE.MAX Delta / ∆T4R4W Delta 50 50 50 50 48 Psi(T-A) DRAM 7A 7A 7A 7A Rev. 1.0, 2006-10 10202006-L0SM-FEYT 65 Internet Data Sheet Product Type HYS64T128020EU–3–B2 HYS64T128920EU–3–B2 HYS72T128020EU–3–B2 HYS72T128920EU–3–B2 HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module Organization 1 GByte 1 GByte 1 GByte 1 GByte ×64 ×64 ×72 ×72 2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8) Label Code PC2– 5300U–444 PC2– 5300U–444 PC2– 5300E–444 PC2– 5300E–444 JEDEC SPD Revision Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Byte# Description HEX HEX HEX HEX 49 ∆T0 (DT0) 53 53 53 53 50 ∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM) 34 34 34 34 51 ∆T2P (DT2P) 36 36 36 36 52 ∆T3N (DT3N) 27 27 27 27 53 ∆T3P.fast (DT3P fast) 4C 4C 4C 4C 54 ∆T3P.slow (DT3P slow) 2A 2A 2A 2A 55 ∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W) 4C 4C 4C 4C 56 ∆T5B (DT5B) 20 20 20 20 57 ∆T7 (DT7) 25 25 25 25 58 Psi(ca) PLL 00 00 00 00 59 Psi(ca) REG 00 00 00 00 60 ∆TPLL (DTPLL) 00 00 00 00 61 ∆TREG (DTREG) / Toggle Rate 00 00 00 00 62 SPD Revision 12 12 12 12 63 Checksum of Bytes 0-62 F8 F8 0A 0A 64 Manufacturer’s JEDEC ID Code (1) 7F 7F 7F 7F 65 Manufacturer’s JEDEC ID Code (2) 7F 7F 7F 7F 66 Manufacturer’s JEDEC ID Code (3) 7F 7F 7F 7F 67 Manufacturer’s JEDEC ID Code (4) 7F 7F 7F 7F 68 Manufacturer’s JEDEC ID Code (5) 7F 7F 7F 7F 69 Manufacturer’s JEDEC ID Code (6) 51 51 51 51 70 Manufacturer’s JEDEC ID Code (7) 00 00 00 00 71 Manufacturer’s JEDEC ID Code (8) 00 00 00 00 72 Module Manufacturer Location xx xx xx xx 73 Product Type, Char 1 36 36 37 37 74 Product Type, Char 2 34 34 32 32 Rev. 1.0, 2006-10 10202006-L0SM-FEYT 66 Internet Data Sheet Product Type HYS64T128020EU–3–B2 HYS64T128920EU–3–B2 HYS72T128020EU–3–B2 HYS72T128920EU–3–B2 HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module Organization 1 GByte 1 GByte 1 GByte 1 GByte ×64 ×64 ×72 ×72 2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8) Label Code PC2– 5300U–444 PC2– 5300U–444 PC2– 5300E–444 PC2– 5300E–444 JEDEC SPD Revision Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Byte# Description HEX HEX HEX HEX 75 Product Type, Char 3 54 54 54 54 76 Product Type, Char 4 31 31 31 31 77 Product Type, Char 5 32 32 32 32 78 Product Type, Char 6 38 38 38 38 79 Product Type, Char 7 30 39 30 39 80 Product Type, Char 8 32 32 32 32 81 Product Type, Char 9 30 30 30 30 82 Product Type, Char 10 45 45 45 45 83 Product Type, Char 11 55 55 55 55 84 Product Type, Char 12 33 33 33 33 85 Product Type, Char 13 42 42 42 42 86 Product Type, Char 14 32 32 32 32 87 Product Type, Char 15 20 20 20 20 88 Product Type, Char 16 20 20 20 20 89 Product Type, Char 17 20 20 20 20 90 Product Type, Char 18 20 20 20 20 91 Module Revision Code 2x 0x 2x 0x 92 Test Program Revision Code xx xx xx xx 93 Module Manufacturing Date Year xx xx xx xx 94 Module Manufacturing Date Week xx xx xx xx 95 - 98 Module Serial Number xx xx xx xx 99 - 127 Not used 00 00 00 00 128 255 FF FF FF FF Blank for customer use Rev. 1.0, 2006-10 10202006-L0SM-FEYT 67 Internet Data Sheet HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module TABLE 33 Product Type HYS64T32000EU–3S–B2 HYS64T32900EU–3S–B2 HYS64T64000EU–3S–B2 HYS64T64900EU–3S–B2 HYS72T64000EU–3S–B2 HYS72T64900EU–3S–B2 SPD Codes for PC2–5300–555 Organization 256MB 256MB 512MB 512MB 512MB 512MB ×64 ×64 ×64 ×64 ×72 ×72 1 Rank (×16) 1 Rank (×16) 1 Rank (×8) 1 Rank (×8) 1 Rank (×8) 1 Rank (×8) Label Code PC2– PC2– PC2– PC2– PC2– PC2– 5300U– 5300U– 5300U– 5300U– 5300E– 5300E– 555 555 555 555 555 555 JEDEC SPD Revision Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Byte# Description HEX HEX HEX HEX HEX HEX 0 Programmed SPD Bytes in EEPROM 80 80 80 80 80 80 1 Total number of Bytes in EEPROM 08 08 08 08 08 08 2 Memory Type (DDR2) 08 08 08 08 08 08 3 Number of Row Addresses 0D 0D 0E 0E 0E 0E 4 Number of Column Addresses 0A 0A 0A 0A 0A 0A 5 DIMM Rank and Stacking Information 60 60 60 60 60 60 6 Data Width 40 40 40 40 48 48 7 Not used 00 00 00 00 00 00 8 Interface Voltage Level 05 05 05 05 05 05 9 tCK @ CLMAX (Byte 18) [ns] tAC SDRAM @ CLMAX (Byte 18) [ns] 30 30 30 30 30 30 10 45 45 45 45 45 45 11 Error Correction Support (non-ECC, ECC) 00 00 00 00 02 02 12 Refresh Rate and Type 82 82 82 82 82 82 13 Primary SDRAM Width 10 10 08 08 08 08 14 Error Checking SDRAM Width 00 00 00 00 08 08 15 Not used 00 00 00 00 00 00 16 Burst Length Supported 0C 0C 0C 0C 0C 0C 17 Number of Banks on SDRAM Device 04 04 04 04 04 04 18 Supported CAS Latencies 38 38 38 38 38 38 19 DIMM Mechanical Characteristics 01 01 01 01 01 01 20 DIMM Type Information 02 02 02 02 02 02 21 DIMM Attributes 00 00 00 00 00 00 Rev. 1.0, 2006-10 10202006-L0SM-FEYT 68 Internet Data Sheet Product Type HYS64T32000EU–3S–B2 HYS64T32900EU–3S–B2 HYS64T64000EU–3S–B2 HYS64T64900EU–3S–B2 HYS72T64000EU–3S–B2 HYS72T64900EU–3S–B2 HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module Organization 256MB 256MB 512MB 512MB 512MB 512MB ×64 ×64 ×64 ×64 ×72 ×72 1 Rank (×16) 1 Rank (×16) 1 Rank (×8) 1 Rank (×8) 1 Rank (×8) 1 Rank (×8) Label Code PC2– PC2– PC2– PC2– PC2– PC2– 5300U– 5300U– 5300U– 5300U– 5300E– 5300E– 555 555 555 555 555 555 JEDEC SPD Revision Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Byte# Description HEX HEX HEX HEX HEX HEX 22 Component Attributes 07 07 07 07 07 07 23 3D 3D 3D 3D 3D 3D 50 50 50 50 50 50 30 tCK @ CLMAX -1 (Byte 18) [ns] tAC SDRAM @ CLMAX -1 [ns] tCK @ CLMAX -2 (Byte 18) [ns] tAC SDRAM @ CLMAX -2 [ns] tRP.MIN [ns] tRRD.MIN [ns] tRCD.MIN [ns] tRAS.MIN [ns] 2D 2D 2D 2D 2D 2D 31 Module Density per Rank 40 40 80 80 80 80 32 20 20 20 20 20 20 38 tAS.MIN and tCS.MIN [ns] tAH.MIN and tCH.MIN [ns] tDS.MIN [ns] tDH.MIN [ns] tWR.MIN [ns] tWTR.MIN [ns] tRTP.MIN [ns] 1E 1E 1E 1E 1E 1E 39 Analysis Characteristics 00 00 00 00 00 00 40 tRC and tRFC Extension tRC.MIN [ns] tRFC.MIN [ns] tCK.MAX [ns] tDQSQ.MAX [ns] tQHS.MAX [ns] 00 00 00 00 00 00 24 25 26 27 28 29 33 34 35 36 37 41 42 43 44 45 Rev. 1.0, 2006-10 10202006-L0SM-FEYT 69 50 50 50 50 50 50 60 60 60 60 60 60 3C 3C 3C 3C 3C 3C 28 28 1E 1E 1E 1E 3C 3C 3C 3C 3C 3C 27 27 27 27 27 27 10 10 10 10 10 10 17 17 17 17 17 17 3C 3C 3C 3C 3C 3C 1E 1E 1E 1E 1E 1E 3C 3C 3C 3C 3C 3C 69 69 69 69 69 69 80 80 80 80 80 80 18 18 18 18 18 18 22 22 22 22 22 22 Internet Data Sheet Product Type HYS64T32000EU–3S–B2 HYS64T32900EU–3S–B2 HYS64T64000EU–3S–B2 HYS64T64900EU–3S–B2 HYS72T64000EU–3S–B2 HYS72T64900EU–3S–B2 HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module Organization 256MB 256MB 512MB 512MB 512MB 512MB ×64 ×64 ×64 ×64 ×72 ×72 1 Rank (×16) 1 Rank (×16) 1 Rank (×8) 1 Rank (×8) 1 Rank (×8) 1 Rank (×8) Label Code PC2– PC2– PC2– PC2– PC2– PC2– 5300U– 5300U– 5300U– 5300U– 5300E– 5300E– 555 555 555 555 555 555 JEDEC SPD Revision Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Byte# Description HEX HEX HEX HEX HEX HEX 46 PLL Relock Time 00 00 00 00 00 00 47 TCASE.MAX Delta / ∆T4R4W Delta 54 54 50 50 50 50 48 Psi(T-A) DRAM 7A 7A 7A 7A 7A 7A 49 ∆T0 (DT0) 67 67 4B 4B 4B 4B 50 ∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM) 34 34 34 34 34 34 51 ∆T2P (DT2P) 36 36 36 36 36 36 52 ∆T3N (DT3N) 27 27 27 27 27 27 53 ∆T3P.fast (DT3P fast) 4C 4C 4C 4C 4C 4C 54 ∆T3P.slow (DT3P slow) 2A 2A 2A 2A 2A 2A 55 ∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W) 5A 5A 4C 4C 4C 4C 56 ∆T5B (DT5B) 20 20 20 20 20 20 57 ∆T7 (DT7) 38 38 23 23 23 23 58 Psi(ca) PLL 00 00 00 00 00 00 59 Psi(ca) REG 00 00 00 00 00 00 60 ∆TPLL (DTPLL) 00 00 00 00 00 00 61 ∆TREG (DTREG) / Toggle Rate 00 00 00 00 00 00 62 SPD Revision 12 12 12 12 12 12 63 Checksum of Bytes 0-62 34 34 20 20 32 32 64 Manufacturer’s JEDEC ID Code (1) 7F 7F 7F 7F 7F 7F 65 Manufacturer’s JEDEC ID Code (2) 7F 7F 7F 7F 7F 7F 66 Manufacturer’s JEDEC ID Code (3) 7F 7F 7F 7F 7F 7F 67 Manufacturer’s JEDEC ID Code (4) 7F 7F 7F 7F 7F 7F 68 Manufacturer’s JEDEC ID Code (5) 7F 7F 7F 7F 7F 7F 69 Manufacturer’s JEDEC ID Code (6) 51 51 51 51 51 51 Rev. 1.0, 2006-10 10202006-L0SM-FEYT 70 Internet Data Sheet Product Type HYS64T32000EU–3S–B2 HYS64T32900EU–3S–B2 HYS64T64000EU–3S–B2 HYS64T64900EU–3S–B2 HYS72T64000EU–3S–B2 HYS72T64900EU–3S–B2 HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module Organization 256MB 256MB 512MB 512MB 512MB 512MB ×64 ×64 ×64 ×64 ×72 ×72 1 Rank (×16) 1 Rank (×16) 1 Rank (×8) 1 Rank (×8) 1 Rank (×8) 1 Rank (×8) Label Code PC2– PC2– PC2– PC2– PC2– PC2– 5300U– 5300U– 5300U– 5300U– 5300E– 5300E– 555 555 555 555 555 555 JEDEC SPD Revision Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Byte# Description HEX HEX HEX HEX HEX HEX 70 Manufacturer’s JEDEC ID Code (7) 00 00 00 00 00 00 71 Manufacturer’s JEDEC ID Code (8) 00 00 00 00 00 00 72 Module Manufacturer Location xx xx xx xx xx xx 73 Product Type, Char 1 36 36 36 36 37 37 74 Product Type, Char 2 34 34 34 34 32 32 75 Product Type, Char 3 54 54 54 54 54 54 76 Product Type, Char 4 33 33 36 36 36 36 77 Product Type, Char 5 32 32 34 34 34 34 78 Product Type, Char 6 30 39 30 39 30 39 79 Product Type, Char 7 30 30 30 30 30 30 80 Product Type, Char 8 30 30 30 30 30 30 81 Product Type, Char 9 45 45 45 45 45 45 82 Product Type, Char 10 55 55 55 55 55 55 83 Product Type, Char 11 33 33 33 33 33 33 84 Product Type, Char 12 53 53 53 53 53 53 85 Product Type, Char 13 42 42 42 42 42 42 86 Product Type, Char 14 32 32 32 32 32 32 87 Product Type, Char 15 20 20 20 20 20 20 88 Product Type, Char 16 20 20 20 20 20 20 89 Product Type, Char 17 20 20 20 20 20 20 90 Product Type, Char 18 20 20 20 20 20 20 91 Module Revision Code 2x 0x 2x 0x 2x 0x 92 Test Program Revision Code xx xx xx xx xx xx 93 Module Manufacturing Date Year xx xx xx xx xx xx Rev. 1.0, 2006-10 10202006-L0SM-FEYT 71 Internet Data Sheet Product Type HYS64T32000EU–3S–B2 HYS64T32900EU–3S–B2 HYS64T64000EU–3S–B2 HYS64T64900EU–3S–B2 HYS72T64000EU–3S–B2 HYS72T64900EU–3S–B2 HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module Organization 256MB 256MB 512MB 512MB 512MB 512MB ×64 ×64 ×64 ×64 ×72 ×72 1 Rank (×16) 1 Rank (×16) 1 Rank (×8) 1 Rank (×8) 1 Rank (×8) 1 Rank (×8) Label Code PC2– PC2– PC2– PC2– PC2– PC2– 5300U– 5300U– 5300U– 5300U– 5300E– 5300E– 555 555 555 555 555 555 JEDEC SPD Revision Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Byte# Description HEX HEX HEX HEX HEX HEX 94 Module Manufacturing Date Week xx xx xx xx xx xx 95 - 98 Module Serial Number xx xx xx xx xx xx 99 - 127 Not used 00 00 00 00 00 00 128 255 FF FF FF FF FF FF Blank for customer use Rev. 1.0, 2006-10 10202006-L0SM-FEYT 72 Internet Data Sheet HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module TABLE 34 Product Type HYS64T128020EU–3S–B2 HYS64T128920EU–3S–B2 HYS72T128020EU–3S–B2 HYS72T128920EU–3S–B2 SPD Codes for PC2–5300–555 Organization 1 GByte 1 GByte 1 GByte 1 GByte ×64 ×64 ×72 ×72 2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8) Label Code PC2– 5300U–555 PC2– 5300U–555 PC2– 5300E–555 PC2– 5300E–555 JEDEC SPD Revision Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Byte# Description HEX HEX HEX HEX 0 Programmed SPD Bytes in EEPROM 80 80 80 80 1 Total number of Bytes in EEPROM 08 08 08 08 2 Memory Type (DDR2) 08 08 08 08 3 Number of Row Addresses 0E 0E 0E 0E 4 Number of Column Addresses 0A 0A 0A 0A 5 DIMM Rank and Stacking Information 61 61 61 61 6 Data Width 40 40 48 48 7 Not used 00 00 00 00 8 Interface Voltage Level 05 05 05 05 9 tCK @ CLMAX (Byte 18) [ns] tAC SDRAM @ CLMAX (Byte 18) [ns] 30 30 30 30 45 45 45 45 11 Error Correction Support (non-ECC, ECC) 00 00 02 02 12 Refresh Rate and Type 82 82 82 82 13 Primary SDRAM Width 08 08 08 08 14 Error Checking SDRAM Width 00 00 08 08 15 Not used 00 00 00 00 16 Burst Length Supported 0C 0C 0C 0C 17 Number of Banks on SDRAM Device 04 04 04 04 18 Supported CAS Latencies 38 38 38 38 19 DIMM Mechanical Characteristics 01 01 01 01 20 DIMM Type Information 02 02 02 02 10 21 DIMM Attributes 00 00 00 00 22 Component Attributes 07 07 07 07 Rev. 1.0, 2006-10 10202006-L0SM-FEYT 73 Internet Data Sheet Product Type HYS64T128020EU–3S–B2 HYS64T128920EU–3S–B2 HYS72T128020EU–3S–B2 HYS72T128920EU–3S–B2 HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module Organization 1 GByte 1 GByte 1 GByte 1 GByte ×64 ×64 ×72 ×72 2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8) Label Code PC2– 5300U–555 PC2– 5300U–555 PC2– 5300E–555 PC2– 5300E–555 JEDEC SPD Revision Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Byte# Description HEX HEX HEX HEX 23 3D 3D 3D 3D 50 50 50 50 30 tCK @ CLMAX -1 (Byte 18) [ns] tAC SDRAM @ CLMAX -1 [ns] tCK @ CLMAX -2 (Byte 18) [ns] tAC SDRAM @ CLMAX -2 [ns] tRP.MIN [ns] tRRD.MIN [ns] tRCD.MIN [ns] tRAS.MIN [ns] 2D 2D 2D 2D 31 Module Density per Rank 80 80 80 80 32 20 20 20 20 38 tAS.MIN and tCS.MIN [ns] tAH.MIN and tCH.MIN [ns] tDS.MIN [ns] tDH.MIN [ns] tWR.MIN [ns] tWTR.MIN [ns] tRTP.MIN [ns] 1E 1E 1E 1E 39 Analysis Characteristics 00 00 00 00 40 tRC and tRFC Extension tRC.MIN [ns] tRFC.MIN [ns] tCK.MAX [ns] tDQSQ.MAX [ns] tQHS.MAX [ns] 00 00 00 00 24 25 26 27 28 29 33 34 35 36 37 41 42 43 44 45 50 50 50 50 60 60 60 60 3C 3C 3C 3C 1E 1E 1E 1E 3C 3C 3C 3C 27 27 27 27 10 10 10 10 17 17 17 17 3C 3C 3C 3C 1E 1E 1E 1E 3C 3C 3C 3C 69 69 69 69 80 80 80 80 18 18 18 18 22 22 22 22 46 PLL Relock Time 00 00 00 00 47 TCASE.MAX Delta / ∆T4R4W Delta 50 50 50 50 Rev. 1.0, 2006-10 10202006-L0SM-FEYT 74 Internet Data Sheet Product Type HYS64T128020EU–3S–B2 HYS64T128920EU–3S–B2 HYS72T128020EU–3S–B2 HYS72T128920EU–3S–B2 HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module Organization 1 GByte 1 GByte 1 GByte 1 GByte ×64 ×64 ×72 ×72 2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8) Label Code PC2– 5300U–555 PC2– 5300U–555 PC2– 5300E–555 PC2– 5300E–555 JEDEC SPD Revision Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Byte# Description HEX HEX HEX HEX 48 Psi(T-A) DRAM 7A 7A 7A 7A 49 ∆T0 (DT0) 4B 4B 4B 4B 50 ∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM) 34 34 34 34 51 ∆T2P (DT2P) 36 36 36 36 52 ∆T3N (DT3N) 27 27 27 27 53 ∆T3P.fast (DT3P fast) 4C 4C 4C 4C 54 ∆T3P.slow (DT3P slow) 2A 2A 2A 2A 55 ∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W) 4C 4C 4C 4C 56 ∆T5B (DT5B) 20 20 20 20 57 ∆T7 (DT7) 23 23 23 23 58 Psi(ca) PLL 00 00 00 00 59 Psi(ca) REG 00 00 00 00 60 ∆TPLL (DTPLL) 00 00 00 00 61 ∆TREG (DTREG) / Toggle Rate 00 00 00 00 62 SPD Revision 12 12 12 12 63 Checksum of Bytes 0-62 21 21 33 33 64 Manufacturer’s JEDEC ID Code (1) 7F 7F 7F 7F 65 Manufacturer’s JEDEC ID Code (2) 7F 7F 7F 7F 66 Manufacturer’s JEDEC ID Code (3) 7F 7F 7F 7F 67 Manufacturer’s JEDEC ID Code (4) 7F 7F 7F 7F 68 Manufacturer’s JEDEC ID Code (5) 7F 7F 7F 7F 69 Manufacturer’s JEDEC ID Code (6) 51 51 51 51 70 Manufacturer’s JEDEC ID Code (7) 00 00 00 00 71 Manufacturer’s JEDEC ID Code (8) 00 00 00 00 72 Module Manufacturer Location xx xx xx xx Rev. 1.0, 2006-10 10202006-L0SM-FEYT 75 Internet Data Sheet Product Type HYS64T128020EU–3S–B2 HYS64T128920EU–3S–B2 HYS72T128020EU–3S–B2 HYS72T128920EU–3S–B2 HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module Organization 1 GByte 1 GByte 1 GByte 1 GByte ×64 ×64 ×72 ×72 2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8) Label Code PC2– 5300U–555 PC2– 5300U–555 PC2– 5300E–555 PC2– 5300E–555 JEDEC SPD Revision Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Byte# Description HEX HEX HEX HEX 73 Product Type, Char 1 36 36 37 37 74 Product Type, Char 2 34 34 32 32 75 Product Type, Char 3 54 54 54 54 76 Product Type, Char 4 31 31 31 31 77 Product Type, Char 5 32 32 32 32 78 Product Type, Char 6 38 38 38 38 79 Product Type, Char 7 30 39 30 39 80 Product Type, Char 8 32 32 32 32 81 Product Type, Char 9 30 30 30 30 82 Product Type, Char 10 45 45 45 45 83 Product Type, Char 11 55 55 55 55 84 Product Type, Char 12 33 33 33 33 85 Product Type, Char 13 53 53 53 53 86 Product Type, Char 14 42 42 42 42 87 Product Type, Char 15 32 32 32 32 88 Product Type, Char 16 20 20 20 20 89 Product Type, Char 17 20 20 20 20 90 Product Type, Char 18 20 20 20 20 91 Module Revision Code 2x 0x 2x 0x 92 Test Program Revision Code xx xx xx xx 93 Module Manufacturing Date Year xx xx xx xx 94 Module Manufacturing Date Week xx xx xx xx 95 - 98 Module Serial Number xx xx xx xx 99 - 127 Not used 00 00 00 00 128 255 FF FF FF FF Blank for customer use Rev. 1.0, 2006-10 10202006-L0SM-FEYT 76 Internet Data Sheet HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module TABLE 35 Product Type HYS64T32000EU–3.7–B2 HYS64T32900EU–3.7–B2 HYS64T64000EU–3.7–B2 HYS64T64900EU–3.7–B2 HYS72T64000EU–3.7–B2 HYS72T64900EU–3.7–B2 SPD Codes for PC2–4200–444 Organization 256MB 256MB 512MB 512MB 512MB 512MB ×64 ×64 ×64 ×64 ×72 ×72 1 Rank (×16) 1 Rank (×16) 1 Rank (×8) 1 Rank (×8) 1 Rank (×8) 1 Rank (×8) Label Code PC2– PC2– PC2– PC2– PC2– PC2– 4200U– 4200U– 4200U– 4200U– 4200E– 4200E– 444 444 444 444 444 444 JEDEC SPD Revision Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Byte# Description HEX HEX HEX HEX HEX HEX 0 Programmed SPD Bytes in EEPROM 80 80 80 80 80 80 1 Total number of Bytes in EEPROM 08 08 08 08 08 08 2 Memory Type (DDR2) 08 08 08 08 08 08 3 Number of Row Addresses 0D 0D 0E 0E 0E 0E 4 Number of Column Addresses 0A 0A 0A 0A 0A 0A 5 DIMM Rank and Stacking Information 60 60 60 60 60 60 6 Data Width 40 40 40 40 48 48 7 Not used 00 00 00 00 00 00 8 Interface Voltage Level 05 05 05 05 05 05 9 3D 3D 3D 3D 3D 3D 10 tCK @ CLMAX (Byte 18) [ns] tAC SDRAM @ CLMAX (Byte 18) [ns] 50 50 50 50 50 50 11 Error Correction Support (non-ECC, ECC) 00 00 00 00 02 02 12 Refresh Rate and Type 82 82 82 82 82 82 13 Primary SDRAM Width 10 10 08 08 08 08 14 Error Checking SDRAM Width 00 00 00 00 08 08 15 Not used 00 00 00 00 00 00 16 Burst Length Supported 0C 0C 0C 0C 0C 0C 17 Number of Banks on SDRAM Device 04 04 04 04 04 04 18 Supported CAS Latencies 38 38 38 38 38 38 19 DIMM Mechanical Characteristics 01 01 01 01 01 01 20 DIMM Type Information 02 02 02 02 02 02 Rev. 1.0, 2006-10 10202006-L0SM-FEYT 77 Internet Data Sheet Product Type HYS64T32000EU–3.7–B2 HYS64T32900EU–3.7–B2 HYS64T64000EU–3.7–B2 HYS64T64900EU–3.7–B2 HYS72T64000EU–3.7–B2 HYS72T64900EU–3.7–B2 HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module Organization 256MB 256MB 512MB 512MB 512MB 512MB ×64 ×64 ×64 ×64 ×72 ×72 1 Rank (×16) 1 Rank (×16) 1 Rank (×8) 1 Rank (×8) 1 Rank (×8) 1 Rank (×8) Label Code PC2– PC2– PC2– PC2– PC2– PC2– 4200U– 4200U– 4200U– 4200U– 4200E– 4200E– 444 444 444 444 444 444 JEDEC SPD Revision Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Byte# Description HEX HEX HEX HEX HEX HEX 21 DIMM Attributes 00 00 00 00 00 00 22 Component Attributes 07 07 07 07 07 07 23 3D 3D 3D 3D 3D 3D 50 50 50 50 50 50 30 tCK @ CLMAX -1 (Byte 18) [ns] tAC SDRAM @ CLMAX -1 [ns] tCK @ CLMAX -2 (Byte 18) [ns] tAC SDRAM @ CLMAX -2 [ns] tRP.MIN [ns] tRRD.MIN [ns] tRCD.MIN [ns] tRAS.MIN [ns] 2D 2D 2D 2D 2D 2D 31 Module Density per Rank 40 40 80 80 80 80 32 25 25 25 25 25 25 38 tAS.MIN and tCS.MIN [ns] tAH.MIN and tCH.MIN [ns] tDS.MIN [ns] tDH.MIN [ns] tWR.MIN [ns] tWTR.MIN [ns] tRTP.MIN [ns] 1E 1E 1E 1E 1E 1E 39 Analysis Characteristics 00 00 00 00 00 00 40 tRC and tRFC Extension tRC.MIN [ns] tRFC.MIN [ns] tCK.MAX [ns] tDQSQ.MAX [ns] 00 00 00 00 00 00 24 25 26 27 28 29 33 34 35 36 37 41 42 43 44 Rev. 1.0, 2006-10 10202006-L0SM-FEYT 78 50 50 50 50 50 50 60 60 60 60 60 60 3C 3C 3C 3C 3C 3C 28 28 1E 1E 1E 1E 3C 3C 3C 3C 3C 3C 37 37 37 37 37 37 10 10 10 10 10 10 22 22 22 22 22 22 3C 3C 3C 3C 3C 3C 1E 1E 1E 1E 1E 1E 3C 3C 3C 3C 3C 3C 69 69 69 69 69 69 80 80 80 80 80 80 1E 1E 1E 1E 1E 1E Internet Data Sheet Product Type HYS64T32000EU–3.7–B2 HYS64T32900EU–3.7–B2 HYS64T64000EU–3.7–B2 HYS64T64900EU–3.7–B2 HYS72T64000EU–3.7–B2 HYS72T64900EU–3.7–B2 HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module Organization 256MB 256MB 512MB 512MB 512MB 512MB ×64 ×64 ×64 ×64 ×72 ×72 1 Rank (×16) 1 Rank (×16) 1 Rank (×8) 1 Rank (×8) 1 Rank (×8) 1 Rank (×8) Label Code PC2– PC2– PC2– PC2– PC2– PC2– 4200U– 4200U– 4200U– 4200U– 4200E– 4200E– 444 444 444 444 444 444 JEDEC SPD Revision Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Byte# Description HEX HEX HEX HEX HEX HEX 45 tQHS.MAX [ns] 28 28 28 28 28 28 46 PLL Relock Time 00 00 00 00 00 00 47 TCASE.MAX Delta / ∆T4R4W Delta 54 54 50 50 50 50 48 Psi(T-A) DRAM 7A 7A 7A 7A 7A 7A 49 ∆T0 (DT0) 5B 5B 43 43 43 43 50 ∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM) 2C 2C 2C 2C 2C 2C 51 ∆T2P (DT2P) 36 36 36 36 36 36 52 ∆T3N (DT3N) 21 21 21 21 21 21 53 ∆T3P.fast (DT3P fast) 41 41 41 41 41 41 54 ∆T3P.slow (DT3P slow) 2A 2A 2A 2A 2A 2A 55 ∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W) 4C 4C 40 40 40 40 56 ∆T5B (DT5B) 1E 1E 1E 1E 1E 1E 57 ∆T7 (DT7) 35 35 22 22 22 22 58 Psi(ca) PLL 00 00 00 00 00 00 59 Psi(ca) REG 00 00 00 00 00 00 60 ∆TPLL (DTPLL) 00 00 00 00 00 00 61 ∆TREG (DTREG) / Toggle Rate 00 00 00 00 00 00 62 SPD Revision 12 12 12 12 12 12 63 Checksum of Bytes 0-62 40 40 34 34 46 46 64 Manufacturer’s JEDEC ID Code (1) 7F 7F 7F 7F 7F 7F 65 Manufacturer’s JEDEC ID Code (2) 7F 7F 7F 7F 7F 7F 66 Manufacturer’s JEDEC ID Code (3) 7F 7F 7F 7F 7F 7F 67 Manufacturer’s JEDEC ID Code (4) 7F 7F 7F 7F 7F 7F 68 Manufacturer’s JEDEC ID Code (5) 7F 7F 7F 7F 7F 7F Rev. 1.0, 2006-10 10202006-L0SM-FEYT 79 Internet Data Sheet Product Type HYS64T32000EU–3.7–B2 HYS64T32900EU–3.7–B2 HYS64T64000EU–3.7–B2 HYS64T64900EU–3.7–B2 HYS72T64000EU–3.7–B2 HYS72T64900EU–3.7–B2 HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module Organization 256MB 256MB 512MB 512MB 512MB 512MB ×64 ×64 ×64 ×64 ×72 ×72 1 Rank (×16) 1 Rank (×16) 1 Rank (×8) 1 Rank (×8) 1 Rank (×8) 1 Rank (×8) Label Code PC2– PC2– PC2– PC2– PC2– PC2– 4200U– 4200U– 4200U– 4200U– 4200E– 4200E– 444 444 444 444 444 444 JEDEC SPD Revision Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Byte# Description HEX HEX HEX HEX HEX HEX 69 Manufacturer’s JEDEC ID Code (6) 51 51 51 51 51 51 70 Manufacturer’s JEDEC ID Code (7) 00 00 00 00 00 00 71 Manufacturer’s JEDEC ID Code (8) 00 00 00 00 00 00 72 Module Manufacturer Location xx xx xx xx xx xx 73 Product Type, Char 1 36 36 36 36 37 37 74 Product Type, Char 2 34 34 34 34 32 32 75 Product Type, Char 3 54 54 54 54 54 54 76 Product Type, Char 4 33 33 36 36 36 36 77 Product Type, Char 5 32 32 34 34 34 34 78 Product Type, Char 6 30 39 30 39 30 39 79 Product Type, Char 7 30 30 30 30 30 30 80 Product Type, Char 8 30 30 30 30 30 30 81 Product Type, Char 9 45 45 45 45 45 45 82 Product Type, Char 10 55 55 55 55 55 55 83 Product Type, Char 11 33 33 33 33 33 33 84 Product Type, Char 12 2E 2E 2E 2E 2E 2E 85 Product Type, Char 13 37 37 37 37 37 37 86 Product Type, Char 14 42 42 42 42 42 42 87 Product Type, Char 15 32 32 32 32 32 32 88 Product Type, Char 16 20 20 20 20 20 20 89 Product Type, Char 17 20 20 20 20 20 20 90 Product Type, Char 18 20 20 20 20 20 20 91 Module Revision Code 2x 0x 2x 0x 2x 0x 92 Test Program Revision Code xx xx xx xx xx xx Rev. 1.0, 2006-10 10202006-L0SM-FEYT 80 Internet Data Sheet Product Type HYS64T32000EU–3.7–B2 HYS64T32900EU–3.7–B2 HYS64T64000EU–3.7–B2 HYS64T64900EU–3.7–B2 HYS72T64000EU–3.7–B2 HYS72T64900EU–3.7–B2 HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module Organization 256MB 256MB 512MB 512MB 512MB 512MB ×64 ×64 ×64 ×64 ×72 ×72 1 Rank (×16) 1 Rank (×16) 1 Rank (×8) 1 Rank (×8) 1 Rank (×8) 1 Rank (×8) Label Code PC2– PC2– PC2– PC2– PC2– PC2– 4200U– 4200U– 4200U– 4200U– 4200E– 4200E– 444 444 444 444 444 444 JEDEC SPD Revision Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Byte# Description HEX HEX HEX HEX HEX HEX 93 Module Manufacturing Date Year xx xx xx xx xx xx 94 Module Manufacturing Date Week xx xx xx xx xx xx 95 - 98 Module Serial Number xx xx xx xx xx xx 99 - 127 Not used 00 00 00 00 00 00 128 255 FF FF FF FF FF FF Blank for customer use Rev. 1.0, 2006-10 10202006-L0SM-FEYT 81 Internet Data Sheet HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module TABLE 36 Product Type HYS64T128020EU–3.7–B2 HYS64T128920EU–3.7–B2 HYS72T128020EU–3.7–B2 HYS72T128920EU–3.7–B2 SPD Codes for PC2–4200–444 Organization 1 GByte 1 GByte 1 GByte 1 GByte ×64 ×64 ×72 ×72 2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8) Label Code PC2– 4200U–444 PC2– 4200U–444 PC2–4200E– PC2–4200E– 444 444 JEDEC SPD Revision Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Byte# Description HEX HEX HEX HEX 0 Programmed SPD Bytes in EEPROM 80 80 80 80 1 Total number of Bytes in EEPROM 08 08 08 08 2 Memory Type (DDR2) 08 08 08 08 3 Number of Row Addresses 0E 0E 0E 0E 4 Number of Column Addresses 0A 0A 0A 0A 5 DIMM Rank and Stacking Information 61 61 61 61 6 Data Width 40 40 48 48 7 Not used 00 00 00 00 8 Interface Voltage Level 05 05 05 05 9 tCK @ CLMAX (Byte 18) [ns] tAC SDRAM @ CLMAX (Byte 18) [ns] 3D 3D 3D 3D 10 50 50 50 50 11 Error Correction Support (non-ECC, ECC) 00 00 02 02 12 Refresh Rate and Type 82 82 82 82 13 Primary SDRAM Width 08 08 08 08 14 Error Checking SDRAM Width 00 00 08 08 15 Not used 00 00 00 00 16 Burst Length Supported 0C 0C 0C 0C 17 Number of Banks on SDRAM Device 04 04 04 04 18 Supported CAS Latencies 38 38 38 38 19 DIMM Mechanical Characteristics 01 01 01 01 20 DIMM Type Information 02 02 02 02 21 DIMM Attributes 00 00 00 00 22 Component Attributes 07 07 07 07 Rev. 1.0, 2006-10 10202006-L0SM-FEYT 82 Internet Data Sheet Product Type HYS64T128020EU–3.7–B2 HYS64T128920EU–3.7–B2 HYS72T128020EU–3.7–B2 HYS72T128920EU–3.7–B2 HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module Organization 1 GByte 1 GByte 1 GByte 1 GByte ×64 ×64 ×72 ×72 2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8) Label Code PC2– 4200U–444 PC2– 4200U–444 PC2–4200E– PC2–4200E– 444 444 JEDEC SPD Revision Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Byte# Description HEX HEX HEX HEX 23 tCK @ CLMAX -1 (Byte 18) [ns] tAC SDRAM @ CLMAX -1 [ns] tCK @ CLMAX -2 (Byte 18) [ns] tAC SDRAM @ CLMAX -2 [ns] tRP.MIN [ns] tRRD.MIN [ns] tRCD.MIN [ns] tRAS.MIN [ns] 24 25 26 27 28 29 30 3D 3D 3D 3D 50 50 50 50 50 50 50 50 60 60 60 60 3C 3C 3C 3C 1E 1E 1E 1E 3C 3C 3C 3C 2D 2D 2D 2D 31 Module Density per Rank 80 80 80 80 32 tAS.MIN and tCS.MIN [ns] tAH.MIN and tCH.MIN [ns] tDS.MIN [ns] tDH.MIN [ns] tWR.MIN [ns] tWTR.MIN [ns] tRTP.MIN [ns] 25 25 25 25 37 37 37 37 10 10 10 10 22 22 22 22 3C 3C 3C 3C 1E 1E 1E 1E 1E 1E 1E 1E 33 34 35 36 37 38 39 Analysis Characteristics 00 00 00 00 40 00 00 00 00 3C 3C 3C 3C 69 69 69 69 80 80 80 80 1E 1E 1E 1E 45 tRC and tRFC Extension tRC.MIN [ns] tRFC.MIN [ns] tCK.MAX [ns] tDQSQ.MAX [ns] tQHS.MAX [ns] 28 28 28 28 46 PLL Relock Time 00 00 00 00 47 TCASE.MAX Delta / ∆T4R4W Delta 50 50 50 50 41 42 43 44 Rev. 1.0, 2006-10 10202006-L0SM-FEYT 83 Internet Data Sheet Product Type HYS64T128020EU–3.7–B2 HYS64T128920EU–3.7–B2 HYS72T128020EU–3.7–B2 HYS72T128920EU–3.7–B2 HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module Organization 1 GByte 1 GByte 1 GByte 1 GByte ×64 ×64 ×72 ×72 2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8) Label Code PC2– 4200U–444 PC2– 4200U–444 PC2–4200E– PC2–4200E– 444 444 JEDEC SPD Revision Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Byte# Description HEX HEX HEX HEX 48 Psi(T-A) DRAM 7A 7A 7A 7A 49 ∆T0 (DT0) 43 43 43 43 50 ∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM) 2C 2C 2C 2C 51 ∆T2P (DT2P) 36 36 36 36 52 ∆T3N (DT3N) 21 21 21 21 53 ∆T3P.fast (DT3P fast) 41 41 41 41 54 ∆T3P.slow (DT3P slow) 2A 2A 2A 2A 55 ∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W) 40 40 40 40 56 ∆T5B (DT5B) 1E 1E 1E 1E 57 ∆T7 (DT7) 22 22 22 22 58 Psi(ca) PLL 00 00 00 00 59 Psi(ca) REG 00 00 00 00 60 ∆TPLL (DTPLL) 00 00 00 00 61 ∆TREG (DTREG) / Toggle Rate 00 00 00 00 62 SPD Revision 12 12 12 12 63 Checksum of Bytes 0-62 35 35 47 47 64 Manufacturer’s JEDEC ID Code (1) 7F 7F 7F 7F 65 Manufacturer’s JEDEC ID Code (2) 7F 7F 7F 7F 66 Manufacturer’s JEDEC ID Code (3) 7F 7F 7F 7F 67 Manufacturer’s JEDEC ID Code (4) 7F 7F 7F 7F 68 Manufacturer’s JEDEC ID Code (5) 7F 7F 7F 7F 69 Manufacturer’s JEDEC ID Code (6) 51 51 51 51 70 Manufacturer’s JEDEC ID Code (7) 00 00 00 00 71 Manufacturer’s JEDEC ID Code (8) 00 00 00 00 72 Module Manufacturer Location xx xx xx xx Rev. 1.0, 2006-10 10202006-L0SM-FEYT 84 Internet Data Sheet Product Type HYS64T128020EU–3.7–B2 HYS64T128920EU–3.7–B2 HYS72T128020EU–3.7–B2 HYS72T128920EU–3.7–B2 HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module Organization 1 GByte 1 GByte 1 GByte 1 GByte ×64 ×64 ×72 ×72 2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8) Label Code PC2– 4200U–444 PC2– 4200U–444 PC2–4200E– PC2–4200E– 444 444 JEDEC SPD Revision Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Byte# Description HEX HEX HEX HEX 73 Product Type, Char 1 36 36 37 37 74 Product Type, Char 2 34 34 32 32 75 Product Type, Char 3 54 54 54 54 76 Product Type, Char 4 31 31 31 31 77 Product Type, Char 5 32 32 32 32 78 Product Type, Char 6 38 38 38 38 79 Product Type, Char 7 30 39 30 39 80 Product Type, Char 8 32 32 32 32 81 Product Type, Char 9 30 30 30 30 82 Product Type, Char 10 45 45 45 45 83 Product Type, Char 11 55 55 55 55 84 Product Type, Char 12 33 33 33 33 85 Product Type, Char 13 2E 2E 2E 2E 86 Product Type, Char 14 37 37 37 37 87 Product Type, Char 15 42 42 42 42 88 Product Type, Char 16 32 32 32 32 89 Product Type, Char 17 20 20 20 20 90 Product Type, Char 18 20 20 20 20 91 Module Revision Code 2x 0x 2x 0x 92 Test Program Revision Code xx xx xx xx 93 Module Manufacturing Date Year xx xx xx xx 94 Module Manufacturing Date Week xx xx xx xx 95 - 98 Module Serial Number xx xx xx xx Rev. 1.0, 2006-10 10202006-L0SM-FEYT 85 Internet Data Sheet Product Type HYS64T128020EU–3.7–B2 HYS64T128920EU–3.7–B2 HYS72T128020EU–3.7–B2 HYS72T128920EU–3.7–B2 HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module Organization 1 GByte 1 GByte 1 GByte 1 GByte ×64 ×64 ×72 ×72 2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8) 2 Ranks (×8) Label Code PC2– 4200U–444 PC2– 4200U–444 PC2–4200E– PC2–4200E– 444 444 JEDEC SPD Revision Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Byte# HEX HEX HEX HEX 99 - 127 Not used 00 00 00 00 128 255 FF FF FF FF Description Blank for customer use Rev. 1.0, 2006-10 10202006-L0SM-FEYT 86 Internet Data Sheet HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module 5 Package Outlines FIGURE 6 Package Outline Raw Card C L-DIM-240-3 $ % & 0$ ; [ & $ % 'HWD LORIFR QWD FWV $ % & %XUU PD [ DOORZ H G */' Notes 1. Drawing according to ISO 8015 2. Dimensions in mm 3. General tolerances +/- 0.15 Rev. 1.0, 2006-10 10202006-L0SM-FEYT 87 Internet Data Sheet HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module FIGURE 7 ¡ $ % & Package Outline L-DIM-240-8 0$; & $ % 0,1 'HWDLO RI FRQWDFWV $ % & %XUU PD[ DOORZHG */' Notes 1. Drawing according to ISO 8015 2. Dimensions in mm 3. General tolerances +/- 0.15 Rev. 1.0, 2006-10 10202006-L0SM-FEYT 88 Internet Data Sheet HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module FIGURE 8 ¡ $ % & Package Outline L-DIM-240-9 0$; & $ % 0,1 'HWDLO RI FRQWDFWV $ % & %XUU PD[ DOORZHG */' Notes 1. Drawing according to ISO 8015 2. Dimensions in mm 3. General tolerances +/- 0.15 Rev. 1.0, 2006-10 10202006-L0SM-FEYT 89 Internet Data Sheet HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module FIGURE 9 ¡ $ % & Package Outline Raw Card F L-DIM-240-6 0$; & $ % 0,1 'HWDLO RI FRQWDFWV $ % & %XUU PD[ DOORZHG */' Notes 1. Drawing according to ISO 8015 2. Dimensions in mm 3. General tolerances +/- 0.15 Rev. 1.0, 2006-10 10202006-L0SM-FEYT 90 Internet Data Sheet HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module FIGURE 10 ¡ $ % & Package Outline Raw Card G L-DIM-240-7 0$; & $ % 0,1 'HWDLO RI FRQWDFWV $ % & %XUU PD[ DOORZHG */' Notes 1. Drawing according to ISO 8015 2. Dimensions in mm 3. General tolerances +/- 0.15 Rev. 1.0, 2006-10 10202006-L0SM-FEYT 91 Internet Data Sheet HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module 6 Product Type Nomenclature This chapter describes Product Type Nomenclature for DDR2 DRAMs and DIMMs. Qimonda’s nomenclature uses simple coding combined with some propriatory coding. Table 37 provides examples for module and component product type number as well as the field number. The detailed field description together with possible values and coding explanation is listed for modules in Table 38 and for components in Table 39. TABLE 37 Nomenclature Fields and Examples Example for Field Number 1 2 3 4 5 6 7 8 9 10 11 Micro-DIMM HYS 64 T 64/128 0 2 0 K M –5 –A DDR2 DRAM HYB 18 T 512/1G 16 0 A C –5 TABLE 38 DDR2 DIMM Nomenclature Field Description Values Coding 1 Qimonda Module Prefix HYS Constant 2 Module Data Width [bit] 64 Non-ECC 72 ECC 3 DRAM Technology T DDR2 4 Memory Density per I/O [Mbit]; Module Density1) 32 256 MByte 64 512 MByte 128 1 GByte 256 2 GByte 512 4 GByte 5 Raw Card Generation 0 .. 9 Look up table 6 Number of Module Ranks 0, 2, 4 1, 2, 4 7 Product Variations 0 .. 9 Look up table 8 Package, Lead-Free Status A .. Z Look up table 9 Module Type D SO-DIMM M Micro-DIMM R Registered U Unbuffered F Fully Buffered Rev. 1.0, 2006-10 10202006-L0SM-FEYT 92 Internet Data Sheet HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module Field Description Values Coding 10 Speed Grade –2.5F PC2–6400 5–5–5 –2.5 PC2–6400 6–6–6 11 Die Revision –3 PC2–5300 4–4–4 –3S PC2–5300 5–5–5 –3.7 PC2–4200 4–4–4 –5 PC2–3200 3–3–3 –A First –B Second 1) Multiplying “Memory Density per I/O” with “Module Data Width” and dividing by 8 for Non-ECC and 9 for ECC modules gives the overall module memory density in MBytes as listed in column “Coding”. TABLE 39 DDR2 DRAM Nomenclature Field Description Values Coding 1 2 Qimonda Component Prefix HYB Constant Interface Voltage [V] 18 SSTL_18 3 DRAM Technology T DDR2 4 Component Density [Mbit] 256 256 Mbit 512 512 Mbit 1G 1 Gbit 2G 2 Gbit 40 ×4 80 ×8 16 ×16 0 .. 9 Look up table 5+6 Number of I/Os 7 Product Variations 8 Die Revision 9 10 Package, Lead-Free Status Speed Grade Rev. 1.0, 2006-10 10202006-L0SM-FEYT A First B Second C FBGA, lead-containing F FBGA, lead-free –25F DDR2-800 5-5-5 –2.5 DDR2-800 6-6-6 –3 DDR2-667 4-4-4 –3S DDR2-667 5-5-5 –3.7 DDR2-533 4-4-4 –5 DDR2-400 3-3-3 93 Internet Data Sheet HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2 Unbuffered DDR2 SDRAM Module Table of Contents 1 1.1 1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 3.1 3.1.1 3.2 3.3 3.3.1 3.3.2 3.3.3 3.4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Speed Grade Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DRAM Component Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ODT AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDD Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6 Product Type Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 16 16 16 17 18 18 21 30 32 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Rev. 1.0, 2006-10 10202006-L0SM-FEYT 94 Internet Data Sheet Edition 2006-10 Published by Qimonda AG Gustav-Heinemann-Ring 212 D-81739 München, Germany © Qimonda AG 2006. All Rights Reserved. Legal Disclaimer The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics (“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office. Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Qimonda Office. Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. www.qimonda.com