Features • High Performance, Low Power AVR® 8-Bit Microcontroller • Advanced RISC Architecture • • • • • • • • – 120 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation Non-volatile Program and Data Memories – 2/4/8K Byte of In-System Programmable Program Memory Flash (ATtiny25/45/85) Endurance: 10,000 Write/Erase Cycles – 128/256/512 Bytes In-System Programmable EEPROM (ATtiny25/45/85) Endurance: 100,000 Write/Erase Cycles – 128/256/512 Bytes Internal SRAM (ATtiny25/45/85) – Programming Lock for Self-Programming Flash Program and EEPROM Data Security Peripheral Features – 8-bit Timer/Counter with Prescaler and Two PWM Channels – 8-bit High Speed Timer/Counter with Separate Prescaler 2 High Frequency PWM Outputs with Separate Output Compare Registers Programmable Dead Time Generator – Universal Serial Interface with Start Condition Detector – 10-bit ADC 4 Single Ended Channels 2 Differential ADC Channel Pairs with Programmable Gain (1x, 20x) – Programmable Watchdog Timer with Separate On-chip Oscillator – On-chip Analog Comparator Special Microcontroller Features – debugWIRE On-chip Debug System – In-System Programmable via SPI Port – External and Internal Interrupt Sources – Low Power Idle, ADC Noise Reduction, and Power-down Modes – Enhanced Power-on Reset Circuit – Programmable Brown-out Detection Circuit – Internal Calibrated Oscillator I/O and Packages – Six Programmable I/O Lines – 8-pin PDIP and 8-pin SOIC Operating Voltage – 1.8 - 5.5V for ATtiny25/45/85V – 2.7 - 5.5V for ATtiny25/45/85 Speed Grade – ATtiny25/45/85V: 0 - 4 MHz @ 1.8 - 5.5V, 0 - 10 MHz @ 2.7 - 5.5V – ATtiny25/45/85: 0 - 10 MHz @ 2.7 - 5.5V, 0 - 20 MHz @ 4.5 - 5.5V Industrial Temperature Range Low Power Consumption – Active Mode: 1 MHz, 1.8V: 450µA – Power-down Mode: 0.1µA at 1.8V 8-bit Microcontroller with 2/4/8K Bytes In-System Programmable Flash ATtiny25/V ATtiny45/V ATtiny85/V Preliminary Summary 2586AS–AVR–02/05 Note: This is a summary document. A complete document is available on our Web site at www.atmel.com. 1. Pin Configurations Figure 1-1. Pinout ATtiny25/45/85 PDIP/SOIC (PCINT5/RESET/ADC0/dW) PB5 (PCINT3/XTAL1/OC1B/ADC3) PB3 (PCINT4/XTAL2/CLKO/OC1B/ADC2) PB4 GND 1.1 1 2 3 4 8 7 6 5 VCC PB2 (SCK/USCK/SCL/ADC1/T0/INT0/PCINT2) PB1 (MISO/DO/AIN1/OC0B/OC1A/PCINT1) PB0 (MOSI/DI/SDA/AIN0/OC0A/OC1A/AREF/PCINT0) Disclaimer Typical values contained in this data sheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized. 2 ATtiny25/45/85 2586AS–AVR–02/05 ATtiny25/45/85 2. Overview The ATtiny25/45/85 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny25/45/85 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 2.1 Block Diagram Figure 2-1. Block Diagram 8-BIT DATABUS CALIBRATED INTERNAL OSCILLATOR PROGRAM COUNTER STACK POINTER PROGRAM FLASH SRAM WATCHDOG TIMER TIMING AND CONTROL VCC MCU CONTROL REGISTER MCU STATUS REGISTER GND INSTRUCTION REGISTER INSTRUCTION DECODER CONTROL LINES GENERAL PURPOSE REGISTERS TIMER/ COUNTER0 X Y Z TIMER/ COUNTER1 ALU UNIVERSAL SERIAL INTERFACE STATUS REGISTER INTERRUPT UNIT PROGRAMMING LOGIC DATA EEPROM DATA REGISTER PORT B DATA DIR. REG.PORT B OSCILLATORS ADC / ANALOG COMPARATOR PORT B DRIVERS RESET PB0-PB5 The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent 3 2586AS–AVR–02/05 registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATtiny25/45/85 provides the following features: 2/4/8K byte of In-System Programmable Flash, 128/256/512 bytes EEPROM, 128/256/256 bytes SRAM, 6 general purpose I/O lines, 32 general purpose working registers, one 8-bit Timer/Counter with compare modes, one 8-bit high speed Timer/Counter, Universal Serial Interface, Internal and External Interrupts, a 4-channel, 10-bit ADC, a programmable Watchdog Timer with internal Oscillator, and three software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counter, ADC, Analog Comparator, and Interrupt system to continue functioning. The Power-down mode saves the register contents, disabling all chip functions until the next Interrupt or Hardware Reset. The ADC Noise Reduction mode stops the CPU and all I/O modules except ADC, to minimize switching noise during ADC conversions. The device is manufactured using Atmel’s high density non-volatile memory technology. The On-chip ISP Flash allows the Program memory to be re-programmed In-System through an SPI serial interface, by a conventional non-volatile memory programmer or by an On-chip boot code running on the AVR core. The ATtiny25/45/85 AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits. 2.2 2.2.1 Pin Descriptions VCC Supply voltage. 2.2.2 GND Ground. 2.2.3 Port B (PB5..PB0) Port B is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATtiny25/45/85 as listed on page 60. On the ATtiny25 device the programmable I/O ports PB3 and PB4 (pins 2 and 3) are exchanged in the ATtiny15 compatibility mode for supporting the backward compatibility with ATtiny15. 2.2.4 RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table 8-1 on page 37. Shorter pulses are not guaranteed to generate a reset. 4 ATtiny25/45/85 2586AS–AVR–02/05 ATtiny25/45/85 3. Register Summary Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x3F SREG Name I T H S V N Z C Page page 7 0x3E SPH – – – – – – – SP8 page 10 0x3D SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 page 10 0x3C Reserved 0x3B GIMSK – INT0 PCIE – – – – – page 49 0x3A GIFR – INTF0 PCIF – – – – – page 50 0x39 TIMSK – OCIE1A OCIE1B OCIE0A OCIE0B TOIE1 TOIE0 – page 81 0x38 TIFR – OCF1A OCF1B OCF0A OCF0B TOV1 TOV0 – page 81 0x37 SPMCSR – – – CTPB RFLB PGWRT PGERS SPMEN page 146 0x36 Reserved 0x35 MCUCR – PUD SE SM1 SM0 – ISC01 ISC00 page 32, page 60, page 49 0x34 MCUSR – – – – WDRF BORF EXTRF PORF page 40, 0x33 TCCR0B FOC0A FOC0B – – WGM02 CS02 CS01 CS00 page 79 0x32 TCNT0 0x31 OSCCAL 0x30 TCCR1 – – Timer/Counter0 page 80 Oscillator Calibration Register CTC1 PWM1A COM1A1 COM1A0 CS13 page 27 CS12 CS11 CS10 page 88, page 100 0x2F TCNT1 Timer/Counter1 page 90, page 101 0x2E OCR1A Timer/Counter1 Output Compare Register A page 90, page 102 0x2D OCR1C Timer/Counter1 Output Compare Register C 0x2C GTCCR 0x2B OCR1B 0x2A TCCR0A 0x29 OCR0A TSM PWM1B COM1B1 COM0A1 COM0A0 COM0B1 COM1B0 FOC1B FOC1A PSR1 PSR0 WGM01 WGM00 Timer/Counter1 Output Compare Register B COM0B0 page 91 – Timer/Counter0 – Output Compare Register A 0x28 OCR0B 0x27 PLLCSR SM 0x26 CLKPR CLKPCE – 0x25 DT1A DT1AH3 DT1AH2 DT1BH3 DT1BH2 - - – page 76 page 80 Timer/Counter0 – Output Compare Register B – page 91, page 102 page 84, page 89, page page 80 – – PCKE PLLE PLOCK page 93, page 103 – – CLKPS3 CLKPS2 CLKPS1 CLKPS0 page 30 DT1AH1 DT1AH0 DT1AL3 DT1AL2 DT1AL1 DT1AL0 page 108 DT1BH1 DT1BH0 DT1BL3 DT1BL2 DT1BL1 DT1BL0 page 109 - - - - DTPS11 DTPS10 page 108 WDE WDP2 WDP1 WDP0 page 42 PRTIM1 PRTIM0 PRUSI PRADC page 33 EEAR8 page 16 0x24 DT1B 0x23 DTPS1 0x22 DWDR 0x21 WDTCR 0x20 PRR 0x1F EEARH 0x1E EEARL 0x1D EEDR 0x1C EECR 0x1B Reserved – 0x1A Reserved – 0x19 Reserved 0x18 PORTB – – PORTB5 0x17 DDRB – – 0x16 PINB – 0x15 PCMSK 0x14 DIDR0 0x13 GPIOR2 General Purpose I/O Register 2 0x12 GPIOR1 General Purpose I/O Register 1 0x11 GPIOR0 General Purpose I/O Register 0 0x10 USIBR USI Buffer Register 0x0F USIDR USI Data Register 0x0E USISR USICIF USIOIF USIPF USIDC USICNT3 USICNT2 USICNT1 USICNT0 page 118 0x0D USICR USISIE USIOIE USIWM1 USIWM0 USICS1 USICS0 USICLK USITC page 119 0x0C Reserved – 0x0B Reserved – 0x0A Reserved – 0x09 Reserved 0x08 ACSR 0x07 DWDR[7:0] WDTIF WDTIE WDP3 WDCE – EEAR7 EEAR6 EEAR5 EEAR4 page 143 EEAR3 EEAR2 EEAR1 EEAR0 page 16 EERIE EEMWE EEWE EERE page 17 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 page 64 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 page 64 – PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 page 64 – – PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 page 51 – – ADC0D ADC2D ADC3D ADC1D EIN1D AIN0D page 124, page 141 EEPROM Data Register – – EEPM1 EEPM0 page 16 – page 118 page 117 – ACD ACBG ACO ACI ACIE – ACIS1 ACIS0 page 122 ADMUX REFS1 REFS0 ADLAR REFS2 MUX3 MUX2 MUX1 MUX0 page 137 0x06 ADCSRA ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 page 138 0x05 ADCH ADC Data Register High Byte 0x04 ADCL ADC Data Register Low Byte 0x03 ADCSRB 0x02 Reserved – 0x01 Reserved – 0x00 Reserved – BIN ACME IPR – – page 140 page 140 ADTS2 ADTS1 ADTS0 page 122, page 140 5 2586AS–AVR–02/05 Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operation the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only. 6 ATtiny25/45/85 2586AS–AVR–02/05 ATtiny25/45/85 4. Instruction Set Summary Mnemonics Operands Description Operation Flags #Clocks ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers Rd ← Rd + Rr Z,C,N,V,H ADC Rd, Rr Add with Carry two Registers Rd ← Rd + Rr + C Z,C,N,V,H 1 ADIW Rdl,K Add Immediate to Word Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S 2 SUB Rd, Rr Subtract two Registers Rd ← Rd - Rr Z,C,N,V,H 1 SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H 1 SBC Rd, Rr Subtract with Carry two Registers Rd ← Rd - Rr - C Z,C,N,V,H 1 SBCI Rd, K Subtract with Carry Constant from Reg. Rd ← Rd - K - C Z,C,N,V,H 1 SBIW Rdl,K Subtract Immediate from Word Rdh:Rdl ← Rdh:Rdl - K Z,C,N,V,S 2 AND Rd, Rr Logical AND Registers Rd ← Rd • Rr Z,N,V 1 ANDI Rd, K Logical AND Register and Constant Rd ← Rd • K Z,N,V 1 OR Rd, Rr Logical OR Registers Rd ← Rd v Rr Z,N,V 1 ORI Rd, K Logical OR Register and Constant Rd ← Rd v K Z,N,V 1 EOR Rd, Rr Exclusive OR Registers Rd ← Rd ⊕ Rr Z,N,V 1 1 COM Rd One’s Complement Rd ← 0xFF − Rd Z,C,N,V 1 NEG Rd Two’s Complement Rd ← 0x00 − Rd Z,C,N,V,H 1 SBR Rd,K Set Bit(s) in Register Rd ← Rd v K Z,N,V 1 CBR Rd,K Clear Bit(s) in Register Rd ← Rd • (0xFF - K) Z,N,V 1 INC Rd Increment Rd ← Rd + 1 Z,N,V 1 DEC Rd Decrement Rd ← Rd − 1 Z,N,V 1 TST Rd Test for Zero or Minus Rd ← Rd • Rd Z,N,V 1 CLR Rd Clear Register Rd ← Rd ⊕ Rd Z,N,V 1 SER Rd Set Register Rd ← 0xFF None 1 2 BRANCH INSTRUCTIONS RJMP k IJMP RCALL k Relative Jump PC ← PC + k + 1 None Indirect Jump to (Z) PC ← Z None 2 Relative Subroutine Call PC ← PC + k + 1 None 3 3 ICALL Indirect Call to (Z) PC ← Z None RET Subroutine Return PC ← STACK None 4 RETI Interrupt Return PC ← STACK I 4 CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC ← PC + 2 or 3 None CP Rd,Rr Compare Rd − Rr Z, N,V,C,H 1 CPC Rd,Rr Compare with Carry Rd − Rr − C Z, N,V,C,H 1 CPI Rd,K Compare Register with Immediate Rd − K Z, N,V,C,H SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC ← PC + 2 or 3 None 1/2/3 1/2/3 1 SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC ← PC + 2 or 3 None 1/2/3 SBIC P, b Skip if Bit in I/O Register Cleared if (P(b)=0) PC ← PC + 2 or 3 None 1/2/3 SBIS P, b Skip if Bit in I/O Register is Set if (P(b)=1) PC ← PC + 2 or 3 None 1/2/3 BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC←PC+k + 1 None 1/2 BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC←PC+k + 1 None 1/2 BREQ k Branch if Equal if (Z = 1) then PC ← PC + k + 1 None 1/2 BRNE k Branch if Not Equal if (Z = 0) then PC ← PC + k + 1 None 1/2 BRCS k Branch if Carry Set if (C = 1) then PC ← PC + k + 1 None 1/2 BRCC k Branch if Carry Cleared if (C = 0) then PC ← PC + k + 1 None 1/2 BRSH k Branch if Same or Higher if (C = 0) then PC ← PC + k + 1 None 1/2 BRLO k Branch if Lower if (C = 1) then PC ← PC + k + 1 None 1/2 BRMI k Branch if Minus if (N = 1) then PC ← PC + k + 1 None 1/2 BRPL k Branch if Plus if (N = 0) then PC ← PC + k + 1 None 1/2 BRGE k Branch if Greater or Equal, Signed if (N ⊕ V= 0) then PC ← PC + k + 1 None 1/2 BRLT k Branch if Less Than Zero, Signed if (N ⊕ V= 1) then PC ← PC + k + 1 None 1/2 BRHS k Branch if Half Carry Flag Set if (H = 1) then PC ← PC + k + 1 None 1/2 BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC ← PC + k + 1 None 1/2 BRTS k Branch if T Flag Set if (T = 1) then PC ← PC + k + 1 None 1/2 BRTC k Branch if T Flag Cleared if (T = 0) then PC ← PC + k + 1 None 1/2 BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ← PC + k + 1 None 1/2 BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1 None 1/2 BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 None 1/2 BRID k Branch if Interrupt Disabled if ( I = 0) then PC ← PC + k + 1 None 1/2 BIT AND BIT-TEST INSTRUCTIONS SBI P,b Set Bit in I/O Register I/O(P,b) ← 1 None 2 CBI P,b Clear Bit in I/O Register I/O(P,b) ← 0 None 2 LSL Rd Logical Shift Left Rd(n+1) ← Rd(n), Rd(0) ← 0 Z,C,N,V 1 LSR Rd Logical Shift Right Rd(n) ← Rd(n+1), Rd(7) ← 0 Z,C,N,V 1 ROL Rd Rotate Left Through Carry Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7) Z,C,N,V 1 7 2586AS–AVR–02/05 Mnemonics Operands Description Operation Flags #Clocks ROR Rd Rotate Right Through Carry Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0) Z,C,N,V 1 ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n=0..6 Z,C,N,V 1 SWAP Rd Swap Nibbles Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0) None 1 BSET s Flag Set SREG(s) ← 1 SREG(s) 1 BCLR s Flag Clear SREG(s) ← 0 SREG(s) 1 BST Rr, b Bit Store from Register to T T ← Rr(b) T 1 BLD Rd, b Bit load from T to Register Rd(b) ← T None 1 SEC Set Carry C←1 C 1 CLC Clear Carry C←0 C 1 SEN Set Negative Flag N←1 N 1 CLN Clear Negative Flag N←0 N 1 SEZ Set Zero Flag Z←1 Z 1 CLZ Clear Zero Flag Z←0 Z 1 SEI Global Interrupt Enable I←1 I 1 CLI Global Interrupt Disable I←0 I 1 SES Set Signed Test Flag S←1 S 1 CLS Clear Signed Test Flag S←0 S 1 SEV Set Twos Complement Overflow. V←1 V 1 CLV Clear Twos Complement Overflow V←0 V 1 SET Set T in SREG T←1 T 1 CLT Clear T in SREG T←0 T 1 SEH CLH Set Half Carry Flag in SREG Clear Half Carry Flag in SREG H←1 H←0 H H 1 Rd ← Rr Rd+1:Rd ← Rr+1:Rr None 1 None 1 1 1 DATA TRANSFER INSTRUCTIONS MOV Rd, Rr Move Between Registers MOVW Rd, Rr Copy Register Word LDI Rd, K Load Immediate Rd ← K None LD Rd, X Load Indirect Rd ← (X) None 2 LD Rd, X+ Load Indirect and Post-Inc. Rd ← (X), X ← X + 1 None 2 2 LD Rd, - X Load Indirect and Pre-Dec. X ← X - 1, Rd ← (X) None LD Rd, Y Load Indirect Rd ← (Y) None 2 LD Rd, Y+ Load Indirect and Post-Inc. Rd ← (Y), Y ← Y + 1 None 2 2 LD Rd, - Y Load Indirect and Pre-Dec. Y ← Y - 1, Rd ← (Y) None LDD Rd,Y+q Load Indirect with Displacement Rd ← (Y + q) None 2 LD Rd, Z Load Indirect Rd ← (Z) None 2 LD Rd, Z+ Load Indirect and Post-Inc. Rd ← (Z), Z ← Z+1 None 2 LD Rd, -Z Load Indirect and Pre-Dec. Z ← Z - 1, Rd ← (Z) None 2 LDD Rd, Z+q Load Indirect with Displacement Rd ← (Z + q) None 2 LDS Rd, k Load Direct from SRAM Rd ← (k) None 2 ST X, Rr Store Indirect (X) ← Rr None 2 ST X+, Rr Store Indirect and Post-Inc. (X) ← Rr, X ← X + 1 None 2 ST - X, Rr Store Indirect and Pre-Dec. X ← X - 1, (X) ← Rr None 2 ST Y, Rr Store Indirect (Y) ← Rr None 2 ST Y+, Rr Store Indirect and Post-Inc. (Y) ← Rr, Y ← Y + 1 None 2 ST - Y, Rr Store Indirect and Pre-Dec. Y ← Y - 1, (Y) ← Rr None 2 STD Y+q,Rr Store Indirect with Displacement (Y + q) ← Rr None 2 ST Z, Rr Store Indirect (Z) ← Rr None 2 ST Z+, Rr Store Indirect and Post-Inc. (Z) ← Rr, Z ← Z + 1 None 2 ST -Z, Rr Store Indirect and Pre-Dec. Z ← Z - 1, (Z) ← Rr None 2 STD Z+q,Rr Store Indirect with Displacement (Z + q) ← Rr None 2 STS k, Rr Store Direct to SRAM (k) ← Rr None 2 Load Program Memory R0 ← (Z) None 3 LPM LPM Rd, Z Load Program Memory Rd ← (Z) None 3 LPM Rd, Z+ Load Program Memory and Post-Inc Rd ← (Z), Z ← Z+1 None 3 Store Program Memory (z) ← R1:R0 None IN Rd, P In Port Rd ← P None OUT P, Rr Out Port P ← Rr None 1 PUSH Rr Push Register on Stack STACK ← Rr None 2 POP Rd Pop Register from Stack Rd ← STACK None 2 SPM 1 MCU CONTROL INSTRUCTIONS NOP No Operation None 1 SLEEP Sleep (see specific descr. for Sleep function) None 1 WDR BREAK Watchdog Reset Break (see specific descr. for WDR/Timer) For On-chip Debug Only None None 1 N/A 8 ATtiny25/45/85 2586AS–AVR–02/05 ATtiny25/45/85 5. Ordering Information 5.1 ATtiny25 Speed (MHz)(3) 10 20 Notes: Ordering Code Package(1) 1.8 - 5.5V ATtiny25V-10PI ATtiny25V-10PU(2) ATtiny25V-10SI ATtiny25V-10SU(2) 8P3 8P3 8S2 8S2 Industrial (-40°C to 85°C) 2.7 - 5.5V ATtiny25-20PI ATtiny25-20PU(2) ATtiny25-20SI ATtiny25-20SU(2) 8P3 8P3 8S2 8S2 Industrial (-40°C to 85°C) Power Supply Operational Range 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. For Speed vs. VCC,see Figure 23.4 on page 168 Package Type 8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8S2 8-lead, 0.209" Wide, Plastic Gull-Wing Small Outline (EIAJ SOIC) 9 2586AS–AVR–02/05 5.2 ATtiny45 Speed (MHz)(3) 10 20 Notes: Ordering Code Package(1) 1.8 - 5.5V ATtiny45V-10PI ATtiny45V-10PU(2) ATtiny45V-10SI ATtiny45V-10SU(2) 8P3 8P3 8S2 8S2 Industrial (-40°C to 85°C) 2.7 - 5.5V ATtiny45-20PI ATtiny45-20PU(2) ATtiny45-20SI ATtiny45-20SU(2) 8P3 8P3 8S2 8S2 Industrial (-40°C to 85°C) Power Supply Operational Range 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. For Speed vs. VCC,see Figure 23.4 on page 168 Package Type 8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8S2 8-lead, 0.209" Wide, Plastic Gull-Wing Small Outline (EIAJ SOIC) 10 ATtiny25/45/85 2586AS–AVR–02/05 ATtiny25/45/85 5.3 ATtiny85 Speed (MHz)(3) 10 20 Notes: Ordering Code Package(1) 1.8 - 5.5V ATtiny85V-10PI ATtiny85V-10PU(2) ATtiny85V-10SI ATtiny85V-10SU(2) 8P3 8P3 8S2 8S2 Industrial (-40°C to 85°C) 2.7 - 5.5V ATtiny85-20PI ATtiny85-20PU(2) ATtiny85-20SI ATtiny85-20SU(2) 8P3 8P3 8S2 8S2 Industrial (-40°C to 85°C) Power Supply Operational Range 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. For Speed vs. VCC,see Figure 23.4 on page 168 Package Type 8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8S2 8-lead, 0.209" Wide, Plastic Gull-Wing Small Outline (EIAJ SOIC) 11 2586AS–AVR–02/05 6. Packaging Information 6.1 8P3 E 1 E1 N Top View c eA End View COMMON DIMENSIONS (Unit of Measure = inches) D e D1 A2 A SYMBOL MIN NOM A b2 b3 b 4 PLCS Side View L 0.210 NOTE 2 A2 0.115 0.130 0.195 b 0.014 0.018 0.022 5 b2 0.045 0.060 0.070 6 b3 0.030 0.039 0.045 6 c 0.008 0.010 0.014 D 0.355 0.365 0.400 D1 0.005 E 0.300 0.310 0.325 4 E1 0.240 0.250 0.280 3 0.150 2 e 3 3 0.100 BSC eA L Notes: MAX 0.300 BSC 0.115 0.130 4 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information. 2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3. 3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch. 4. E and eA measured with the leads constrained to be perpendicular to datum. 5. Pointed or rounded lead tips are preferred to ease insertion. 6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm). 01/09/02 R 12 2325 Orchard Parkway San Jose, CA 95131 TITLE 8P3, 8-lead, 0.300" Wide Body, Plastic Dual In-line Package (PDIP) DRAWING NO. REV. 8P3 B ATtiny25/45/85 2586AS–AVR–02/05 ATtiny25/45/85 6.2 8S2 C 1 E E1 L N Top View ∅ End View e b COMMON DIMENSIONS (Unit of Measure = mm) A SYMBOL A1 D Side View NOM MAX NOTE 1.70 2.16 A1 0.05 0.25 b 0.35 0.48 5 C 0.15 0.35 5 D 5.13 5.35 E1 5.18 5.40 E 7.70 8.26 L 0.51 0.85 ∅ 0˚ e Notes: 1. 2. 3. 4. 5. MIN A 2, 3 8˚ 1.27 BSC 4 This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information. Mismatch of the upper and lower dies and resin burrs are not included. It is recommended that upper and lower cavities be equal. If they are different, the larger dimension shall be regarded. Determines the true geometric position. Values b and C apply to pb/Sn solder plated terminal. The standard thickness of the solder layer shall be 0.010 +0.010/−0.005 mm. 10/7/03 R 2325 Orchard Parkway San Jose, CA 95131 TITLE 8S2, 8-lead, 0.209" Body, Plastic Small Outline Package (EIAJ) DRAWING NO. 8S2 REV. C 13 2586AS–AVR–02/05 7. Errata The revision letter in this section refers to the revision of the ATtiny25/45/85 device. 7.1 ATtiny25/45/85 Rev. A • Too high power down power consumption • DebugWIRE looses communication when single stepping into interrupts • PLL not locking 1. Too high power down power consumption Three situations will lead to a too high power down power consumption. These are: – An external clock is selected by fuses, but the IO PORT is still enabled as an output. – The EEPROM is read before entering power down. – VCC is 4.5 volts or higher. Problem fix / Workaround – When using external clock, avoid setting the clock pin as Output. – Do not read the EEPROM if power down power consumption is important. – Use VCC lower than 4.5 Volts. 2. DebugWIRE looses communication when single stepping into interrupts When receiving an interrupt during single stepping, debugwire will loose communication. Problem fix / Workaround – When singlestepping disable interrupts. – When debugging interrupts, use breakpoints within the interrupt routine, and run into the interrupt. 3. PLL not locking When running at frequencies below 6.0 MHz, the PLL will not lock Problem fix / Workaround – When using the PLL, run at 6.0 MHz or higher. 14 ATtiny25/45/85 2586AS–AVR–02/05 ATtiny25/45/85 8. Datasheet Revision History 8.1 Rev. 2586A-02/05 1. Initial revision. 15 2586AS–AVR–02/05 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards 1150 East Cheyenne Mtn. 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