ON ASX340AT Color cmos ntsc/pal digital image Datasheet

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ASX340AT: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Features
1/4-Inch Color CMOS NTSC/PAL Digital Image
SOC with Overlay Processor
ASX340AT Datasheet, Rev. H
For the latest datasheet, please visit www.onsemi.com
Features
Table 1:
• Low-power CMOS image sensor with integrated
image flow processor (IFP) and video encoder
• 1/4-inch optical format, VGA resolution (640H x
480V)
• 2x upscaling zoom and pan control
• ±40 additional columns and ± 36 additional rows to
compensate for lens alignment tolerances
• Option to use single 2.8 V power supply with off-chip
bypass transistor
• Overlay generator for dynamic bitmap overlay
• Integrated video encoder for NTSC/PAL with overlay
capability and 10-bit I-DAC
• Integrated microcontroller for flexibility
• On-chip image flow processor performs
sophisticated processing, such as color recovery and
correction, sharpening, gamma, lens shading
correction, on-the-fly defect correction, auto white
balancing, and auto exposure
• Auto black-level calibration
• 10-bit, on-chip analog-to-digital converter (ADC)
• Internal master clock generated by on-chip phaselocked loop (PLL)
• Two-wire serial programming interface
• Interface to low-cost EEPROM and Flash through SPI
bus
• High-level host command interface
• Stand-alone operation support
• Comprehensive tool support for overlay generation
and lens correction setup
• Development system with DevWare
Applications
Parameter
Typical Value
Pixel size
and type
5.6 m x 5.6 m active pinnedphotodiode with high-sensitivity
mode for low-light conditions
Sensor clear pixels
728H x 560V (includes VGA active
pixels, demosaic and lens alignment
pixels)
NTSC output
720H x 487V
PAL output
720H x 576V
Optical area
(clear pixels)
4.077 mm x 3.136 mm
Optical format
¼-inch
Frame rate
50/60 fields/sec
Sensor scan mode
Progressive scan
Color filter array
RGB standard Bayer
Chief ray angle (CRA)
0°
Shutter type
Electronic rolling shutter (ERS)
Automatic Functions
Exposure, white balance, black level
offset correction, flicker detection and
avoidance, color saturation control,
on the-fly defect correction, aperture
correction
Programmable
Controls
Exposure, white balance, horizontal
and vertical blanking, color,
sharpness, gamma correction, lens
shading correction, horizontal and
vertical image flip, zoom, windowing,
sampling rates, GPIO control
Key parameters are continued on next page.
See “New Features” on page 3.
• Automotive rear view camera and side mirror
• Blind spot and surround view
ASX340AT/D Rev. H, 8/15 EN
Key Parameters
See “Ordering Information” on page 3
1
©Semiconductor Components Industries, LLC 2015,
ASX340AT: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Applications
Table 2:
Key Parameters (continued)
Parameter
Typical Value
Overlay Support
Utilizes SPI interface to load overlay data from external flash/EEPROM memory with the
following features:
•Available in Analog output and BT656 Digital output
•Overlay Size 360 x 480 pixel rendered into 720 x 480 (NTSC) or 720 x 576 (PAL)
•Up to four (4) overlays may be blended simultaneously
•Selectable readout: Rotating order user-selected
•Dynamic scenes by loading pre-rendered frames from external memory
•Palette of 32 colors out of 64,000
•8 colors per bitmap
•Blend factor dynamically-programmable for smooth transitions
•Fast update rate of up to 30 fps
•Every bitmap object has independent x/y position
•Statistic Engine to calibrate optical alignment
•Number Generator
Windowing
Programmable to any size
Analog gain range
0.5–16x
ADC
10-bit, on-chip
Output interface
Analog composite video out, single-ended or differential; 8-, 10-bit parallel digital output
Output data formats1
Digital: Raw Bayer 8-,10-bit, CCIR656, 565RGB, 555RGB, 444RGB
Parallel: 27 MHz Pixel clock
Data rate
Control interface
NTSC: 60 fields/sec
PAL: 50 fields/sec
Two-wire I/F for register interface plus high-level command exchange. SPI port to interface to
external memory to load overlay data, register settings, or firmware extensions.
Input clock for PLL
27 MHz
SPI Clock Frequencies
1.6875 – 18 MHz, programmable
Analog: 2.8V ± 5%
Supply voltage
Core: 1.8 V ± 5% (2.8V ± 5% power supply with off-chip bypass transistor generates a
1.70 - 1.95 V core voltage supply, which is acceptable for performance.)
IO: 2.8 V ± 5%
Analog output only
Power
consumption Digital output only
Full resolution at 60 fps: 192 mW
Full resolution at 60 fps: 291 mW
Package
63-BGA, 7.5 mm x 7.5 mm, 0.65mm pin pitch
Operating: -40 °C to 105 °C
Ambient temperature
Functional: -40 °C to + 85 °C
Storage: -50°C to + 150°C
Dark Current
< 200 e/s at 60 °C with a gain of 1
Fixed pattern Column
noise
Row
<2%
<2%
Responsivity
16.5 V/lux-s at 550 nm
Signal to noise ratio (S/N)
46 dB
Pixel dynamic range
87 dB
ASX340AT/D Rev. H, 8/15 EN
2
©Semiconductor Components Industries, LLC,2015.
ASX340AT: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
New Features
New Features
•
•
•
•
•
•
•
Temperature sensor for dynamic feedback and sensor control
Automatic 50Hz/60Hz flicker detection
2x upscaling zoom and pan/tilt control
Independent control of colorburst parameters in the NTSC/PAL encoder
Horizontal field of view adjustment between 700 and 720 pixels on the analog output
Option to use single 2.8V power supply with off-chip bypass transistor
SPI EEPROM support for lower cost system design.
Ordering Information
Table 3:
Available Part Numbers
Part Number
Product Description
Orderable Product Attribute Description
ASX340AT2C00XPED0-DPBR
Rev2, Color, 0deg CRA, iBGA Package
Drypack, Protective Film, Anti-Reflective Glass
ASX340AT2C00XPED0-DRBR
Rev2, Color, 0deg CRA, iBGA Package
Drypack, Anti-Reflective Glass
ASX340AT2C00XPED0-TPBR
Rev2, Color, 0deg CRA, iBGA Package
Tape & Reel, Protective Film, Anti-Reflective Glass
ASX340AT2C00XPED0-TRBR
Rev2, Color, 0deg CRA, iBGA Package
Tape & Reel, Anti-Reflective Glass
ASX340AT2C00XPEDD3-GEVK
Rev2, Color, Demo Kit
ASX340AT2C00XPEDH3-GEVB
Rev2, Color, Head Board
ASX340AT3C00XPED0-DPBR
Rev3, Color, 0deg CRA, iBGA Package
Drypack, Protective Film, Anti-Reflective Glass
ASX340AT3C00XPED0-DRBR
Rev3, Color, 0deg CRA, iBGA Package
Drypack, Anti-Reflective Glass
ASX340AT3C00XPED0-TPBR
Rev3, Color, 0deg CRA, iBGA Package
Tape & Reel, Protective Film, Anti-Reflective Glass
ASX340AT3C00XPED0-TRBR
Rev3, Color, 0deg CRA, iBGA Package
Tape & Reel, Anti-Reflective Glass
See the ON Semiconductor Device Nomenclature document (TND310/D) for a full
description of the naming convention used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at
www.onsemi.com.
ASX340AT/D Rev. H, 8/15 EN
3
©Semiconductor Components Industries, LLC,2015.
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Table of Contents
Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
New Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Pin Descriptions and Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
SOC Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Sensor Pixel Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
System Configuration and Usage Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Multicamera Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
External Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Slave Two-Wire Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Overlay Capability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
NVM Partition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Overlay Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Overlay Character Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Modes and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Spectral Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
ASX340AT/D Rev. H, 8/15 EN
4
©Semiconductor Components Industries, LLC, 2015.
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
List of Figures
List of Figures
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Figure 51:
Internal Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
System Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Using a Crystal Instead of an External Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Sensor Core Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Pixel Array Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Image Capture Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Pixel Color Pattern Detail (top right corner) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Spatial Illustration of Image Readout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Color Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Color Bars . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Gamma Correction Curve. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Multicamera System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
External Signal Processing Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Power-Up Sequence – Configuration Options Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Interface Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Host Command Process Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Single READ from Random Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Single Read from Current Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Sequential READ, Start from Random Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Sequential READ, Start from Current Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Single WRITE to Random Location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Sequential WRITE, Start at Random Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Overlay Data Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Memory Partitioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Overlay Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Internal Block Diagram Overlay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Example of Character Descriptor 0 Stored in ROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Full Character Set for Overlay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
CCIR656 8-Bit Parallel Interface Format for 525/60 (625/50) Video Systems . . . . . . . . . . . . . . . . . . . .49
Typical CCIR656 Vertical Blanking Intervals for 525/60 Video System. . . . . . . . . . . . . . . . . . . . . . . . . .50
Typical CCIR656 Vertical Blanking Intervals for 625/50 Video System. . . . . . . . . . . . . . . . . . . . . . . . . .51
Primary Clock Relationships . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Typical I/O Equivalent Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
NTSC Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Serial Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Digital Output I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Slew Rate Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Power Down Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
FRAME_SYNC to FRAME_VALID/LINE_VALID. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Reset to SPI Access Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Reset to Serial Access Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Reset to AE/AWB Image . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
SPI Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Video Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Equalizing Pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
V Pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Two-Wire Serial Bus Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Quantum Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
63-Ball iBGA Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
ASX340AT/D Rev. H, 8/15 EN
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©Semiconductor Components Industries, LLC, 2015.
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
List of Tables
List of Tables
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Table 25:
Table 26:
Table 27:
Table 28:
Table 29:
Table 30:
Table 31:
Table 32:
Table 33:
Table 34:
Table 35:
Table 36:
Table 37:
Table 38:
Table 39:
Table 40:
Table 41:
Table 42:
Table 43:
Table 44:
Table 45:
Table 46:
Table 47:
Table 48:
Key Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Key Parameters (continued). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Available Part Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Reset/Default State of Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
EIA Color Bars (NTSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
EBU Color Bars (PAL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
NTSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
PAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
YCbCr Output Data Ordering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
RGB Ordering in Default Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
2-Byte Bayer Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
System Manager Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Overlay Host Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
GPIO Host Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Flash Manager Host Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Sequencer Host Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Patch Loader Host Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Miscellaneous Host Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Calibration Stats Host Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Two-Wire Interface ID Address Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Transfer Time Estimate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Character Generator Details. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Field, Vertical Blanking, EAV, and SAV States 525/60 Video System . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Field, Vertical Blanking, EAV, and SAV States for 625/50 Video System . . . . . . . . . . . . . . . . . . . . . . . . .51
Output Data Ordering in DOUT RGB Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Output Data Ordering in Sensor Stand-Alone Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Parallel Digital Output I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Slew Rate for PIXCLK and DOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Power Down Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
FRAME_SYNC to FRAME_VALID/LINE_VALID Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
RESET_BAR Delay Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
SPI Data Setup and Hold Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Electrical Characteristics and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Video DAC Electrical Characteristics–Single-Ended Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Video DAC Electrical Characteristics–Differential Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Digital I/O Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Power Consumption – Condition 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Power Consumption – Condition 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
NTSC Signal Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Video Timing: Specification from Rec. ITU-R BT.470. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Equalizing Pulse: Specification from Rec. ITU-R BT.470 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
V Pulse: Specification from Rec. ITU-R BT.470 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Two-Wire Serial Bus Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
ASX340AT/D Rev. H, 8/15 EN
6
©Semiconductor Components Industries, LLC, 2015.
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
General Description
General Description
The ON Semiconductor ASX340AT is a VGA-format, single-chip CMOS active-pixel
digital image sensor for automotive applications. It captures high-quality color images
at VGA resolution and outputs NTSC or PAL interlaced composite video.
The VGA CMOS image sensor features ON Semiconductor’s breakthrough low-noise
imaging technology that achieves superior image quality (based on signal-to-noise ratio
and low-light sensitivity) while maintaining the inherent size, cost, low power, and integration advantages of ON Semiconductor's advanced active pixel CMOS process technology.
The ASX340AT is a complete camera-on-a-chip. It incorporates sophisticated camera
functions on-chip and is programmable through a simple two-wire serial interface or by
an attached SPI EEPROM or Flash memory that contains setup information that may be
loaded automatically at startup.
The ASX340AT performs sophisticated processing functions including color recovery,
color correction, sharpening, programmable gamma correction, auto black reference
clamping, auto exposure, 50Hz/60Hz flicker detection and avoidance, lens shading
correction, auto white balance (AWB), and on-the-fly defect identification and correction.
The ASX340AT outputs interlaced-scan images at 60 or 50 fields per second, supporting
both NTSC and PAL video formats. The image data can be output on one or two output
ports:
• Composite analog video (single-ended and differential output support)
• Parallel 8-, 10-bit digital
Architecture
Internal Block Diagram
Figure 1:
Internal Block Diagram
SPI
4
Two-Wire I/F
2. 8V
1 .8 V
2
Camera Control
SPI & 2W I/F
Interface
AWB
AE
640 x 480 Active Array
Image Flow Processor
¼” VGA ROI
@ 60 frames per sec.
10
Color & Gamma Correction
Color Space Conversion
Edge Enhancement
Overlay
Graphics
Generation
VideoEncoder
DAC
ASX340AT/D Rev. H, 8/15 EN
7
8
BT -656
NTSC /
PAL
©Semiconductor Components Industries, LLC, 2015.
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Architecture
System Block Diagram
The system block diagram will depend on the application. The system block diagram in
Figure 2 shows all components; optional peripheral components are highlighted.
Control information will be received by a microcontroller through the automotive bus to
communicate with the ASX340AT through its two-wire serial bus. Optional components
will vary by application.
Figure 2:
System Block Diagram
18 pF - NPO
EXTCLK
27.000 MHz
XTAL
18 pF - NPO
System Bus
μC
RESET_BAR
FRAME _SYNC
SPI
2WIRE I/F
Serial Data
EEPROM/Flash
1KB - 16MB
LP Filter
DAC _POS
2.35kΩ
DAC _REF
Composite
Video
PAL /NTSC
DAC _NEG
37.5Ω
VDD_DAC (2.8V)
VDD_PLL (2.8V)
.
2.8V
VDD_IO (2.8V)
.
Optional
VAA _PIX (2.8V)
VAA (2.8V)
VDD (1.8V )
VREG_BASE
DOUT[7:0]
DOUT_LSB0, 1
CCIR 656/
GPO
PIXCLK
FRAME_VALID
LINE_VALID
ASX340AT/D Rev. H, 8/15 EN
8
©Semiconductor Components Industries, LLC, 2015.
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Architecture
Crystal Usage
As an alternative to using an external oscillator, a fundamental 27 MHz crystal may be
connected between EXTCLK and XTAL. Two small loading capacitors of 10–22 pF of NPO
dielectric should be added as shown in Figure 3.
ON Semiconductor does not recommend using the crystal option for applications above
85°C. A crystal oscillator with temperature compensation is recommended.
Figure 3:
Using a Crystal Instead of an External Oscillator
Sensor
18 pF - NPO
EXTCLK
27.000 MHz
XTAL
18pF - NPO
Note:
ASX340AT/D Rev. H, 8/15 EN
Value of load capacitor is crystal dependent. Crystal with small load capacitor is recommended.
9
©Semiconductor Components Industries, LLC, 2015.
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Pin Descriptions and Assignments
Pin Descriptions and Assignments
Table 4:
Pin Descriptions
Pin Number
Pin Name
Type
Description
Clock and Reset
A2
EXTCLK
Input
Master input clock (27MHz): This can either be a square-wave generated from an
oscillator (in which case the XTAL input must be left unconnected) or connected
directly to a crystal.
B1
XTAL
Output
If EXTCLK is connected to one pin of a crystal, this signal is connected to the other
pin; otherwise this signal must be left unconnected.
D2
RESET_BAR
Input
Asynchronous active-low reset: When asserted, the device will return all interfaces
to their reset state. When released, the device will initiate the boot sequence. This
signal has an internal pull-up resistor.
E1
FRAME_SYNC
Input
This input can be used to set the output timing of the ASX340AT to a fixed point in
the frame.
The input buffer associated with this input is permanently enabled. This signal
must be connected to GND if not used.
Register Interface
F1
F2
E2
SCLK
SDATA
SADDR
D4
SPI_SCLK
Input
These two signals implement the serial communications protocol for access to the
Input/Output internal registers and variables.
Input
This signal controls the device ID that will respond to serial communication
commands.
Two-wire serial interface device ID selection:
0: 0x90
1: 0xBA
SPI Interface
Output
Clock output for interfacing to an external SPI memory such as Flash/EEPROM.
Tri-state when RESET_BAR is asserted.
E4
SPI_SDI
Input
H3
SPI_SDO
Output
Data in from SPI device. This signal has an internal pull-up resistor.
Data out to SPI device. Tri-state when RESET_BAR is asserted.
H2
SPI_CS_N
Output
Chip selects to SPI device. Tri-state when RESET_BAR is asserted.
F7
G7
E6
F8, D6, D7,
C6, C7, B6,
B7, A6
FRAME_VALID
LINE_VALID
PIXCLK
DOUT[7:0]
Input/Output
Input/Output
Output
Output
B3
C2
DOUT_LSB1
DOUT_LSB0
(Parallel) Pixel Data Output
ASX340AT/D Rev. H, 8/15 EN
Pixel data from the ASX340AT can be routed out on this interface and processed
externally.
To save power, these signals are driven to a constant logic level unless the parallel
pixel data output or alternate (GPIO) function is enabled for these pins.
This interface is disabled by default.
The slew rate of these outputs is programmable.
These signals can also be used as general purpose input/outputs.
Input/Output When the sensor core is running in bypass mode, it will generate 10 bits of output
Input/Output data per pixel. These two pins make the two LSB of pixel data available externally.
Leave DOUT_LSB1and DOUT_LSB0 unconnected if not used. To save power, these
signals are driven to a constant logic level unless the sensor core is running in
bypass mode or the alternate function is enabled for these pins. The slew rate of
these outputs is programmable.
10
©Semiconductor Components Industries, LLC, 2015.
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Pin Descriptions and Assignments
Table 4:
Pin Descriptions (continued)
Pin Number
Pin Name
Type
Description
Composite Video Output
F5
DAC_POS
Output
Positive video DAC output in differential mode.
Video DAC output in single-ended mode. This interface is enabled by default using
NTSC/PAL signaling. For applications where composite video output is not
required, the video DAC can be placed in a power-down state under software
control.
G5
DAC_NEG
Output
Negative video DAC output in differential mode.
A4
DAC_REF
Output
External reference resistor for the video DAC.
Manufacturing Test Interface
D3
TDI
Input
JTAG Test pin (Reserved for Test Mode)
G2
TDO
Output
JTAG Test pin (Reserved for Test Mode)
F3
TMS
Input
JTAG Test pin (Reserved for Test Mode)
C3
TCK
Input
JTAG Test pin (Reserved for Test Mode)
C4
TRST_N
Input
Connect to GND.
G6
ATEST1
Input
Analog test input. Connect to GND in normal operation.
F6
ATEST2
Input
Analog test input. Connect to GND in normal operation.
GPIO
C1
GPIO12
Input/Output Dedicated general-purpose input/output pin.
A3
GPIO13
Input/Output Dedicated general-purpose input/output pin.
Power
G4
VREG_BASE
Supply
Voltage regulator control. Leave floating if not used.
A5, A7, D8,
E7, G1, G3
VDD
Supply
Supply for VDD core: 1.8V nominal. Can be connected to the output of the
transistor of the off-chip bypass transistor or an external 1.8V power supply.
B2, B8, C8,
E3, E8, G8,
H8
H5
VDD_IO
Supply
VDD_DAC
Supply
Supply for video DAC: 2.8V nominal.
A8
VDD_PLL
Supply
Supply for PLL: 2.8V nominal.
Supply for digital IOs: 2.8V nominal.
B4, H6
VAA
Supply
Analog power: 2.8V nominal.
H7
VAA_PIX
Supply
Analog pixel array power: 2.8V nominal. Must be at same voltage potential as VAA.
H4
Reserved
B5, C5, D1,
D5, H1
E5, F4
DGND
Supply
AGND
Supply
ASX340AT/D Rev. H, 8/15 EN
Leave floating for normal operation.
Digital ground.
Analog ground.
11
©Semiconductor Components Industries, LLC, 2015.
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Pin Descriptions and Assignments
Pin Assignments
Pin 1 is not populated with a ball. That allows the device to be identified by an additional
marking.
Table 5:
Pin Assignments
1
2
A
3
EXTCLK
GPIO13
4
5
6
7
8
DAC_REF
VDD
DOUT0
VDD
VDD_PLL
B
XTAL
VDD_IO
DOUT_LSB1
VAA
GND
DOUT2
DOUT1
VDD_IO
C
GPIO12
DOUT_LSB0
TCK
TRST_N
GND
DOUT4
DOUT3
VDD_IO
D
GND
RESET_BAR
TDI
SPI_SCLK
GND
DOUT6
DOUT5
VDD
E
FRAME_SYNC
SADDR
VDD_IO
SPI_SDI
AGND
PIXCLK
VDD
VDD_IO
F
SCLK
SDATA
TMS
AGND
DAC_POS
ATEST2
FRAME_VALID
DOUT7
G
VDD
TDO
VDD
VREG_BASE
DAC_NEG
ATEST1
LINE_VALID
VDD_IO
H
GND
SPI_CS_N
SPI_SDO
Reserved
VDD_DAC
VAA
VAA_PIX
VDD_IO
Table 6:
Reset/Default State of Interfaces
Name
Reset State
Default State
Notes
EXTCLK
Clock running or stopped
Clock running
Input
XTAL
N/A
N/A
Input
RESET_BAR
Asserted
De-asserted
Input
SCLK
N/A
N/A
Input. Must always be driven to high via
a pull-up resistor in the range of 1.5 to 4.7 k.
SDATA
High impedance
High impedance
Input/Output. Must always be driven to high
via
a pull-up resistor in the range of 1.5 to 4.7 k.
SADDR
N/A
N/A
Input. Must be permanently tied to VDD_IO or
GND.
SPI_SCLK
High impedance.
Driven, logic 0
Output. Output enable is R0x0032[13].
SPI_SDI
Internal pull-up enabled.
Internal pull-up enabled
Input. Internal pull-up is permanently
enabled.
SPI_SDO
High impedance
Driven, logic 0
Output enable is R0x0032[13].
Output enable is R0x0032[13].
SPI_CS_N
High impedance
Driven, logic 1
FRAME_VALID
LINE_VALID
High impedance
High impedance
ASX340AT/D Rev. H, 8/15 EN
12
Input/Output. This interface is disabled by
default. Input buffers (used for GPIO function)
powered down by default, so these pins can
be left unconnected (floating). After reset,
these pins are powered up, sampled, then
powered down again as part of the autoconfiguration mechanism. See Note 2.
©Semiconductor Components Industries, LLC, 2015.
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Pin Descriptions and Assignments
Table 6:
Reset/Default State of Interfaces (continued)
Name
Reset State
Default State
PIXCLK
DOUT7
DOUT6
DOUT5
DOUT4
DOUT3
DOUT2
DOUT1
DOUT0
DOUT_LSB1
DOUT_LSB0
High impedance
Driven, logic 0
Notes
Output. This interface disabled by default.
See Note 1.
High impedance
High impedance
High impedance
High impedance
Input/Output. This interface disabled by
default. Input buffers (used for GPIO function)
powered down by default, so these pins can
be left unconnected (floating). After reset,
these pins are powered-up, sampled, then
powered down again as part of the autoconfiguration mechanism.
DAC_POS
DAC_NEG
DAC_REF
TDI
High impedance
Driven
Output. Interface disabled by hardware reset
and enabled by default when the device starts
streaming.
Internal pull-up enabled
Internal pull-up enabled
Input. Internal pull-up means that this pin can
be left unconnected (floating).
TDO
High impedance
High impedance
Output. Driven only during appropriate parts
of the JTAG shifter sequence.
TMS
Internal pull-up enabled
Internal pull-up enabled
Input. Internal pull-up means that this pin can
be left unconnected (floating).
TCK
Internal pull-up enabled
Internal pull-up enabled
Input. Internal pull-up means that this pin can
be left unconnected (floating).
TRST_N
N/A
N/A
Input. Must always be driven to a valid logic
level. Must be driven to GND for normal
operation.
FRAME_SYNC
N/A
N/A
Input. Must always be driven to a valid logic
level. Must be driven to GND if not used.
GPIO12
High impedance
High impedance
Input/Output. This interface disabled by
default. Input buffers (used for GPIO function)
powered down by default, so these pins can
be left unconnected (floating)
GPIO13
High impedance
High impedance
Input/Output. This interface disabled by
default. Input buffers (used for GPIO function)
powered down by default, so these pins can
be left unconnected (floating).
ATEST1
N/A
N/A
Must be driven to GND for normal operation.
ATEST2
N/A
N/A
Must be driven to GND for normal operation.
Notes:
ASX340AT/D Rev. H, 8/15 EN
1. The reason for defining the default state as logic 0 rather than high impedance is this: when wired
in a system (for example, on ON Semiconductor’s demo boards), these outputs will be connected,
and the inputs to which they are connected will want to see a valid logic level. No current drain
should result from driving these to a valid logic level (unless there is a pull-up at the system level).
2. These pads have their input circuitry powered down, but they are not output-enabled. Therefore,
they can be left floating but they will not drive a valid logic level to an attached device.
13
©Semiconductor Components Industries, LLC, 2015.
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
SOC Description
SOC Description
Detailed Architecture Overview
Sensor Core
The sensor consists of a pixel array, an analog readout chain, a 10-bit ADC with programmable
gain and black offset, and timing and control as illustrated in Figure 4.
Figure 4:
Sensor Core Block Diagram
Active Pixel
Sensor (APS)
Array
Control Register
Communication
Bus
to IFP
Timing and Control
Clock
Sync
Signals
Analog Processing
10-Bit Data
to IFP
ADC
Pixel Array Structure
The sensor core pixel array is configured as 728 columns by 560 rows, as shown in
Figure 5.
Figure 5:
Pixel Array Description
(40, 36)
(0, 0)
Pixel logical address = (727, 559)
demosaic columns
Active pixel array
640 x 480
Pixel logical address = (0, 0)
lens alignment columns
lens alignment columns
demosaic columns
lens alignment rows
demosaic rows
demosaic rows
lens alignment rows
(687, 523)
(not to scale)
Black rows used internally for automatic black level adjustment are not addressed by
default, but can be read out in raw output mode via a register setting.
There are 728 columns by 560 rows of optically-active pixels (that is, clear pixels) that
include a pixel boundary around the VGA (640 x 480) image to avoid boundary effects
during color interpolation and correction. Among the 728 columns by 560 rows of clear
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ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
SOC Description
pixels, there are 36 lens alignment rows on the top and bottom, and 40 lens alignment
columns on the left and right; and there are 4 demosaic rows and 4 demosaic columns
on each side.
Figure 6 illustrates the process of capturing the image. The original scene is flipped and
mirrored by the sensor optics. Sensor readout starts at the lower right corner. The image
is presented in true orientation by the output display.
Figure 6:
Image Capture Example
SCENE
(Front view)
fI
so
es
oc
Pr
e
ag
m
in
er
th
Ga
OPTICS
g
d
an
e
IMAGE CAPTURE
ag
Im
IMAGE SENSOR
(Rear view)
isp
D
Row by Row
y
la
Start Rasterization
Start Readout
IMAGE RENDERING
DISPLAY
(Front view)
ASX340AT/D Rev. H, 8/15 EN
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ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Sensor Pixel Array
Sensor Pixel Array
The active pixel array is 640 x 480 pixels. In addition, there are 72 rows and 80 columns
for lens alignment and 8 rows and 8 columns for demosaic.
Figure 7:
Pixel Color Pattern Detail (top right corner)
Column Readout Direction
..
.
Row
Readout
Direction
...
Black Pixels
G
R
G
R
G
R
G
B
G
B
G
B
G
B
G
R
G
R
G
R
G
B
G
B
G
B
G
B
G
R
G
R
G
R
G
B
G
B
G
B
G
B
First Lens Alignment
Pixel
(64, 0)
Output Data Format
The sensor core image data are read out in progressive scan order. Valid image data are
surrounded by horizontal and vertical blanking, shown in Figure 8.
For NTSC output, the horizontal size is stretched from 640 to 720 pixels. The vertical size
is 243 pixels per field; 240 image pixels and 3 dark pixels that are located at the bottom of
the image field.
For PAL output, the horizontal size is also stretched from 640 to 720 pixels. The vertical
size is 288 pixels per field.
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ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Sensor Pixel Array
Figure 8:
Spatial Illustration of Image Readout
P0,0 P0,1 P0,2.....................................P0,n-1 P0,n
P2,0 P2,1 P2,2.....................................P2,n-1 P2,n
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
Valid Image Odd Field
Horizontal
Blanking
Pm-2,0 Pm-2,1.....................................Pm-2,n-1 Pm-2,n 00 00 00 .................. 00 00 00
Pm,0 Pm,1.....................................Pm,n-1 Pm,n
00 00 00 .................. 00 00 00
00 00 00 ..................................... 00 00 00
00 00 00 ..................................... 00 00 00
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
Vertical Even Blanking
Vertical/Horizontal
Blanking
00 00 00 ..................................... 00 00 00
00 00 00 ..................................... 00 00 00
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
P1,0 P1,1 P1,2.....................................P1,n-1 P1,n
P3,0 P3,1 P3,2.....................................P3,n-1 P3,n
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
Valid Image Even Field
Horizontal
Blanking
Pm-1,0 Pm-1,1.....................................Pm-1,n-1 Pm-1,n 00 00 00 .................. 00 00 00
Pm+1,0 Pm+1,1..................................Pm+1,n-1 Pm+1,n 00 00 00 .................. 00 00 00
ASX340AT/D Rev. H, 8/15 EN
00 00 00 ..................................... 00 00 00
00 00 00 ..................................... 00 00 00
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
Vertical Odd Blanking
Vertical/Horizontal
Blanking
00 00 00 ..................................... 00 00 00
00 00 00 ..................................... 00 00 00
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
17
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ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Sensor Pixel Array
Image Flow Processor
Image and color processing in the ASX340AT are implemented as an image flow
processor (IFP) coded in hardware logic. During normal operation, the embedded
microcontroller will automatically adjust the operation parameters. The IFP is broken
down into different sections, as outlined in Figure 9.
Figure 9:
Color Pipeline
RAW 10
Pixel Array
ADC
Raw Data
IFP
Test Pattern
Generator
MUX
Black
Level
Subtraction
Digital Gain Control
Lens Shading
Correction
Defect Correction,
Noise Reduction,
Color Interpolation
Statistics
Engine
8-bit
RGB
RGB to YUV
10/12-Bit
RGB
8-bit
YUV
Color Correction
Color Kill
Aperture
Correction
Output
Formatting
YUV to RGB
Gamma
Correction
(12-to-8 Lookup)
Overlay Control
Output
Interface
Analog Output Mux
NTSC/PAL
ASX340AT/D Rev. H, 8/15 EN
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Parallel Output Mux
Parallel
Output
©Semiconductor Components Industries, LLC, 2015.
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Sensor Pixel Array
Test Patterns
During normal operation of the ASX340AT, a stream of raw image data from the sensor
core is continuously fed into the color pipeline. For test purposes, this stream can be
replaced with a fixed image generated by a special test module in the pipeline. The
module provides a selection of test patterns sufficient for basic testing of the pipeline.
NTSC/PAL Test Pattern Generation
There is a built-in standard EIA (NTSC) and EBU (PAL) color bars to support hue and
color saturation characterization. Each pattern consists of seven color bars (white,
yellow, cyan, green, magenta, red, and blue). The Y, Cb and Cr values for each bar are
detailed in Tables 7 and 8.
Figure 10:
Color Bars
Table 7:
EIA Color Bars (NTSC)
Y
Cb
Cr
Table 8:
Y
Cb
Cr
Nominal Range
White
Yellow
Cyan
Green
Magenta
Red
Blue
16 to 235
16 to 240
16 to 240
180
128
128
162
44
142
131
156
44
112
72
58
84
184
198
65
100
212
35
212
114
EBU Color Bars (PAL)
Nominal Range
White
Yellow
Cyan
Green
Magenta
Red
Blue
16 to 235
16 to 240
16 to 240
235
128
128
162
44
142
131
156
44
112
72
58
84
184
198
65
100
212
35
212
114
CCIR-656 Format
The color bar data is encoded in 656 data streams. The duration of the blanking and
active video periods of the generated 656 data are summarized in Tables 9 and 10.
Table 9:
NTSC
ASX340AT/D Rev. H, 8/15 EN
Line Numbers
Field
1-3
2
Blanking
4-19
1
Blanking
19
Description
©Semiconductor Components Industries, LLC, 2015.
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Sensor Pixel Array
Table 9:
Table 10:
NTSC (continued)
Line Numbers
Field
Description
20-263
1
Active video
264-265
1
Blanking
266-282
2
Blanking
283-525
2
Active Video
Line Numbers
Field
Description
1-22
1
Blanking
23-310
1
Active video
311-312
1
Blanking
313-335
2
Blanking
336-623
2
Active video
624-625
2
Blanking
PAL
Black Level Subtraction and Digital Gain
Image stream processing starts with black level subtraction and multiplication of all
pixel values by a programmable digital gain. Both operations can be independently set
to separate values for each color channel (R, Gr., Gb, B). Independent color channel
digital gain can be adjusted with registers. Independent color channel black level adjustments can also be made. If the black level subtraction produces a negative result for a
particular pixel, the value of this pixel is set to 0.
Positional Gain Adjustments (PGA)
Lenses tend to produce images whose brightness is significantly attenuated near the
edges. There are also other factors causing fixed pattern signal gradients in images
captured by image sensors. The cumulative result of all these factors is known as image
shading. The ASX340AT has an embedded shading correction module that can be
programmed to counter the shading effects on each individual R, Gb, Gr., and B color
signal.
The Correction Function
The correction functions can then be applied to each pixel value to equalize the
response across the image as follows:
P corrected (row,col)=P sensor (row,col)*f(row,col)
(EQ 1)
where P is the pixel values and f is the color dependent correction functions for each
color channel.
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ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Sensor Pixel Array
Color Interpolation
In the raw data stream fed by the sensor core to the IFP, each pixel is represented by a
10-bit integer number, which can be considered proportional to the pixel's response to a
one-color light stimulus, red, green, or blue, depending on the pixel's position under the
color filter array. Initial data processing steps, up to and including the defect correction,
preserve the one-color-per-pixel nature of the data stream, but after the defect correction it must be converted to a three-colors-per-pixel stream appropriate for standard
color processing. The conversion is done by an edge-sensitive color interpolation
module. The module pads the incomplete color information available for each pixel
with information extracted from an appropriate set of neighboring pixels. The algorithm
used to select this set and extract the information seeks the best compromise between
preserving edges and filtering out high frequency noise in flat field areas. The edge
threshold can be set through register settings.
Color Correction and Aperture Correction
To achieve good color fidelity of the IFP output, interpolated RGB values of all pixels are
subjected to color correction. The IFP multiplies each vector of three pixel colors by a
3 x 3 color correction matrix. The three components of the resulting color vector are all
sums of three 10-bit numbers. Since such sums can have up to 12 significant bits, the bit
width of the image data stream is widened to 12 bits per color (36 bits per pixel). The
color correction matrix can be either programmed by the user or automatically selected
by the auto white balance (AWB) algorithm implemented in the IFP. Color correction
should ideally produce output colors that are corrected for the spectral sensitivity and
color crosstalk characteristics of the image sensor. The optimal values of the color
correction matrix elements depend on those sensor characteristics and on the spectrum
of light incident on the sensor. The color correction parameters can be adjusted through
register settings.
To increase image sharpness, a programmable 2D aperture correction (sharpening filter)
is applied to color-corrected image data. The gain and threshold for 2D correction can
be defined through register settings.
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ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Sensor Pixel Array
Gamma Correction
The ASX340AT includes a block for gamma correction that can adjust its shape based on
brightness to enhance the performance under certain lighting conditions. Two custom
gamma correction tables may be uploaded corresponding to a brighter lighting condition and a darker lighting condition. At power-up, the IFP loads the two tables with
default values. The final gamma correction table used depends on the brightness of the
scene and takes the form of an interpolated version of the two tables.
The gamma correction curve (as shown in Figure 11) is implemented as a piecewise
linear function with 19 knee points, taking 12-bit arguments and mapping them to 8-bit
output. The abscissas of the knee points are fixed at 0, 64, 128, 256, 512, 768, 1024, 1280,
1536, 1792, 2048, 2304, 2560, 2816, 3072, 3328, 3584, 3840, and 4096. The 8-bit ordinates
are programmable through registers.
Figure 11:
Gamma Correction Curve
RGB to YUV Conversion
For further processing, the data is converted from RGB color space to YUV color space.
Color Kill
To remove high-or low-light color artifacts, a color kill circuit is included. It affects only
pixels whose luminance exceeds a certain preprogrammed threshold. The U and V
values of those pixels are attenuated proportionally to the difference between their luminance and the threshold.
YUV Color Filter
As an optional processing step, noise suppression by one-dimensional low-pass filtering
of Y and/or UV signals is possible. A 3- or 5-tap filter can be selected for each signal.
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ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Sensor Pixel Array
YUV-to-RGB/YUV Conversion and Output Formatting
The YUV data stream emerging from the colorpipe can either exit the color pipeline as-is
or be converted before exit to an alternative YUV or RGB data format.
Output Format and Timing
YUV/RGB Data Ordering
The ASX340AT supports swapping YCbCr mode, as illustrated in Table 11.
Table 11:
YCbCr Output Data Ordering
Mode
Data Sequence
Default (no swap)
Swapped CbCr
Swapped YC
Swapped CbCr, YC
Yi
Yi
Cbi
Cri
Cbi
Cri
Yi
Yi
Cri
Cbi
Yi+1
Yi+1
Yi+1
Yi+1
Cri
Cbi
The RGB output data ordering in default mode is shown in Table 12. The odd and even
bytes are swapped when luma/chroma swap is enabled. R and B channels are bit-wise
swapped when chroma swap is enabled.
Table 12:
RGB Ordering in Default Mode
Mode (Swap Disabled)
Byte
D7D6D5D4D3D2D1D0
565RGB
Odd
Even
Odd
Even
Odd
Even
Odd
Even
R7R6R5R4R3G7G6G5
G4G3G2B7B6B5B4B3
0 R7R6R5R4R3G7G6
G5G4G3B7B6B5B4B3
R7R6R5R4G7G6G5G4
B7B6B5B4 0 0 0 0
0 0 0 0 R7R6R5R4
G7G6G5G4B7B6B5B4
555RGB
444xRGB
x444RGB
Uncompressed 10-Bit Bypass Output
Raw 10-bit Bayer data from the sensor core can be output in bypass mode in two ways:
• Using 8 data output signals (DOUT[7:0]) and GPIO[1:0]. The GPIO signals are the least
significant 2 bits of data.
• Using only 8 signals (DOUT[7:0]) and a special 8 + 2 data format, shown in Table 13.
Table 13:
2-Byte Bayer Format
Byte
Bits Used
Bit Sequence
Odd bytes
8 data bits
D9D8D7D6D5D4D3D2
Even bytes
2 data bits + 6 unused bits
0 0 0 0 0 0 D1D0
Readout Formats
Progressive format is used for raw Bayer output.
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ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Sensor Pixel Array
Output Formats
ITU-R BT.656 and RGB Output
TheASX340AT can output processed video as a standard ITU-R BT.656 (CCIR656) stream,
an RGB stream, or as unprocessed Bayer data. The ITU-R BT.656 stream contains YCbCr
4:2:2 data with embedded synchronization codes. This output is typically suitable for
subsequent display by standard video equipment or JPEG/MPEG compression.
Colorpipe data (pre-lens correction and overlay) can also be output in YCbCr 4:2:2 and a
variety of RGB formats in 640 by 480 progressive format in conjunction with
LINE_VALID and FRAME_VALID.
The ASX340AT can be configured to output 16-bit RGB (565RGB), 15-bit RGB (555RGB),
and two types of 12-bit RGB (444RGB). Refer to Table 24 and Table 25 on page 50 for
details.
Bayer Output
Unprocessed Bayer data are generated when bypassing the IFP completely—that is, by
simply outputting the sensor Bayer stream as usual, using FRAME_VALID, LINE_VALID,
and PIXCLK to time the data. This mode is called sensor bypass mode.
Output Ports
Composite Video Output
The composite video output DAC is external-resistor-programmable and supports both
single-ended and differential output. The DAC is driven by the on-chip video encoder
output.
Parallel Output
Parallel output uses either 8-bit or 10-bit output. Eight-bit output is used for ITU-R
BT.656 and RGB output. Ten-bit output is used for raw Bayer output.
Zoom Support
The ASX340AT supports zoom x1 and x2 modes, in interlaced and progressive scan
modes. The progressive support is limited to the VGA at either 60 fps or 50 fps.
In the zoom x2 modes, the sensor is configured for QVGA (320 x 240), and the zoom x2
window can be configured to pan around the VGA window.
FOV Stretch Support
The ASX340AT supports the ability to control the active 'width' of the TV output line,
between 692 and 720 pixels. The hardware supports two margins, each a maximum of 14
pixels width, and has to be an even number of pixels.
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ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
System Configuration and Usage Modes
System Configuration and Usage Modes
How a camera based on the ASX340AT will be configured depends on what features are
used. There are essentially three configuration modes for ASX340AT: Auto-Config Mode,
Flash-Config Mode, and Host-Config Mode. Refer to System Configuration and Usage
Modes in the Developer Guide document for details.
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ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Multicamera Support
Multicamera Support
Two or more ASX340AT sensors may be synchronized to a frame by asserting the
FRAME_SYNC signal. At that point, the sensor and video encoder will reset without
affecting any register settings. The ASX340AT may be triggered to be synchronized with
another ASX340AT or an external event.
Figure 12:
Multicamera System Block Diagram
Decoder/DSP
Dual Camera
CVBS
ASX340
OSC
Camera 1
F_SYNC
CVBS
Camera 2
ASX340
F_SYNC
1
System Bus
ASX340AT/D Rev. H, 8/15 EN
μC
26
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ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
External Signal Processing
External Signal Processing
An external signal processor can take data from ITU656 or raw Bayer output format and
post-process or compress the data in various formats.
Figure 13:
External Signal Processing Block Diagram
27 MHz
EXTCLK
SPI
Serial
EEPROM/Flash
1KB to 16MB
VIDEO_P
VIDEO_N
CVBS
PAL/NTSC
DOUT [7:0]
PIXCLK
ASX340AT/D Rev. H, 8/15 EN
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Signal processor
©Semiconductor Components Industries, LLC, 2015.
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
External Signal Processing
Device Configuration
After power is applied and the device is out of reset by de-asserting the RESET_BAR pin,
it will enter a boot sequence to configure its operating mode. There are essentially three
three configuration modes: Flash/EEPROM Config, Auto Config, and Host Config. Figure
14: “Power-Up Sequence – Configuration Options Flow Chart,” on page 29 contains
more details on the configuration options.
The SOC firmware supports a System Configuration phase at start-up. This consists of
five modes of execution:
1. Flash Detection
2. Flash-Config
3. Auto-Config
4. Host-Config
5. Change-Config (commences streaming - completes the System Configuration mode).
The System Configuration phase is entered immediately after the firmware initializes
following SOC power-up or reset. By default, the firmware first enters the Flash Detection mode.
The Flash Detection mode attempts to detect the presence of an SPI Flash or EEPROM
device:
• If no device is detected, the firmware then samples the SPI_SDI pin state to determine
the next mode:
– If SPI_SDI == 0 then it enters the Host-Config mode.
– If SPI_SDI == 1 then it enters the Auto-Config mode.
• If a device is detected, the firmware switches to the Flash-Config mode.
In the Flash-Config phase, the firmware interrogates the device to determine if it
contains valid configuration records:
• If no records are detected, then the firmware enters the Auto-Config mode.
• If records are detected, the firmware processes them. By default, when all Flash
records are processed the firmware switches to the Host-Config mode. However, the
records encoded into the Flash can optionally be used to instruct the firmware to
proceed to one of the other mode (auto-config/change-config).
The Auto-Config mode uses the FRAME_VALID, LINE_VALID, DOUT_LSB0 and
DOUT_LSB1 pins to configure the operation of the device, such as video format and
pedestal (refer to the Developer Guide for more details). After Auto-Config completes
the firmware switches to the Change-Config mode.
In the Host-Config mode, the firmware performs no configuration, and remains idle
waiting for configuration and commands from the host. The System Configuration
phase is effectively complete and the SOC will take no actions until the host issues
commands.
In the Change-Config mode, the firmware performs a 'Change-Config' operation. This
applies the current configuration settings to the SOC, and commences streaming. This
completes the System Configuration phase.
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ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
External Signal Processing
Power Sequence
In power-up, refer to the power-up sequence in Figure 39: “Power Up Sequence,” on
page 59.
In power down, refer to Figure 40: “Power Down Sequence,” on page 60 for details.
Figure 14:
Power-Up Sequence – Configuration Options Flow Chart
Power Up/ RESET
EEPROM/Flash
device present?
yes
no
yes
Disable Auto-Config
EEPROM/Flash
contents valid?
no
SPI _SDI = 0?
Parse
EEPROM/Flash
Content
no
(optional)
:
Auto-Config
Change-Config
(default)
Auto Configuration:
FRAME_VALID
LINE_VALID
D OUT _LSB 0
D OUT _LSB 1
Auto-Config
Wait for Host
Command
Host Config
Wait for Host
Command
Change Config
Change-Config
Wait for Host
Command
ASX340AT/D Rev. H, 8/15 EN
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ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
External Signal Processing
Supported NVM Devices
The ASX340AT supports a variety of SPI non-volatile memory (NVM) devices. Refer to
Flash/EEPROM Programming section in Developer Guide document for details.
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ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
External Signal Processing
Host Command Interface
ON Semiconductor sensors and SOCs contain numerous registers that are accessed
through a two-wire interface with speeds up to 400 kHz.
The ASX340AT in addition to writing or reading straight to/from registers or firmware
variables, has a mechanism to write higher level commands, the Host Command Interface (HCI). Once a command has been written through the HCI, it will be executed by
on-chip firmware and the results are reported back. In general, registers should not be
accessed with the exception of registers that are marked for “User Access.”
EEPROM or Flash memory is also available to store commands for later execution.
Under DMA control, a command is written into the SOC and executed.
For a complete description of host commands, refer to the ASX340AT Host Command
Interface Specification.
Figure 15:
Interface Structure
bit
Addr 0x40
15
1
0
14
0
Host Command to FW
Response from FW
command register
door bell
bit
Addr 0xFC00
0
Parameter 0
cmd_handler_params_pool_0
Addr 0xFC02
cmd_handler_params_pool_1
Addr 0xFC04
cmd_handler_params_pool_2
Addr 0xFC06
cmd_handler_params_pool_3
Addr 0xFC08
cmd_handler_params_pool_4
Addr 0xFC0A
cmd_handler_params_pool_5
Addr 0xFC0C
cmd_handler_params_pool_6
Addr 0xFC0E
ASX340AT/D Rev. H, 8/15 EN
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Parameter 7
31
cmd_handler_params_pool_7
©Semiconductor Components Industries, LLC, 2015.
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
External Signal Processing
Host Command Process Flow
Figure 16: Host Command Process Flow
Issu e
C o mma n d
Wa it fo r a
re sp o n se?
H o st co u ld in se rt a n
o p tio n a l d e la y here
Ye s
R e a d C o mma n d
re g ister
H o st co u ld in se rt a n
o p tio n a l d e la y here
No
R e a d C o mma n d
re g iste r
No
D o o rb e ll
b it cle a r ?
D o o rb e ll b it
cle a r?
Ye s
At th is p o in t
C o mma n d R e g iste r
co n ta in s re sp o n se co d e
C o mma n d h a s
p a ra me te rs?
Ye s
C o mma n d
h a s response
parameters ?
Ye s
No
No
Write p a ra me te rs
to
Pa ra me te r Po o l
No
Ye s
R e a d re sp o n se
p a ra me te rs fro m
Pa ra me te r Po o l
Write co mma n d
to
C o mma n d re g iste r
Done
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ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
External Signal Processing
Command Flow
The host issues a command by writing (through a two-wire interface bus) to the
command register. All commands are encoded with bit 15 set, which automatically
generates the host command (doorbell) interrupt to the microprocessor.
Assuming initial conditions, the host first writes the command parameters (if any) to the
parameters pool (in the command handler's logical page), then writes the command to
command register. The firmware interrupt handler then signals the Command Handler
task to process the command.
If the host wishes to determine the outcome of the command, it must poll the command
register waiting for the doorbell bit to be cleared. This indicates that the firmware
completed processing the command. When the doorbell bit is cleared, the contents of
the command register indicate the command's result status. If the command generated
response parameters, the host can now retrieve these from the parameters pool.
Note:
The host must not write to the parameters pool, nor issue another command, until
the previous command completes. This is true even if the host does not care about the
result of the previous command. Therefore, the host must always poll the command
register to determine the state of the doorbell bit, and ensure the bit is cleared before
issuing a command.
For a complete command list and further information consult the Host Command Interface Specification.
An example of how (using DevWare) a command may be initiated in the form of a
“Preset” follows.
Issue the SYSMGR_SET_STATE Command
All DevWare presets supplied by ON Semiconductor poll and test the doorbell bit after
issuing the command. Therefore there is no need to check if the doorbell bit is clear
before issuing the next command.
# Set the desired next state in the parameters pool(SYS_STATE_ENTER_CONFIG_CHANGE)
REG= 0xFC00, 0x2800 // CMD_HANDLER_PARAMS_POOL_0
# Issue the HC_SYSMGR_SET_STATE command
REG= 0x0040, 0x8100 // COMMAND_REGISTER
# Wait for the FW to complete the command (clear the Doorbell bit)
POLL_FIELD= COMMAND_REGISTER, DOORBELL,!=0, DELAY=10, TIMEOUT=100
# Check the command was successful
ERROR_IF= COMMAND_REGISTER, HOST_COMMAND,!=0, "Set State command
failed",
ASX340AT/D Rev. H, 8/15 EN
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ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
External Signal Processing
Summary of Host Commands
Table 14 on page 34 through Table 21 on page 36 show summaries of the host
commands. The commands are divided into the following sections:
• System Manager
• Overlay
• GPIO
• Flash Manager
• Sequencer
• Patch Loader
• Miscellaneous
• Calibration Stats
Following is a summary of the Host Interface commands. The description gives a quick
orientation. The “Type” column shows if it is an asynchronous or synchronous
command. For a complete list of all commands including parameters, consult the Host
Command Interface Specification document.
Table 14:
System Manager Commands
System Manager
Host Command
Value
Type
Description
Set State
0x8100
Synchronous
Request the system enter a new state
Get State
0x8101
Synchronous
Get the current state of the system
Table 15:
Overlay Host Commands
Overlay Host Command
Value
Type
Enable Overlay
0x8200
Synchronous
Enable or disable the overlay subsystem
Get Overlay State
0x8201
Synchronous
Retrieve the state of the overlay subsystem
Set Calibration
0x8202
Synchronous
Set the calibration offset
Set Bitmap Property
0x8203
Synchronous
Set a property of a bitmap
Get Bitmap Property
0x8204
Synchronous
Get a property of a bitmap
Set String Property
0x8205
Synchronous
Set a property of a character string
Load Buffer
0x8206
Asynchronous
Load an overlay buffer with a bitmap (from Flash)
Load Status
0x8207
Synchronous
Retrieve status of an active load buffer operation
Write Buffer
0x8208
Synchronous
Write directly to an overlay buffer
Read Buffer
0x8209
Synchronous
Read directly from an overlay buffer
Enable Layer
0x820A
Synchronous
Enable or disable an overlay layer
Get Layer Status
0x820B
Synchronous
Retrieve the status of an overlay layer
Set String
0x820C
Synchronous
Set the character string
Get String
0x820D
Synchronous
Get the current character string
Load String
0x820E
Asynchronous
Load a character string (from Flash)
ASX340AT/D Rev. H, 8/15 EN
Description
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ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
External Signal Processing
Table 16:
GPIO Host Commands
GPIO Host Command
Value
Type
Set GPIO Property
0x8400
Synchronous
Set a property of one or more GPIO pins
Get GPIO Property
0x8401
Synchronous
Retrieve a property of a GPIO pin
Set GPO State
0x8402
Synchronous
Set the state of a GPO pin or pins
Get GPIO State
0x8403
Synchronous
Get the state of a GPI pin or pins
Set GPI Association
0x8404
Synchronous
Associate a GPI pin state with a Command Sequence stored in SPI Flash
Get GPI Association
0x8405
Synchronous Retrieve an GPIO pin association
Table 17:
Description
Flash Manager Host Commands
Flash Manager
Host Command
Value
Type
Description
Get Lock
0x8500
Asynchronous Request the Flash Manager access lock
Lock Status
0x8501
Synchronous
Retrieve the status of the access lock request
Release Lock
0x8502
Synchronous
Release the Flash Manager access lock
Config
0x8503
Synchronous
Configure the Flash Manager and underlying SPI Flash subsystem
Read
0x8504
Asynchronous Read data from the SPI Flash
Write
0x8505
Asynchronous Write data to the SPI Flash
Erase Block
0x8506
Asynchronous Erase a block of data from the SPI Flash
Erase Device
0x8507
Asynchronous Erase the SPI Flash device
Query Device
0x8508
Asynchronous Query device-specific information
Status
0x8509
Synchronous
Obtain status of current asynchronous operation
Config Device
0x850A
Synchronous
Configure the attached SPI NVM device
Table 18:
Sequencer Host Commands
Sequencer Host
Command
Value
Type
Refresh
0x8606
Synchronous
Refresh the automatic image processing algorithm configuration
Refresh Status
0x8607
Synchronous
Retrieve the status of the last Refresh operation
Table 19:
Description
Patch Loader Host Commands
Patch Loader Host
Command
Value
Type
Description
Load Patch
0x8700
Asynchronous
Load a patch from SPI Flash and automatically apply
Status
0x8701
Synchronous
Get status of an active Load Patch or Apply Patch request
Apply Patch
0x8702
Asynchronous
Apply a patch (already located in Patch RAM)
Reserve RAM
0x8706
Synchronous
Reserve RAM to contain a patch
Table 20:
Miscellaneous Host Commands
Miscellaneous Host Command
Value
Type
Description
Invoke Command Seq
0x8900
Synchronous
Invoke a sequence of commands stored in NVM
Config Command Seq Processor
0x8901
Synchronous
Configures the Command Sequencer processor
Wait For Event
0x8902
Synchronous
Wait for a system event to be signalled
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ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
External Signal Processing
Table 21:
Calibration Stats Host Commands
Calibration Stats Host
Command
Value
Type
Description
Control
0x8B00
Asynchronous
Start statistics gathering
Read
0x8B01
Synchronous
Read the results back
ASX340AT/D Rev. H, 8/15 EN
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©Semiconductor Components Industries, LLC, 2015.
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Slave Two-Wire Serial Interface
Slave Two-Wire Serial Interface
The two-wire serial interface bus enables read/write access to control and status registers within the ASX340AT. This interface is designed to be compatible with the MIPI Alliance Standard for Camera Serial Interface 2 (CSI-2) 1.0, which uses the electrical
characteristics and transfer protocols of the two-wire serial interface specification.
The interface protocol uses a master/slave model in which a master controls one or
more slave devices. The sensor acts as a slave device. The master generates a clock (SCLK)
that is an input to the sensor and used to synchronize transfers.
Data is transferred between the master and the slave on a bidirectional signal (SDATA).
SDATA is pulled up to VDD_IO off-chip by a pull-up resistor in the range of 1.5 to 4.7 k.
Protocol
Data transfers on the two-wire serial interface bus are performed by a sequence of lowlevel protocol elements, as follows:
• a start or restart condition
• a slave address/data direction byte
• a 16-bit register address
• an acknowledge or a no-acknowledge bit
• data bytes
• a stop condition
The bus is idle when both SCLK and SDATA are HIGH. Control of the bus is initiated with a
start condition, and the bus is released with a stop condition. Only the master can generate the start and stop conditions.
The SADDR pin is used to select between two different addresses in case of conflict with
another device. If SADDR is LOW, the slave address is 0x90; if SADDR is HIGH, the slave
address is 0xBA. See Table 22.
Table 22:
Two-Wire Interface ID Address Switching
SADDR
Two-Wire Interface Address ID
0
1
0x90
0xBA
Start Condition
A start condition is defined as a HIGH-to-LOW transition on SDATA while SCLK is HIGH.
At the end of a transfer, the master can generate a start condition without previously
generating a stop condition; this is known as a “repeated start” or “restart” condition.
Data Transfer
Data is transferred serially, 8 bits at a time, with the MSB transmitted first. Each byte of
data is followed by an acknowledge bit or a no-acknowledge bit. This data transfer
mechanism is used for the slave address/data direction byte and for message bytes.
One data bit is transferred during each SCLK clock period. SDATA can change when SCLK
is low and must be stable while SCLK is HIGH.
ASX340AT/D Rev. H, 8/15 EN
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ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Slave Two-Wire Serial Interface
Slave Address/Data Direction Byte
Bits [7:1] of this byte represent the device slave address and bit [0] indicates the data
transfer direction. A “0” in bit [0] indicates a write, and a “1” indicates a read. The default
slave addresses used by the ASX340AT are 0x90 (write address) and 0x91 (read address).
Alternate slave addresses of 0xBA (write address) and 0xBB (read address) can be
selected by asserting the SADDR input signal.
Message Byte
Message bytes are used for sending register addresses and register write data to the slave
device and for retrieving register read data. The protocol used is outside the scope of the
two-wire serial interface specification.
Acknowledge Bit
Each 8-bit data transfer is followed by an acknowledge bit or a no-acknowledge bit in the
SCLK clock period following the data transfer. The transmitter (which is the master when
writing, or the slave when reading) releases SDATA. The receiver indicates an acknowledge bit by driving SDATA LOW. As for data transfers, SDATA can change when SCLK is
LOW and must be stable while SCLK is HIGH.
No-Acknowledge Bit
The no-acknowledge bit is generated when the receiver does not drive SDATA low during
the SCLK clock period following a data transfer. A no-acknowledge bit is used to terminate a read sequence.
Stop Condition
A stop condition is defined as a LOW-to-HIGH transition on SDATA while SCLK is HIGH.
ASX340AT/D Rev. H, 8/15 EN
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ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Slave Two-Wire Serial Interface
Typical Operation
A typical READ or WRITE sequence begins by the master generating a start condition on
the bus. After the start condition, the master sends the 8-bit slave address/data direction
byte. The last bit indicates whether the request is for a READ or a WRITE, where a “0”
indicates a WRITE and a “1” indicates a READ. If the address matches the address of the
slave device, the slave device acknowledges receipt of the address by generating an
acknowledge bit on the bus.
If the request was a WRITE, the master then transfers the 16-bit register address to which
a WRITE will take place. This transfer takes place as two 8-bit sequences and the slave
sends an acknowledge bit after each sequence to indicate that the byte has been
received. The master will then transfer the 16-bit data, as two 8-bit sequences and the
slave sends an acknowledge bit after each sequence to indicate that the byte has been
received. The master stops writing by generating a (re)start or stop condition. If the
request was a READ, the master sends the 8-bit write slave address/data direction byte
and 16-bit register address, just as in the write request. The master then generates a
(re)start condition and the 8-bit read slave address/data direction byte, and clocks out
the register data, 8 bits at a time. The master generates an acknowledge bit after each
8-bit transfer. The data transfer is stopped when the master sends a no-acknowledge bit.
Single READ from Random Location
Figure 17 shows the typical READ cycle of the host to the ASX340AT. The first two bytes
sent by the host are an internal 16-bit register address. The following 2-byte READ cycle
sends the contents of the registers to host.
Figure 17:
Single READ from Random Location
Previous Reg Address, N
S
Slave Address
0 A Reg Address[15:8]
S = start condition
P = stop condition
Sr = restart condition
A = acknowledge
A = no-acknowledge
A
M+1
Reg Address, M
Reg Address[7:0]
A Sr
Slave Address
1 A
Read Data
Read Data
A
A
[15:8]
[7:0]
P
slave to master
master toslave
Single READ from Current Location
Figure 18 shows the single READ cycle without writing the address. The internal address
will use the previous address value written to the register.
Figure 18:
Single Read from Current Location
Previous Reg Address, N
S
Slave Address
ASX340AT/D Rev. H, 8/15 EN
1 A
Reg Address, N+1
Read Data
Read Data
A
A
[7:0]
[15:8]
P
S
39
Slave Address
N+2
1 A
Read Data
Read Data
A P
A
[15:8]
[7:0]
©Semiconductor Components Industries, LLC, 2015.
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Slave Two-Wire Serial Interface
Sequential READ, Start from Random Location
This sequence (Figure 19) starts in the same way as the single READ from random location (Figure 17 on page 39). Instead of generating a no-acknowledge bit after the first
byte of data has been transferred, the master generates an acknowledge bit and
continues to perform byte READs until “L” bytes have been read.
Figure 19:
Sequential READ, Start from Random Location
Previous Reg Address, N
S
Slave Address
0 A Reg Address[15:8]
M+1
Read Data
(15:8)
M+2
Read Data
(7:0)
A
A
A
Read Data
(15:8)
A
Reg Address, M
Reg Address[7:0]
Read Data
(15:8)
A
A
1 A
Slave Address
M+L-2
M+3
Read Data
(7:0)
A Sr
M+1
Read Data
M+L-1
Read Data
(7:0)
A
Read Data
(15:8)
A
A
M+L
Read Data
(7:0)
A P
Sequential READ, Start from Current Location
This sequence (Figure 20) starts in the same way as the single READ from current location (Figure 18). Instead of generating a no-acknowledge bit after the first byte of data
has been transferred, the master generates an acknowledge bit and continues to
perform byte reads until “L” bytes have been read.
Figure 20:
Sequential READ, Start from Current Location
Previous Reg Address, N
S
Slave Address
1 A
N+1
Read Data
Read Data
(15:8)ReadAData
(7:0)
A
N+2
Read Data
Read Data
(15:8)ReadAData
(7:0)
A
Read Data
Read Data
ReadAData
(15:8)
(7:0)
N+L-1
Read Data
Read Data
Data
A Read
(15:8)
(7:0)
A
N+L
A P
Single Write to Random Location
Figure 21 shows the typical WRITE cycle from the host to the ASX340AT.The first 2 bytes
indicate a 16-bit address of the internal registers with most-significant byte first. The
following 2 bytes indicate the 16-bit data.
Figure 21:
Single WRITE to Random Location
Previous Reg Address, N
S
ASX340AT/D Rev. H, 8/15 EN
Slave Address
0 A Reg Address[15:8]
40
A Reg Address[7:0]
Reg Address, M
A
Write Data
M+1
A P
A
©Semiconductor Components Industries, LLC, 2015.
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Slave Two-Wire Serial Interface
Sequential WRITE, Start at Random Location
This sequence (Figure 22) starts in the same way as the single WRITE to random location
(Figure 21). Instead of generating a no-acknowledge bit after the first byte of data has
been transferred, the master generates an acknowledge bit and continues to perform
byte writes until “L” bytes have been written. The WRITE is terminated by the master
generating a stop condition.
Figure 22:
Sequential WRITE, Start at Random Location
Previous Reg Address, N
S
Slave Address
0 A Reg Address[15:8]
M+1
Write Data
(15:8)
ASX340AT/D Rev. H, 8/15 EN
A
M+2
Write Data
(7:0)
A
Write Data
Write Data
WriteAData
(15:8)
(7:0)
A
Reg Address, M
Reg Address[7:0]
A
Write Data
M+L-2
M+3
Write Data
Write Data
WriteAData
(15:8)
(7:0)
A
A
41
M+1
A
M+L-1
A
Write Data
Write Data
WriteAData
(15:8)
(7:0)
M+L
A
P
A
©Semiconductor Components Industries, LLC, 2015.
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Overlay Capability
Overlay Capability
Figure 23 highlights the graphical overlay data flow of theASX340AT. The images are
separated to fit into 2 KB blocks of memory after compression.
• Up to four overlays may be blended simultaneously
• Overlay size 360 x 480 pixels rendered into a display area of 720 x 480 pixels (NTSC) or
720 x 576 (PAL)
• Selectable readout: rotating order is user programmable
• Dynamic movement through predefined overlay images
• Palette of 32 colors out of 64,000 with eight colors per bitmap
• Blend factors may be changed dynamically to achieve smooth transitions
The host commands allow a bitmap to be written piecemeal to a memory buffer through
the two-wire serial interface, and also through DMA direct from SPI Flash memory.
Multiple encoding passes may be required to fit an image into a 2KB block of memory;
alternatively, the image can be divided into two or more blocks to make the image fit.
Every graphic image may be positioned in the horizontal and vertical direction and
overlap with other graphic images.
The host may load an image at any time. Under control of DMA assist, data are transferred to the off-screen buffer in compressed form. This assures that no display data are
corrupted during the replenishment of the four active overlay buffers.
Figure 23:
Overlay Data Flow
Overlay buffers: 2KB each
Flash
Decompress
Blend and Overlay
Bitmaps - compressed
Note:
ASX340AT/D Rev. H, 8/15 EN
Off-screen
buffer
These images are not actually rendered, but show conceptual objects and object blending.
42
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ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
NVM Partition
NVM Partition
The contents of the Flash/EEPROM memory partition logically into three blocks (see
Figure 24):
• Memory for overlay data and descriptors
• Memory for register settings, which may be loaded at boot-up
• Firmware extensions or software patches; in addition to the on-chip firmware, extensions reside in this block of memory
These blocks are not necessarily contiguous.
Figure 24:
Memory Partitioning
F lash
Partitioning
Flash
Partitioning
Fixed-size
Fix
ed Siz e
Overlays – RLE
OverlaysRL E
Fix
ed Siz e
Fixed-size
Overlays – RLE
OverlaysRL E
12-byte
Header
12Byte Header
Overlay
Data
Overlay Data
RLE
Encoded
RL
E Encoded
Data
Data
2KB
2kByte
Lens Shading
Correction
Parameter
AlternateReg.
Alternate
Register Setting
S/W Patch
Software
Patch
External Memory Speed Requirement
For a 2 KB block of overlay to be transferred within a frame time to achieve maximum
update rate, the SPI NVM must operate at a certain minimum speed.
Table 23:
Transfer Time Estimate
ASX340AT/D Rev. H, 8/15 EN
Frame Time
SPI Clock
Transfer Time for 2 KB
33.3ms
4.5 MHz
1ms
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©Semiconductor Components Industries, LLC, 2015.
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Overlay Adjustment
Overlay Adjustment
To ensure a correct position of the overlay to compensate for assembly deviation, the
overlay can be adjusted with assistance from the overlay statistics engine:
• The overlay statistics engine supports a windowed 8-bin luma histogram, either rowwise (vertical) or column-wise (horizontal).
• The calibration statistics can be used to perform an automatic successive-approximation search of a cross-hair target within the scene.
• On the first frame, the firmware performs a coarse horizontal search, followed by a
coarse vertical search in the second frame.
• In subsequent frames, the firmware reduces the region-of-interest of the search to the
histogram bins containing the greatest accumulator values, thereby refining the
search.
• The resultant row and column location of the cross-hair target can be used to assign a
calibration value to offset selected overlay graphic image positions within the output
image.
• The calibration statistics patch also supports a manual mode, which allows the host
to access the raw accumulator values directly.
ASX340AT/D Rev. H, 8/15 EN
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ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Overlay Character Generator
Figure 25:
Overlay Calibration
The position of the target will be used to determine the calibration value that shifts the
row and column position of adjustable overlay graphics.
The overlay calibration is intended to be applied on a device by device basis “in system,”
which means after the camera has been installed. ON Semiconductor provides basic
programming scripts that may reside in the SPI Flash memory to assist in this effort.
Overlay Character Generator
In addition to the four overlay layers, a fifth layer exists for a character generator overlay
string.
There are a total of:
• 16 alphanumeric characters available
• 22 characters maximum per line
• 16 x 32 pixels with 1-bit color depth
ASX340AT/D Rev. H, 8/15 EN
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ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Overlay Character Generator
Any update to the character generator string requires the string to be passed in its
entirety with the Host Command. Character strings have their own control properties
aside from the Overlay bitmap properties.
Figure 26:
Internal Block Diagram Overlay
B T 65 6
O verla y
L ayer3
R e giste r B u s
U ser R egiste rs
L ayer2
D a ta B u s
D M A /C P U
L ayer1
Tim in g co ntrol
L ayer0
N u m be r
G en era to r
ROM
B T 65 6
ASX340AT/D Rev. H, 8/15 EN
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ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Overlay Character Generator
Character Generator
The character generator can be seen as the fifth top layer, but instead of getting the
source from RLE data in the memory buffers, it has 16 predefined characters stored in
ROM.
All the characters are 1-bit depth color and are sharing the same YCbCr look up table.
Figure 27:
Example of Character Descriptor 0 Stored in ROM
ROM 15 14
0x00 0 0
0x02 0 0
0x04
0 0
0x06
0 0
0x08
0 0
0x0a
0 0
0x0c
0 0
0x0e
0 0
0x10
0 0
0x12
0 0
0x14
0 1
0x16
0 1
0x18
0 1
0x1a
0 1
0x1c
0 1
0x1e
0 1
0x20
0 1
0x22
0 1
0x24
0 1
0x26
0 1
0x28
0 0
0x2a
0 0
0x2c
0 0
0x2e
0 0
0x30
0 0
0x32
0 0
0x34
0 0
0x36
0 0
0x38
0 0
0x3a 0 0
0x3c 0 0
0x3e 0 0
…
13
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
12
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
11
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
10
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
9
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
8
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
7
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
6
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
5
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
4
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
3
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
2
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
It can show a row of up to 22 characters of 16 x 32 pixels resolution (32 x 32 pixels when
blended with the BT 656 data).
ASX340AT/D Rev. H, 8/15 EN
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©Semiconductor Components Industries, LLC, 2015.
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Overlay Character Generator
Character Generator Details
Table 24 shows the characters that can be generated.
Table 24:
Character Generator Details
Item
Quantity
Description
16-bit character
22
Code for one of these characters: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, /, (space), :, –, (comma), (period)
1 bpp color
1
Depth of the bit map is 1 bpp
It is the responsibility of the user to set up proper values in the character positioning to
fit them in the same row (that is one of the reasons that 22 is the maximum number of
characters).
Note:
No error is generated if the character row overruns the horizontal or vertical limits of
the frame.
Full Character Set for Overlay
Figure 28 shows all of the characters that can be generated by the ASX340AT.
Figure 28:
Full Character Set for Overlay
0x0 0x4 0x8 0xC
0x1 0x5 0x9 0xD
0x2 0x6 0xA 0xE
0x3 0x7 0xB 0xF
ASX340AT/D Rev. H, 8/15 EN
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©Semiconductor Components Industries, LLC, 2015.
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Modes and Timing
Modes and Timing
This section provides an overview of the typical usage modes and related timing information for the ASX340AT.
Composite Video Output
The external pin DOUT_LSB0 can be used to configure the device for default NTSC or PAL
operation (auto-config mode). This and other video configuration settings are available
as register settings accessible through the serial interface.
NTSC
Both differential and single-ended connections of the full NTSC format are supported.
The differential connection that uses two output lines is used for low noise or long
distance applications. The single-ended connection is used for PCB tracks and screened
cable where noise is not a concern. The NTSC format has three black lines at the bottom
of each image for padding (which most LCDs do not display).
PAL
The PAL format is supported with 576 active image rows.
Single-Ended and Differential Composite Output
The composite output can be operated in a single-ended or differential mode by simply
changing the external resistor configuration. Refer to the Developer Guide for configuration options.
Parallel Output (DOUT)
The DOUT[7:0] port supports both progressive and Interlaced mode. Progressive mode
(with FV and LV signal) include raw bayer(8 or 10 bit), YCbCr, RGB. Interlaced mode is
CCIR656 compliant.
Figure 29 shows the data that is output on the parallel port for CCIR656. Both NTSC and
PAL formats are displayed. The blue values in Figure 29 represent NTSC (525/60). The
red values represent PAL (625/50).
Figure 29:
CCIR656 8-Bit Parallel Interface Format for 525/60 (625/50) Video Systems
Start of digital line
Start of digital active line
EAV CODE
F
F
0
0
0
0
4
4
X
Y
BLANKING
8
0
1
0
8
0
SAV CODE
1
0
8
0
268
280
1
0
F
F
0
0
0
0
4
4
CO -SITED _
CO -SITED _
X C
Y B
Y
C
R
Next line
Y
C
B
Y
C
R
Y
C
R
Y
F
F
Digital
video
stream
1440
1440
1716
1728
ASX340AT/D Rev. H, 8/15 EN
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©Semiconductor Components Industries, LLC, 2015.
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Modes and Timing
Figure 30 shows detailed vertical blanking information for NTSC timing. See Table 25 for
data on field, vertical blanking, EAV, and SAV states.
Figure 30:
Typical CCIR656 Vertical Blanking Intervals for 525/60 Video System
Line 4
Line 1 (V = 1)
Blanking
Field 1
(F = 0)
Odd
Line 20 (V = 0)
Field 1 Active Video
266
Line 264 (V = 1)
Blanking
Field 2
(F = 1)
Even
Line 283 (V = 0)
Field 2 Active Video
Line 525 (V = 0)
H=1
EAV
Table 25:
H=0
SAV
Field, Vertical Blanking, EAV, and SAV States 525/60 Video System
Line Number
F
V
H
(EAV)
H
(SAV)
1–3
4–9
20–263
264–265
266–282
283–525
1
0
0
0
1
1
1
1
0
1
1
0
1
1
1
1
1
1
0
0
0
0
0
0
Figure 31 on page 51 shows detailed vertical blanking information for PAL timing. See
Table 26 on page 51 for data on field, vertical blanking, EAV, and SAV states.
ASX340AT/D Rev. H, 8/15 EN
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©Semiconductor Components Industries, LLC, 2015.
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Modes and Timing
Figure 31:
Typical CCIR656 Vertical Blanking Intervals for 625/50 Video System
Line 1 (V = 1)
Blanking
Line 23 (V = 0)
Field 1
(F = 0)
Odd
Field 1 Active Video
Line 311 (V = 1)
Blanking
Line 336 (V = 0)
Field 2
(F = 1)
Even
Field 2 Active Video
Line 624 (V = 1)
Blanking
Line 625 (V = 1)
H =1
EAV
Table 26:
ASX340AT/D Rev. H, 8/15 EN
H= 0
SAV
Field, Vertical Blanking, EAV, and SAV States for 625/50 Video System
Line Number
F
V
H
(EAV)
H
(SAV)
1–22
23–310
311–312
313–335
336–623
624–625
0
0
0
1
1
1
1
0
1
1
0
1
1
1
1
1
1
1
0
0
0
0
0
0
51
©Semiconductor Components Industries, LLC, 2015.
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Modes and Timing
Reset and Clocks
Reset
Power-up reset is asserted or de-asserted with the RESET_BAR pin, which is active LOW.
In the reset state, all control registers are set to default values. See “Device Configuration” on page 28 for more details on Auto, Host, and Flash configurations.
Soft reset is asserted or de-asserted by the two-wire serial interface. In soft-reset mode,
the two-wire serial interface and the register bus are still running. All control registers
are reset using default values.
Clocks
The ASX340AT has two primary clocks:
• A master clock coming from the EXTCLK signal.
• In default mode, a pixel clock (PIXCLK) running at 2 * EXTCLK. In raw Bayer bypass
mode, PIXCLK runs at the same frequency as EXTCLK.
When the ASX340AT operates in raw Bayer bypass mode, the image flow pipeline clocks
can be shut off to conserve power.
The sensor core is a master in the system. The sensor core frame rate defines the overall
image flow pipeline frame rate. Horizontal blanking and vertical blanking are influenced
by the sensor configuration, and are also a function of certain image flow pipeline functions. The relationship of the primary clocks is depicted in Figure 32.
The image flow pipeline typically generates up to 16 bits per pixel—for example, YCbCr
or 565RGB—but has only an 8-bit port through which to communicate this pixel data.
To generate NTSC or PAL format images, the sensor core requires a 27 MHz clock.
Figure 32:
Primary Clock Relationships
EXTCLK
Sensor
Master Clock
Sensor Core
Sensor
Pixel Clock
10 bits/pixel
1 pixel/clock
Colorpipe
16 bits/pixel
1 pixel/clock
Output Interface
16 bits/pixel (TYP)
0.5 pixel/clock
ASX340AT/D Rev. H, 8/15 EN
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©Semiconductor Components Industries, LLC, 2015.
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Modes and Timing
Floating Inputs
The following ASX340AT pins cannot be floated:
• SDATA–This pin is bidirectional and should not be floated
• FRAME_SYNC
• TRST_N
• SCLK
• SADDR
• ATEST1
• ATEST2
Output Data Ordering
Table 27:
Output Data Ordering in DOUT RGB Mode
Mode
(Swap Disabled)
565RGB
555RGB
444xRGB
x444RGB
Byte
D7
D6
D5
D4
D3
D2
D1
D0
First
Second
First
Second
First
Second
First
Second
R7
G4
0
G5
R7
B7
0
G7
R6
G3
R7
G4
R6
B6
0
G6
R5
G2
R6
G3
R5
B5
0
G5
R4
B7
R5
B7
R4
B4
0
G4
R3
B6
R4
B6
G7
0
R7
B7
G7
B5
R3
B5
G6
0
R6
B6
G6
B4
G7
B4
G5
0
R5
B5
G5
B3
G6
B3
G4
0
R4
B4
Note:
Table 28:
PIXCLK is 54 MHz when EXTCLK is 27 MHz.
Output Data Ordering in Sensor Stand-Alone Mode
Mode
D7
D6
D5
D4
D3
D2
D1
D0
DOUT_LSB1
DOUT_LSB0
10-bit Output
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Note:
ASX340AT/D Rev. H, 8/15 EN
PIXCLK is 27 MHz when EXTCLK is 27 MHz.
53
©Semiconductor Components Industries, LLC, 2015.
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Modes and Timing
I/O Circuitry
Figure 33 illustrates typical circuitry used for each input, output, or I/O pad.
Figure 33:
Typical I/O Equivalent Circuits
VDD_IO
Input Pad
Pad
Receiver
GND
VDD_IO
SPI_SDI and RESET_BAR
Input Pad
Pad
Receiver
GND
VDD_IO
Receiver
I/O Pad
Pad
Slew
Rate
Control
GND
VDD_IO
SCLK and XTAL_IN
Input Pad
Pad
Receiver
GND
Pad
VDD_IO
XTAL
Output Pad
GND
Note:
ASX340AT/D Rev. H, 8/15 EN
All I/O circuitry shown above is for reference only. The actual implementation may be different.
54
©Semiconductor Components Industries, LLC, 2015.
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Modes and Timing
Figure 34:
NTSC Block
NTSC Block
VDD_DAC
DAC_REF
Pad
ESD
Pad
DAC_POS
Pad
DAC_NEG
ESD
Resistor
2.35kΩ
ESD
GND
Note:
Figure 35:
All I/O circuitry shown above is for reference only. The actual implementation may be different.
Serial Interface
ASX340AT/D Rev. H, 8/15 EN
55
©Semiconductor Components Industries, LLC, 2015.
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Modes and Timing
I/O Timing
Digital Output
By default, the ASX340AT launches pixel data, FV, and LV synchronously with the falling
edge of PIXCLK. The expectation is that the user captures data, FV, and LV using the
rising edge of PIXCLK. The timing diagram is shown in Figure 36.
As an option, the polarity of the PIXCLK can be inverted from the default by programming R0x0016[14].
Figure 36:
Digital Output I/O Timing
t
extclk_period
Input
EXT C LK
O utput
PIXC LK
t
t
pixclkf_dout
O utput
D OUT [7:0]
dout_ho
t
dout_su
t
fvlv_ho
t
pixclkf_fvlv
O utput F R AM E_VALID
LIN E _VALID
Table 29:
t
fvlv_su
Parallel Digital Output I/O Timing
fEXTCLK = 27 MHz; VDD = 1.8V; VDD_IO = 2.8V; VAA = 2.8V; VAA_PIX = 2.8V;
VDD_PLL = 2.8V; VDD_DAC = 2.8V; Default slew rate
Signal
Parameter
Conditions
fextclk
EXTCLK
t
extclk_period
Duty cycle
f
pixclk
PIXCLK1
t
pixclk_period
Duty cycle
FV/LV
Max
Unit
27
54
MHz
18.52
37
166.67
ns
45
50
55
%
6
27
54
MHz
18.52
37.04
166.67
ns
45
50
55
%
1.55
–
1.9
ns
t
dout_su
18
–
20
ns
tdout_ho
18
–
20
ns
t
pixclkf_fvlv
1.6
–
3.05
ns
tfvlv_su
15
–
16
ns
tfvlv_ho
20
–
21
ns
Note:
ASX340AT/D Rev. H, 8/15 EN
Typ
6
t
pixclkf_dout
DATA[7:0]
Min
PIXCLK can be inverted from the default by programming R0x0016[14].
56
©Semiconductor Components Industries, LLC, 2015.
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Modes and Timing
Slew Rate
Table 30:
Slew Rate for PIXCLK and DOUT
f
EXTCLK = 27 MHz; VDD = 1.8V; VDD_IO = 2.8V; VAA = 2.8V; V_PIX = 2.8V;
VDD_PLL = 2.8V; VDD_DAC = 2.8V; T = 25°C; CLOAD = 40 pF
PIXCLK
DOUT[7:0]
R0x1E [10:8]
Rise Time
Fall Time
R0x1E [2:0]
Rise Time
Fall Time
Unit
000
001
010
011
100
101
110
111
NA
NA
7.0
5.2
4.0
3.0
2.4
1.9
NA
NA
6.9
5.0
3.8
2.8
2.2
1.7
000
001
010
011
100
101
110
111
15.0
9.0
6.8
5.2
3.8
3.3
3.0
2.8
13.5
8.5
6.0
4.8
3.5
3.3
3.0
2.8
ns
ns
ns
ns
ns
ns
ns
ns
Figure 37:
Slew Rate Timing
90%
10%
PIXCLK
tr is e
tfa ll
90%
D OUT
10%
tr is e
ASX340AT/D Rev. H, 8/15 EN
57
tfa ll
©Semiconductor Components Industries, LLC, 2015.
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Modes and Timing
Configuration Timing
During start-up, the Dout_LSB0, LV and FV are sampled. Setup and hold timing for the
RESET_BAR signal with respect to DOUT_LSB0, LV, and FV are shown in Figure 38 and
Table 31. These signals are sampled once by the on-chip firmware, which yields a long
tHOLD time.
Figure 38:
Configuration Timing
RESET_BAR
t
SETUP
DOUT_LSB0
FRAME_VALID
LINE_VALID
Table 31:
t
HOLD
Valid Data
Configuration Timing
Signal
Parameter
DOUT_LSB0, FRAME_VALID, LINE_VALID
Note:
ASX340AT/D Rev. H, 8/15 EN
Min
Typ
Max
Unit
tSETUP
0
s
tHOLD
50
s
Table data is based on EXTCLK = 27 MHz.
58
©Semiconductor Components Industries, LLC, 2015.
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Modes and Timing
Figure 39:
Power Up Sequence
VDD_PLL
VDD_DAC (2.8)
t0
VAA_PIX
VAA (2.8)
t1
VDD_IO (2.8)
t2
VDD (1.8)
EXTCLK
RESET_BAR
t4
t3
Internal
Initialization
Hard Reset
Table 32:
t5
Patch Config
SPI or Host
Streaming
Power Up Sequence
Definition
Symbol
Minimum
Typical
Maximum
Unit
VDD_PLL to VAA/VAA_PIX
VAA/VAA_PIX to VDD_IO
VDD_IO to VDD
Hard Reset
Internal Initialization
t0
t1
t2
t3
t4
0
0
0
2
14
–
–
–
–
–
–
–
–
–
–
s
s
s
s
ms
Notes:
ASX340AT/D Rev. H, 8/15 EN
1. Delay between VDD and EXTCLK depends on customer devices, i.e. Xtal, Oscillator, and so on. There
is no requirement on this from the sensor.
2. Hard reset time is the minimum time required after power rails are settled. Ten clock cycles are
required for the sensor itself, assuming all power rails are settled. In a circuit where Hard reset is
performed by the RC circuit, then the RC time must include the all power rail settle time and Xtal.
3. The time for Patch Config SPI or Host, that is, t5, depends on the patches being applied.
59
©Semiconductor Components Industries, LLC, 2015.
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Modes and Timing
Figure 40:
Power Down Sequence
VDD (1.8)
t0
VDD_IO (2.8)
t1
VAA_PIX
VAA (2.8)
t2
VDD_PLL
VDD_DAC (2.8)
EXTCLK
t3
Power Down until next Power Up Cycle
Table 33:
Power Down Sequence
Definition
Symbol
Minimum
Typical
Maximum
Unit
VDD to VDD_IO
VDD_IO to VAA/VAA_PIX
VAA/VAA_PIX to VDD_PLL/DAC
Power Down until Next Power Up Time
t0
t1
t2
t3
0
0
0
1001
–
–
–
–
–
–
–
–
s
s
s
ms
(1) t3 is required between power down and next power up time, all decoupling caps from
regulators must completely discharge before next power up.
Figure 41:
FRAME_SYNC to FRAME_VALID/LINE_VALID
t
FRAME_SYNC
FRAME_SYNC
t
FRMSYNH_FVH
FRAME_VALID
LINE_VALID
Table 34:
FRAME_SYNC to FRAME_VALID/LINE_VALID Parameters
Parameter
Name
Conditions
Min
Typ
Max
Unit
FRAME_SYNC to FV/LV
t
FRAME_SYNC
tFRMSYNC_FVH
Interlaced mode
1.22
1
–
–
ms
s
ASX340AT/D Rev. H, 8/15 EN
t
FRAMESYNC
60
©Semiconductor Components Industries, LLC, 2015.
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Modes and Timing
Figure 42:
Reset to SPI Access Delay
R ESET_BAR
t
RSTH_CSL
SPI_CS_N
Figure 43:
Reset to Serial Access Delay
RESET_BAR
tRSTH_SDATAL
SDATA
Figure 44:
Reset to AE/AWB Image
RESET_BAR
VIDEO
First Frame
t
Overlay from
Flash
RSTH_FVL
t
RSTH_OVL
t
Table 35:
AE/AWB settled
RSTH_AEAWB
RESET_BAR Delay Parameters
Parameter
RESET_BAR HIGH to SPI_CS_N LOW
RESET_BAR HIGH to SDATA LOW
Name
Condition
Min
Typ
Max
Unit
tRSTH_CSL
13
–
–
ms
tRSTH_SDATAL
18
–
–
ms
14
–
–
ms
–
–
–
ms
RESET_BAR HIGH to FRAME_VALID
tRSTH_FVL
RESET_BAR HIGH to first Overlay
tRSTH_OVL
Overlay size dependent
RESET_BAR HIGH to AE/AWB settled
tRSTH_AEAWB
Scene dependent
–
–
–
ms
RESET_BAR HIGH to first NTSC frame
tRSTH_NTSC
47
–
–
ms
tRSTH_PAL
53
–
–
ms
RESET_BAR HIGH to first PAL frame
ASX340AT/D Rev. H, 8/15 EN
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©Semiconductor Components Industries, LLC, 2015.
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Electrical Specifications
Electrical Specifications
Figure 45:
SPI Output Timing
SPI_CS_N
tCS_SCLK
SPI_SCLK
SPI_SDI
tsu
tSCLK_SDO
SPI_SDO
Table 36:
SPI Data Setup and Hold Timing
Parameter
Description
fSPI_SCLK
SPI_SCLK Frequency
tsu
Setup time
tSCLK_SDO
Hold time
tCS_SCLK
Delay from falling edge of SPI_CS_N to rising edge of SPI_SCLK
Caution
Table 37:
Min
Typ
Max
Units
1.6875
4.5
18
MHz
–
–
110
ns
110
ns
–
ns
–
230
Stresses greater than those listed in Table 37 may cause permanent damage to the device.
This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Absolute Maximum Ratings
Rating
Symbol
Note:
ASX340AT/D Rev. H, 8/15 EN
Parameter
Min
Max
Unit
VDD
Digital power (1.8V)
-0.3
2.4
V
VDD_IO
I/O power (2.8v)
-0.3
4
V
VAA
VAA analog power (2.8V)
-0.3
4
V
VAA_PIX
Pixel array power (2.8v)
-0.3
4
V
VDD_PLL
PLL power (2.8V)
-0.3
4
V
VDD_DAC
DAC power (2.8V)
-0.3
4
V
VIN
DC Input Voltage
-0.3
VDD_IO+0.3
V
VOUT
DC Output Voltage
-0.3
VDD_IO+0.3
V
TSTG
Storage temperature
-50
150
°C
“Rating” column gives the maximum and minimum values that the device can tolerate.
62
©Semiconductor Components Industries, LLC, 2015.
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Electrical Specifications
Table 38:
Electrical Characteristics and Operating Conditions
Parameter1
Condition
Min
Typ
Max
Unit
Core digital voltage (VDD)
–
1.70
1.8
1.95
V
IO digital voltage (VDD_IO)
–
2.66
2.8
2.94
V
2.8
2.94
V
Video DAC voltage (VDD_DAC)
–
2.66
PLL Voltage (VDD_PLL)
–
2.66
2.8
2.94
V
Analog voltage (VAA)
–
2.66
2.8
2.94
V
Pixel supply voltage (VAA_PIX)
–
2.66
2.8
2.94
V
Imager operating temperature2
–
–40
+105
°C
–40
+85
°C
–50
+150
°C
Functional operating temperature3
Storage temperature
–
Notes:
Table 39:
1. VAA and VAA_PIX must all be at the same potential to avoid excessive current draw. Care must be
taken to avoid excessive noise injection in the analog supplies if all three supplies are tied together.
2. The imager operates in this temperature range, but image quality may degrade if it operates
beyond the functional operating temperature range.
3. Image quality is not guaranteed at temperatures equal to or greater than this range.
Video DAC Electrical Characteristics–Single-Ended Mode
fEXTCLK = 27 MHz; VDD = 1.8V; VDD_IO = 2.8V; VAA = 2.8V; VAA_PIX = 2.8V;
VDD_PLL = 2.8V; VDD_DAC = 2.8V
Parameter
Condition
Min
Typ
Max
Unit
Resolution
–
10
-
bits
DNL
–
0.2
0.4
bits
–
0.7
3.5
bits
–
37.5
-

INL
Output local load
Output voltage
Output current
Output pad (DAC_POS)
Unused output (DAC_NEG)
–
37.5
-

Single-ended mode, code 000h
–
.021
-
V
Single-ended mode, code 3FFh
–
1.392
-
V
Single-ended mode, code 000h
–
0.560
-
mA
Single-ended mode, code 3FFh
–
37.120
-
mA
Supply current
Estimate
–
-
25.0
mA
DAC_REF
DAC Reference
–
1.200
-
V
R DAC_REF
DAC Reference
–
2.4
-
K
Note:
ASX340AT/D Rev. H, 8/15 EN
DAC_POS, DAC_NEG, and DAC_REF are loaded with resistors to simulate video output driving into
a low pass filter and achieve a full output swing of 1.4V. Their resistor loadings may be different
from the loadings in a real single-ended or differential-ended video output system with an actual
receiving end. Please refer to the Developer Guide for proper resistor loadings.
63
©Semiconductor Components Industries, LLC, 2015.
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Electrical Specifications
Table 40:
Video DAC Electrical Characteristics–Differential Mode
f
EXTCLK = 27 MHz; VDD = 1.8V; VDD_IO = 2.8V; VAA = 2.8V; VAA_PIX = 2.8V;
VDD_PLL = 2.8V; VDD_DAC = 2.8V
Parameter
Condition
DNL
INL
Output local load
Typ
Max
Unit
–
–
–
0.2
0.7
37.5
0.4
3.5
–
Bits
Bits

–
–
–
–
–
–
–
–
–
–
.022
1.421
1.421
.022
.587
37.893
37.893
.587
–
1.2
2.4
–
–
–
–
–
–
–
–
50
V
V
V
V
mA
mA
mA
mA
mA
V
K
Differential mode per pad
(DAC_POS and DAC_NEG)
Differential mode, code 000h, pad dacp
Differential mode, code 000h, pad dacn
Differential mode, code 3FFh, pad dacp
Differential mode, code 3FFH, pad dacn
Differential mode, code 000h, pad dacp
Differential mode, code 000h, pad dacn
Differential mode, code 3FFh, pad dacp
Differential mode, code 3FFH, pad dacn
Estimate
DAC Reference
DAC Reference
Output voltage
Output current
Supply current
DAC_REF
R DAC_REF
Note:
Table 41:
Min
DAC_POS, DAC_NEG, and DAC_REF are loaded with resistors to simulate video output driving into
a low pass filter and achieve a full output swing of 1.4V. Their resistor loadings may be different
from the loadings in a real single-ended or differential-ended video output system with an actual
receiving end. Please refer to the Developer Guide for proper resistor loadings.
Digital I/O Parameters
TA = Ambient = 25°C; All supplies at 2.8V
Signal
Parameter
All
Outputs
VOH
Output high voltage
VOL
Output low voltage
IOH
Output high current
VOH = VDD_IO - 0.4V
VOL = 0.4V
All
Inputs
Definitions
Condition
Load capacitance
Min
Typ
Max
Unit
5
–
30
pF
–
V
0.7 * VDD_IO
–
–
0.3* VDD_IO
V
20
–
35
mA
IOL
Output low current
29
–
53
mA
VIH
Input high voltage
0.7 * VDD_IO
–
VDD_IO + 0.5
V
VIL
Input low voltage
–0.3
–
0.3 * VDD_IO
V
IIH
Input high leakage
current
0.02
–
0.26
A
IIL
Input low leakage
current
0.01
–
0.05
A
–
6.5
–
pF
Signal CAP
Input signal
capacitance
Notes:
ASX340AT/D Rev. H, 8/15 EN
1. All inputs are protected and may be active when all supplies (2.8V and 1.8V) are turned off.
64
©Semiconductor Components Industries, LLC, 2015.
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Electrical Specifications
Power Consumption, Operating Mode
Table 42:
Power Consumption – Condition 1
f
EXTCLK = 27 MHz; T = 25ºC, dark condition (lens with cover)
Power Plane
Supply
VDD
VDD_IO
VAA
VAA_PIX
VDD_DAC
VDD_PLL
1.8
2.8
2.8
2.8
2.8
2.8
Condition 1
Parallel off
Single 75
Total
Typ Power
Max Power
Unit
48.2
2.2
96
2.2
122.9
18.8
290.3
72
10
140
5
146
25
398
mW
mW
mW
mW
mW
mW
mW
Analog output uses single-ended mode: DAC_Pos = 75, DAC_Neg = 37.5, DAC_Ref =
2.4k, parallel output is disabled.
Table 43:
Power Consumption – Condition 2
fEXTCLK = 27 MHz; T = 25ºC, dark condition (lens with cover), CLOAD = 40pF
Power Plane
Supply
VDD
VDD_IO
VAA
VAA_PIX
VDD_DAC
VDD_PLL
1.8
2.8
2.8
2.8
2.8
2.8
Condition 2
Typ Power
Max Power
Unit
47.5
26.6
95.5
2.2
1.1
18.8
191.7
72
50
140
5
5
25
297
mW
mW
mW
mW
mW
mW
mW
Parallel on
VDAC off
Total
Analog output is disabled; parallel output is enabled.
ASX340AT/D Rev. H, 8/15 EN
65
©Semiconductor Components Industries, LLC, 2015.
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Electrical Specifications
NTSC Signal Parameters
Table 44:
NTSC Signal Parameters
f
EXTCLK = 27 MHz; VDD = 1.8V; VDD_IO = 2.8V; VAA = 2.8V; VAA_PIX = 2.8V;
VDD_PLL = 2.8V; VDD_DAC = 2.8V
Parameter
Conditions
Min
Typ
Max
Units
Notes
Line Frequency
15734.25
15734.27
15734.28
Hz
Field Frequency
59.94
59.94
59.94
Hz
Sync Rise Time
111
148
222
ns
Sync Fall Time
111
148
222
ns
Sync Width
4.6
4.74
4.8
s
Sync Level
39
40
41
IRE
2, 4
Burst Level
36
40
44
IRE
2, 4
Sync to Setup
(with pedestal off)
9.2
9.5
10.3
s
Sync to Burst Start
4.71
5.3
5.71
s
Front Porch
1.27
1.7
2.22
s
Black Level
5
7.5
10
IRE
1, 2, 4
White Level
90
100
110
IRE
1, 2, 3, 4
Notes:
ASX340AT/D Rev. H, 8/15 EN
1.
2.
3.
4.
Black and white levels are referenced to the blanking level.
NTSC convention standardized by the IRE (1 IRE = 7.14mV).
Encoder contrast setting R0x3C0A[5:4] = 0.
DAC ref = 2.8k, load = 37.5
66
©Semiconductor Components Industries, LLC, 2015.
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Electrical Specifications
Figure 46:
Video Timing
A
D
E
C
B
F
H
Table 45:
A
B
C
D
E
F
G
H
ASX340AT/D Rev. H, 8/15 EN
G
H
Video Timing: Specification from Rec. ITU-R BT.470
Signal
NTSC
27 MHz
PAL
27 MHz
Units
H Period
Hsync to burst
burst
Hsync to Signal
Video Signal
Front
Hsync Period
Sync rising/falling edge
63.556
4.71 to 5.71
2.23 to 3.11
9.20 to 10.30
52.655 ±0.20
1.27 to 2.22
4.70 ± 0.10
 0.25
64.00
5.60 ± 0.10
2.25 ± 0.23
10.20 ± 0.30
52 +0, -0.3
1.5 +0.3, -0.0
4.70 ± 0.20
0.20 ±0.10
s
s
s
s
s
s
s
s
67
©Semiconductor Components Industries, LLC, 2015.
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Electrical Specifications
Figure 47:
Equalizing Pulse
L
I
J
K
Table 46:
I
J
K
L
ASX340AT/D Rev. H, 8/15 EN
K
Equalizing Pulse: Specification from Rec. ITU-R BT.470
Signal
NTSC
27 MHz
PAL
27 MHz
Units
H/2 Period
Pulse width
Pulse rising/falling edge
Signal to pulse
31.778
2.30 ± 0.10
0.25
1.50 ± -0.10
32.00
2.35 ± 0.10
0.25 ± 0.05
3.0 ± 2.0
s
s
s
s
68
©Semiconductor Components Industries, LLC, 2015.
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Electrical Specifications
Figure 48:
V Pulse
M
O
N
P
Table 47:
M
N
O
P
ASX340AT/D Rev. H, 8/15 EN
P
V Pulse: Specification from Rec. ITU-R BT.470
Signal
NTSC
27 MHz
PAL
27 MHz
Units
H/2 Period
Pulse width
V pulse interval
Pulse rising/falling edge
31.778
27.10 (nominal)
4.70 ± 0.10
0.25
32.00
27.30 ± 0.10
4.70 ± 0.10
0.25 ± 0.05
s
s
s
s
69
©Semiconductor Components Industries, LLC, 2015.
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Electrical Specifications
Two-Wire Serial Bus Timing
Figure 49 and Table 48 describe the timing for the two-wire serial interface.
Figure 49:
Two-Wire Serial Bus Timing Parameters
SDATA
tLOW
tf
tSU;DAT
tr
tf
tHD;STA
tr
tBUF
SCLK
S
Table 48:
tHD;STA
tHD;DAT
tHIGH
tSU;STA
tSU;STO
Sr
P
S
Two-Wire Serial Bus Characteristics
fEXTCLK = 27 MHz; VDD = 1.8V; VDD_IO = 2.8V; VAA = 2.8V; VAA_PIX = 2.8V;
VDD_PLL = 2.8V; VDD_DAC = 2.8V; TA = 25°C
Standard Mode
Parameter
SCLK Clock Frequency
Fast Mode
Symbol
Min
Max
Min
Max
Unit
fSCL
0
100
0
400
KHz
tHD;STA
4.0
-
0.6
-
s
tLOW
4.7
-
1.3
-
s
Hold time (repeated) START condition.
After this period, the first clock pulse is
generated
LOW period of the SCLK clock
tHIGH
4.0
-
0.6
-
s
tSU;STA
4.7
-
0.6
-
s
Data hold time
tHD;DAT
04
3.455
06
0.95
s
Data set-up time
tSU;DAT
250
-
1006
-
ns
HIGH period of the SCLK clock
Set-up time for a repeated START condition
Rise time of both SDATA and SCLK signals
tr
-
1000
20 + 0.1Cb7
300
ns
Fall time of both SDATA and SCLK signals
tf
-
300
300
ns
tSU;STO
4.0
-
20 +
0.1Cb7
0.6
-
s
tBUF
4.7
-
1.3
-
s
Cb
-
400
-
400
pF
CIN_SI
-
3.3
-
3.3
pF
Set-up time for STOP condition
Bus free time between a STOP and START
condition
Capacitive load for each bus line
Serial interface input pin capacitance
SDATA max load capacitance
SDATA pull-up resistor
Notes:
ASX340AT/D Rev. H, 8/15 EN
CLOAD_SD
-
30
-
30
pF
RSD
1.5
4.7
1.5
4.7
K
This table is based on I2C standard (v2.1 January 2000). Philips Semiconductor.
Two-wire control is I2C-compatible.
All values referred to VIHmin = 0.9 VDD and VILmax = 0.1VDD levels. Sensor EXCLK = 27 MHz.
A device must internally provide a hold time of at least 300 ns for the SDATA signal to bridge the
undefined region of the falling edge of SCLK.
5. The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of
the SCLK signal.
6. A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement
tSU;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch
the LOW period of the SCLK signal. If such a device does stretch the LOW period of the SCLK signal, it
1.
2.
3.
4.
70
©Semiconductor Components Industries, LLC, 2015.
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Electrical Specifications
must output the next data bit to the SDATA line tr max + tSU;DAT = 1000 + 250 = 1250 ns (according
to the Standard-mode I2C-bus specification) before the SCLK line is released.
7. Cb = total capacitance of one bus line in pF.
ASX340AT/D Rev. H, 8/15 EN
71
©Semiconductor Components Industries, LLC, 2015.
ASX340AT/D Rev. H, 8/15 EN
Spectral Characteristics
Figure 50:
Quantum Efficiency
Red
60
GreenR
GreenB
Blue
40
30
20
72
10
0
350
Note:
450
550
650
750
850
Wavelength (nm)
950
1050
1150
The measurements were done on packaged parts with regular glass coating (that is, without Anti-Reflective Glass (ARC) coating).
©Semiconductor Components Industries, LLC, 2015
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Spectral Characteristics
Quantum Efficiency (%)
50
63-Ball iBGA Package Outline Drawing
Figure 51:
ASX340AT/D Rev. H, 8/15 EN
Package and Die Dimensions
©Semiconductor Components Industries, LLC, 2015
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Spectral Characteristics
73
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Revision History
Revision History
Rev. H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8/31/15
• Updated “Ordering Information” on page 3
Rev. G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6/1/15
• Updated “Ordering Information” on page 3
Rev. F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5/29/15
• Updated “Ordering Information” on page 3
• Removed Confidential marking
Rev. E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11/12/14
• Applied ON Semiconductor template
• Updated Table 2, “Key Parameters (continued),” on page 2
• Updated Figure 2: “System Block Diagram,” on page 8
• Updated note to Figure 3: “Using a Crystal Instead of an External Oscillator,” on
page 9
• Updated Table 4, “Pin Descriptions,” on page 10
• Updated “Pixel Array Structure” on page 15
• Updated Figure 5: “Pixel Array Description,” on page 14
• Updated “Power Sequence” on page 29
• Updated “Host Command Interface” on page 31
• Updated “Slave Two-Wire Serial Interface” on page 37
• Updated “Overlay Capability” on page 42
• Changed heading “Serial Memory Partition” to “NVM Partition” on page 43
• Updated “External Memory Speed Requirement” on page 43
• Updated “Overlay Adjustment” on page 44
• Updated Figure 34: “NTSC Block,” on page 55
• Updated Table 29, “Parallel Digital Output I/O Timing,” on page 56
• Updated “Reset” on page 52
• Updated “Clocks” on page 52
• Updated Table 31, “Configuration Timing,” on page 58
• Updated Table 32, “Power Up Sequence,” on page 59
• Updated Figure 39: “Power Up Sequence,” on page 59
• Updated Table 34, “FRAME_SYNC to FRAME_VALID/LINE_VALID Parameters,” on
page 60
• Updated Table 35, “RESET_BAR Delay Parameters,” on page 61
• Updated Table 37, “Absolute Maximum Ratings,” on page 62
• Updated Table 39, “Video DAC Electrical Characteristics–Single-Ended Mode,” on
page 63
• Updated Table 40, “Video DAC Electrical Characteristics–Differential Mode,” on
page 64
• Updated Table 41, “Digital I/O Parameters,” on page 64
• Updated Table 42, “Power Consumption – Condition 1,” on page 65
• Updated Table 43, “Power Consumption – Condition 2,” on page 65
• Updated Table 44, “NTSC Signal Parameters,” on page 66
• Updated Figure 46: “Video Timing,” on page 67
• Updated Figure 50: “Quantum Efficiency,” on page 72
ASX340AT/D Rev. H, 8/15 EN
74
©Semiconductor Components Industries, LLC, 2015.
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Revision History
• Updated Figure 51: “63-Ball iBGA Package Outline Drawing,” on page 73
Rev. D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9/25/12
• Updated Table 38, “Electrical Characteristics and Operating Conditions,” on page 63
• Updated Table 39, “Video DAC Electrical Characteristics–Single-Ended Mode,” on
page 63
• Updated “Power Consumption, Operating Mode” on page 65
• Updated Table 44, “NTSC Signal Parameters,” on page 66
• Updated Table 45, “Video Timing: Specification from Rec. ITU-R BT.470,” on page 67
• Updated Table 46, “Equalizing Pulse: Specification from Rec. ITU-R BT.470,” on
page 68
• Updated Table 47, “V Pulse: Specification from Rec. ITU-R BT.470,” on page 69
• Updated note for Figure 50: “Quantum Efficiency,” on page 72
Rev. C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7/18/12
• Updated Figure 49: “Two-Wire Serial Bus Timing Parameters,” on page 70
• Updated Table 41, “Digital I/O Parameters,” on page 64
• Updated Table 48, “Two-Wire Serial Bus Characteristics,” on page 70
Rev. B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4/18/12
• Updated to Production
• Updated Table 1: “Key Parameters,” on page 1
• Updated Table 6, “Reset/Default State of Interfaces,” on page 12
• Updated “Pixel Array Structure” on page 15
• Updated “FOV Stretch Support” on page 25
• Updated Table 29, “Parallel Digital Output I/O Timing,” on page 56
• Updated Table 30, “Slew Rate for PIXCLK and DOUT,” on page 57
• Updated Table 32, “Power Up Sequence,” on page 59
• Updated Table 33, “Power Down Sequence,” on page 60
• Updated Table 34, “FRAME_SYNC to FRAME_VALID/LINE_VALID Parameters,” on
page 60
• Updated Table 38, “Electrical Characteristics and Operating Conditions,” on page 63
• Updated Figure 51: “63-Ball iBGA Package Outline Drawing,” on page 73
Rev. A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11/10/11
• Initial release
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ASX340AT/D Rev. H, 8/15 EN
75
©Semiconductor Components Industries, LLC, 2015 .