IDT72511 IDT72521 PARALLEL BIDIRECTIONAL FIFO 512 x 18 & 1024 x 18 Integrated Device Technology, Inc. FEATURES: DESCRIPTION: • Two side-by-side FIFO memory arrays for bidirectional data transfers • 512 x 18-Bit - 512 x 18-Bit (IDT72511) • 1024 x 18-Bit - 1024 x 18-Bit (IDT72521) • 18-bit data buses on Port A side and Port B side • Can be configured for 18-to-18-bit or 36-to-36-bit communication • Fast 35ns access time • Fully programmable standard microprocessor interface • Built-in bypass path for direct data transfer between two ports • Two fixed flags, Empty and Full, for both the A-to-B and the B-to-A FIFO • Two programmable flags, Almost-Empty and Almost-Full for each FIFO • Programmable flag offset can be set to any depth in the FIFO • Any of the eight flags can be assigned to four external flag pins • Flexible reread/rewrite capabilities • Six general-purpose programmable I/O pins • Standard DMA control pins for data exchange with peripherals • 68-pin PGA and PLCC packages The IDT72511 and IDT72521 are highly integrated first-in, first-out memories that enhance processor-to-processor and processor-to-peripheral communications. IDT BiFIFOs integrate two side-by-side memory arrays for data transfers in two directions. The BiFIFOs have two ports, A and B, that both have standard microprocessor interfaces. All BiFIFO operations are controlled from the 18-bit wide Port A. Port B is also 18 bits wide and can be connected to another processor or a peripheral controller. The BiFIFOs have a 9-bit bypass path that allows the device connected to Port A to pass messages directly to the Port B device. Ten registers are accessible through Port A, a Command Register, a Status Register, and eight Configuration Registers. The IDT BiFIFO has programmable flags. Each FIFO memory array has four internal flags, Empty, Almost-Empty, Almost-Full and Full, for a total of eight internal flags. The Almost-Empty and Almost-Full flag offsets can be set to any depth through the Configuration Registers. These eight internal flags can be assigned to any of four external flag pins (FLGA-FLGD) through one Configuration Register. Port B has programmable I/O, reread/rewrite and DMA functions. Six programmable I/O pins are manipulated through SIMPLIFIED BLOCK DIAGRAM 18-Bit FIFO 18-bits 9-bits Bypass Data Data Port A Control Flags 18-bits Port B 18-Bit FIFO Processor Interface A Registers Programmable Flag Logic Programmable I/O Logic I/O Processor Interface B Control Handshake Interface DMA 2668 drw 01 The IDT logo is a registered trademark of Integrated Device Techology, Inc. MILITARY AND COMMERCIAL TEMPERATURE RANGES 1996 Integrated Device Technology, Inc. DECEMBER 1995 DSC-2668/6 5.32 1 IDT72511/IDT72521 BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY MILITARY AND COMMERCIAL TEMPERATURE RANGES two Configuration Registers. The Reread and Rewrite controls will read or write Port B data blocks multiple times. The BiFIFO has three pins, REQ, ACK and CLK, to control DMA transfers from Port B devices. PIN CONFIGURATIONS DB13 DB14 DB17 FLGB FLGD 11 DA15 DA13 DA11 10 DB11 DB12 DB15 FLGA FLGC 09 DB9 DB10 DA9 DA10 08 GND DB8 PIO 3 DA8 07 RB GND GND LDRER 06 WB VCC G68-1 VCC DSA 05 DB7 DB16 PGA TOP VIEW GND RS 04 DB5 DB6 PIO 2 LDREW 03 DB3 DB4 DA7 DA16 02 DB2 D DB13 B1 CLK REQ RER R/WA PIO 0 DA0 DA2 D DB13 A5 DA6 PIO 1 DA1 DA3 DA4 J K 01 DB0 A PIN 1 A1 A0 DA17 DA14 DA12 PIO DB135 PIO 4 ACK REW GND CSA B C D E F G H L 2668 drw 02 D A5 D A6 D A7 D A16 PIO 2 LDREW GND RS V CC DS A GND LDRER PIO 3 D A8 D A9 D A10 PIO 4 9 10 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 60 11 59 12 58 13 57 14 15 56 55 16 54 53 17 18 J68-1 52 19 51 20 50 21 22 23 PLCC TOP VIEW 49 48 47 24 46 25 45 44 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 PIO 5 D A11 D A12 DA13 DA14 D A15 D A17 A0 A1 FLG D FLGC FLGB FLG A D B17 D B15 D B14 D B13 INDEX D A4 D A3 D A2 D A1 D A0 PIO 1 PIO 0 CS A R/W A GND RER REW REQ ACK CLK D B0 D B1 DESIGNATOR 5.32 D B2 D B3 D B4 D B5 D B6 D B7 D B16 W B (R/WB ) V CC R B (DS B) GND GND D B8 D B9 D B10 D B11 D B12 2668 drw 03 2 IDT72511/IDT72521 BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY MILITARY AND COMMERCIAL TEMPERATURE RANGES PIN DESCRIPTION Symbol DA0-DA17 CSA DSA Name Data A I/O I/O Description Data inputs and outputs for the 18-bit Port A bus. Chip Select A I Port A is accessed when Chip Select A is LOW. I Data is written into Port A on the rising edge of Data Strobe when Chip Select is LOW. Data is read out of Port A on the falling edge of Data Strobe when Chip Select is LOW. R/WA Data Strobe A Read/Write A A0, A1 Addresses I DB0-DB17 Data B RB (DSB) Read B WB (R/WB) I or O If Port B is programmed to processor mode, this pin functions as an input. If Port B is programmed to peripheral mode this pin functions as an output. This pin can function as part of an Intel-style interface (RB) or as part of a Motorola-style interface (DSB). As an Intel-style interface, data is read from Port B on a falling edge of RB. As a Motorola-style interface, data is read on the falling edge of DSB or written on the rising edge of DSB through Port B. The default is Intel-style processor mode. (RB as an input). Write B I or O If Port B is programmed to processor mode, this pin functions as an input. If Port B is programmed to peripheral mode this pin functions as an output. This pin can function as part of an Intel-style interface ( WB) or as part of a Motorola-style interface (R/ WB). As an Intel-style interface, data is written to Port B on a rising edge of WB. As a Motorola-style interface, data is read (R/WB = HIGH) or written (R/WB = LOW) to Port B in conjunction with a Data Strobe B falling or rising edge. The default is Intel-style processor mode ( WB as an input.) RER REW I I/O This pin controls the read or write direction of Port A. When CSA is LOW and R/WA is HIGH, data is read from Port A on the falling edge of DSA. When CSA is LOW and R/WA is LOW, data is written into Port A on the rising edge of DSA. When Chip Select A is asserted, A 0, A1, and Read/Write A are used to select one of six internal resources. Data inputs and outputs for the 18-bit Port B bus. Reread I Loads A→ B FIFO Read Pointer with the value of the Reread Pointer when LOW. Rewrite I Loads B→ A FIFO Write Pointer with the value of the Rewrite Pointer when LOW. LDRER Load Reread I Loads the Reread Pointer with the value of the A→B FIFO Read Pointer when HIGH. LDREW Load Rewrite I Loads the Rewrite Pointer with the value of the B→A FIFO Write Pointer when HIGH. REQ Request I When Port B is programmed in peripheral mode, asserting this pin begins a data transfer. Request can be programmed either active HIGH or active LOW. ACK Acknowledge O When Port B is programmed in peripheral mode, Acknowledge is asserted in response to a Request signal. This confirms that a data transfer may begin. Acknowledge can be programmed either active HIGH or active LOW. CLK Clock I This pin is used to generate timing for ACK, peripheral mode. FLGAFLGD Flags O These four outputs pins can be assigned any one of the eight internal flags in the BiFIFO. Each of the two internal FIFOs (A→B and B→A) has four internal flags: Empty, Almost-Empty, Almost-Full and Full. PIO0-PIO5 Programmable Inputs/ Outputs I/O Six general purpose I/O pins. The input or output direction of each pin can be set independently. RS Reset VCC Power There are two +5V power pins. GND Ground There are five Ground pins at 0V. I RB , WB, DSB and R/WB when Port B is in the A LOW on this pin will perform a reset of all BiFIFO functions. 2668 tbl 01 5.32 3 IDT72511/IDT72521 BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY MILITARY AND COMMERCIAL TEMPERATURE RANGES DETAILED BLOCK DIAGRAM Reread Pointer CSA DSA R/WA A1 A0 Reread Load Reread Write Pointer Port A Control Read Pointer LDRER LDREW RER REW RB (DSB) == Port B Control WB (R/WB) == A B FIFO 18 18 Bypass Path Port B DB0-DB17 Port A DA0-DA17 9 9 B A FIFO 18 18 Read Pointer Write Pointer Load Rewrite Rewrite Rewrite Pointer 16 FLGA* FLGB* FLGC* FLGD* Command Reset Status Configuration 0 Programmable Flag Logic DMA Control Configuration 1 RS REQ* ACK* CLK Configuration 2 Configuration 3 Configuration 4 Configuration 5 Programmable I/O Logic Configuration 6 Configuration 7 NOTES: (*) Can be programmed either active high or active low in internal configuration registerers. (==) Can be programmed through an internal configuration register to be either an input or an output. 5.32 PIO5 == PIO4 == PIO3 == PIO2 == PIO1 == PIO0 == 2668 drw 04 4 IDT72511/IDT72521 BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY MILITARY AND COMMERCIAL TEMPERATURE RANGES FUNCTIONAL DESCRIPTION IDT’s BiFIFO family is versatile for both multiprocessor and peripheral applications. Data can be sent through both FIFO memories concurrently, thus freeing both processors from laborious direct memory access (DMA) protocols and frequent interrupts. Two full 18-bit wide FIFOs are integrated into the IDT BiFIFO, making simultaneous data exchange possible. Each FIFO is monitored by separate internal read and write pointers, so communication is not only bidirectional, it is also totally independent in each direction. The processor connected to Port A of the BiFIFO can send or receive messages directly to the Port B device using the BiFIFO’s 9-bit bypass path. The BiFIFO can be used in different bus configurations: 18 bits to 18 bits and 36 bits to 36 bits. One BiFIFO can be used for the 18- to 18-bit configuration, and two BiFIFOs are required for 36- to 36-bit configuration. This configuration can be extended to wider bus widths (54- to 54-bits, 72- to 72-bits, …) by adding more BiFIFOs to the configuration. The microprocessor or microcontroller connected to Port A controls all operations of the BiFIFO. Thus, all Port A interface pins are inputs driven by the controlling processor. Port B can be programmed to interface either with a second processor or a peripheral device. When Port B is programmed in processor interface mode, the Port B interface pins are inputs driven by the second processor. If a peripheral device is connected to the BiFIFO, Port B is programmed to peripheral interface mode and the interface pins are outputs. 18- to 18-bit Configurations A single BiFIFO can be configured to connect an 18-bit processor to another 18-bit processor or an 18-bit peripheral. The upper BiFIFO shown in each of the Figures 1 and 2 can be used in 18- to 18-bit configurations for processor and peripheral interface modes respectively. 36- to 36-bit Configurations In a 36- to 36-bit configuration, two BiFIFOs operate in parallel. Both BiFIFOs are programmed simultaneously, 18 data bits to each device. Figures 1 and 2 show multiple BiFIFOs configured for processor and peripheral interface modes respectively. Processor Interface Mode When a microprocessor or microcontroller is connected to Port B, all BiFIFOs in the configuration must be programmed to processor interface mode. In this mode, all Port B interface controls are inputs. Both REQ and CLK pins should be pulled LOW to ensure that the setup and hold time requirements for these pins are met during reset. Figure 1 shows the BiFIFO in processor interface mode. IDT BiFIFO Cntl A Cntl B ACK REQ CLK Data 36 Control Logic 36-bit bus Control 36-bit bus Address Control Logic Data A Data B Processor A IDT BiFIFO Cntl A RAM Cntl B ACK REQ CLK Processor B Control Data 36 RAM Data A Data B 18 18 2668 drw 05 Figure 1. 36-Bit Processor to 36-Bit Processor Configuration NOTE: 1. 36- to 36-bit processor interface configuration. Upper BiFIFO only is used in 18- to 18-bit configuration. Note that Cntl A refers to CSA, A1, A0, R/WA, and DSA; Cntl B refers to R/WB and DSB or RB and WB. 5.32 5 IDT72511/IDT72521 BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY MILITARY AND COMMERCIAL TEMPERATURE RANGES Peripheral Interface Mode If Port B is connected to a peripheral controller, all BiFIFOs in the configuration must be programmed in peripheral interface mode. In this mode, all the Port B interface pins are all outputs. To assure fixed high states for RB and WB before they are programmed into an output, these two pins should be pulled up to VCC with 10K resistors. Of course, only one set of Port B interface pins should be used to control a single peripheral device, while the other interface pins are all ignored. Figure 2 shows a BiFIFO configuration connected to a peripheral. Port A Interface The BiFIFO is straightforward to use in microprocessorbased systems because each BiFIFO port has a standard microprocessor control set. Port A has access to six resources: the A→B FIFO, the B→A FIFO, the 9-bit direct data bus (bypass path), the configuration registers, status and command registers. The Port A Address and Read/Write pins determine the resource being accessed as shown in Table 1. Data Strobe is used to move data in and out of the BiFIFO. When either of the internal FIFOs are accessed, 18 bits of data are transferred across Port A. Since the bypass path is only 9 bits wide, the least significant byte (DA0-DA7, DA16) is used on Port A. All of the registers are 16 bits wide which means only the data bits (DA0-DA15) are passed by Port A. Bypass Path The bypass path acts as a bidirectional bus transceiver directly between Port A and Port B. The direct connection requires that the Port A interface pins are inputs and the Port B interface pins are outputs. The bypass path is 9 bits wide in an 18- to 18-bit configuration or 18 bits wide in a 36- to 36bit configuration. During bypass operations, the BiFIFOs must be programmed into peripheral interface mode. Bit 10 of Configuration Register 5 (see Table 10) is set to 1 for peripheral interface mode. Command Register Ten registers are accessible through Port A, a Command Register, a Status Register, and eight Configuration Registers. IDT BiFIFO Cntl A Cntl B ACK REQ CLK DMA or System Clock Data A Data B Data 36 Cntl ACK REQ 36-bit bus Control 36-bit bus Address Peripheral Controller Control Logic Processor IDT BiFIFO Cntl A RAM Data 36 I/O Data Cntl B ACK REQ CLK Data A Data B 18 18 Figure 2. 36-Bit Processor to 36-Bit Peripheral Configuration NOTE: 1. 36- to 36-bit peripheral interface configuration. Upper BiFIFO only is used in 18- to 18-bit configuration. Note that Cntl A refers to WA, and DSA; Cntl B refers to R/WB and DSB or RB and WB. 5.32 2668 drw 06 CSA, A1, A0, R/ 6 IDT72511/IDT72521 BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY MILITARY AND COMMERCIAL TEMPERATURE RANGES The Command Register is written by setting CSA = 0, A1 = 1, A0 = 1. Commands written into the BiFIFO have a 4-bit opcode (bit8 – bit 11) and a 3-bit operand (bit 0 – bit 2) as shown in Figure 3. The commands can be used to reset the BiFIFO, to select the Configuration Register, to perform intelligent reread/rewrite, to set the Port B DMA direction, to set the Status Register format, and to modify the Port B Read and Write Pointers. The command opcodes are shown in Table 2. The reset command initializes different portions of the BiFIFO depending on the command operand. Table 3 shows the reset command operands. The configuration Register address is set directly by the command operands shown in Table 4. Intelligent reread/rewrite is performed by interchanging the Port B Read Pointer with the Reread Pointer or by interchanging the Port B Write Pointer with the Rewrite Pointer. No command operands are required to perform a reread/ rewrite operation. When Port B of the BiFIFO is in peripheral mode, the DMA direction is controlled by the Command Register. Table 5 shows the Port B read/write DMA direction operands. Two commands are provided to increment the Port B Read and Write Pointers. No operands are required for these commands. COMMAND FORMAT 15 X 12 X X X 11 8 Command Opcode 7 X 3 X X X X 2 0 Command Operand 2668 tbl 02 Figure 3. Format for Commands Written into Port A 5.32 7 IDT72511/IDT72521 BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY MILITARY AND COMMERCIAL TEMPERATURE RANGES Reset The IDT72511 and IDT72521 have a hardware reset pin (RS) that resets all BiFIFO functions. A hardware reset requires the following four conditions: RB and WB must be HIGH, RER and REW must be HIGH, LDRER and LDREW must be LOW, and DSA must be HIGH (Figure 9). After a hardware reset, the BiFIFO is in the following state: Configuration Registers 0-3 are 0000H, Configuration Register 4 is set to 6420H, and Configuration Registers 5, 6 and 7 are 0000H. Additionally, all the pointers including the Reread and Rewrite Pointers are set to 0, the DMA direction is set to B→A write, and the internal DMA request circuitry is cleared (set to its initial state). A software reset command can reset A→B pointers and the B→A pointers to 0 independently or together. The internal PORT A RESOURCE SELECTION CSA A1 A0 Read request DMA circuitry can also be reset independently. A software Reset All command resets all the pointers, the DMA request circuitry, and sets all the Configuration Registers to their default condition. Note that a hardware reset is NOT the same as a software Reset All command. Table 6 shows the BiFIFO state after the different hardware and software resets Status Register The Status Register reports the state of the programmable flags and the DMA read/write direction. The Status Register is read by setting CSA = 0, A1 = 1, A0 = 1 (see Table 1). See Table 7 for the Status Register format. Configuration Registers The eight Configuration Register formats are shown in RESET COMMAND FUNCTIONS Reset Operands Write 0 0 0 B→A FIFO A→B FIFO 0 0 1 9-bit Bypass Path 9-bit Bypass Path 0 1 0 Configuration Registers Configuration Registers 0 1 1 Status Register Command Register 1 X X Disabled Disabled 2668 tbl 03 Table 1. Accessing Port A Resources Using CSA, A0 and A1 COMMAND OPERATIONS Command Opcode Function 000 No Operation 001 Reset B→A FIFO (Read, Write, and Rewrite Pointers = 0) 010 Reset A→B FIFO (Read, Write, and Reread Pointers = 0) 011 Reset B→A and A→B FIFO 100 Reset Internal DMA Request Circuitry 101 No Operation 110 No Operation 111 Reset All 2668 tbl 04 Function Table 3. Reset Command Functions 0000 Reset BiFIFO (see Table 3) 0001 Select Configuration Register (see Table 4) 0010 Load Reread Pointer with Read Pointer Value 0011 Load Rewrite Pointer with Write Pointer Value Operands 0100 Load Read Pointer with Reread Pointer Value 000 Select Configuration Register 0 0101 Load Write Pointer with Rewrite Pointer Value 001 Select Configuration Register 1 0110 Set DMA Transfer Direction (see Table 5) 010 Select Configuration Register 2 0111 Reserved 011 Select Configuration Register 3 1000 Increment A→B FIFO Read Pointer (Port B) 100 Select Configuration Register 4 1001 Increment B→A FIFO Write Pointer (Port B) 101 Select Configuration Register 5 1010 Reserved 110 Select Configuration Register 6 1011 Reserved 111 Select Configuration Register 7 SELECT CONFIGURATION REGISTER/ COMMAND FUNCTIONS Function 2668 tbl 06 2668 tbl 05 Table 4. Select Configuration Register Functions. Table 2. Functions Performed by Port A Commands DMA DIRECTION COMMAND FUNCTIONS Operands Function XX0 Write B→A FIFO XX1 Read A→B FIFO 2668 tbl 07 Table 5. Set DMA Direction Command Functions. Command Only Operates in Peripheral Interface Mode 5.32 8 IDT72511/IDT72521 BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY MILITARY AND COMMERCIAL TEMPERATURE RANGES STATE AFTER RESET Software Reset A→B(010) B→A and A→B(011) Internal Request (100) All(111) — — — — 0000H — — — — 6420H 0000H — — — — 0000H 0000H — — — — 0000H — — — — — Hardware Reset (RS asserted) B→A(001) Configuration Registers 0-3 0000H Configuration Register 4 6420H Configuration Register 5 Configuration Register 6-7 0 Status Register format B→A Read, Write, Rewrite Pointers 0 0 — 0 — 0 A→B Read, Write, Reread Pointers 0 B→A write — — 0 — 0 — — — 0 — clear — — — clear clear DMA direction DMA internal request 2668 tbl 08 Table 6. The BiFIFO State After a Reset Command Table 8. Configuration Registers 0-3 contain the programmable flag offsets for the Almost-Empty and Almost-Full flags. These offsets are set to 0 when a hardware reset or a software Reset All is applied. Note that Table 8 shows that Configuration Registers 0-3 are 10 bits wide to accommodate the 1024 locations in each FIFO memory of the IDT7252/520. Only 9 least significant bits are used for the 512 locations of the IDT7251/510; the most significant bit, bit 9, must be set to 0. Configuration Register 4 is used to assign the internal flags to the external flag pins (FLGA-FLGD). Each external flag pin is assigned an internal flag based on the four bit codes shown in Table 9. The default condition for Configuration Register 4 is 6420H as shown in Table 6. The default flag assignments are: FLGD is assigned B→A Full, FLGC is assigned B→A Empty, FLGB is assigned A→B Full, FLGA is assigned A→B Empty. Configuration Register 5 is a general control register. The format of Configuration Register 5 is shown in Table 10. Bit 0 sets the Intel-style interface (RB, WB) or Motorola-style interface (DSB, R/WB) for Port B. Bits 2 and 3 redefine Full and Empty Flags for reread/rewrite data protection. Bits 4-9 control the DMA interface and are only applicable in peripheral interface mode. In processor interface mode, these bits are don’t care states. Bits 4 and 5 set the polarity of the DMA control pins REQ and ACK respectively. An internal clock controls all DMA operations. This internal clock is derived from the external clock (CLK). Bit 9 determines the internal clock frequency: the internal clock = CLK or the internal clock = CLK divided by 2. Bit 8 sets whether RB, WB, and DSB are asserted for either one or two internal clocks. Bits 6 and 7 set the number of internal clocks between REQ assertion and ACK assertion. The timing can be from 2 to 5 cycles as shown in Figure 17. Bit 10 controls Port B processor or peripheral interface mode. In processor mode, the Port B control pins (RB, WB, DSB, R/WB) are inputs and the DMA controls are ignored. In peripheral mode, the Port B control pins are outputs and the DMA controls are active. Six PIO pins can be programmed as an input or output by the corresponding mask bits in Configuration Register 7. The format of Configuration Register 7 is shown in Figure 5. Each bit of the register set the I/O direction independently. A logic 1 indicates that the corresponding PIO pin is an output, while a logic 0 indicates that the PIO pin is an input. This I/O mask register can be read or written. A programmed output PIOi pin (i = 0, 1, . . . 5) displays the data latched in Bit i of Configuration Register 6. A programmed input PIOi pin allows Port A bus to sample the data on DAi by reading Configuration Register 6. STATUS REGISTER FORMAT Bit Signal 0 Reserved 1 Reserved 2 Reserved 3 DMA Direction 4 A→B Empty Flag 5 A→B Almost-Empty Flag 6 B→A Full Flag 7 B→A Almost-Full Flag 8 Reserved 9 Reserved 10 Reserved 11 Reserved 12 A→B Full Flag 13 A→B Almost-Full Flag 14 B→A Empty Flag 15 B→A Almost-Empty Flag 2668 tbl 09 Table 7. The Status Register Format 5.32 9 IDT72511/IDT72521 BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY MILITARY AND COMMERCIAL TEMPERATURE RANGES CONFIGURATION REGISTER FORMATS 10 15 Config. Reg. 0 X X X X X X 10 X X X X X 10 X X X X X 10 15 Config. Reg. 4 X X X X 12 11 Flag D Pin Assignment 9 0 A→B FIFO Almost Full Flag Offset 9 0 X 15 Config. Reg. 3 A→B FIFO Almost Empty Flag Offset X 15 Config. Reg. 2 0 X 15 Config. Reg. 1 9 B→A FIFO Almost Empty Flag Offset 9 0 X B→A FIFO Almost Full Flag Offset 8 7 Flag C Pin Assignment 4 Flag B Pin Assignment 3 0 Flag A Pin Assignment 0 15 General Control Config. Reg. 5 0 15 Config. Reg. 6 I/O Data 0 15 Config. Reg. 7 I/O Direction Control 2668 drw 02 2668 tbl 10 NOTE: 1. Bit 9 of Configuration Registers 0-3 must be set to 0 on the IDT72511. Table 8. The BiFIFO Configuration Register Formats EXTERNAL FLAG ASSIGNMENT CODES Programmable Flags The IDT BiFIFO has eight internal flags. Associated with each FIFO memory array are four internal flags, Empty, Almost-Empty, Almost-Full and Full, for the total of eight internal flags. The Almost-Empty and Almost-Full offsets can be set to any depth through the Configuration Registers 0-3 (see Table 8). The flags are asserted at the depths shown in Table 11. After a hardware reset or a software Reset All, the almost flag offsets are set to 0. Even though the offsets are equivalent, the Empty and Almost-Empty flags have different timing which means that the flags are not coincident. Similarly, the Full and Almost-Full flags are not coincident after reset because of timing. These eight internal flags can be assigned to any of four external flag pins (FLGA-FLGD) through Configuration Register 4 (see Table 9). For the specific flag timings, see Figures 20-23. The current state of all eight flags is available in the Status Register. Assignment Code 0000 0001 0010 0011 0100 0101 0110 Internal Flag Assigned to Flag Pin A→B Empty A→B Almost-Empty A→B Full A→B Almost-Full B→A Empty B→A Almost-Empty B→A Full 0111 B→A Almost-Full 1000 A→B Empty 1001 A→B Almost-Empty 1010 A→B Full 1011 A→B Almost-Full 1100 B→A Empty 1101 B→A Almost-Empty 1110 B→A Full 1111 B→A Almost-Full 2668 tbl 11 Table 9. Configuration Register 4 Internal Flag Assignments to External Flag Pins 5.32 10 IDT72511/IDT72521 BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY MILITARY AND COMMERCIAL TEMPERATURE RANGES CONFIGURATION REGISTER 5 FORMAT Bit 0 Function Select Port B Interface 1 Unused 2 Full Flag Definition 3 Empty Flag Definition 4 REQ Pin Polarity 5 7-6 8 ACK Pin Polarity REQ / ACK Timing Port B Read & Write Timing Control for Peripheral Mode 9 Internal Clock Frequency Control 10 Port B Interface Mode Control 11 Unused 12 Unused 13 Unused 14 Unused 15 Unused Pins are RB and WB (Intel-style interface) 0 RB and WB or DSB and R/WB 1 Pins are DSB and R/WB (Motorola-style interface) 0 Write pointer meets read pointer 1 Write pointer meets reread pointer 0 Read pointer meets write pointer 1 Read pointer meets rewrite pointer 0 REQ pin active HIGH 1 REQ pin active LOW 0 ACK pin active LOW 1 ACK pin active HIGH 00 2 internal clocks between REQ assertion and ACK assertion 01 3 internal clocks between REQ assertion and ACK assertion 10 4 internal clocks between REQ assertion and ACK assertion 11 5 internal clocks between REQ assertion and ACK assertion 1 RB, WB, and DSB are asserted for 1 internal clock RB, WB, and DSB are asserted for 2 internal clocks 0 Internal clock = CLK 1 Internal clock = CLK divided by 2 0 Processor interface mode (Port B controls are inputs) 1 Peripheral interface mode (Port B controls are outputs) 0 2668 tbl 12 Table 10. BiFIFO Configuration Register 5 Format CONFIGURATION REGISTER 6 FORMAT 15 6 Unused 5 4 3 2 1 0 PIO5 PIO4 PIO3 PIO2 PIO1 PIO0 2668 tbl 13 Figure 4. BiFIFO Configuration Register 6 Format for Programmable I/O Data CONFIGURATION REGISTER 7 FORMAT 15 6 Unused 5 4 3 2 1 MIO5 MIO4 MIO3 MIO2 MIO1 0 MIO0 2668 tbl 14 Figure 5. BiFIFO Configuration Register 7 Format for Programmable I/O Direction Mask 5.32 11 IDT72511/IDT72521 BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY MILITARY AND COMMERCIAL TEMPERATURE RANGES Port B Interface Port B has reread/rewrite and DMA functions. Port B can be configured to interface to either Intel-style (RB, WB) or Motorola-style (DSB, R/WB) devices in Configuration Register 5 (see Table 10). Port B can also be configured to talk to a processor or a peripheral device through Configuration Register 5. In processor interface mode, the Port B interface controls are inputs. In peripheral interface mode, the Port B interface controls are outputs. After a hardware reset or a software Reset All command, Port B defaults to an Intel-style processor interface; the controls are inputs. DMA Control Interface The BiFIFO has DMA control to simplify data transfers with peripherals. For the BiFIFO DMA controls (REQ, ACK and CLK) to operate, the BiFIFO must be in peripheral interface mode (Configuration Register 5, Table 10). DMA timing is controlled by the external clock input, CLK. An internal clock is derived from this CLK signal to generate the RB, WB, DSB and R/WB output signals. The internal clock also determines the timing between REQ assertion and ACK assertion. Bit 9 of Configuration Register 5 determines whether the internal clock is the same as CLK or whether the internal clock is CLK divided by 2. Bit 8 of Configuration Register 5 set whether RB, WB and DSB are asserted for 1 or 2 internal clocks. Bits 6 and 7 of Configuration Register 5 set the number of clocks between REQ assertion and ACK assertion. The clocks between REQ assertion and ACK assertion can be 2, 3, 4 or 5. Bits 4 and 5 of Configuration Register 5 set the polarity of the REQ and ACK pins respectively. A DMA transfer command sets the Port B read/write direction (see Table 5). The timing diagram for DMA transfers is shown in Figure 17. The basic DMA transfer starts with REQ assertion. After 2 to 5 internal clocks, ACK is asserted by the BiFIFO. ACK will not be asserted if a read is attempted on an empty A→B FIFO or if a write is attempted on a full B→A FIFO. If the BiFIFO is in Motorola-style interface mode, R/WB is set at the same time that ACK is asserted. One internal clock later, DSB is asserted. If the BiFIFO is in Intel-style interface mode, either RB or WB is asserted one internal clock after ACK assertion. These read/write controls stay asserted for 1 or 2 internal clocks, then ACK, DSB, RB and WB are made inactive. This completes the transfer of one 9-bit word. On the next rising edge of CLK, REQ is sampled. If REQ is still asserted, another DMA transfer starts with the assertion of ACK. Data transfers will continue as long as REQ is asserted. Intelligent Reread/Rewrite Intelligent reread/rewrite is a method the BiFIFO uses to help assure data integrity. Port B of the BiFIFO has two extra pointers, the Reread Pointer and the Rewrite Pointer.The Reread Pointer is associated with the A->B FIFO Read Pointer, while the Rewrite Pointer is associated with the B->A FIFO Write Pointer. The Reread Pointer holds the start address of a data block in the A->B FIFO RAM, and the Read Pointer is the current address of the same FIFO RAM array. By loading the Read Pointer with the value held in the Reread Pointer (RER asserted), reads will start over at the beginning of the data block. In order to mark the beginning of a data block, the Reread Pointer should be loaded with the Read Pointer value (LDRER asserted) before the first read is performed on this data block. Figure 6 shows a Reread operation. Similarly, the Rewrite Pointer holds the start address of a data block in the B->A FIFO RAM, while the Write Pointer is the current address within the RAM array. The operation of the REW and LDREW is identical to the RER and LDRER discussed above. Figure 7 shows a Rewrite operation. For the reread data protection, Bit 2 of Configuration Register 5 can be set to 1 to prevent the data block from being overwritten. In this way, the assertion of A->B full flag will occur when the write pointer meets the reread pointer instead of the read pointer as in the normal definition. For the rewrite data protection, Bit 3 of Configuration Register 5 can be set to 1 to INTERNAL FLAG TRUTH TABLE Number of Words in FIFO From To Empty Flag Almost-Empty Flag Almost-Full Flag Full Flag 0 0 Asserted Asserted Not Asserted Not Asserted 1 n Not Asserted Asserted Not Asserted Not Asserted n+1 D – (m + 1) Not Asserted Not Asserted Not Asserted Not Asserted D–m D–1 Not Asserted Not Asserted Asserted Not Asserted D D Not Asserted Not Asserted Asserted Asserted NOTE: 2668 tbl 15 1. BiFIFO flags must be assigned to external flag pins to be observed. D = FIFO depth (IDT72511 = 512, IDT72521 = 1024), n = Almost-Empty flag offset, m = Almost-Full flag offset. Table 11. Internal Flag Truth Table 5.32 12 IDT72511/IDT72521 BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY MILITARY AND COMMERCIAL TEMPERATURE RANGES Programmable Input/Output The BiFlFO has six programmable I/0 pins (PlO0 - PIO5) which are controlled by Port A through Configuration Registers 6 and 7. Data from the programmable I/O pins is mapped directly to the six least significant bits of Configuration Regis- ter 6. Figure 4 shows the format of Configuration Register 6. This data is read or written by Port A on the data pins (DA0- DA5). A programmed output PIOi pin (i = 0, 1, . . . , 5) displays the data latched in Bit i of Configuration Register 6. A programmed input PIOi pin allows Port A bus to sample its data on DAi by reading Configuration Register 6. The read and write timing for the programmable I/O pins is shown in Figure 19. The direction of each programmable I/O pin can be set independently by programming the mask in Configuration Register 7. Each P10 pin has a corresponding input/output direction mask bit in Configuration Register 7. Figure 5 shows the format of Configuration Register 7. Setting a mask bit to a logic 1 makes the corresponding I/O pin an output. Mask bits set to logic 0 force the corresponding I/O pin to an input. REREAD OPERATIONS (1,2) REWRITE OPERATIONS (3,4) prevent the data block from being read. In this case the assertion of B->A empty flag will occur when the read pointer meets the rewrite pointer instead of the write pointer. In conclusion, Bit 2 and 3 of Configuration Register 5 are used to redefine Full & Empty flags for data block partition. Although it can serve the purpose of data protection, the setting of these 2 bits is independent of the functions caused by RER/REW, or LDRER/LDREW assertions. Reread Pointer Read Pointer Reread function Write Pointer Write Pointer A→B FIFO Load Reread function Load Rewrite function Read Pointer Rewrite function 2668 drw 08 NOTES: 1. If bit 2 is set to 1, Empty flag asserted if Read = Write Full flag asserted if Reread + FIFO size = Write 2. If bit 2 is set to 0, Empty flag asserted if Read = Write Full flag asserted if Read + FIFO size = Write B→A FIFO NOTES: 1. If bit 3 is set to 1, Empty flag asserted if Read = Rewrite Full flag asserted if Read + FIFO size = Write 2. If bit 3 is set to 0, Empty flag asserted if Read = Write Full flag asserted if Read + FIFO size = Write Figure 6. BiFIFO Reread Operations Rewrite Pointer 2668 drw 09 Figure 7. BiFIFO Rewrite Operations 5.32 13 IDT72511/IDT72521 BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY MILITARY AND COMMERCIAL TEMPERATURE RANGES ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM Rating Commercial Military Unit Terminal Voltage With Respect To Ground –0.5 to +7.0 –0.5 to +7.0 V RECOMMENDED DC OPERATING CONDITIONS Symbol Parameter Min. Typ. Max. Unit VCCM Military Supply Voltage 4.5 5.0 5.5 V 4.5 5.0 5.5 V TA Operating Temperature 0 to +70 –55 to +125 °C VCCC Commercial Supply Voltage TBIAS Temperature Under Bias –55 to +125 –65 to +135 °C GND Supply Voltage 0 0 0 V VIH Input HIGH Voltage Commercial 2.0 — — V VIH Input HIGH Voltage Military 2.2 — — V VIL(1) Input LOW Voltage Commercial and Military — — 0.8 V TSTG Storage Temperature IOUT DC Output Current –55 to +125 –65 to +155 °C 50 50 mA NOTE: 2668 tbl 16 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. NOTE: 1. 1.5V undershoots are allowed for 10ns once per cycle. 2668 tbl 17 DC ELECTRICAL CHARACTERISTICS (Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Military: VCC = 5V ± 10%, TA = –55°C to +125°C) Symbol IDT72511L IDT72521L Commercial tA = 25, 35, 50ns Min. Typ. Max. Parameter Min. IDT72521L Military tA = 40, 50ns Typ. Max. Unit –1 — 1 –10 — 10 µA IOL(2) Output Leakage Current –10 — 10 –10 — 10 µA VOH Output Logic "1" Voltage I OUT = –1mA 2.4 — — 2.4 — — V VOL Output Logic "0" Voltage IOUT = 4mA — — 0.4 — — 0.4 V ICC1 (3)(4) Average VCC Power Supply Current — 150 230 — 180 250 mA ICC2 (3) Average Standby Current (RB = WB = DSA = VIH) — 16 30 — 24 50 mA I IL (1) Input Leakage Current (Any Input) 2668 tbl 18 NOTES: 1. Measurements with 0.4V ≤ VIN ≤ VCC, DSA = DSB ≥ VIH 2. Measurements with 0.4V ≤ VOUT ≤ VCC, DSA = DSB ≥ VIH 3. Measurements are made with outputs open. +5V AC TEST CONDITIONS Input Pulse Levels 1.1 kΩ GND to 3.0V Input Rise/Fall Times 3ns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V Output Load D.U.T. 680 Ω 30 pF* See Figure 8 2668 tbl 19 CAPACITANCE (TA = +25°C, f = 1.0MHz) Symbol Parameter CIN (2) Input Capacitance COUT (1,2) Output Capacitance 2668 drw 09 Conditions Max. Unit VIN = 0V 8 pF VOUT = 0V 12 pF NOTES: 1. With output deselected. 2. Characterized values, not currently tested. or equivalent circuit Figure 8. Output Load *Includes jig and scope capacitances 2668 tbl 20 5.32 14 IDT72511/IDT72521 BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY MILITARY AND COMMERCIAL TEMPERATURE RANGES AC ELECTRICAL CHARACTERISTICS (Commercial: VCC = 5V ± 10%, TA = 0°C to + 70°C; Military: V CC = 5V ± 10%, TA = –55°C to + 125°C) Commercial Military Com'l & Mil.(2) IDT72511L25 IDT72511L35 IDT72521L25 IDT72521L35 IDT72521L40 IDT72521L50 Min. Max. Min. Max. Min. Max. Min. Max. Unit Timing Figure Reset cycle time 35 — 45 — 50 — 65 — ns 9 tRS Reset pulse width 25 — 35 — 40 — 50 — ns 9 tRSS Reset set-up time 25 — 35 — 40 — 50 — ns 9 tRSR Reset recovery time 10 — 10 — 10 — 15 — ns 9 tRSF Reset to flag time — 35 — 45 — 50 — 65 ns 9 Symbol Parameter IDT72511L50 RESET TIMING (Port A and Port B) tRSC PORT A TIMING taA Port A access time — 25 — 35 — 40 — 50 ns 12, 14, 15 taLZ Read or write pulse LOW to data bus at Low-Z 5 — 5 — 5 — 5 — ns 12, 15, 16 taHZ Read or write pulse HIGH to data bus at High- Z — 15 — 20 — 25 — 30 ns 12, 14, 15, 16 taDV Data valid from read pulse HIGH 5 — 5 — 5 — 5 — ns 12, 14, 16 taRC Read cycle time 35 — 45 — 50 — 65 — ns 12 taRPW Read pulse width 25 — 35 — 40 — 50 — ns 12, 14, 15 taRR Read recovery time 10 — 10 — 10 — 15 — ns 12 taS CSA , A0, A1, R/WA set - 5 — 5 — 5 — 5 — ns 10, 12, 16 CSA , A0, A1, R/WA hold 5 — 5 — 5 — 5 — ns 10, 12 taDS Data set-up time 15 — 18 — 20 — 30 — ns 11, 12, 14, 15 taDH(1) Data hold time 0 — 2 — 5 — 5 — ns 11, 12, 14, 15 taWC Write cycle time 35 — 45 — 50 — 65 — ns 12 taWPW Write pulse width 25 — 35 — 40 — 50 — ns 11, 12, 14 taWR Write recovery time 10 — 10 — 10 — 15 — ns 12 taWRCOM Write recovery time after a command 25 — 35 — 40 — 50 — ns 11 up time taH time NOTE: 1. The minimum data hold time is 5ns (10ns for the 80ns speed grade) when writing to the Command or Configuration registers. 2668 tbl 21 2. IDT72511 not available in military. 5.32 15 IDT72511/IDT72521 BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY MILITARY AND COMMERCIAL TEMPERATURE RANGES AC ELECTRICAL CHARACTERISTICS (Commercial: VCC = 5V ± 10%, TA = 0°C to + 70°C; Military: V CC = 5V ± 10%, TA = –55°C to + 125°C) Commercial Symbol Parameter Military Com'l & Mil.(1) IDT72511L25 IDT72511L35 IDT72511L50 IDT72521L25 IDT72521L35 IDT72521L40 IDT72521L50 Min. Max. Min. Max. Min. Max. Min. Max. Timing Unit Figure PORT B PROCESSOR INTERFACE TIMING tbA Port B access time — 25 — 35 — 40 — 50 ns 13, 14, 15 tbLZ Read or write pulse LOW to data bus at Low-Z 5 — 5 — 5 — 5 — ns 13, 14, 15 tbHZ Read or write pulse HIGH to data bus at High-Z — 15 — 20 — 25 — 30 ns 14, 13, 15 tbDV Data valid from read pulse HIGH 5 — 5 — 5 — 5 — ns 13, 14, 15, 16 tbRC Read cycle time 35 — 45 — 50 — 65 — ns 13 tbRPW Read pulse width 25 — 35 — 40 — 50 — ns 13 tbRR Read recovery time 10 — 10 — 10 — 15 — ns 13 R/WB set-up time tbS 5 — 5 — 5 — 5 — ns 13 tbH R/WB hold time 5 — 5 — 5 — 5 — ns 13 tbDS Data set-up time 15 — 18 — 20 — 30 — ns 13, 14, 15 tbDH Data hold time 0 — 2 — 5 — 5 — ns 13, 14, 15 tbWC Write cycle time 35 — 45 — 50 — 65 — ns 13 tbWPW Write pulse width 25 — 35 — 40 — 50 — ns 13, 15 tbWR Write recovery time 10 — 10 — 10 — 15 — ns 13 PORT B PERIPHERAL INTERFACE TIMING tbA Port B access time — 25 — 40 — 45 — 55 ns 17 tbCKC Clock cycle time 15 — 20 — 20 — 25 — ns 17 tbCKH Clock pulse HIGH time 6 — 6 — 8 — 10 — ns 17 tbCKL Clock pulse LOW time 6 — 6 — 8 — 10 — ns 17 tbREQS Request set-up time 5 — 5 — 5 — 10 — ns 17 tbREQH Request hold time 5 — 5 — 5 — 5 — ns 17 tbACKL Delay from a rising clock edge to ACK switching — 15 — 18 — 20 — 25 ns 17 NOTE: 1. IDT72511 not available in military. 2668 tbl 22 5.32 16 IDT72511/IDT72521 BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY MILITARY AND COMMERCIAL TEMPERATURE RANGES AC ELECTRICAL CHARACTERISTICS (Commercial: VCC = 5V ± 10%, TA = 0°C to + 70°C; Military: V CC = 5V ± 10%, TA = –55°C to + 125°C) Commercial Symbol Parameter Military Com'l & Mil.(4) IDT72511L25 IDT72511L35 IDT72511L50 IDT72521L25 IDT72521L35 IDT72521L40 IDT72521L50 Min. Max. Min. Max. Min. Max. Min. Max. Unit Figure 10 — 10 — 10 — 15 — ns 9, 18 Timing PORT B RETRANSMIT TIMING tbDSBH RER , REW, LDRER, LDREW set-up and recovery time PROGRAMMABLE I/O TIMING tPIOA Programmable I/O access time — 20 — 25 — 25 — 30 ns 19 tPIOS Programmable I/O setup time 8 — 10 — 10 — 15 — ns 19 tPIOH Programmable I/O hold time 8 — 10 — 10 — 15 — ns 19 BYPASS TIMING tBYA Bypass access time — 18 — 20 — 25 — 30 ns 16 tBYD Bypass delay — 10 — 15 — 20 — 20 ns 16 taBYDV Bypass data valid time from DSA 15 — 15 — 15 — 15 — ns 16 tbBYDV (3) Bypass data valid time from DSB 3 — 3 — 3 — 3 — ns 16 FLAG TIMING (1) (2) tREF Read clock edge to Empty Flag asserted — 25 — 35 — 40 — 45 ns 14, 15, 20, 22 tWEF Write clock edge to Empty Flag not asserted — 25 — 35 — 40 — 45 ns 14, 15, 20, 22 tRFF Read clock edge to Full Flag not asserted — 25 — 35 — 40 — 45 ns 14, 15, 21, 23 tWFF Write clock edge to Full Flag asserted — 25 — 35 — 40 — 45 ns 14, 15, 21, 23 tRAEF Read clock edge to Almost-Empty Flag asserted — 40 — 50 — 55 — 60 ns 20, 22 tWAEF Write clock edge to Almost-Empty Flag not asserted — 40 — 50 — 55 — 60 ns 20, 22 tRAFF Read clock edge to Almost-Full Flag not asserted — 40 — 50 — 55 — 60 ns 21, 23 tWAFF Write clock edge to Almost-Full Flag asserted — 40 — 50 — 55 — 60 ns 21, 23 NOTES: 2668 tbl 23 1. Read and write are internal signals derived from DSA, R/WA, DSB, R/WB, RB, and WB. 2. Although the flags, Empty, Almost-Empty, Almost-Full, and Full Flags are internal flags, the timing given is for those assigned to external pins. 3. Values guaranteed by design, not currently tested. 4. IDT72511 not available in military. 5.32 17 IDT72511/IDT72521 BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY MILITARY AND COMMERCIAL TEMPERATURE RANGES t RSC t RS RS t RSR t RSS WB, RB (or R/WB , DSB) RER, REW LDRER, LDREW REQ t RSR DSA t RSF FLGA , FLGC t RSF FLGB , FLGD 2668 drw 10 Figure 9. Hardware Reset Timing CSA A 0 , A1 R/WA DSA ta S ta H 2668 drw 11 Figure 10. Basic Port A Control Signal Timing (Applies to All Port A Timing) 5.32 18 IDT72511/IDT72521 BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY MILITARY AND COMMERCIAL TEMPERATURE RANGES R/WA t WPW DSA t WRCOM Opcode DA8 - DA12 or Operand DA0 - DA12 2668 drw 12 ta DS ta DH Figure 11. Port A Command Timing (write). WRITE ta WC R/WA ta WPW DSA ta S ta RR ta H Input DA0 - DA17 ta DS ta DH READ R/WA ta RC ta RPW DSA ta S ta RR ta H Output DA0 - DA17 ta LZ ta DV ta A ta HZ 2668 drw 13 Figure 12. Read and Write Timing for Port A 5.32 19 IDT72511/IDT72521 BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY MILITARY AND COMMERCIAL TEMPERATURE RANGES WRITE tb WC (R/WB) WB (or DSB) tb WPW tb WR tb S tb H Input DB0 –DB8 tb DS tb DH NOTE: 1. RB = 1 READ (R/WB) tb RC RB (or DSB ) tb RPW tb RR tb H tb S Output DB0 –DB8 tb LZ tb DV tb A tb HZ 2668 drw 14 NOTE: 1. WB = 1 Figure 13. Port B Read and Write Timing, Processor Interface Mode Only 5.32 20 IDT72511/IDT72521 BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY MILITARY AND COMMERCIAL TEMPERATURE RANGES A→B FIFO WRITE FLOW-THROUGH ta WPW DSA DA0 - DA17 DATA INPUTS ta DS ta DH A→B (1) Full Flag t WFF t RFF RB (or DS B) tb LZ tb DV DB0 - DB17 DATA OUT tb A tb HZ NOTES: 1. Assume the flag pin is programmed active LOW. 2. R/WA = 0 B→A FIFO READ FLOW-THROUGH ta RPW DSA ta LZ ta A ta DV DA0 - DA17 DATA OUTPUT ta HZ B→A Empty Flag (1) t WEF t REF WB (or DSB ) DB0 - DB17 DATA INPUT tb DH tb DS 2668 drw 15 NOTES: 1. Assume the flag pin is programmed active LOW. 2. R/WA = 1 Figure 14. Port A Read and Write Flow-Through Timing, Processor Interface Mode Only 5.32 21 IDT72511/IDT72521 BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY MILITARY AND COMMERCIAL TEMPERATURE RANGES A→B FIFO WRITE FLOW-THROUGH DSA ta LZ DA0–DA17 DATA OUT tb A ta HZ B→A Full Flag(1)t RFF RB = 1 (or R/WB = 0) WB (or DSB) t WFF tb WPW DB0 –DB8 DATA INPUT NOTES: 1. Assume the flag pin is programmed active LOW. 2. R/WA = 1 tb DS tb DH A→B FIFO READ FLOW-THROUGH DSA DA0–DA17 DATA INPUT ta DS ta DH A→B Empty Flag (1)- t WEF t REF WB = 1 (or R/WB = 1) RB (or DSB) ta LZ DB0 –DB8 DATA OUT tb A NOTES: 1. Assume the flag pin is programmed active LOW. 2. R/WA = 0 tb DV tb RPW ta HZ 2668 drw 16 Figure 15. Port B Read and Write Flow-Through Timing, Processor Interface Mode Only 5.32 22 IDT72511/IDT72521 BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY MILITARY AND COMMERCIAL TEMPERATURE RANGES B→A READ BYPASS R/WA t aS t aH DSA t aLZ t aDV (1) DA0 –DA7, DA16 BYTE 0 BYTE 1 BYTE 2 t BYA t aHZ RB (or DSB) t BYD t BYD (R/WB) t BYD t BYD t BYD (1) DB0 –DB8 BYTE 0 BYTE 1 BYTE 2 NOTES: 1. Once the bypass mode starts, any data change on Port B bus (Byte 0→Byte 1) will be passed to Port A bus. 2. WB = 1 A→B WRITE BYPASS R/WA t aS t aH DSA t BYD (1) DA0 –DA7 , DA16 BYTE 1 BYTE 0 BYTE 2 t BYD WB (or DSB ) t BYD t BYD t BYD (R/WB ) tb BYDV t bLZ ta BYDV (1) BYTE 0 DB0 –DB8 BYTE 1 t BYA BYTE 2 t bHZ NOTES: 1. Once the bypass mode starts, any data change on Port A bus (Byte 0→Byte 1) will be passed to Port B bus. 2. RB = 1 2668 drw 17 Figure 16. Bypass Path Timing, BiFIFO Must Be in Peripheral Interface Mode 5.32 23 IDT72511/IDT72521 BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY MILITARY AND COMMERCIAL TEMPERATURE RANGES SINGLE WORD DMA TRANSFER 2 to 5 cycles 1 cycle 1 to 2 cycles t CKC t CKH t CKL CLK REQ t REQS t REQH ACK WRITE (R/WB ) t ACKL WB (or DSB ) ta CKL ta CKL Output DB0 -DB17 tb LZ tb DV tb A READ tb HZ (R/WB) RB (or DSB ) t ACKL t ACKL Input DB0 -DB17 tb DS tb DH BLOCK DMA TRANSFER 2 to 5 cycles 1 to 2 cycles 2 to 5 cycles 1 to 2 cycles CLK REQ ACK , R/WB RB , WB (or DSB) 2668 drw 18 Figure 17. Port B Read and Write DMA timing. Peripheral Interface Mode Only 5.32 24 IDT72511/IDT72521 BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY RB, WB (or R/WB , DSB) MILITARY AND COMMERCIAL TEMPERATURE RANGES tb DSBH tb WPW tb DSBH RER REW LDRER, LDREW 2668 drw 19 Figure 18. Port B Reread and Rewrite Timing for Intelligent Reread/Rewrite Port A → PIO WRITE ta WC R/WA DSA ta WPW ta WR ta S ta H Input DA0-DA5 ta DS ta DH Output PIO 0-PIO 5 t PIOA t PIOH PIO → Port A READ R/WA ta RC DSA ta RPW ta RR ta H ta S Output DA0-DA5 ta LZ ta DV ta A ta HZ Input PIO 0-PIO 5 t PIOS t PIOH 2668 drw 20 Figure 19. Programmable I/O Timing 5.32 25 IDT72511/IDT72521 BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY MILITARY AND COMMERCIAL TEMPERATURE RANGES Read DSA 1 WB (or R/WB = 0, DSB) 2 n+1 Write 1 2 n+1 t WEF t REF B→A Empty Flag t RAEF t WAEF B→A AlmostEmpty Flag 2668 drw 21 NOTES: 1. B→A FIFO is initially empty. 2. Assume the flag pins are programmed active LOW. 3. R/WA = 1. Figure 20. Empty and Almost-Empty Flag Timing for B→A FIFO, (n = programmed offset) Read DSA 1 WB (or R/WB =1, ) 2 m+1 Write 1 2 m+1 t WEF t RAFF (2) B→A AlmostFull Flag (2) t RFF t WFF B→A Full Flag 2668 drw 22 NOTES: 1. B→A FIFO initially contains D – (M + 1) data words. D = 512 for IDT72511; D = 1024 for IDT72521. 2. Assume the flag pins are programmed active LOW. 3. R/WA = 1. Figure 21. Full and Almost-Full Flag Timing for B→A FIFO, (m = programmed offset) 5.32 26 IDT72511/IDT72521 BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY MILITARY AND COMMERCIAL TEMPERATURE RANGES Write DSA 1 2 n+1 RB Read (or R/WB =1, DSB) 1 2 t WEF n+1 t REF A→B Empty (2) Flag t RAEF t WAE F A→B Almost- (2) Empty Flag 2668 drw 23 NOTES: 1. A→B FIFO is initially empty. 2. Assume the flag pins are programmed active LOW. 3. R/WA = 1. Figure 22. Empty and Almost-Empty Flag Timing for A→B FIFO, (n = programmed offset) Read DSA WB (or R/WB=1, DSB) 1 2 m+1 Write 1 2 m+1 t WEF t RAFF (2) B→A AlmostFull Flag (2) t RFF t WFF B→A Full Flag 2668 drw 24 NOTES: 1. B→A FIFO initially contains D – (M + 1) data words. D = 512 for IDT72511; D = 1024 for IDT72521. 2. Assume the flag pins are programmed active LOW. 3. R/WA = 1. Figure 23. Full and Almost-Full Flag Timing for A→B FIFO, (m = programmed offset) 5.32 27 IDT72511/IDT72521 BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY MILITARY AND COMMERCIAL TEMPERATURE RANGES ORDERING INFORMATION IDT XXXXX X XXX X X Device Type Power Speed Package Process/ Temperature Range Blank B Commercial (0°C to +70°C) Military (–55°C to +125°C) Compliant to MIL-STD-883, Class B G J 68-pin PGA 68-pin PLCC 25 35 40 50 Commercial Only Commercial Only Military Only * Com'l & Mil. * L 72511 72521 Access Time (tA ) in ns Low Power 512 x 18 Parallel BiFIFO 1024 x 18 Parallel BiFIFO 2668 drw 25 * 40 Military Only, IDT72521 * 50 Commercial and Military, IDT72511 available in commercial only 5.32 28